diff --git a/src/Makefile b/src/Makefile index 233414ed4..79f32b6f9 100644 --- a/src/Makefile +++ b/src/Makefile @@ -146,6 +146,11 @@ VARIO = YES # Values = YES, NO SDCARD = NO +# RTCLOCK +# Values = YES, NO +# default = YES (means enabled when available) +RTCLOCK = YES + # BLUETOOTH # Values = YES, NO BLUETOOTH = NO @@ -452,46 +457,71 @@ endif RUN_FROM_FLASH = 1 -ifeq ($(PCB), X9D) - # X9D, so ... +ifeq ($(PCB), ACT) + # ACT, so ... OPT = 2 - CPPDEFS += -DPCBX9D -DCPUARM -DEEPROM_VARIANT=0 -DAUDIO -DHAPTIC -DPXX -DDSM2 -DDSM2_PPM -DROTARY_ENCODERS=1 -DLCD212 + CPPDEFS += -DPCBACT -DCPUARM -DEEPROM_VARIANT=0 -DAUDIO -DHAPTIC -DPXX -DDSM2 -DDSM2_PPM -DROTARY_ENCODERS=1 -DLCD260 EXTRAINCDIRS += sky9x CoOS/kernel CoOS/portable + EXTRAINCDIRS += x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include BOARDSRC = board_x9d.cpp EXTRABOARDSRC += x9d/lcd_driver.cpp SRC += sky9x/core_cm3.c sky9x/board_lowlevel.c sky9x/crt.c sky9x/vectors_sam3s.c - SRC += CoOS/kernel/core.c CoOS/kernel/hook.c CoOS/kernel/task.c CoOS/kernel/event.c CoOS/kernel/time.c CoOS/kernel/timer.c CoOS/kernel/flag.c CoOS/kernel/mutex.c CoOS/kernel/serviceReq.c CoOS/portable/GCC/port.c CoOS/portable/arch.c - SRC += sky9x/usb/device/core/USBD_UDP.c sky9x/usb/device/core/USBDDriver.c - SRC += sky9x/usb/device/massstorage/MSDDriver.c sky9x/usb/device/massstorage/MSDDStateMachine.c sky9x/usb/device/massstorage/MSDLun.c sky9x/usb/device/massstorage/MSDDriverDescriptors.c sky9x/usb/device/massstorage/SBCMethods.c - SRC += sky9x/usb/common/core/USBEndpointDescriptor.c sky9x/usb/common/core/USBGenericRequest.c sky9x/usb/common/core/USBFeatureRequest.c sky9x/usb/common/core/USBInterfaceRequest.c sky9x/usb/common/core/USBGetDescriptorRequest.c sky9x/usb/common/core/USBSetAddressRequest.c sky9x/usb/common/core/USBSetConfigurationRequest.c sky9x/usb/common/core/USBConfigurationDescriptor.c sky9x/usb/common/core/USBGenericDescriptor.c - SRC += sky9x/MEDSdcard.c +# SRC += CoOS/kernel/core.c CoOS/kernel/hook.c CoOS/kernel/task.c CoOS/kernel/event.c CoOS/kernel/time.c CoOS/kernel/timer.c CoOS/kernel/flag.c CoOS/kernel/mutex.c CoOS/kernel/serviceReq.c CoOS/portable/GCC/port.c CoOS/portable/arch.c +# SRC += sky9x/usb/device/core/USBD_UDP.c sky9x/usb/device/core/USBDDriver.c +# SRC += sky9x/usb/device/massstorage/MSDDriver.c sky9x/usb/device/massstorage/MSDDStateMachine.c sky9x/usb/device/massstorage/MSDLun.c sky9x/usb/device/massstorage/MSDDriverDescriptors.c sky9x/usb/device/massstorage/SBCMethods.c +# SRC += sky9x/usb/common/core/USBEndpointDescriptor.c sky9x/usb/common/core/USBGenericRequest.c sky9x/usb/common/core/USBFeatureRequest.c sky9x/usb/common/core/USBInterfaceRequest.c sky9x/usb/common/core/USBGetDescriptorRequest.c sky9x/usb/common/core/USBSetAddressRequest.c sky9x/usb/common/core/USBSetConfigurationRequest.c sky9x/usb/common/core/USBConfigurationDescriptor.c sky9x/usb/common/core/USBGenericDescriptor.c +# SRC += sky9x/MEDSdcard.c EEPROMSRC = eeprom_arm.cpp eeprom_conversions.cpp PULSESSRC = pulses_arm.cpp - CPPSRC += sky9x/audio.cpp haptic.cpp - CPPSRC += sky9x/sound_driver.cpp sky9x/sdcard_driver.cpp +# CPPSRC += sky9x/audio.cpp haptic.cpp +# CPPSRC += sky9x/sound_driver.cpp sky9x/sdcard_driver.cpp CPPSRC += bmp.cpp monitors_views.cpp ifeq ($(SDCARD), YES) - EXTRABOARDSRC += FatFs/ff.c FatFs/fattime.c FatFs/option/ccsbcs.c sky9x/diskio.cpp + EXTRABOARDSRC += FatFs/ff.c FatFs/fattime.c FatFs/option/ccsbcs.c # sky9x/diskio.cpp CPPDEFS += -DVOICE EXTRAINCDIRS += FatFs FatFs/option endif - - ifeq ($(BLUETOOTH), YES) - CPPDEFS += -DBLUETOOTH - CPPSRC += sky9x/bluetooth.cpp - endif - + ifeq ($(DEBUG), YES) CPPSRC += sky9x/debug.cpp SRC += sky9x/syscalls.c endif endif +ifeq ($(PCB), X9D) + # X9D, so ... + OPT = 2 + CPPDEFS += -DPCBX9D -DCPUARM -DEEPROM_VARIANT=0 -DAUDIO -DPXX -DDSM2 -DDSM2_PPM -DROTARY_ENCODERS=1 -DLCD212 + EXTRAINCDIRS += sky9x CoOS/kernel CoOS/portable + EXTRAINCDIRS += x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include + BOARDSRC = board_x9d.cpp + EXTRABOARDSRC += x9d/lcd_driver.cpp x9d/aspi.cpp + SRC += CoOS/kernel/core.c CoOS/kernel/hook.c CoOS/kernel/task.c CoOS/kernel/event.c CoOS/kernel/time.c CoOS/kernel/timer.c CoOS/kernel/flag.c CoOS/kernel/mutex.c CoOS/kernel/serviceReq.c CoOS/portable/GCC/port.c CoOS/portable/arch.c + EEPROMSRC = eeprom_arm.cpp eeprom_conversions.cpp + PULSESSRC = pulses_arm.cpp + CPPSRC += sky9x/audio.cpp + CPPSRC += x9d/eeprom_driver.cpp x9d/pulses_driver.cpp x9d/keys_driver.cpp x9d/audio_driver.cpp + CPPSRC += bmp.cpp monitors_views.cpp + SRC += x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c + SRC += x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c + + ifeq ($(SDCARD), YES) + EXTRABOARDSRC += FatFs/ff.c FatFs/fattime.c FatFs/option/ccsbcs.c x9d/diskio.cpp + CPPDEFS += -DVOICE + EXTRAINCDIRS += FatFs FatFs/option + endif + + ifeq ($(RTCLOCK), YES) + CPPDEFS += -DRTCLOCK + CPPSRC += rtc.cpp x9d/rtc_driver.cpp + endif +endif + ifeq ($(PCB), SKY9X) # SKY9X, so ... OPT = 2 - CPPDEFS += -DPCBSKY9X -DCPUARM -DEEPROM_VARIANT=0 -DAUDIO -DHAPTIC -DRTCLOCK -DPXX -DDSM2 -DDSM2_PPM -DROTARY_ENCODERS=1 + CPPDEFS += -DPCBSKY9X -DCPUARM -DEEPROM_VARIANT=0 -DAUDIO -DHAPTIC -DPXX -DDSM2 -DDSM2_PPM -DROTARY_ENCODERS=1 EXTRAINCDIRS += sky9x CoOS/kernel CoOS/portable BOARDSRC = board_sky9x.cpp EXTRABOARDSRC += sky9x/lcd_driver.cpp @@ -503,9 +533,8 @@ ifeq ($(PCB), SKY9X) SRC += sky9x/MEDSdcard.c EEPROMSRC = eeprom_arm.cpp eeprom_conversions.cpp PULSESSRC = pulses_arm.cpp - CPPSRC += rtc.cpp sky9x/rtc_driver.cpp CPPSRC += sky9x/audio.cpp haptic.cpp - CPPSRC += sky9x/sound_driver.cpp sky9x/haptic_driver.cpp sky9x/sdcard_driver.cpp sky9x/massstorage.cpp + CPPSRC += sky9x/eeprom_driver.cpp sky9x/pulses_driver.cpp sky9x/keys_driver.cpp sky9x/audio_driver.cpp sky9x/haptic_driver.cpp sky9x/sdcard_driver.cpp sky9x/massstorage.cpp ifeq ($(SDCARD), YES) EXTRAINCDIRS += FatFs FatFs/option @@ -513,6 +542,11 @@ ifeq ($(PCB), SKY9X) CPPDEFS += -DVOICE endif + ifeq ($(RTCLOCK), YES) + CPPDEFS += -DRTCLOCK + CPPSRC += rtc.cpp sky9x/rtc_driver.cpp + endif + ifeq ($(BLUETOOTH), YES) CPPDEFS += -DBLUETOOTH CPPSRC += sky9x/bluetooth.cpp diff --git a/src/beeper.h b/src/beeper.h index a49b19312..aa71e0724 100644 --- a/src/beeper.h +++ b/src/beeper.h @@ -87,6 +87,9 @@ extern void beep(uint8_t val); #define IS_AUDIO_BUSY() (g_beepCnt || beepAgain || beepOn) #define AUDIO_RESET() +#define PLAY_PHASE_OFF(phase) +#define PLAY_PHASE_ON(phase) + #if !defined(CPUARM) inline void AUDIO_HEARTBEAT() { diff --git a/src/board_sky9x.cpp b/src/board_sky9x.cpp index f81422a5a..d2e3130ce 100644 --- a/src/board_sky9x.cpp +++ b/src/board_sky9x.cpp @@ -762,128 +762,6 @@ void board_init() } #endif -// keys: -// KEY_EXIT PA31 (PC24) -// KEY_MENU PB6 (PB5) -// KEY_DOWN LCD5 PC3 (PC5) -// KEY_UP LCD6 PC2 (PC1) -// KEY_RIGHT LCD4 PC4 (PC4) -// KEY_LEFT LCD3 PC5 (PC3) -// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU -// LCD pins 5 DOWN, 4 RIGHT, 3 LEFT, 1 UP -uint32_t read_keys() -{ - register uint32_t x; - register uint32_t y; - - x = lcdLock ? lcdInputs : PIOC->PIO_PDSR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - x <<= 1; - -#if defined(REVA) - y = (x & 0x00000060); - if (x & 0x00000008) - y |= 0x10; - if (x & 0x00000010) - y |= 0x08; - if (PIOA->PIO_PDSR & 0x80000000) - y |= 0x04; // EXIT - if (PIOB->PIO_PDSR & 0x000000040) - y |= 0x02; // MENU -#else - y = (x & 0x00000020); // RIGHT - if (x & 0x00000004) - y |= 0x02 << KEY_UP; // UP - if (x & 0x00000010) - y |= 0x02 << KEY_LEFT; // LEFT - if (x & 0x00000040) - y |= 0x02 << KEY_DOWN; // DOWN - if (x & 0x02000000) - y |= 0x02 << KEY_EXIT; // EXIT - if (PIOB->PIO_PDSR & 0x000000020) - y |= 0x02 << KEY_MENU; // MENU -#endif - - return y ; -} - -uint32_t read_trims() -{ - uint32_t trims; - uint32_t trima; - - trims = 0; - - trima = PIOA->PIO_PDSR; - -// TRIM_LH_DOWN PA7 (PA23) -#if defined(REVA) - if ( ( trima & 0x0080 ) == 0 ) -#else - if ((trima & 0x00800000) == 0) -#endif - { - trims |= 1; - } - -// TRIM_LV_DOWN PA27 (PA24) -#if defined(REVA) - if ( ( trima & 0x08000000 ) == 0 ) -#else - if ((trima & 0x01000000) == 0) -#endif - { - trims |= 4; - } - -// TRIM_RV_UP PA30 (PA1) -#if defined(REVA) - if ( ( trima & 0x40000000 ) == 0 ) -#else - if ((trima & 0x00000002) == 0) -#endif - { - trims |= 0x20; - } - -// TRIM_RH_DOWN PA29 (PA0) -#if defined(REVA) - if ( ( trima & 0x20000000 ) == 0 ) -#else - if ((trima & 0x00000001) == 0) -#endif - { - trims |= 0x40; - } - -// TRIM_LH_UP PB4 - if ((PIOB->PIO_PDSR & 0x10) == 0) { - trims |= 2; - } - - trima = PIOC->PIO_PDSR; -// TRIM_LV_UP PC28 - if ((trima & 0x10000000) == 0) { - trims |= 8; - } - -// TRIM_RV_DOWN PC10 - if ((trima & 0x00000400) == 0) { - trims |= 0x10; - } - -// TRIM_RH_UP PC9 - if ((trima & 0x00000200) == 0) { - trims |= 0x80; - } - - return trims; -} - -uint8_t keyDown() -{ - return ~read_keys() & 0x7E ; -} - extern uint32_t keyState(EnumKeys enuk) { register uint32_t a ; @@ -1000,29 +878,6 @@ void read_9_adc() } } -void readKeysAndTrims() -{ - register uint32_t i; - -#if defined(ROTARY_ENCODERS) - keys[BTN_REa].input(!(PIOB->PIO_PDSR & 0x40), BTN_REa); -#endif - - uint8_t enuk = KEY_MENU; - uint8_t in = ~read_keys(); - for (i = 1; i < 7; i++) { - keys[enuk].input(in & (1 << i), (EnumKeys) enuk); - ++enuk; - } - - in = read_trims(); - - for (i = 1; i < 256; i <<= 1) { - keys[enuk].input(in & i, (EnumKeys) enuk); - ++enuk; - } -} - #define RX_UART_BUFFER_SIZE 32 struct t_rxUartBuffer @@ -1176,7 +1031,7 @@ uint16_t getCurrent() static uint32_t Current_sum ; static uint8_t Current_count ; - Current_sum += anaIn(NUMBER_ANALOG-1); // TODO enum + Current_sum += anaIn(8); // TODO enum if (++Current_count >= 50) { Current = Current_sum / 5 ; Current_sum = 0 ; diff --git a/src/board_sky9x.h b/src/board_sky9x.h index 523e5b25c..69339ee2e 100644 --- a/src/board_sky9x.h +++ b/src/board_sky9x.h @@ -36,7 +36,7 @@ #include #include "sky9x/board.h" -#include "sky9x/sound_driver.h" +#include "sky9x/audio_driver.h" #include "sky9x/haptic_driver.h" #include "sky9x/debug.h" @@ -84,8 +84,8 @@ uint8_t getTemperature(); #define strcpy_P strcpy #define strcat_P strcat -extern uint32_t read_keys(); -#define KEYS_PRESSED() (~read_keys()) +extern uint32_t readKeys(); +#define KEYS_PRESSED() (~readKeys()) #define DBLKEYS_PRESSED_RGT_LFT(i) ((in & (0x20 + 0x40)) == (0x20 + 0x40)) #define DBLKEYS_PRESSED_UP_DWN(i) ((in & (0x10 + 0x08)) == (0x10 + 0x08)) #define DBLKEYS_PRESSED_RGT_UP(i) ((in & (0x20 + 0x10)) == (0x20 + 0x10)) @@ -99,6 +99,8 @@ extern uint32_t Current_used; extern uint16_t sessionTimer; #endif +void soft_power_off(); + #if defined(REVC) #define BOOTLOADER_REQUEST() (usbPlugged()) #else @@ -111,4 +113,12 @@ extern uint16_t sessionTimer; void setSticksGain(uint8_t gains); +uint32_t spi_operation( register uint8_t *tx, register uint8_t *rx, register uint32_t count ); + +#define wdt_disable() +#define wdt_enable(x) WDT->WDT_MR = 0x3FFF217F; +#define wdt_reset() WDT->WDT_CR = 0xA5000001 + +#define setBacklight(xx) PWM->PWM_CH_NUM[0].PWM_CDTYUPD = xx; + #endif diff --git a/src/board_x9d.cpp b/src/board_x9d.cpp index 3ec7c3edc..344bf1a3a 100644 --- a/src/board_x9d.cpp +++ b/src/board_x9d.cpp @@ -32,876 +32,112 @@ */ #include "open9x.h" -#include "sky9x/board.h" -uint32_t Master_frequency ; -volatile uint32_t Tenms ; +uint16_t Analog_values[NUMBER_ANALOG] ; +uint8_t temperature = 0; // Raw temp reading +uint8_t maxTemperature = 0 ; // Raw temp reading +volatile uint32_t Tenms ; // TODO to remove everywhere / use a #define -/** Console baudrate 9600. */ -#define CONSOLE_BAUDRATE 9600 -/** Usart Hw interface used by the console (UART0). */ -#define CONSOLE_USART UART0 -/** Usart Hw ID used by the console (UART0). */ -#define CONSOLE_ID ID_UART0 -/** Pins description corresponding to Rxd,Txd, (UART pins) */ -#define CONSOLE_PINS {PINS_UART} - -/** Second serial baudrate 9600. */ -#define SECOND_BAUDRATE 9600 -/** Usart Hw interface used by the console (UART0). */ -#define SECOND_USART USART0 -/** Usart Hw ID used by the console (UART0). */ -#define SECOND_ID ID_USART0 -/** Pins description corresponding to Rxd,Txd, (UART pins) */ -#define SECOND_PINS {PINS_USART0} - -#define CPU_INT int32_t -#define CPU_UINT uint32_t - -#if !defined(REVA) inline void init_soft_power() { - // Configure RF_power (PC17) - configure_pins( PIO_PC17, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_NO_PULLUP | PIN_PULLDOWN ) ; - configure_pins( PIO_PA8, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP ) ; // Enable bit A8 (Soft Power) } -#endif uint32_t check_soft_power() { -#ifdef SIMU return e_power_on; -#else - if ( PIOC->PIO_PDSR & PIO_PC17 ) // Power on - { - return e_power_on ; - } - - if (usbPlugged()) - { - return e_power_usb ; // Detected USB - } - - if ( PIOA->PIO_PDSR & PIO_PA8 ) // Trainer plugged in - { - return e_power_trainer ; - } - - return e_power_off; -#endif } // turn off soft power void soft_power_off() { - configure_pins( PIO_PA8, PIN_ENABLE | PIN_OUTPUT | PIN_LOW | PIN_PORTA | PIN_NO_PULLUP ) ; } -extern "C" void sam_boot( void ) ; - -// Prototype -// Free pins (PA16 is stock buzzer) -// PA23, PA24, PA25, PB7, PB13 -// PC20, PC21(labelled 17), PC22, PC24 -// REVB -// PA25, use for stock buzzer -// PB14, PB6 -// PC21, PC19, PC15 (PPM2 output) -inline void config_free_pins() +uint8_t getTemperature() { -#if defined(REVA) - register Pio * pioptr = PIOA ; - pioptr->PIO_PER = 0x03800000L ; // Enable bits A25,24,23 - pioptr->PIO_ODR = 0x03800000L ; // Set as input - pioptr->PIO_PUER = 0x03800000L ; // Enable pullups - - pioptr = PIOB ; - pioptr->PIO_PER = 0x00002080L ; // Enable bits B13, 7 - pioptr->PIO_ODR = 0x00002080L ; // Set as input - pioptr->PIO_PUER = 0x00002080L ; // Enable pullups - - pioptr = PIOC ; - pioptr->PIO_PER = 0x01700000L ; // Enable bits C24,22,21,20 - pioptr->PIO_ODR = 0x01700000L ; // Set as input - pioptr->PIO_PUER = 0x01700000L ; // Enable pullups -#else - configure_pins( PIO_PB14, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; -#endif + return temperature + g_eeGeneral.temperatureCalib; } -// Assumes PMC has already enabled clocks to ports -inline void setup_switches() +uint32_t keyState(EnumKeys enuk) { -#if defined(REVA) - register Pio *pioptr = PIOA ; - pioptr->PIO_PER = 0xF8008184 ; // Enable bits - pioptr->PIO_ODR = 0xF8008184 ; // Set bits input - pioptr->PIO_PUER = 0xF8008184 ; // Set bits with pullups + register uint32_t a = GPIOB->IDR; - pioptr = PIOB ; - pioptr->PIO_PER = 0x00000010 ; // Enable bits - pioptr->PIO_ODR = 0x00000010 ; // Set bits input - pioptr->PIO_PUER = 0x00000010 ; // Set bits with pullups - - pioptr = PIOC ; - pioptr->PIO_PER = 0x10014900 ; // Enable bits - pioptr->PIO_ODR = 0x10014900 ; // Set bits input - pioptr->PIO_PUER = 0x10014900 ; // Set bits with pullups -#else - configure_pins( 0x01808087, PIN_ENABLE | PIN_INPUT | PIN_PORTA | PIN_PULLUP ) ; - configure_pins( 0x00000030, PIN_ENABLE | PIN_INPUT | PIN_PORTB | PIN_PULLUP ) ; - configure_pins( 0x91114900, PIN_ENABLE | PIN_INPUT | PIN_PORTC | PIN_PULLUP ) ; -#endif -} - -#ifdef SIMU -#define end_ppm_capture() -#define sam_boot() -#else - -inline void UART3_Configure( uint32_t baudrate, uint32_t masterClock) -{ -// const Pin pPins[] = CONSOLE_PINS; - register Uart *pUart = BT_USART; - - /* Configure PIO */ - configure_pins( (PIO_PB2 | PIO_PB3), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTB | PIN_NO_PULLUP ) ; - - /* Configure PMC */ - PMC->PMC_PCER0 = 1 << BT_ID; - - /* Reset and disable receiver & transmitter */ - pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX - | UART_CR_RXDIS | UART_CR_TXDIS; - - /* Configure mode */ - pUart->UART_MR = 0x800 ; // NORMAL, No Parity - - /* Configure baudrate */ - /* Asynchronous, no oversampling */ - pUart->UART_BRGR = ( (masterClock / baudrate) + 8 ) / 16; - - /* Disable PDC channel */ - pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; - - /* Enable receiver and transmitter */ - pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; - -#if 0 - pUart->UART_IER = UART_IER_RXRDY ; - NVIC_EnableIRQ(UART1_IRQn) ; -#endif -} - -void UART3_Stop() -{ - BT_USART->UART_IDR = UART_IDR_RXRDY ; - NVIC_DisableIRQ(UART1_IRQn) ; -} - -// USART0 configuration -// Work in Progress, UNTESTED -// Uses PA5 and PA6 (RXD and TXD) -inline void UART2_Configure( uint32_t baudrate, uint32_t masterClock) -{ -//// const Pin pPins[] = CONSOLE_PINS; - register Usart *pUsart = SECOND_USART; - - /* Configure PIO */ - configure_pins( (PIO_PA5 | PIO_PA6), PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ; - -// /* Configure PMC */ - PMC->PMC_PCER0 = 1 << SECOND_ID; - -// /* Reset and disable receiver & transmitter */ - pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX - | US_CR_RXDIS | US_CR_TXDIS; - -// /* Configure mode */ - pUsart->US_MR = 0x000008C0 ; // NORMAL, No Parity, 8 bit - -// /* Configure baudrate */ -// /* Asynchronous, no oversampling */ - pUsart->US_BRGR = (masterClock / baudrate) / 16; - -// /* Disable PDC channel */ - pUsart->US_PTCR = US_PTCR_RXTDIS | US_PTCR_TXTDIS; - -// /* Enable receiver and transmitter */ - pUsart->US_CR = US_CR_RXEN | US_CR_TXEN; -} - -// Starts TIMER0 at full speed (MCK/2) for delay timing -// @ 36MHz this is 18MHz -// This was 6 MHz, we may need to slow it to TIMER_CLOCK2 (MCK/8=4.5 MHz) -inline void start_timer0() -{ - register Tc *ptc ; - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x00800000L ; // Enable peripheral clock to TC0 - - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 2 ; - ptc->TC_CHANNEL[0].TC_CMR = 0x00008001 ; // Waveform mode MCK/8 for 36MHz osc. - ptc->TC_CHANNEL[0].TC_RC = 0xFFF0 ; - ptc->TC_CHANNEL[0].TC_RA = 0 ; - ptc->TC_CHANNEL[0].TC_CMR = 0x00008040 ; // 0000 0000 0000 0000 1000 0000 0100 0000, stop at regC - ptc->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) -} - -// TIMER2 at 200Hz, provides 5mS for sound and 10mS tick on interrupt -// Starts TIMER2 at 200Hz, commentd out drive of TIOA2 (A26, EXT2) -inline void start_timer2() -{ - register Tc *ptc ; - register uint32_t timer ; - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x02000000L ; // Enable peripheral clock to TC2 - - timer = Master_frequency / 12800 / 2; // MCK/128 and 200 Hz - - ptc = TC0 ; // Tc block 0 (TC0-2) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 0 ; - ptc->TC_CHANNEL[2].TC_CMR = 0x00008000 ; // Waveform mode - ptc->TC_CHANNEL[2].TC_RC = timer ; // 10 Hz - ptc->TC_CHANNEL[2].TC_RA = timer >> 1 ; - ptc->TC_CHANNEL[2].TC_CMR = 0x0009C003 ; // 0000 0000 0000 1001 1100 0000 0000 0011 - ptc->TC_CHANNEL[2].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - - NVIC_EnableIRQ(TC2_IRQn) ; - TC0->TC_CHANNEL[2].TC_IER = TC_IER0_CPCS ; -} - -// Start TIMER3 for input capture -inline void start_timer3() -{ - register Tc *ptc ; - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x04000000L ; // Enable peripheral clock to TC3 - - ptc = TC1 ; // Tc block 1 (TC3-5) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 2 ; - ptc->TC_CHANNEL[0].TC_CMR = 0x00000000 ; // Capture mode - ptc->TC_CHANNEL[0].TC_CMR = 0x00090005 ; // 0000 0000 0000 1001 0000 0000 0000 0101, XC0, A rise, b fall - ptc->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) - - configure_pins( PIO_PC23, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_PULLUP ) ; - - NVIC_SetPriority( TC3_IRQn, 14 ) ; // Low priority interrupt - NVIC_EnableIRQ(TC3_IRQn) ; - ptc->TC_CHANNEL[0].TC_IER = TC_IER0_LDRAS ; -} - -// Start Timer4 to provide 0.5uS clock for input capture -void start_timer4() -{ - register Tc *ptc ; - register uint32_t timer ; - - timer = Master_frequency / (2*2000000) ; // MCK/2 and 2MHz - - // Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28 - PMC->PMC_PCER0 |= 0x08000000L ; // Enable peripheral clock to TC4 - - ptc = TC1 ; // Tc block 1 (TC3-5) - ptc->TC_BCR = 0 ; // No sync - ptc->TC_BMR = 0 ; - ptc->TC_CHANNEL[1].TC_CMR = 0x00008000 ; // Waveform mode - ptc->TC_CHANNEL[1].TC_RC = timer ; - ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ; - ptc->TC_CHANNEL[1].TC_CMR = 0x0009C000 ; // 0000 0000 0000 1001 1100 0000 0100 0000 - // MCK/2, set @ RA, Clear @ RC waveform - ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger) -} - -// Timer3 used for PPM_IN pulse width capture. Counter running at 16MHz / 8 = 2MHz -// equating to one count every half millisecond. (2 counts = 1ms). Control channel -// count delta values thus can range from about 1600 to 4400 counts (800us to 2200us), -// corresponding to a PPM signal in the range 0.8ms to 2.2ms (1.5ms at center). -// (The timer is free-running and is thus not reset to zero at each capture interval.) -// Timer 4 generates the 2MHz clock to clock Timer 3 - -extern "C" void TC3_IRQHandler() //capture ppm in at 2MHz -{ - uint16_t capture ; - static uint16_t lastCapt ; - - capture = TC1->TC_CHANNEL[0].TC_RA ; - (void) TC1->TC_CHANNEL[0].TC_SR ; // Acknowledgethe interrupt - - uint16_t val = (capture - lastCapt) / 2; - - // G: We process g_ppmIns immediately here, to make servo movement as smooth as possible - // while under trainee control - if (val>4000 && val < 16000) // G: Prioritize reset pulse. (Needed when less than 8 incoming pulses) - ppmInState = 1; // triggered - else - { - if (ppmInState && ppmInState<=8) - { - if (val>800 && val<2200) // if valid pulse-width range - { - g_ppmIns[ppmInState++ - 1] = - (int16_t)(val - 1500)*(g_eeGeneral.PPM_Multiplier+10)/10; //+-500 != 512, but close enough. - } - else - ppmInState = 0; // not triggered - } - } - - lastCapt = capture; -} - -void start_ppm_capture() -{ - start_timer4() ; - start_timer3() ; -} - -void end_ppm_capture() -{ - TC1->TC_CHANNEL[0].TC_IDR = TC_IDR0_LDRAS ; - NVIC_DisableIRQ(TC3_IRQn) ; -} - -extern "C" void TC2_IRQHandler() -{ - register uint32_t dummy; - static uint32_t pre_scale ; // Used to get 10 Hz counter - - /* Clear status bit to acknowledge interrupt */ - dummy = TC0->TC_CHANNEL[2].TC_SR; - (void) dummy ; // Discard value - prevents compiler warning - - HAPTIC_HEARTBEAT(); - AUDIO_HEARTBEAT(); - - if ( ++pre_scale >= 2 ) { - Tenms |= 1 ; // 10 mS has passed - if ( Buzzer_count ) { - if ( --Buzzer_count == 0 ) - buzzer_off() ; - } - pre_scale = 0 ; - per10ms(); - } -} - -// Settings for mode register ADC_MR -// USEQ off - silicon problem, doesn't work -// TRANSFER = 1 -// TRACKTIM = 4 (5 clock periods) -// ANACH = 0 -// SETTLING = 1 (not used if ANACH = 0) -// STARTUP = 1 (8 clock periods) -// PRESCAL = 3.6 MHz clock (between 1 and 20MHz) -// FREERUN = 0 -// FWUP = 0 -// SLEEP = 0 -// LOWRES = 0 -// TRGSEL = 0 -// TRGEN = 0 (software trigger only) -inline void init_adc() -{ - register Adc *padc ; - register uint32_t timer ; - - timer = ( Master_frequency / (3600000*2) ) << 8 ; - // Enable peripheral clock ADC = bit 29 - PMC->PMC_PCER0 |= 0x20000000L ; // Enable peripheral clock to ADC - padc = ADC ; - padc->ADC_MR = 0x14110000 | timer ; // 0001 0100 0001 0001 xxxx xxxx 0000 0000 - padc->ADC_ACR = ADC_ACR_TSON ; // Turn on temp sensor -#if defined(REVA) - padc->ADC_CHER = 0x0000E23E ; // channels 1,2,3,4,5,9,13,14,15 -#else - padc->ADC_CHER = 0x0000E33E ; // channels 1,2,3,4,5,8,9,13,14,15 -#endif - padc->ADC_CGR = 0 ; // Gain = 1, all channels - padc->ADC_COR = 0 ; // Single ended, 0 offset, all channels -} - -// PWM used for PPM generation, and LED Backlight -// Output pin PB5 not used, PA17 used as PWMH3 peripheral C -// PWM peripheral ID = 31 (0x80000000) -// Ensure PB5 is three state/input, used on REVB for MENU KEY - -// Configure PWM3 as PPM drive, -// PWM0 is LED backlight PWM on PWMH0 -// This is PC18 peripheral B, Also enable PC22 peripheral B, this is PPM-JACK (PWML3) -// -// REVB board: -// PWML2, output as peripheral C on PA16, is for HAPTIC -// For testing, just drive it out with PWM -// PWML1 for PPM2 output as peripheral B on PC15 -// For testing, just drive it out with PWM -void init_pwm() -{ - register Pwm *pwmptr ; - register uint32_t timer ; - - PMC->PMC_PCER0 |= ( 1 << ID_PWM ) ; // Enable peripheral clock to PWM - - MATRIX->CCFG_SYSIO |= 0x00000020L ; // Disable TDO let PB5 work! - - /* Configure PIO */ -#if defined(REVA) - register Pio *pioptr = PIOB ; - pioptr->PIO_PER = 0x00000020L ; // Enable bit B5 - pioptr->PIO_ODR = 0x00000020L ; // set as input -#else - configure_pins( PIO_PA16, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_C | PIN_PORTA | PIN_NO_PULLUP ) ; -#endif - - configure_pins( PIO_PC18, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; - -#if !defined(REVA) - configure_pins( PIO_PC15, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; - configure_pins( PIO_PC22, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ; -#endif - - // Configure clock - depends on MCK frequency - timer = Master_frequency / 2000000 ; - timer |= ( Master_frequency / ( 32* 10000 ) ) << 16 ; - timer &= 0x00FF00FF ; - - pwmptr = PWM ; - pwmptr->PWM_CLK = 0x05000000 | timer ; // MCK for DIVA, DIVA = 18 gives 0.5uS clock period @35MHz // MCK/32 / timer = 10000Hz for CLKB - - // PWM0 for LED backlight - pwmptr->PWM_CH_NUM[0].PWM_CMR = 0x0000000C ; // CLKB - pwmptr->PWM_CH_NUM[0].PWM_CPDR = 100 ; // Period - pwmptr->PWM_CH_NUM[0].PWM_CPDRUPD = 100 ; // Period - pwmptr->PWM_CH_NUM[0].PWM_CDTY = 40 ; // Duty - pwmptr->PWM_CH_NUM[0].PWM_CDTYUPD = 40 ; // Duty - pwmptr->PWM_ENA = PWM_ENA_CHID0 ; // Enable channel 0 - -#if !defined(REVA) - // PWM1 for PPM2 output 100Hz test - pwmptr->PWM_CH_NUM[1].PWM_CMR = 0x0000000C ; // CLKB - pwmptr->PWM_CH_NUM[1].PWM_CPDR = 100 ; // Period - pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = 100 ; // Period - pwmptr->PWM_CH_NUM[1].PWM_CDTY = 40 ; // Duty - pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = 40 ; // Duty - pwmptr->PWM_ENA = PWM_ENA_CHID1 ; // Enable channel 1 -#endif - -#if !defined(REVA) - // PWM2 for HAPTIC drive 100Hz test - pwmptr->PWM_CH_NUM[2].PWM_CMR = 0x0000000C ; // CLKB - pwmptr->PWM_CH_NUM[2].PWM_CPDR = 100 ; // Period - pwmptr->PWM_CH_NUM[2].PWM_CPDRUPD = 100 ; // Period - pwmptr->PWM_CH_NUM[2].PWM_CDTY = 40 ; // Duty - pwmptr->PWM_CH_NUM[2].PWM_CDTYUPD = 40 ; // Duty - pwmptr->PWM_OOV &= ~0x00040000 ; // Force low - pwmptr->PWM_OSS = 0x00040000 ; // Force low - // pwmptr->PWM_ENA = PWM_ENA_CHID2 ; // Enable channel 2 // TODO on REVA? -#endif -} - -// LCD i/o pins -// LCD_RES PC27 -// LCD_CS1 PC26 -// LCD_E PC12 -// LCD_RnW PC13 -// LCD_A0 PC15 -// LCD_D0 PC0 -// LCD_D1 PC7 -// LCD_D2 PC6 -// LCD_D3 PC5 -// LCD_D4 PC4 -// LCD_D5 PC3 -// LCD_D6 PC2 -// LCD_D7 PC1 - -#define LCD_DATA 0x000000FFL -#if defined(REVA) -#define LCD_A0 0x00008000L -#else -#define LCD_A0 0x00000080L -#endif -#define LCD_RnW 0x00002000L -#define LCD_E 0x00001000L -#define LCD_CS1 0x04000000L -#define LCD_RES 0x08000000L - -void configure_pins( uint32_t pins, uint16_t config ) -{ - register Pio *pioptr ; - - pioptr = PIOA + ( ( config & PIN_PORT_MASK ) >> 6) ; - if ( config & PIN_PULLUP ) - { - pioptr->PIO_PPDDR = pins ; - pioptr->PIO_PUER = pins ; - } - else - { - pioptr->PIO_PUDR = pins ; - } - - if ( config & PIN_PULLDOWN ) - { - pioptr->PIO_PUDR = pins ; - pioptr->PIO_PPDER = pins ; - } - else - { - pioptr->PIO_PPDDR = pins ; - } - - if ( config & PIN_HIGH ) - { - pioptr->PIO_SODR = pins ; - } - else - { - pioptr->PIO_CODR = pins ; - } - - if ( config & PIN_INPUT ) - { - pioptr->PIO_ODR = pins ; - } - else - { - pioptr->PIO_OER = pins ; - } - - if ( config & PIN_PERI_MASK_L ) - { - pioptr->PIO_ABCDSR[0] |= pins ; - } - else - { - pioptr->PIO_ABCDSR[0] &= ~pins ; - } - if ( config & PIN_PERI_MASK_H ) - { - pioptr->PIO_ABCDSR[1] |= pins ; - } - else - { - pioptr->PIO_ABCDSR[1] &= ~pins ; - } - - if ( config & PIN_ENABLE ) - { - pioptr->PIO_PER = pins ; - } - else - { - pioptr->PIO_PDR = pins ; - } -} - -void board_init() -{ - // register uint32_t goto_usb ; - register Pio *pioptr ; - // Debug variable - // uint32_t both_on ; - - MATRIX->CCFG_SYSIO |= 0x000000F0L ; // Disable syspins, enable B4,5,6,7 - - PMC->PMC_PCER0 = (1<PIO_PER = PIO_PA21 ; // Enable bit A21 (EXT3) - pioptr->PIO_OER = PIO_PA21 ; // Set bit A21 as output - pioptr->PIO_SODR = PIO_PA21 ; // Set bit A21 ON -#else - init_soft_power() ; -#endif - - // pioptr->PIO_PUER = 0x80000000 ; // Enable pullup on bit A31 (EXIT) - // pioptr->PIO_PER = 0x80000000 ; // Enable bit A31 - - pioptr = PIOC ; - pioptr->PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect) - // pioptr->PIO_OER = 0x80000000L ; // Set bit C31 as output - // pioptr->PIO_SODR = 0x80000000L ; // Set bit C31 - -#if defined(REVA) - // Configure RF_power (PC17) and PPM-jack-in (PC19), neither need pullups - pioptr->PIO_PER = 0x000A0000L ; // Enable bit C19, C17 - pioptr->PIO_ODR = 0x000A0000L ; // Set bits C19 and C17 as input -#endif - - config_free_pins() ; - - // Next section configures the key inputs on the LCD data -#if defined(REVA) - pioptr->PIO_PER = 0x0000003DL ; // Enable bits 2,3,4,5, 0 - pioptr->PIO_OER = PIO_PC0 ; // Set bit 0 output - pioptr->PIO_ODR = 0x0000003CL ; // Set bits 2, 3, 4, 5 input - pioptr->PIO_PUER = 0x0000003CL ; // Set bits 2, 3, 4, 5 with pullups -#else - pioptr->PIO_PER = 0x0000003BL ; // Enable bits 1,3,4,5, 0 - pioptr->PIO_OER = PIO_PC0 ; // Set bit 0 output - pioptr->PIO_ODR = 0x0000003AL ; // Set bits 1, 3, 4, 5 input - pioptr->PIO_PUER = 0x0000003AL ; // Set bits 1, 3, 4, 5 with pullups -#endif - - pioptr = PIOB ; -#if defined(REVA) - pioptr->PIO_PUER = PIO_PB6 ; // Enable pullup on bit B6 (MENU) - pioptr->PIO_PER = PIO_PB6 ; // Enable bit B6 -#else - pioptr->PIO_PUER = PIO_PB5 ; // Enable pullup on bit B5 (MENU) - pioptr->PIO_PER = PIO_PB5 ; // Enable bit B5 -#endif - - setup_switches() ; - - // Enable PCK2 on PB3, This is for testing of Timer 2 working - // It will be used as serial data to the Bluetooth module - pioptr->PIO_ABCDSR[0] |= PIO_PB3 ; // Peripheral B - pioptr->PIO_ABCDSR[1] &= ~PIO_PB3 ; // Peripheral B - pioptr->PIO_PDR = PIO_PB3 ; // Assign to peripheral - PMC->PMC_SCER |= 0x0400 ; // PCK2 enabled - PMC->PMC_PCK[2] = 2 ; // PCK2 is PLLA - - DEBUG_UART_Configure( 9600, Master_frequency ) ; - UART2_Configure( 9600, Master_frequency ) ; // Testing - UART3_Configure( 9600, Master_frequency ) ; // TODO not needed, done after ... - - start_timer2() ; - start_timer0() ; - init_adc() ; - init_pwm() ; - - __enable_irq() ; - - startSound() ; - - codecsInit(); - - eeprom_init(); - - init_SDcard(); - -} -#endif - -// keys: -// KEY_EXIT PA31 (PC24) -// KEY_MENU PB6 (PB5) -// KEY_DOWN LCD5 PC3 (PC5) -// KEY_UP LCD6 PC2 (PC1) -// KEY_RIGHT LCD4 PC4 (PC4) -// KEY_LEFT LCD3 PC5 (PC3) -// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU -// LCD pins 5 DOWN, 4 RIGHT, 3 LEFT, 1 UP -uint32_t read_keys() -{ - register uint32_t x; - register uint32_t y; - - x = PIOC->PIO_PDSR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () - x <<= 1; - - y = 0; - if (x & 0x00000020) - y |= 0x02 << KEY_PLUS; - if (x & 0x00000004) - y |= 0x02 << KEY_MENU; - if (x & 0x00000010) - y |= 0x02 << KEY_MINUS; - if (x & 0x00000040) - y |= 0x02 << KEY_PAGE; - if (x & 0x02000000) - y |= 0x02 << KEY_EXIT; - if (PIOB->PIO_PDSR & 0x000000020) - y |= 0x02 << KEY_ENTER; - - return y ; -} - -uint32_t read_trims() -{ - uint32_t trims; - uint32_t trima; - - trims = 0; - - trima = PIOA->PIO_PDSR; - -// TRIM_LH_DOWN PA7 (PA23) -#if defined(REVA) - if ( ( trima & 0x0080 ) == 0 ) -#else - if ((trima & 0x00800000) == 0) -#endif - { - trims |= 1; - } - -// TRIM_LV_DOWN PA27 (PA24) -#if defined(REVA) - if ( ( trima & 0x08000000 ) == 0 ) -#else - if ((trima & 0x01000000) == 0) -#endif - { - trims |= 4; - } - -// TRIM_RV_UP PA30 (PA1) -#if defined(REVA) - if ( ( trima & 0x40000000 ) == 0 ) -#else - if ((trima & 0x00000002) == 0) -#endif - { - trims |= 0x20; - } - -// TRIM_RH_DOWN PA29 (PA0) -#if defined(REVA) - if ( ( trima & 0x20000000 ) == 0 ) -#else - if ((trima & 0x00000001) == 0) -#endif - { - trims |= 0x40; - } - -// TRIM_LH_UP PB4 - if ((PIOB->PIO_PDSR & 0x10) == 0) { - trims |= 2; - } - - trima = PIOC->PIO_PDSR; -// TRIM_LV_UP PC28 - if ((trima & 0x10000000) == 0) { - trims |= 8; - } - -// TRIM_RV_DOWN PC10 - if ((trima & 0x00000400) == 0) { - trims |= 0x10; - } - -// TRIM_RH_UP PC9 - if ((trima & 0x00000200) == 0) { - trims |= 0x80; - } - - return trims; -} - -uint8_t keyDown() -{ - return ~read_keys() & 0x7E ; -} - -extern uint32_t keyState(EnumKeys enuk) -{ - register uint32_t c ; - - CPU_UINT xxx = 0; + register uint32_t xxx = 0; if (enuk < (int) DIM(keys)) return keys[enuk].state() ? 1 : 0; - c = PIOC->PIO_PDSR ; - - // printf("c=%x\n", c); fflush(stdout); - switch ((uint8_t) enuk) { case SW_SA0: - xxx = !(c & 0x80000000); + xxx = ~a & (1<<31); break; - case SW_SA2: - xxx = c & 0x80000000; + xxx = a & (1<<31); break; case SW_SB0: - xxx = !(c & 0x08000000) && !(c & 0x04000000); + xxx = !(a & ((1<<26) | (1<<27))); break; - case SW_SB1: - xxx = (c & 0x08000000) && !(c & 0x04000000); + xxx = (a & (1<<27)) && (~a & (1<<26)); break; - case SW_SB2: - xxx = !(c & 0x08000000) && (c & 0x04000000); + xxx = (~a & (1<<27)) && (a & (1<<26)); break; case SW_SC0: - xxx = !(c & 0x00800000) && !(c & 0x00400000); + xxx = !(a & ((1<<22) | (1<<23))); break; - case SW_SC1: - xxx = (c & 0x00800000) && !(c & 0x00400000); + xxx = (a & (1<<23)) && (~a & (1<<22)); break; - case SW_SC2: - xxx = !(c & 0x00800000) && (c & 0x00400000); + xxx = (~a & (1<<23)) && (a & (1<<22)); break; case SW_SD0: - xxx = !(c & 0x00200000) && !(c & 0x00100000); + xxx = !(a & ((1<<20) | (1<<21))); break; - case SW_SD1: - xxx = (c & 0x00200000) && !(c & 0x00100000); + xxx = (a & (1<<21)) && (~a & (1<<20)); break; - case SW_SD2: - xxx = !(c & 0x00200000) && (c & 0x00100000); + xxx = (~a & (1<<21)) && (a & (1<<20)); break; case SW_SE0: - xxx = !(c & 0x00080000) && !(c & 0x00040000); + xxx = !(a & ((1<<18) | (1<<19))); break; - case SW_SE1: - xxx = (c & 0x00080000) && !(c & 0x00040000); + xxx = (a & (1<<19)) && (~a & (1<<18)); break; - case SW_SE2: - xxx = !(c & 0x00080000) && (c & 0x00040000); + xxx = (~a & (1<<19)) && (a & (1<<18)); break; case SW_SF0: - xxx = !(c & 0x00020000) && !(c & 0x00010000); + xxx = !(a & ((1<<16) | (1<<17))); break; - case SW_SF1: - xxx = (c & 0x00020000) && !(c & 0x00010000); + xxx = (a & (1<<17)) && (~a & (1<<16)); break; - case SW_SF2: - xxx = !(c & 0x00020000) && (c & 0x00010000); + xxx = (~a & (1<<17)) && (a & (1<<16)); break; case SW_SG0: - xxx = !(c & 0x00008000) && !(c & 0x00004000); + xxx = !(a & ((1<<14) | (1<<15))); break; - case SW_SG1: - xxx = (c & 0x00008000) && !(c & 0x00004000); + xxx = (a & (1<<15)) && (~a & (1<<14)); break; - case SW_SG2: - xxx = !(c & 0x00008000) && (c & 0x00004000); + xxx = (~a & (1<<15)) && (a & (1<<14)); break; case SW_SH0: - xxx = !(c & 0x00002000); + xxx = ~a & (1<<13); break; - case SW_SH2: - xxx = c & 0x00002000; + xxx = a & (1<<13); break; default: @@ -911,243 +147,31 @@ extern uint32_t keyState(EnumKeys enuk) if (xxx) { return 1; } + return 0; } -uint16_t Analog_values[NUMBER_ANALOG] ; -uint8_t temperature = 0; // Raw temp reading -uint8_t maxTemperature = 0 ; // Raw temp reading - -// Read 8 (9 for REVB) ADC channels -// Documented bug, must do them 1 by 1 +// TODO change this function! void read_9_adc() { - register Adc *padc; - register uint32_t y; - register uint32_t x; - - padc = ADC; - y = padc->ADC_ISR; // Clear EOC flags - for (y = NUMBER_ANALOG+1; --y > 0;) { - padc->ADC_CR = 2; // Start conversion - x = 0; - while ((padc->ADC_ISR & 0x01000000) == 0) { - // wait for DRDY flag - if (++x > 1000000) { - break; // Software timeout - } - } - x = padc->ADC_LCDR; // Clear DRSY flag - } - // Next bit may be done using the PDC - Analog_values[0] = ADC->ADC_CDR1; - Analog_values[1] = ADC->ADC_CDR2; - Analog_values[2] = ADC->ADC_CDR3; - Analog_values[3] = ADC->ADC_CDR4; - Analog_values[4] = ADC->ADC_CDR5; - Analog_values[5] = ADC->ADC_CDR9; - Analog_values[6] = ADC->ADC_CDR13; - Analog_values[7] = ADC->ADC_CDR14; - -#if defined(REVA) - Analog_values[8] = ADC->ADC_CDR8 ; -#endif - - temperature = (((int32_t)temperature * 7) + ((((int32_t)ADC->ADC_CDR15 - 838) * 621) >> 11)) >> 3; // Filter it - if (get_tmr10ms() >= 100 && temperature > maxTemperature) { - maxTemperature = temperature; - } } -void readKeysAndTrims() +void start_ppm_capture() { - register uint32_t i; - -#if defined(ROTARY_ENCODERS) - keys[BTN_REa].input(!(PIOB->PIO_PDSR & 0x40), BTN_REa); -#endif - - uint8_t enuk = KEY_MENU; - uint8_t in = ~read_keys(); - for (i = 1; i < 7; i++) { - keys[enuk].input(in & (1 << i), (EnumKeys) enuk); - ++enuk; - } - - in = read_trims(); - - for (i = 1; i < 256; i <<= 1) { - keys[enuk].input(in & i, (EnumKeys) enuk); - ++enuk; - } -} - -#define RX_UART_BUFFER_SIZE 32 - -struct t_rxUartBuffer -{ - uint8_t fifo[RX_UART_BUFFER_SIZE] ; - uint8_t *outPtr ; -} ; - -struct t_rxUartBuffer TelemetryInBuffer[2] ; -uint32_t TelemetryActiveBuffer ; - -void startPdcUsartReceive() -{ - register Usart *pUsart = SECOND_USART; - - TelemetryInBuffer[0].outPtr = TelemetryInBuffer[0].fifo ; - TelemetryInBuffer[1].outPtr = TelemetryInBuffer[1].fifo ; -#ifndef SIMU - // TODO because of the 64bits cast ... - pUsart->US_RPR = (uint32_t)TelemetryInBuffer[0].fifo ; - pUsart->US_RNPR = (uint32_t)TelemetryInBuffer[1].fifo ; -#endif - pUsart->US_RCR = RX_UART_BUFFER_SIZE ; - pUsart->US_RNCR = RX_UART_BUFFER_SIZE ; - pUsart->US_PTCR = US_PTCR_RXTEN ; - TelemetryActiveBuffer = 0 ; -} - -void endPdcUsartReceive() -{ - register Usart *pUsart = SECOND_USART; - - pUsart->US_PTCR = US_PTCR_RXTDIS ; -} - -void rxPdcUsart( void (*pChProcess)(uint8_t x) ) -{ -#if !defined(SIMU) - register Usart *pUsart = SECOND_USART; - uint8_t *ptr ; - uint8_t *endPtr ; -// uint32_t bufIndex ; -// uint32_t i ; - uint32_t j ; - - //Find out where the DMA has got to - __disable_irq() ; - pUsart->US_PTCR = US_PTCR_RXTDIS ; // Freeze DMA - ptr = (uint8_t *)pUsart->US_RPR ; - j = pUsart->US_RNCR ; - pUsart->US_PTCR = US_PTCR_RXTEN ; // DMA active again - __enable_irq() ; - - endPtr = ptr - 1 ; - ptr = TelemetryInBuffer[TelemetryActiveBuffer].outPtr ; - if ( j == 0 ) // First buf is full - { - endPtr = &TelemetryInBuffer[TelemetryActiveBuffer].fifo[RX_UART_BUFFER_SIZE-1] ; // last byte - } - while ( ptr <= endPtr ) - { - (*pChProcess)(*ptr++) ; - } - TelemetryInBuffer[TelemetryActiveBuffer].outPtr = ptr ; - if ( j == 0 ) // First buf is full - { - TelemetryInBuffer[TelemetryActiveBuffer].outPtr = TelemetryInBuffer[TelemetryActiveBuffer].fifo ; - pUsart->US_RNPR = (uint32_t)TelemetryInBuffer[TelemetryActiveBuffer].fifo ; - pUsart->US_RNCR = RX_UART_BUFFER_SIZE ; - TelemetryActiveBuffer ^= 1 ; // Other buffer is active - rxPdcUsart( pChProcess ) ; // Get any chars from second buffer - } -#endif -} - -uint32_t txPdcUsart( uint8_t *buffer, uint32_t size ) -{ - register Usart *pUsart = SECOND_USART; - - if ( pUsart->US_TNCR == 0 ) - { -#ifndef SIMU - pUsart->US_TNPR = (uint32_t)buffer ; -#endif - pUsart->US_TNCR = size ; - pUsart->US_PTCR = US_PTCR_TXTEN ; - return 1 ; - } - return 0 ; -} - -uint32_t txPdcPending() -{ - register Usart *pUsart = SECOND_USART; - uint32_t x ; - - __disable_irq() ; - pUsart->US_PTCR = US_PTCR_TXTDIS ; // Freeze DMA - x = pUsart->US_TNCR ; // Total - x += pUsart->US_TCR ; // Still to send - pUsart->US_PTCR = US_PTCR_TXTEN ; // DMA active again - __enable_irq() ; - - return x ; -} - -void end_bt_tx_interrupt() -{ - Uart *pUart = BT_USART ; - pUart->UART_IDR = UART_IDR_TXBUFE ; - NVIC_DisableIRQ(UART1_IRQn) ; } void usbBootloader() { - // This might be replaced by a software reset - // Any interrupts that have been enabled must be disabled here - // BEFORE calling sam_boot() - endPdcUsartReceive() ; // Terminate any serial reception - end_bt_tx_interrupt() ; - end_ppm_capture() ; - end_spi() ; - end_sound() ; - - TC0->TC_CHANNEL[2].TC_IDR = TC_IDR0_CPCS ; - TC0->TC_CHANNEL[0].TC_CCR = TC_CCR0_CLKDIS ; - TC0->TC_CHANNEL[1].TC_CCR = TC_CCR0_CLKDIS ; - TC0->TC_CHANNEL[2].TC_CCR = TC_CCR0_CLKDIS ; - TC1->TC_CHANNEL[0].TC_CCR = TC_CCR0_CLKDIS ; - TC1->TC_CHANNEL[1].TC_CCR = TC_CCR0_CLKDIS ; - TC1->TC_CHANNEL[2].TC_CCR = TC_CCR0_CLKDIS ; - PWM->PWM_DIS = PWM_DIS_CHID0 | PWM_DIS_CHID1 | PWM_DIS_CHID2 | PWM_DIS_CHID3 ; // Disable all - NVIC_DisableIRQ(TC2_IRQn) ; - - disable_main_ppm() ; - // PWM->PWM_IDR1 = PWM_IDR1_CHID3 ; - // NVIC_DisableIRQ(PWM_IRQn) ; - disable_ssc() ; - - DEBUG_UART_Stop(); - UART3_Stop(); - - sam_boot() ; } -#if !defined(REVA) -uint16_t getCurrent() +void usbMassStorage() { - static uint16_t Current ; - static uint32_t Current_sum ; - static uint8_t Current_count ; +} - Current_sum += anaIn(NUMBER_ANALOG-1); - if (++Current_count >= 50) { - Current = Current_sum / 5 ; - Current_sum = 0 ; - Current_count = 0 ; - } - - uint32_t current_scale = 488 + g_eeGeneral.currentCalib ; - return (current_scale * Current) / 8192; +#if !defined(SIMU) +void board_init() +{ } #endif -uint8_t getTemperature() -{ - return temperature + g_eeGeneral.temperatureCalib; -} diff --git a/src/board_x9d.h b/src/board_x9d.h index 9e7196249..a1c510aa9 100644 --- a/src/board_x9d.h +++ b/src/board_x9d.h @@ -35,15 +35,22 @@ #define board_sky9x_h #include -#include "sky9x/board.h" -#include "sky9x/sound_driver.h" -#include "sky9x/haptic_driver.h" -#include "sky9x/debug.h" -#if defined(BLUETOOTH) -#include "sky9x/bluetooth.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx.h" + +#include "x9d/hal.h" +#include "x9d/aspi.h" + +#include "x9d/audio_driver.h" + +// TODO elsewhere +#if !defined(SIMU) +#define SD_IS_HC() (1) #endif + extern "C" { extern void init_SDcard(); extern void sdInit(); @@ -53,26 +60,9 @@ extern void sdInit(); void usbMassStorage(); -#define PIN_ENABLE 0x001 -#define PIN_PERIPHERAL 0x000 -#define PIN_INPUT 0x002 -#define PIN_OUTPUT 0x000 -#define PIN_PULLUP 0x004 -#define PIN_NO_PULLUP 0x000 -#define PIN_PULLDOWN 0x008 -#define PIN_NO_PULLDOWN 0x000 -#define PIN_PERI_MASK_L 0x010 -#define PIN_PERI_MASK_H 0x020 -#define PIN_PER_A 0x000 -#define PIN_PER_B 0x010 -#define PIN_PER_C 0x020 -#define PIN_PER_D 0x030 -#define PIN_PORT_MASK 0x0C0 -#define PIN_PORTA 0x000 -#define PIN_PORTB 0x040 -#define PIN_PORTC 0x080 -#define PIN_LOW 0x000 -#define PIN_HIGH 0x100 +void setVolume( register uint8_t volume ); +#define JACK_PPM_OUT() +#define JACK_PPM_IN() void configure_pins( uint32_t pins, uint16_t config ); uint16_t getCurrent(); @@ -81,32 +71,39 @@ extern uint8_t temperature ; // Raw temp reading extern uint8_t maxTemperature ; // Raw temp reading uint8_t getTemperature(); +extern int32_t Card_state; +extern volatile uint32_t Card_initialized; +#define SD_ST_DATA 9 +#define SD_ST_MOUNTED 10 + +#define SD_GET_SIZE_MB() (0) +#define SD_GET_BLOCKNR() (0) +#define SD_GET_SPEED() (0) + +void soft_power_off(); + #define strcpy_P strcpy #define strcat_P strcat -extern uint32_t read_keys(); -#define KEYS_PRESSED() (~read_keys()) +extern uint32_t readKeys(); +#define KEYS_PRESSED() (~readKeys()) #define DBLKEYS_PRESSED_RGT_LFT(i) ((in & (0x20 + 0x40)) == (0x20 + 0x40)) #define DBLKEYS_PRESSED_UP_DWN(i) ((in & (0x10 + 0x08)) == (0x10 + 0x08)) #define DBLKEYS_PRESSED_RGT_UP(i) ((in & (0x20 + 0x10)) == (0x20 + 0x10)) #define DBLKEYS_PRESSED_LFT_DWN(i) ((in & (0x40 + 0x08)) == (0x40 + 0x08)) -#if !defined(REVA) -extern uint16_t Current_analogue; -extern uint16_t Current_max; -extern uint32_t Current_accumulator; -extern uint32_t Current_used; extern uint16_t sessionTimer; + +#define BOOTLOADER_REQUEST() (0/*usbPlugged()*/) + +#define SLAVE_MODE() (0/*check_soft_power() == e_power_trainer*/) + +#if !defined(SIMU) +#define wdt_disable() +#define wdt_enable(x) +#define wdt_reset() #endif -#if defined(REVC) -#define BOOTLOADER_REQUEST() (usbPlugged()) -#else -#define BOOTLOADER_REQUEST() (check_soft_power() == e_power_usb) -#endif - -#define SLAVE_MODE() (check_soft_power() == e_power_trainer) -#define JACK_PPM_OUT() PIOC->PIO_PDR = PIO_PC22 -#define JACK_PPM_IN() PIOC->PIO_PER = PIO_PC22 +#define setBacklight(xx) #endif diff --git a/src/eeprom_arm.cpp b/src/eeprom_arm.cpp index a518453c9..3401bfe1c 100644 --- a/src/eeprom_arm.cpp +++ b/src/eeprom_arm.cpp @@ -1,7 +1,24 @@ /* - * Author - Erez Raviv + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer * - * Based on th9x -> http://code.google.com/p/th9x/ + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -19,7 +36,7 @@ #include "inttypes.h" #include "string.h" -volatile uint32_t Spi_complete ; +volatile uint32_t Spi_complete; // TODO in the driver ? uint8_t s_eeDirtyMsk; uint16_t s_eeDirtyTime10ms; @@ -40,10 +57,10 @@ uint16_t s_eeDirtyTime10ms; // These may not be needed, or might just be smaller +// TODO in the driver ? uint8_t Spi_tx_buf[24] ; uint8_t Spi_rx_buf[24] ; - struct t_file_entry File_system[MAX_MODELS+1] ; char ModelNames[MAX_MODELS][sizeof(g_model.name)] ; // Allow for general @@ -60,6 +77,8 @@ uint32_t Eeprom32_data_size ; #define EE_NOWAIT 1 +void init_spi(); + void eeDirty(uint8_t msk) { s_eeDirtyMsk |= msk; @@ -155,113 +174,6 @@ void eeSwapModels(uint8_t id1, uint8_t id2) eeWaitFinished(); } -uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count ) -{ -#ifndef SIMU - - register Spi *spiptr ; - register uint32_t condition ; - static uint8_t discard_rx_command[4] ; - -// PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI - - Spi_complete = 0 ; - if ( comlen > 4 ) - { - Spi_complete = 1 ; - return 0x4FFFF ; - } - condition = SPI_SR_TXEMPTY ; - spiptr = SPI ; - spiptr->SPI_CR = 1 ; // Enable - (void) spiptr->SPI_RDR ; // Dump any rx data - (void) spiptr->SPI_SR ; // Clear error flags - spiptr->SPI_RPR = (uint32_t)discard_rx_command ; - spiptr->SPI_RCR = comlen ; - if ( rx ) - { - spiptr->SPI_RNPR = (uint32_t)rx ; - spiptr->SPI_RNCR = count ; - condition = SPI_SR_RXBUFF ; - } - spiptr->SPI_TPR = (uint32_t)command ; - spiptr->SPI_TCR = comlen ; - if ( tx ) - { - spiptr->SPI_TNPR = (uint32_t)tx ; - } - else - { - spiptr->SPI_TNPR = (uint32_t)rx ; - } - spiptr->SPI_TNCR = count ; - - spiptr->SPI_PTCR = SPI_PTCR_RXTEN | SPI_PTCR_TXTEN ; // Start transfers - - // Wait for things to get started, avoids early interrupt - for ( count = 0 ; count < 1000 ; count += 1 ) - { - if ( ( spiptr->SPI_SR & SPI_SR_TXEMPTY ) == 0 ) - { - break ; - } - } - spiptr->SPI_IER = condition ; - -#endif - - return 0 ; -} - -uint32_t eeprom_write_one( uint8_t byte, uint8_t count ) -{ -#ifndef SIMU - register Spi *spiptr; - register uint32_t result; - - spiptr = SPI; - spiptr->SPI_CR = 1; // Enable - (void) spiptr->SPI_RDR; // Dump any rx data - - spiptr->SPI_TDR = byte; - - result = 0; - while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { - // wait for received - if (++result > 10000) { - break; - } - } - if (count == 0) { - spiptr->SPI_CR = 2; // Disable - return spiptr->SPI_RDR; - } - (void) spiptr->SPI_RDR; // Dump the rx data - spiptr->SPI_TDR = 0; - result = 0; - while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { - // wait for received - if (++result > 10000) { - break; - } - } - spiptr->SPI_CR = 2; // Disable - return spiptr->SPI_RDR ; -#else - return !Spi_complete; -#endif -} - -void eeprom_write_enable() -{ - eeprom_write_one( 6, 0 ) ; -} - -uint32_t eeprom_read_status() -{ - return eeprom_write_one( 5, 1 ) ; -} - // Read eeprom data starting at random address void read32_eeprom_data(uint32_t eeAddress, register uint8_t *buffer, uint32_t size, uint32_t immediate) { @@ -470,7 +382,7 @@ void eeLoadModel(uint8_t id) memset(&g_model, 0, sizeof(g_model)); -#ifdef SIMU +#if defined(SIMU) if (size > 0 && size != sizeof(g_model)) { printf("Model data read=%d bytes vs %d bytes\n", size, (int)sizeof(ModelData)); } @@ -567,125 +479,6 @@ void eeReadAll() stickMode = g_eeGeneral.stickMode; // TODO common! } -uint32_t spi_operation( register uint8_t *tx, register uint8_t *rx, register uint32_t count ) -{ - register Spi *spiptr; - register uint32_t result; - -// PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI - - result = 0; - spiptr = SPI; - spiptr->SPI_CR = 1; // Enable - (void) spiptr->SPI_RDR; // Dump any rx data - while (count) { - result = 0; - while ((spiptr->SPI_SR & SPI_SR_TXEMPTY) == 0) { - // wait - if (++result > 10000) { - result = 0xFFFF; - break; - } - } - if (result > 10000) { - break; - } -// if ( count == 1 ) -// { -// spiptr->SPI_CR = SPI_CR_LASTXFER ; // LastXfer bit -// } - spiptr->SPI_TDR = *tx++; - result = 0; - while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { - // wait for received - if (++result > 10000) { - result = 0x2FFFF; - break; - } - } - if (result > 10000) { - break; - } - *rx++ = spiptr->SPI_RDR; - count -= 1; - } - if (result <= 10000) { - result = 0; - } - spiptr->SPI_CR = 2; // Disable - -// Power save -// PMC->PMC_PCER0 &= ~0x00200000L ; // Disable peripheral clock to SPI - - return result ; -} - -// SPI i/f to EEPROM (4Mb) -// Peripheral ID 21 (0x00200000) -// Connections: -// SS PA11 (peripheral A) -// MISO PA12 (peripheral A) -// MOSI PA13 (peripheral A) -// SCK PA14 (peripheral A) -// Set clock to 3 MHz, AT25 device is rated to 70MHz, 18MHz would be better -void init_spi() -{ - register Spi *spiptr ; - register uint32_t timer ; - register uint8_t *p ; - uint8_t spi_buf[4] ; - - PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI - /* Configure PIO */ - configure_pins( 0x00007800, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ; - - spiptr = SPI ; - timer = ( Master_frequency / 3000000 ) << 8 ; // Baud rate 3Mb/s - spiptr->SPI_MR = 0x14000011 ; // 0001 0100 0000 0000 0000 0000 0001 0001 Master - spiptr->SPI_CSR[0] = 0x01180009 | timer ; // 0000 0001 0001 1000 xxxx xxxx 0000 1001 - NVIC_EnableIRQ(SPI_IRQn) ; - - p = spi_buf ; - -// *p = 0x39 ; // Unprotect sector command -// *(p+1) = 0 ; -// *(p+2) = 0 ; -// *(p+3) = 0 ; // 3 bytes address - -// spi_operation( p, spi_buf, 4 ) ; - - eeprom_write_enable() ; - - *p = 1 ; // Write status register command - *(p+1) = 0 ; - spi_operation( p, spi_buf, 2 ) ; -} - -#ifndef SIMU -extern "C" void SPI_IRQHandler() -{ - register Spi *spiptr ; - - spiptr = SPI ; - SPI->SPI_IDR = 0x07FF ; // All interrupts off - spiptr->SPI_CR = 2 ; // Disable - (void) spiptr->SPI_RDR ; // Dump any rx data - (void) spiptr->SPI_SR ; // Clear error flags - spiptr->SPI_PTCR = SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS ; // Stop tramsfers - Spi_complete = 1 ; // Indicate completion - -// Power save -// PMC->PMC_PCER0 &= ~0x00200000L ; // Disable peripheral clock to SPI -} -#endif - -void end_spi() -{ - SPI->SPI_CR = 2 ; // Disable - SPI->SPI_IDR = 0x07FF ; // All interrupts off - NVIC_DisableIRQ(SPI_IRQn) ; -} - void eeWaitFinished() { while (Eeprom32_process_state != E32_IDLE) { @@ -901,27 +694,12 @@ void ee32_read_model_names() void eeprom_init() { #ifndef SIMU - init_spi() ; + init_spi(); #endif fill_file_index() ; Eeprom32_process_state = E32_IDLE ; } -uint32_t unprotect_eeprom() -{ - register uint8_t *p; - - eeprom_write_enable(); - - p = Spi_tx_buf; - *p = 0x39; // Unprotect sector command - *(p + 1) = 0; - *(p + 2) = 0; - *(p + 3) = 0; // 3 bytes address - - return spi_operation( p, Spi_rx_buf, 4 ) ; -} - #if defined(SDCARD) const pm_char * eeBackupModel(uint8_t i_fileSrc) { diff --git a/src/eeprom_arm.h b/src/eeprom_arm.h index 06a203170..e871b7c52 100644 --- a/src/eeprom_arm.h +++ b/src/eeprom_arm.h @@ -83,7 +83,10 @@ extern ModelData g_model; extern uint8_t Spi_tx_buf[] ; extern uint8_t Spi_rx_buf[] ; +void eeprom_write_enable(); +uint32_t eeprom_read_status(); void read32_eeprom_data(uint32_t eeAddress, register uint8_t *buffer, uint32_t size, uint32_t immediate=0); +uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count ); #if defined(SDCARD) const pm_char * eeBackupModel(uint8_t i_fileSrc); diff --git a/src/frsky.cpp b/src/frsky.cpp index 4a363a2fe..91daee8a2 100644 --- a/src/frsky.cpp +++ b/src/frsky.cpp @@ -577,7 +577,9 @@ ISR(USART0_RX_vect) #if defined(CPUARM) void frskyTransmitBuffer( uint32_t size ) { +#if defined(PCBSKY9X) txPdcUsart( frskyTxBuffer, size ) ; +#endif } #else void frskyTransmitBuffer() @@ -607,8 +609,10 @@ void frskyPushValue(uint8_t *&ptr, uint8_t value) inline void FRSKY10mspoll(void) { +#if defined(PCBSKY9X) if (txPdcPending()) return; // we only have one buffer. If it's in use, then we can't send yet. +#endif uint8_t *ptr = &frskyTxBuffer[0]; @@ -702,7 +706,7 @@ inline void FRSKY10mspoll(void) NOINLINE void check_frsky() { -#if defined(CPUARM) +#if defined(PCBSKY9X) rxPdcUsart(processSerialData); // Receive serial data here #endif @@ -869,7 +873,9 @@ void FRSKY_Init(void) // clear frsky variables resetTelemetry(); -#if defined(CPUARM) +#if defined(PCBX9D) + // TODO +#elif defined(PCBSKY9X) startPdcUsartReceive() ; #elif !defined(SIMU) diff --git a/src/lcd.h b/src/lcd.h index 7e9fb4bdc..be62c97da 100644 --- a/src/lcd.h +++ b/src/lcd.h @@ -34,7 +34,13 @@ #ifndef lcd_h #define lcd_h -#if defined(LCD212) +#if defined(LCD260) +#define DISPLAY_W 260 +#define DISPLAY_H 75 +#define xcoord_t uint16_t +#define CENTER "\015" +#define CENTER_OFS (7*FW-FW/2) +#elif defined(LCD212) #define DISPLAY_W 212 #define DISPLAY_H 64 #define xcoord_t uint16_t diff --git a/src/main_views.cpp b/src/main_views.cpp index 6781cbbbd..bb101bd33 100644 --- a/src/main_views.cpp +++ b/src/main_views.cpp @@ -219,9 +219,11 @@ void displayVoltage() if (g_vbat100mV > g_eeGeneral.vBatWarn && g_eeGeneral.temperatureWarn && getTemperature() >= g_eeGeneral.temperatureWarn) { putsTelemetryValue(6*FW-1, 3*FH, getTemperature(), UNIT_DEGREES, BLINK|INVERS|DBLSIZE); } +#if defined(PCBSKY9X) else if (g_vbat100mV > g_eeGeneral.vBatWarn && g_eeGeneral.mAhWarn && (g_eeGeneral.mAhUsed + Current_used * (488 + g_eeGeneral.currentCalib)/8192/36) / 500 >= g_eeGeneral.mAhWarn) { putsTelemetryValue(7*FW-1, 3*FH, (g_eeGeneral.mAhUsed + Current_used*(488 + g_eeGeneral.currentCalib)/8192/36)/10, UNIT_MAH, BLINK|INVERS|DBLSIZE); } +#endif else { LcdFlags att = (g_vbat100mV <= g_eeGeneral.vBatWarn ? BLINK|INVERS : 0) | MIDSIZE; putsVBat(VBATT_X-1, VBATT_Y, att|NO_UNIT); diff --git a/src/open9x.cpp b/src/open9x.cpp index 6f5d3603b..e59f3090d 100644 --- a/src/open9x.cpp +++ b/src/open9x.cpp @@ -243,7 +243,7 @@ void per10ms() /* Update global Date/Time every 100 per10ms cycles */ if (++g_ms100 == 100) { g_rtcTime++; // inc global unix timestamp one second -#if defined(CPUARM) +#if defined(PCBSKY9X) if (g_rtcTime < 60 || rtc_count<5) { rtc_init(); rtc_count++; @@ -1496,15 +1496,15 @@ uint8_t checkTrim(uint8_t event) #endif } -#if defined(CPUARM) && !defined(REVA) +#if defined(PCBSKY9X) && !defined(REVA) uint16_t Current_analogue; uint16_t Current_max; uint32_t Current_accumulator; uint32_t Current_used; +#endif + +#if defined(CPUARM) && !defined(REVA) uint16_t sessionTimer; -#define NUMBER_ANALOG 9 -#else -#define NUMBER_ANALOG 8 #endif #if !defined(SIMU) @@ -1535,13 +1535,15 @@ uint16_t anaIn(uint8_t chan) // ana-in: 3 1 2 0 4 5 6 7 //static pm_char crossAna[] PROGMEM ={4,2,3,1,5,6,7,0}; // wenn schon Tabelle, dann muss sich auch lohnen // Google Translate (German): // if table already, then it must also be worthwhile -#if defined(CPUARM) - static const uint8_t crossAna[]={1,5,7,0,4,6,2,3,8}; -#if !defined(REVA) + +#if defined(PCBSKY9X) && !defined(REVA) if (chan == 8) { return Current_analogue ; } #endif + +#if defined(CPUARM) + static const uint8_t crossAna[]={1,5,7,0,4,6,2,3}; #else static const pm_char crossAna[] PROGMEM ={3,1,2,0,4,5,6,7}; #endif @@ -1558,6 +1560,7 @@ void getADC() uint16_t temp[NUMBER_ANALOG] = { 0 }; for( y = 0; y < 4; y += 1 ) { + // TODO change this function! read_9_adc(); for( x = 0; x < NUMBER_ANALOG; x += 1 ) { @@ -1956,7 +1959,8 @@ void evalFunctions() { MASK_FUNC_TYPE newActiveFunctions = 0; -#if defined(ROTARY_ENCODERS) && defined(GVARS) +#if defined(ROTARY_ENCODERS) && defined(GVARS) && !defined(PCBX9D) + // TODO modify the PCBX9D ifdef static rotenc_t rePreviousValues[ROTARY_ENCODERS]; #endif @@ -2131,7 +2135,8 @@ void evalFunctions() if (FSW_PARAM(sd) >= MIXSRC_TrimRud-1 && FSW_PARAM(sd) <= MIXSRC_TrimAil-1) { trimGvar[FSW_PARAM(sd)-MIXSRC_TrimRud+1] = sd->func-FUNC_ADJUST_GV1; } -#if defined(ROTARY_ENCODERS) +#if defined(ROTARY_ENCODERS) && !defined(PCBX9D) + // TODO modify these ifdef else if (FSW_PARAM(sd) >= MIXSRC_REa-1 && FSW_PARAM(sd) < MIXSRC_TrimRud-1) { int8_t scroll = rePreviousValues[FSW_PARAM(sd)-MIXSRC_REa+1] - (g_rotenc[FSW_PARAM(sd)-MIXSRC_REa+1] / ROTARY_ENCODER_GRANULARITY); if (scroll) { @@ -2180,7 +2185,8 @@ void evalFunctions() activeFunctions = newActiveFunctions; -#if defined(ROTARY_ENCODERS) && defined(GVARS) +#if defined(ROTARY_ENCODERS) && defined(GVARS) && !defined(PCBX9D) + // TODO review #ifdef PCBX9D for (uint8_t i=0; i> 5 ; if (Current_analogue > Current_max) Current_max = Current_analogue ; @@ -2537,13 +2543,13 @@ FORCEINLINE void doMixerCalculations() static uint16_t fp_act[MAX_PHASES] = {0}; static uint16_t delta = 0; static ACTIVE_PHASES_TYPE s_fade_flight_phases = 0; - static uint8_t s_last_phase = 255; + static uint8_t s_last_phase = 255; // TODO reinit everything here when the model changes, no??? uint8_t phase = getFlightPhase(); int32_t weight = 0; if (s_last_phase != phase) { - // PLAY_PHASE_OFF(s_last_phase); - // PLAY_PHASE_ON(phase); + if (s_last_phase != 255) PLAY_PHASE_OFF(s_last_phase); + PLAY_PHASE_ON(phase); if (s_last_phase == 255) { fp_act[phase] = MAX_ACT; @@ -2849,7 +2855,9 @@ void perMain() #if defined(CPUARM) if (!Tenms) return; Tenms = 0 ; +#endif +#if defined(PCBSKY9X) Current_accumulator += Current_analogue ; static uint32_t OneSecTimer; if (++OneSecTimer >= 100) { @@ -2920,7 +2928,7 @@ void perMain() if (counter-- == 0) { counter = 10; #if defined(PCBX9D) - int32_t instant_vbat = anaIn(8); + int32_t instant_vbat = anaIn(7); instant_vbat = ( instant_vbat + instant_vbat*(g_eeGeneral.vBatCalib)/128 ) * 4191 ; instant_vbat /= 55296 ; #elif defined(PCBSKY9X) @@ -2956,6 +2964,8 @@ void perMain() else if (g_eeGeneral.temperatureWarn && getTemperature() >= g_eeGeneral.temperatureWarn) { AUDIO_TX_TEMP_HIGH(); } +#endif +#if defined(PCBSKY9X) else if (g_eeGeneral.mAhWarn && (g_eeGeneral.mAhUsed + Current_used * (488 + g_eeGeneral.currentCalib)/8192/36) / 500 >= g_eeGeneral.mAhWarn) { AUDIO_TX_MAH_HIGH(); } @@ -3348,7 +3358,7 @@ inline void open9xInit(OPEN9X_INIT_ARGS) #if defined(CPUARM) setVolume(g_eeGeneral.speakerVolume); - PWM->PWM_CH_NUM[0].PWM_CDTYUPD = g_eeGeneral.backlightBright; + setBacklight(g_eeGeneral.backlightBright); #elif defined(VOICE) SET_VOLUME(g_eeGeneral.speakerVolume+7); #endif @@ -3473,11 +3483,15 @@ void menusTask(void * pdata) saveTimers(); +#if defined(PCBSKY9X) uint32_t mAhUsed = g_eeGeneral.mAhUsed + Current_used * (488 + g_eeGeneral.currentCalib) / 8192 / 36; if (g_eeGeneral.mAhUsed != mAhUsed) g_eeGeneral.mAhUsed = mAhUsed; +#endif + if (sessionTimer > 0) g_eeGeneral.globalTimer += sessionTimer; + g_eeGeneral.unexpectedShutdown = 0; eeDirty(EE_GENERAL); diff --git a/src/open9x.h b/src/open9x.h index 3b929f008..a85caaea7 100644 --- a/src/open9x.h +++ b/src/open9x.h @@ -178,9 +178,6 @@ typedef const int8_t pm_int8_t; #define pgm_read_adr(x) *(x) #define cli() #define sei() -#define wdt_disable() -#define wdt_enable(x) WDT->WDT_MR = 0x3FFF217F; -#define wdt_reset() WDT->WDT_CR = 0xA5000001 extern void board_init(); #else #include @@ -768,17 +765,19 @@ enum PerOutMode { e_perout_mode_noinput = e_perout_mode_notrainer+e_perout_mode_notrims+e_perout_mode_nosticks }; -#ifdef SIMU +#if defined(SIMU) #ifndef FORCEINLINE #define FORCEINLINE #endif #ifndef NOINLINE #define NOINLINE #endif +#define CONVERT_PTR(x) ((uint32_t)(uint64_t)(x)) #else #define FORCEINLINE inline __attribute__ ((always_inline)) #define NOINLINE __attribute__ ((noinline)) #define SIMU_SLEEP(x) +#define CONVERT_PTR(x) ((uint32_t)(x)) #endif // Fiddle to force compiler to use a pointer @@ -877,7 +876,9 @@ extern uint8_t s_traceWr; extern int8_t s_traceCnt; #endif -#if defined(CPUARM) +#if defined(PCBX9D) +static inline uint16_t getTmr2MHz() { return 0; } +#elif defined(PCBSKY9X) static inline uint16_t getTmr2MHz() { return TC1->TC_CHANNEL[0].TC_CV; } #else uint16_t getTmr16KHz(); @@ -920,16 +921,23 @@ void getADC(); extern void backlightOn(); -#if defined (CPUARM) +#if defined(PCBSKY9X) && !defined(REVA) +#define NUMBER_ANALOG 9 +#else +#define NUMBER_ANALOG 8 +#endif + +#if defined(PCBSKY9X) +// TODO remove +void read_9_adc(void); +#endif + +#if defined(PCBX9D) +#define __BACKLIGHT_ON +#define __BACKLIGHT_OFF +#elif defined (PCBSKY9X) #define __BACKLIGHT_ON (PWM->PWM_CH_NUM[0].PWM_CDTY = g_eeGeneral.backlightBright) #define __BACKLIGHT_OFF (PWM->PWM_CH_NUM[0].PWM_CDTY = 100) -#if defined(REVA) -#define NUMBER_ANALOG 8 -#else -#define NUMBER_ANALOG 9 -#endif -extern uint16_t Analog_values[NUMBER_ANALOG] ; -void read_9_adc(void ) ; #elif defined (PCBGRUVIN9X) #define SPEAKER_ON TCCR0A |= (1 << COM0A0) #define SPEAKER_OFF TCCR0A &= ~(1 << COM0A0) @@ -1348,11 +1356,10 @@ void putsTelemetryValue(uint8_t x, uint8_t y, int16_t val, uint8_t unit, uint8_t #if defined(CPUARM) uint8_t zlen(const char *str, uint8_t size); char * strcat_zchar(char * dest, char * name, uint8_t size, const char *defaultName, uint8_t defaultNameSize, uint8_t defaultIdx); -#define strcat_modelname(dest, idx) strcat_zchar(dest, ModelNames[idx], sizeof(g_model.name), STR_MODEL, PSIZE(TR_MODEL), idx+1) -#define strcat_phasename_default(dest, idx) strcat_zchar(dest, NULL, 0, STR_FP, PSIZE(TR_FP), idx+1) -#define strcat_phasename_nodefault(dest, idx) strcat_zchar(dest, g_model.phaseData[idx].name, sizeof(PhaseData), NULL, 0, 0) -#define strcat_mixername_default(dest, idx) strcat_zchar(dest, NULL, 0, STR_MIX, PSIZE(TR_MIX), idx+1) -#define strcat_mixername_nodefault(dest, idx) strcat_zchar(dest, g_model.mixData[idx].name, sizeof(MixData), NULL, 0, 0) +#define strcat_modelname(dest, idx) strcat_zchar(dest, ModelNames[idx], LEN_MODEL_NAME, STR_MODEL, PSIZE(TR_MODEL), idx+1) +#define strcat_phasename_default(dest, idx) strcat_zchar(dest, NULL, 0, STR_FP, PSIZE(TR_FP), idx) +#define strcat_phasename_nodefault(dest, idx) strcat_zchar(dest, g_model.phaseData[idx].name, LEN_FP_NAME, NULL, 0, 0) +#define strcat_mixername_nodefault(dest, idx) strcat_zchar(dest, g_model.mixData[idx].name, LEN_EXPOMIX_NAME, NULL, 0, 0) #define ZLEN(s) zlen(s, sizeof(s)) #endif diff --git a/src/pulses_arm.cpp b/src/pulses_arm.cpp index 5f2b56826..cd1761366 100644 --- a/src/pulses_arm.cpp +++ b/src/pulses_arm.cpp @@ -60,87 +60,17 @@ void setupPulsesPPM(); void setupPulsesDsm2(uint8_t chns); void setupPulsesPXX(); -static void init_main_ppm( uint32_t period, uint32_t out_enable ) -{ - register Pio *pioptr ; - register Pwm *pwmptr ; - - setupPulsesPPM() ; - - if ( out_enable ) - { - pioptr = PIOA ; - pioptr->PIO_ABCDSR[0] &= ~PIO_PA17 ; // Peripheral C - pioptr->PIO_ABCDSR[1] |= PIO_PA17 ; // Peripheral C - pioptr->PIO_PDR = PIO_PA17 ; // Disable bit A17 Assign to peripheral - } - - pwmptr = PWM ; - // PWM3 for PPM output - pwmptr->PWM_CH_NUM[3].PWM_CMR = 0x0000000B ; // CLKA - if (g_model.pulsePol) - pwmptr->PWM_CH_NUM[3].PWM_CMR |= 0x00000200 ; // CPOL - pwmptr->PWM_CH_NUM[3].PWM_CPDR = period ; // Period in half uS - pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period ; // Period in half uS - pwmptr->PWM_CH_NUM[3].PWM_CDTY = g_model.ppmDelay*100+600; // Duty in half uS - pwmptr->PWM_CH_NUM[3].PWM_CDTYUPD = g_model.ppmDelay*100+600; // Duty in half uS - pwmptr->PWM_ENA = PWM_ENA_CHID3 ; // Enable channel 3 - - NVIC_EnableIRQ(PWM_IRQn) ; - pwmptr->PWM_IER1 = PWM_IER1_CHID3 ; -} - -void disable_main_ppm() -{ - register Pio *pioptr ; - - pioptr = PIOA ; - pioptr->PIO_PER = PIO_PA17 ; // Assign A17 to PIO - - PWM->PWM_IDR1 = PWM_IDR1_CHID3 ; - NVIC_DisableIRQ(PWM_IRQn) ; -} - -// Initialise the SSC to allow PXX output. -// TD is on PA17, peripheral A -void init_ssc() -{ - register Ssc *sscptr ; - - PMC->PMC_PCER0 |= 0x00400000L ; // Enable peripheral clock to SSC - - configure_pins( PIO_PA17, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ; - - sscptr = SSC ; - sscptr->SSC_CMR = Master_frequency / (125000*2) ; // 8uS per bit - sscptr->SSC_TCMR = 0 ; // 0000 0000 0000 0000 0000 0000 0000 0000 - sscptr->SSC_TFMR = 0x00000027 ; // 0000 0000 0000 0000 0000 0000 1010 0111 (8 bit data, lsb) - sscptr->SSC_CR = SSC_CR_TXEN ; -} - -void disable_ssc() -{ - register Pio *pioptr ; - register Ssc *sscptr ; - - // Revert back to pwm output - pioptr = PIOA ; - pioptr->PIO_PER = PIO_PA17 ; // Assign A17 to PIO - - sscptr = SSC ; - sscptr->SSC_CR = SSC_CR_TXDIS ; -} - void startPulses() { - init_main_ppm( 3000, 1 ) ; // Default for now, initial period 1.5 mS, output on + init_main_ppm(3000, 1) ; // Default for now, initial period 1.5 mS, output on } void setupPulsesPPM() // Don't enable interrupts through here { - register Pwm *pwmptr; +#if !defined(PCBX9D) + register Pwm *pwmptr = PWM; +#endif - pwmptr = PWM; // Now set up pulses int16_t PPM_range = g_model.extendedLimits ? 640 * 2 : 512 * 2; //range of 0.7..1.7msec @@ -152,11 +82,13 @@ void setupPulsesPPM() // Don't enable interrupts through here ptr = Pulses; uint32_t p = 8 + g_model.ppmNCH * 2; //Channels *2 +#if !defined(PCBX9D) pwmptr->PWM_CH_NUM[3].PWM_CDTYUPD = (g_model.ppmDelay * 50 + 300) * 2; //Stoplen *2 if (g_model.pulsePol) pwmptr->PWM_CH_NUM[3].PWM_CMR |= 0x00000200 ; // CPOL else pwmptr->PWM_CH_NUM[3].PWM_CMR &= ~0x00000200 ; // CPOL +#endif uint32_t rest = 22500u * 2; //Minimum Framelen=22.5 ms rest += (int32_t(g_model.ppmFrameLength)) * 1000; @@ -405,6 +337,7 @@ void setupPulsesDsm2(uint8_t chns) } } +#if !defined(SIMU) && !defined(PCBX9D) extern "C" void PWM_IRQHandler(void) { register Pwm *pwmptr; @@ -418,24 +351,21 @@ extern "C" void PWM_IRQHandler(void) case PROTO_PXX: // Alternate periods of 15.5mS and 2.5 mS period = pwmptr->PWM_CH_NUM[3].PWM_CPDR; - if (period == 5000) // 2.5 mS - { + if (period == 5000) { // 2.5 mS period = 15500 * 2; } else { period = 5000; } pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period; // Period in half uS - if (period != 5000) // 2.5 mS - { + if (period != 5000) { // 2.5 mS setupPulses(); } else { + // Kick off serial output here sscptr = SSC; -#ifndef SIMU sscptr->SSC_TPR = (uint32_t) Bit_pulses; -#endif sscptr->SSC_TCR = Serial_byte_count; sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers } @@ -459,9 +389,7 @@ extern "C" void PWM_IRQHandler(void) else { // Kick off serial output here sscptr = SSC; -#ifndef SIMU sscptr->SSC_TPR = (uint32_t) Bit_pulses; -#endif sscptr->SSC_TCR = Serial_byte_count; sscptr->SSC_PTCR = SSC_PTCR_TXTEN; // Start transfers } @@ -478,6 +406,7 @@ extern "C" void PWM_IRQHandler(void) } } } +#endif void setupPulses() { diff --git a/src/pulses_arm.h b/src/pulses_arm.h index 81fa5d298..3abd735a1 100644 --- a/src/pulses_arm.h +++ b/src/pulses_arm.h @@ -42,7 +42,10 @@ inline bool pulsesStarted() { return s_current_protocol != 255; } inline void pausePulses() { s_pulses_paused = true; } inline void resumePulses() { s_pulses_paused = false; } +void init_main_ppm(uint32_t period, uint32_t out_enable); void disable_main_ppm(); + +void init_ssc(); void disable_ssc(); #endif diff --git a/src/simpgmspace.cpp b/src/simpgmspace.cpp index 2551e91cb..33a46d850 100644 --- a/src/simpgmspace.cpp +++ b/src/simpgmspace.cpp @@ -43,13 +43,19 @@ uint16_t dummyport16; const char *eepromFile = NULL; FILE *fp = NULL; -#if defined(CPUARM) +#if defined(PCBX9D) +GPIO_TypeDef gpiob; +GPIO_TypeDef gpioc; +#elif defined(PCBSKY9X) Pio Pioa, Piob, Pioc; Pwm pwm; Twi Twio; Usart Usart0; Dacc dacc; Adc Adc0; +#endif + +#if defined(CPUARM) uint32_t eeprom_pointer; char* eeprom_buffer_data; volatile int32_t eeprom_buffer_size; @@ -82,93 +88,94 @@ sem_t *eeprom_write_sem; break; #endif + void setSwitch(int8_t swtch) { switch (swtch) { #if defined(PCBX9D) case DSW(SW_SA0): - PIOC->PIO_PDSR &= ~(1<<31); + GPIOB->IDR &= ~(1<<31); break; case DSW(SW_SA2): - PIOC->PIO_PDSR |= (1<<31); + GPIOB->IDR |= (1<<31); break; case DSW(SW_SB0): - PIOC->PIO_PDSR &= ~(1<<26); - PIOC->PIO_PDSR &= ~(1<<27); + GPIOB->IDR &= ~(1<<26); + GPIOB->IDR &= ~(1<<27); break; case DSW(SW_SB1): - PIOC->PIO_PDSR |= (1<<27); - PIOC->PIO_PDSR &= ~(1<<26); + GPIOB->IDR |= (1<<27); + GPIOB->IDR &= ~(1<<26); break; case DSW(SW_SB2): - PIOC->PIO_PDSR |= (1<<26); - PIOC->PIO_PDSR &= ~(1<<27); + GPIOB->IDR |= (1<<26); + GPIOB->IDR &= ~(1<<27); break; case DSW(SW_SC0): - PIOC->PIO_PDSR &= ~(1<<22); - PIOC->PIO_PDSR &= ~(1<<23); + GPIOB->IDR &= ~(1<<22); + GPIOB->IDR &= ~(1<<23); break; case DSW(SW_SC1): - PIOC->PIO_PDSR |= (1<<23); - PIOC->PIO_PDSR &= ~(1<<22); + GPIOB->IDR |= (1<<23); + GPIOB->IDR &= ~(1<<22); break; case DSW(SW_SC2): - PIOC->PIO_PDSR |= (1<<22); - PIOC->PIO_PDSR &= ~(1<<23); + GPIOB->IDR |= (1<<22); + GPIOB->IDR &= ~(1<<23); break; case DSW(SW_SD0): - PIOC->PIO_PDSR &= ~(1<<20); - PIOC->PIO_PDSR &= ~(1<<21); + GPIOB->IDR &= ~(1<<20); + GPIOB->IDR &= ~(1<<21); break; case DSW(SW_SD1): - PIOC->PIO_PDSR |= (1<<21); - PIOC->PIO_PDSR &= ~(1<<20); + GPIOB->IDR |= (1<<21); + GPIOB->IDR &= ~(1<<20); break; case DSW(SW_SD2): - PIOC->PIO_PDSR |= (1<<20); - PIOC->PIO_PDSR &= ~(1<<21); + GPIOB->IDR |= (1<<20); + GPIOB->IDR &= ~(1<<21); break; case DSW(SW_SE0): - PIOC->PIO_PDSR &= ~(1<<18); - PIOC->PIO_PDSR &= ~(1<<19); + GPIOB->IDR &= ~(1<<18); + GPIOB->IDR &= ~(1<<19); break; case DSW(SW_SE1): - PIOC->PIO_PDSR |= (1<<19); - PIOC->PIO_PDSR &= ~(1<<18); + GPIOB->IDR |= (1<<19); + GPIOB->IDR &= ~(1<<18); break; case DSW(SW_SE2): - PIOC->PIO_PDSR |= (1<<18); - PIOC->PIO_PDSR &= ~(1<<19); + GPIOB->IDR |= (1<<18); + GPIOB->IDR &= ~(1<<19); break; case DSW(SW_SF0): - PIOC->PIO_PDSR &= ~(1<<16); - PIOC->PIO_PDSR &= ~(1<<17); + GPIOB->IDR &= ~(1<<16); + GPIOB->IDR &= ~(1<<17); break; case DSW(SW_SF1): - PIOC->PIO_PDSR |= (1<<17); - PIOC->PIO_PDSR &= ~(1<<16); + GPIOB->IDR |= (1<<17); + GPIOB->IDR &= ~(1<<16); break; case DSW(SW_SF2): - PIOC->PIO_PDSR |= (1<<16); - PIOC->PIO_PDSR &= ~(1<<17); + GPIOB->IDR |= (1<<16); + GPIOB->IDR &= ~(1<<17); break; case DSW(SW_SG0): - PIOC->PIO_PDSR &= ~(1<<14); - PIOC->PIO_PDSR &= ~(1<<15); + GPIOB->IDR &= ~(1<<14); + GPIOB->IDR &= ~(1<<15); break; case DSW(SW_SG1): - PIOC->PIO_PDSR |= (1<<15); - PIOC->PIO_PDSR &= ~(1<<14); + GPIOB->IDR |= (1<<15); + GPIOB->IDR &= ~(1<<14); break; case DSW(SW_SG2): - PIOC->PIO_PDSR |= (1<<14); - PIOC->PIO_PDSR &= ~(1<<15); + GPIOB->IDR |= (1<<14); + GPIOB->IDR &= ~(1<<15); break; case DSW(SW_SH0): - PIOC->PIO_PDSR &= ~(1<<13); + GPIOB->IDR &= ~(1<<13); break; case DSW(SW_SH2): - PIOC->PIO_PDSR |= (1<<13); + GPIOB->IDR |= (1<<13); break; #elif defined(PCBSKY9X) case DSW(SW_ID0): @@ -325,6 +332,10 @@ void *main_thread(void *) checkLowEEPROM(); #endif +#if defined(CPUARM) + eeLoadModel(g_eeGeneral.currModel); +#endif + checkTHR(); checkSwitches(); checkAlarm(); @@ -439,7 +450,7 @@ FATFS g_FATFS_Obj; FRESULT f_stat (const TCHAR * path, FILINFO *) { struct stat tmp; - // printf("f_stat(%s)\n", path); fflush(stdout); + printf("f_stat(%s)\n", path); fflush(stdout); return stat(path, &tmp) ? FR_INVALID_NAME : FR_OK; } diff --git a/src/simpgmspace.h b/src/simpgmspace.h index 305b4221a..af09db075 100644 --- a/src/simpgmspace.h +++ b/src/simpgmspace.h @@ -95,8 +95,14 @@ typedef const uint8_t pm_uint8_t; typedef const int16_t pm_int16_t; typedef const int8_t pm_int8_t; -extern sem_t *eeprom_write_sem; -#if defined(CPUARM) +#if defined(PCBX9D) +extern GPIO_TypeDef gpiob; +#undef GPIOB +#define GPIOB (&gpiob) +extern GPIO_TypeDef gpioc; +#undef GPIOC +#define GPIOC (&gpioc) +#elif defined(PCBSKY9X) extern Pio Pioa, Piob, Pioc; extern Twi Twio; extern Dacc dacc; @@ -119,6 +125,10 @@ extern Adc Adc0; extern Pwm pwm; #undef PWM #define PWM (&pwm) +#endif + +extern sem_t *eeprom_write_sem; +#if defined(CPUARM) extern uint32_t eeprom_pointer; extern char* eeprom_buffer_data; extern volatile int32_t eeprom_buffer_size; diff --git a/src/simu.cpp b/src/simu.cpp index 5bbc51c6e..e75c75897 100644 --- a/src/simu.cpp +++ b/src/simu.cpp @@ -47,6 +47,60 @@ #define H2 H*2 int g_snapshot_idx = 0; +uint64_t toto = 0; + +#if defined(PCBX9D) +#define ERSKY9X_RETURN_PIO GPIOC->IDR +#define ERSKY9X_RETURN_MASK 0x20 +#define ERSKY9X_EXIT_PIO GPIOC->IDR +#define ERSKY9X_EXIT_MASK (0x01000000) +#define ERSKY9X_UP_MASK 0x00 +#define ERSKY9X_DOWN_MASK 0x00 +#define ERSKY9X_RIGHT_PIO GPIOC->IDR +#define ERSKY9X_RIGHT_MASK 0x10 +#define ERSKY9X_LEFT_PIO GPIOC->IDR +#define ERSKY9X_LEFT_MASK 0x08 +#define KEY_MENU_PIO GPIOC->IDR +#define KEY_MENU_MASK 0x02 +#define KEY_PAGE_PIO GPIOC->IDR +#define KEY_PAGE_MASK 0x40 +#elif defined(PCBSKY9X) && defined(REVA) +#define ERSKY9X_RETURN_PIO PIOB->PIO_PDSR +#define ERSKY9X_RETURN_MASK (0x40) +#define ERSKY9X_EXIT_PIO PIOA->PIO_PDSR +#define ERSKY9X_EXIT_MASK (0x80000000) +#define ERSKY9X_UP_MASK (0x08 >> 1) +#define ERSKY9X_RIGHT_PIO PIOC->PIO_PDSR +#define ERSKY9X_RIGHT_MASK (0x20 >> 1) +#define ERSKY9X_DOWN_MASK (0x10 >> 1) +#define ERSKY9X_LEFT_PIO PIOC->PIO_PDSR +#define ERSKY9X_LEFT_MASK (0x40 >> 1) +#elif defined(PCBSKY9X) +#define ERSKY9X_RETURN_PIO PIOB->PIO_PDSR +#define ERSKY9X_RETURN_MASK (0x20) +#define ERSKY9X_EXIT_MASK (0x01000000) +#define ERSKY9X_EXIT_PIO PIOC->PIO_PDSR +#define ERSKY9X_UP_MASK (0x04 >> 1) +#define ERSKY9X_RIGHT_PIO PIOC->PIO_PDSR +#define ERSKY9X_RIGHT_MASK (0x20 >> 1) +#define ERSKY9X_DOWN_MASK (0x40 >> 1) +#define ERSKY9X_LEFT_PIO PIOC->PIO_PDSR +#define ERSKY9X_LEFT_MASK (0x10 >> 1) +#define ERSKY9X_MENU_MASK (0x04 >> 1) +#else +// TODO to remove +#define ERSKY9X_RETURN_PIO toto +#define ERSKY9X_RETURN_MASK toto +#define ERSKY9X_EXIT_MASK toto +#define ERSKY9X_EXIT_PIO toto +#define ERSKY9X_UP_MASK toto +#define ERSKY9X_RIGHT_PIO toto +#define ERSKY9X_RIGHT_MASK toto +#define ERSKY9X_DOWN_MASK toto +#define ERSKY9X_LEFT_PIO toto +#define ERSKY9X_LEFT_MASK toto +#define ERSKY9X_MENU_MASK toto +#endif class Open9xSim: public FXMainWindow { @@ -239,48 +293,36 @@ long Open9xSim::onTimeout(FXObject*,FXSelector,void*) if(hasFocus()) { -#if defined(PCBSKY9X) && defined(REVA) -#define ERSKY9X_RETURN_MASK (0x40) -#define ERSKY9X_EXIT_MASK (0x80000000) -#define ERSKY9X_EXIT_PIO PIOA -#define ERSKY9X_UP_MASK (0x08 >> 1) -#define ERSKY9X_RIGHT_MASK (0x20 >> 1) -#define ERSKY9X_DOWN_MASK (0x10 >> 1) -#define ERSKY9X_LEFT_MASK (0x40 >> 1) -#else -#define ERSKY9X_RETURN_MASK (0x20) -#define ERSKY9X_EXIT_MASK (0x01000000) -#define ERSKY9X_EXIT_PIO PIOC -#define ERSKY9X_UP_MASK (0x04 >> 1) -#define ERSKY9X_RIGHT_MASK (0x20 >> 1) -#define ERSKY9X_DOWN_MASK (0x40 >> 1) -#define ERSKY9X_LEFT_MASK (0x10 >> 1) -#define ERSKY9X_MENU_MASK (0x04 >> 1) -#define ERSKY9X_PAGE_MASK (0x40 >> 1) -#endif static uint64_t keys1[]={ - KEY_Return, INP_B_KEY_MEN, INP_L_KEY_MEN, (uint64_t)PIOB, ERSKY9X_RETURN_MASK, - KEY_BackSpace, INP_B_KEY_EXT, INP_L_KEY_EXT, (uint64_t)ERSKY9X_EXIT_PIO, ERSKY9X_EXIT_MASK, - KEY_KP_0, INP_B_KEY_EXT, INP_L_KEY_EXT, (uint64_t)ERSKY9X_EXIT_PIO, ERSKY9X_EXIT_MASK, - KEY_Right, INP_B_KEY_RGT, INP_L_KEY_RGT, (uint64_t)PIOC, ERSKY9X_RIGHT_MASK, - KEY_Left, INP_B_KEY_LFT, INP_L_KEY_LFT, (uint64_t)PIOC, ERSKY9X_LEFT_MASK, +// TODO change everything here! + KEY_Return, INP_B_KEY_MEN, INP_L_KEY_MEN, (uint64_t)&ERSKY9X_RETURN_PIO, ERSKY9X_RETURN_MASK, + KEY_BackSpace, INP_B_KEY_EXT, INP_L_KEY_EXT, (uint64_t)&ERSKY9X_EXIT_PIO, ERSKY9X_EXIT_MASK, + KEY_KP_0, INP_B_KEY_EXT, INP_L_KEY_EXT, (uint64_t)&ERSKY9X_EXIT_PIO, ERSKY9X_EXIT_MASK, + KEY_Right, INP_B_KEY_RGT, INP_L_KEY_RGT, (uint64_t)&ERSKY9X_RIGHT_PIO, ERSKY9X_RIGHT_MASK, + KEY_Left, INP_B_KEY_LFT, INP_L_KEY_LFT, (uint64_t)&ERSKY9X_LEFT_PIO, ERSKY9X_LEFT_MASK, #if defined(PCBX9D) - KEY_Page_Up, INP_B_KEY_MEN, INP_L_KEY_MEN, (uint64_t)PIOC, ERSKY9X_MENU_MASK, - KEY_Page_Down, INP_B_KEY_EXT, INP_L_KEY_EXT, (uint64_t)PIOC, ERSKY9X_PAGE_MASK, + KEY_Page_Up, INP_B_KEY_MEN, INP_L_KEY_MEN, (uint64_t)&KEY_MENU_PIO, KEY_MENU_MASK, + KEY_Page_Down, INP_B_KEY_EXT, INP_L_KEY_EXT, (uint64_t)&KEY_PAGE_PIO, KEY_PAGE_MASK, #else KEY_Up, INP_B_KEY_UP, INP_L_KEY_UP, (uint64_t)PIOC, ERSKY9X_UP_MASK, KEY_Down, INP_B_KEY_DWN, INP_L_KEY_DWN, (uint64_t)PIOC, ERSKY9X_DOWN_MASK, #endif }; -#if defined(CPUARM) - PIOC->PIO_PDSR |= ERSKY9X_DOWN_MASK | ERSKY9X_UP_MASK | ERSKY9X_RIGHT_MASK | ERSKY9X_LEFT_MASK ; - ERSKY9X_EXIT_PIO->PIO_PDSR |= ERSKY9X_EXIT_MASK; - PIOB->PIO_PDSR |= ERSKY9X_RETURN_MASK; -// PIOA->PIO_PDSR = 0xFFFFFFFF; - temperature = 31; +#if defined(PCBSKY9X) Coproc_temp = 23; Coproc_maxtemp = 28; +#endif + +#if defined(CPUARM) + ERSKY9X_RIGHT_PIO |= ERSKY9X_DOWN_MASK | ERSKY9X_UP_MASK | ERSKY9X_RIGHT_MASK | ERSKY9X_LEFT_MASK ; + ERSKY9X_EXIT_PIO |= ERSKY9X_EXIT_MASK; + ERSKY9X_RETURN_PIO |= ERSKY9X_RETURN_MASK; +#if defined(PCBX9D) + KEY_MENU_PIO |= KEY_MENU_MASK; + KEY_PAGE_PIO |= KEY_PAGE_MASK; +#endif + temperature = 31; maxTemperature = 42; #elif defined(PCBGRUVIN9X) uint8_t pin = (pinl & ~0x3f); @@ -291,7 +333,7 @@ long Open9xSim::onTimeout(FXObject*,FXSelector,void*) for(unsigned i=0; igetKeyState(keys1[i])) { #if defined(CPUARM) - ((Pio*)keys1[i+3])->PIO_PDSR &= ~(keys1[i+4]); + *((uint32_t*)keys1[i+3]) &= ~(keys1[i+4]); #elif defined(PCBGRUVIN9X) pin |= (1<PIO_PDSR |= (0x00800000 | 0x01000000 | 0x00000002 | 0x00000001); PIOB->PIO_PDSR |= (0x00000050); PIOC->PIO_PDSR |= (0x10000000 | 0x00000400 | 0x00000200); @@ -327,7 +369,7 @@ long Open9xSim::onTimeout(FXObject*,FXSelector,void*) for(unsigned i=0; igetKeyState(keys2[i])) { -#if defined(CPUARM) +#if defined(PCBSKY9X) switch(i) { case 6: PIOA->PIO_PDSR &= ~0x00800000; @@ -425,7 +467,10 @@ void Open9xSim::refreshDiplay() { if (lcd_refresh) { lcd_refresh = false; -#if defined(CPUARM) +#if defined(PCBX9D) + if (1) + // TODO here a define +#elif defined(PCBSKY9X) if (PWM->PWM_CH_NUM[0].PWM_CDTY != 100) #elif defined(PCBGRUVIN9X) if (portc & 1<> 24); +#if defined(SIMU) + printf("isAudioFileAvailable(%08x)\n", i); fflush(stdout); +#endif + if (category == SYSTEM_AUDIO_CATEGORY) { if (sdAvailableSystemAudioFiles & ((uint32_t)1 << i)) { strcpy(filename, SYSTEM_SOUNDS_PATH "/"); @@ -154,7 +155,6 @@ bool isAudioFileAvailable(uint32_t i, char * filename) return true; } } -#if 0 else if (category == PHASE_AUDIO_CATEGORY) { uint8_t index = (i >> 16) & 0xFF; uint8_t event = i & 0xFF; @@ -162,7 +162,7 @@ bool isAudioFileAvailable(uint32_t i, char * filename) strcpy(filename, SOUNDS_PATH "/"); char *str = strcat_modelname(filename+sizeof(SOUNDS_PATH), g_eeGeneral.currModel); *str++ = '/'; - char * tmp = strcat_phasename_nodefault(str, i); + char * tmp = strcat_phasename_nodefault(str, index); if (tmp != str) { strcpy(tmp, suffixes[event]); strcat(tmp, SOUNDS_EXT); @@ -173,7 +173,7 @@ bool isAudioFileAvailable(uint32_t i, char * filename) strcpy(filename, SOUNDS_PATH "/"); char *str = strcat_modelname(filename+sizeof(SOUNDS_PATH), g_eeGeneral.currModel); *str++ = '/'; - char * tmp = strcat_phasename_default(str, i); + char * tmp = strcat_phasename_default(str, index); if (tmp != str) { strcpy(tmp, suffixes[event]); strcat(tmp, SOUNDS_EXT); @@ -188,18 +188,7 @@ bool isAudioFileAvailable(uint32_t i, char * filename) strcpy(filename, SOUNDS_PATH "/"); char *str = strcat_modelname(filename+sizeof(SOUNDS_PATH), g_eeGeneral.currModel); *str++ = '/'; - char * tmp = strcat_mixername_nodefault(str, i); - if (tmp != str) { - strcpy(tmp, suffixes[event]); - strcat(tmp, SOUNDS_EXT); - return true; - } - } - else if ((sdAvailableMixerAudioFiles[index] >> 4) & (1 << event)) { - strcpy(filename, SOUNDS_PATH "/"); - char *str = strcat_modelname(filename+sizeof(SOUNDS_PATH), g_eeGeneral.currModel); - *str++ = '/'; - char * tmp = strcat_mixername_default(str, i); + char * tmp = strcat_mixername_nodefault(str, index); if (tmp != str) { strcpy(tmp, suffixes[event]); strcat(tmp, SOUNDS_EXT); @@ -207,7 +196,7 @@ bool isAudioFileAvailable(uint32_t i, char * filename) } } } -#endif + return false; } #else @@ -381,11 +370,11 @@ void AudioQueue::sdWakeup(AudioContext & context) } read /= 2; - register Dacc *dacptr = DACC; +#if defined(PCBSKY9X) + register Dacc *dacptr = DACC; if (read) { state = AUDIO_PLAYING_WAV; - if (dacptr->DACC_ISR & DACC_ISR_TXBUFE) { dacptr->DACC_TPR = CONVERT_PTR(wavSamplesBuffer); dacptr->DACC_TCR = read; @@ -403,7 +392,6 @@ void AudioQueue::sdWakeup(AudioContext & context) CoSetTmrCnt(audioTimer, (WAV_BUFFER_SIZE * 500) / context.pcmFreq, 0); CoStartTmr(audioTimer); } - wavSamplesBuffer += WAV_BUFFER_SIZE; if (wavSamplesBuffer >= wavSamplesArray + 3 * WAV_BUFFER_SIZE) wavSamplesBuffer = wavSamplesArray; @@ -412,6 +400,7 @@ void AudioQueue::sdWakeup(AudioContext & context) state = AUDIO_RESUMING; CoSetFlag(audioFlag); } +#endif } } else { @@ -439,11 +428,13 @@ void AudioQueue::wakeup() if (state != AUDIO_PLAYING_TONE) { state = AUDIO_PLAYING_TONE; +#if !defined(PCBX9D) register Dacc *dacptr = DACC; dacptr->DACC_TPR = CONVERT_PTR(Sine_values); dacptr->DACC_TNPR = CONVERT_PTR(Sine_values); dacptr->DACC_TCR = 50 ; // words, 100 16 bit values dacptr->DACC_TNCR = 50 ; // words, 100 16 bit values +#endif } setFrequency(fragment.freq * 6100 / 4); @@ -483,11 +474,13 @@ void AudioQueue::wakeup() else if (ridx == widx && prioIdx < 0 && backgroundContext.fragment.duration > 0) { if (state != AUDIO_PLAYING_TONE) { state = AUDIO_PLAYING_TONE; +#if !defined(PCBX9D) register Dacc *dacptr = DACC; dacptr->DACC_TPR = CONVERT_PTR(Sine_values); dacptr->DACC_TNPR = CONVERT_PTR(Sine_values); dacptr->DACC_TCR = 50 ; // words, 100 16 bit values dacptr->DACC_TNCR = 50 ; // words, 100 16 bit values +#endif } CoSetTmrCnt(audioTimer, backgroundContext.fragment.duration*2, 0); backgroundContext.fragment.duration = 0; diff --git a/src/sky9x/audio.h b/src/sky9x/audio.h index ded6f41db..4c0366ca2 100644 --- a/src/sky9x/audio.h +++ b/src/sky9x/audio.h @@ -190,10 +190,8 @@ extern void pushPrompt(uint16_t prompt, uint8_t id=0); #define PLAY_FILE(f, flags, id) audioQueue.playFile((f), (flags), (id)) #define STOP_PLAY(id) audioQueue.stopPlay((id)) #define AUDIO_RESET() audioQueue.reset() -#define PLAY_PHASE_OFF(phase) -// do { char filename[42/*TODO check*/]; if (isAudioFileAvailable((PHASE_AUDIO_CATEGORY << 24) + (phase << 16) + AUDIO_EVENT_OFF, filename)) audioQueue.playFile(filename); } while (0) -#define PLAY_PHASE_ON(phase) -// do { char filename[42]; if (isAudioFileAvailable((PHASE_AUDIO_CATEGORY << 24) + (phase << 16) + AUDIO_EVENT_ON, filename)) audioQueue.playFile(filename); } while (0) +#define PLAY_PHASE_OFF(phase) do { char filename[64]; if (isAudioFileAvailable((PHASE_AUDIO_CATEGORY << 24) + (phase << 16) + AUDIO_EVENT_OFF, filename)) audioQueue.playFile(filename); } while (0) +#define PLAY_PHASE_ON(phase) do { char filename[64]; if (isAudioFileAvailable((PHASE_AUDIO_CATEGORY << 24) + (phase << 16) + AUDIO_EVENT_ON, filename)) audioQueue.playFile(filename); } while (0) extern void refreshSystemAudioFiles(); extern void refreshModelAudioFiles(); diff --git a/src/sky9x/sound_driver.cpp b/src/sky9x/audio_driver.cpp similarity index 84% rename from src/sky9x/sound_driver.cpp rename to src/sky9x/audio_driver.cpp index bfd8bdfc8..9e700fdd2 100644 --- a/src/sky9x/sound_driver.cpp +++ b/src/sky9x/audio_driver.cpp @@ -1,36 +1,35 @@ -/**************************************************************************** -* Copyright (c) 2011 by Michael Blandford. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* History: -* -****************************************************************************/ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ #include "../open9x.h" diff --git a/src/sky9x/audio_driver.h b/src/sky9x/audio_driver.h new file mode 100644 index 000000000..a734c3289 --- /dev/null +++ b/src/sky9x/audio_driver.h @@ -0,0 +1,75 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef audio_driver_h +#define audio_driver_h + +#define NUM_VOL_LEVELS 24 + +extern void startSound( void ) ; +extern void buzzer_on( void ) ; +extern void buzzer_off( void ) ; +extern void buzzer_sound( uint8_t time ) ; +extern void setFrequency( uint32_t frequency ) ; +extern uint32_t getFrequency(); +extern void start_timer1( void ) ; +extern void initDac( void ) ; +extern void end_sound( void ) ; +extern void write_coprocessor( uint8_t *ptr, uint32_t count ) ; +extern void read_coprocessor( bool onlytemp=false ) ; +extern uint8_t Coproc_read ; +extern int8_t Coproc_valid ; +extern int8_t Coproc_temp ; +extern int8_t Coproc_maxtemp ; + +extern uint16_t *nextAudioData; +extern uint16_t nextAudioSize; + +inline void toneStart() +{ + PMC->PMC_PCER0 |= 0x40000000L ; // Enable peripheral clock to DAC + DACC->DACC_IER = DACC_IER_ENDTX ; +} + +inline void toneStop() +{ + DACC->DACC_IDR = DACC_IDR_ENDTX ; // Disable interrupt +} + +extern volatile uint8_t Buzzer_count ; + +extern void init_twi( void ) ; +extern void setVolume( register uint8_t volume ) ; +extern "C" void TWI0_IRQHandler (void) ; + +#endif diff --git a/src/sky9x/board.h b/src/sky9x/board.h index ae9a3346b..2eda35247 100644 --- a/src/sky9x/board.h +++ b/src/sky9x/board.h @@ -39,17 +39,14 @@ #include #include "chip.h" -#ifdef REVA +#if defined(REVA) #include "AT91SAM3S2.h" #else #include "AT91SAM3S4.h" #endif -#ifdef SIMU -#define CONVERT_PTR(x) ((uint32_t)(uint64_t)(x)) -#else +#if !defined(SIMU) #include "core_cm3.h" -#define CONVERT_PTR(x) ((uint32_t)(x)) #endif //------------------------------------------------------------------------------ diff --git a/src/sky9x/eeprom_driver.cpp b/src/sky9x/eeprom_driver.cpp new file mode 100644 index 000000000..70c85587d --- /dev/null +++ b/src/sky9x/eeprom_driver.cpp @@ -0,0 +1,271 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "../open9x.h" + +uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count ) +{ +#ifndef SIMU + + register Spi *spiptr ; + register uint32_t condition ; + static uint8_t discard_rx_command[4] ; + +// PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI + + Spi_complete = 0 ; + if ( comlen > 4 ) + { + Spi_complete = 1 ; + return 0x4FFFF ; + } + condition = SPI_SR_TXEMPTY ; + spiptr = SPI ; + spiptr->SPI_CR = 1 ; // Enable + (void) spiptr->SPI_RDR ; // Dump any rx data + (void) spiptr->SPI_SR ; // Clear error flags + spiptr->SPI_RPR = (uint32_t)discard_rx_command ; + spiptr->SPI_RCR = comlen ; + if ( rx ) + { + spiptr->SPI_RNPR = (uint32_t)rx ; + spiptr->SPI_RNCR = count ; + condition = SPI_SR_RXBUFF ; + } + spiptr->SPI_TPR = (uint32_t)command ; + spiptr->SPI_TCR = comlen ; + if ( tx ) + { + spiptr->SPI_TNPR = (uint32_t)tx ; + } + else + { + spiptr->SPI_TNPR = (uint32_t)rx ; + } + spiptr->SPI_TNCR = count ; + + spiptr->SPI_PTCR = SPI_PTCR_RXTEN | SPI_PTCR_TXTEN ; // Start transfers + + // Wait for things to get started, avoids early interrupt + for ( count = 0 ; count < 1000 ; count += 1 ) + { + if ( ( spiptr->SPI_SR & SPI_SR_TXEMPTY ) == 0 ) + { + break ; + } + } + spiptr->SPI_IER = condition ; + +#endif + + return 0 ; +} + +uint32_t spi_operation( register uint8_t *tx, register uint8_t *rx, register uint32_t count ) +{ + register Spi *spiptr; + register uint32_t result; + + result = 0; + spiptr = SPI; + spiptr->SPI_CR = 1; // Enable + (void) spiptr->SPI_RDR; // Dump any rx data + + while (count) { + result = 0; + while ((spiptr->SPI_SR & SPI_SR_TXEMPTY) == 0) { + // wait + if (++result > 10000) { + result = 0xFFFF; + break; + } + } + if (result > 10000) { + break; + } + + spiptr->SPI_TDR = *tx++; + result = 0; + while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { + // wait for received + if (++result > 10000) { + result = 0x2FFFF; + break; + } + } + if (result > 10000) { + break; + } + *rx++ = spiptr->SPI_RDR; + count -= 1; + } + if (result <= 10000) { + result = 0; + } + spiptr->SPI_CR = 2; // Disable + + return result ; +} + +uint32_t eeprom_write_one(uint8_t byte, uint8_t count) +{ +#ifndef SIMU + register Spi *spiptr; + register uint32_t result; + + spiptr = SPI; + spiptr->SPI_CR = 1; // Enable + (void) spiptr->SPI_RDR; // Dump any rx data + + spiptr->SPI_TDR = byte; + + result = 0; + while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { + // wait for received + if (++result > 10000) { + break; + } + } + if (count == 0) { + spiptr->SPI_CR = 2; // Disable + return spiptr->SPI_RDR; + } + (void) spiptr->SPI_RDR; // Dump the rx data + spiptr->SPI_TDR = 0; + result = 0; + while ((spiptr->SPI_SR & SPI_SR_RDRF) == 0) { + // wait for received + if (++result > 10000) { + break; + } + } + spiptr->SPI_CR = 2; // Disable + return spiptr->SPI_RDR ; +#else + return !Spi_complete; +#endif +} + +void eeprom_write_enable() +{ + eeprom_write_one(6, 0); +} + +uint32_t eeprom_read_status() +{ + return eeprom_write_one(5, 1); +} + +// SPI i/f to EEPROM (4Mb) +// Peripheral ID 21 (0x00200000) +// Connections: +// SS PA11 (peripheral A) +// MISO PA12 (peripheral A) +// MOSI PA13 (peripheral A) +// SCK PA14 (peripheral A) +// Set clock to 3 MHz, AT25 device is rated to 70MHz, 18MHz would be better +void init_spi() +{ + register Spi *spiptr ; + register uint32_t timer ; + register uint8_t *p ; + uint8_t spi_buf[4] ; + + PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI + /* Configure PIO */ + configure_pins( 0x00007800, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ; + + spiptr = SPI ; + timer = ( Master_frequency / 3000000 ) << 8 ; // Baud rate 3Mb/s + spiptr->SPI_MR = 0x14000011 ; // 0001 0100 0000 0000 0000 0000 0001 0001 Master + spiptr->SPI_CSR[0] = 0x01180009 | timer ; // 0000 0001 0001 1000 xxxx xxxx 0000 1001 + NVIC_EnableIRQ(SPI_IRQn) ; + + p = spi_buf ; + +// *p = 0x39 ; // Unprotect sector command +// *(p+1) = 0 ; +// *(p+2) = 0 ; +// *(p+3) = 0 ; // 3 bytes address + +// spi_operation( p, spi_buf, 4 ) ; + + eeprom_write_enable() ; + + *p = 1 ; // Write status register command + *(p+1) = 0 ; + spi_operation( p, spi_buf, 2 ) ; +} + +#ifndef SIMU +extern "C" void SPI_IRQHandler() +{ + register Spi *spiptr ; + + spiptr = SPI ; + SPI->SPI_IDR = 0x07FF ; // All interrupts off + spiptr->SPI_CR = 2 ; // Disable + (void) spiptr->SPI_RDR ; // Dump any rx data + (void) spiptr->SPI_SR ; // Clear error flags + spiptr->SPI_PTCR = SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS ; // Stop tramsfers + Spi_complete = 1 ; // Indicate completion + +// Power save +// PMC->PMC_PCER0 &= ~0x00200000L ; // Disable peripheral clock to SPI +} +#endif + +void end_spi() +{ + SPI->SPI_CR = 2 ; // Disable + SPI->SPI_IDR = 0x07FF ; // All interrupts off + NVIC_DisableIRQ(SPI_IRQn) ; +} + +#if 0 +uint32_t unprotect_eeprom() +{ + register uint8_t *p; + + eeprom_write_enable(); + + p = Spi_tx_buf; + *p = 0x39; // Unprotect sector command + *(p + 1) = 0; + *(p + 2) = 0; + *(p + 3) = 0; // 3 bytes address + + return spi_operation( p, Spi_rx_buf, 4 ) ; +} +#endif + diff --git a/src/sky9x/haptic_driver.h b/src/sky9x/haptic_driver.h index 032b9f622..6608e7ac3 100644 --- a/src/sky9x/haptic_driver.h +++ b/src/sky9x/haptic_driver.h @@ -31,5 +31,10 @@ * */ +#ifndef haptic_driver_h +#define haptic_driver_h + extern void hapticOff(void) ; extern void hapticOn( uint32_t pwmPercent ) ; + +#endif diff --git a/src/sky9x/keys_driver.cpp b/src/sky9x/keys_driver.cpp new file mode 100644 index 000000000..3a6fcdf3b --- /dev/null +++ b/src/sky9x/keys_driver.cpp @@ -0,0 +1,180 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "../open9x.h" + + +// keys: +// KEY_EXIT PA31 (PC24) +// KEY_MENU PB6 (PB5) +// KEY_DOWN LCD5 PC3 (PC5) +// KEY_UP LCD6 PC2 (PC1) +// KEY_RIGHT LCD4 PC4 (PC4) +// KEY_LEFT LCD3 PC5 (PC3) +// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU +// LCD pins 5 DOWN, 4 RIGHT, 3 LEFT, 1 UP +uint32_t readKeys() +{ + register uint32_t x; + register uint32_t y; + + x = lcdLock ? lcdInputs : PIOC->PIO_PDSR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP () + x <<= 1; + +#if defined(REVA) + y = (x & 0x00000060); + if (x & 0x00000008) + y |= 0x10; + if (x & 0x00000010) + y |= 0x08; + if (PIOA->PIO_PDSR & 0x80000000) + y |= 0x04; // EXIT + if (PIOB->PIO_PDSR & 0x000000040) + y |= 0x02; // MENU +#else + y = (x & 0x00000020); // RIGHT + if (x & 0x00000004) + y |= 0x02 << KEY_UP; // UP + if (x & 0x00000010) + y |= 0x02 << KEY_LEFT; // LEFT + if (x & 0x00000040) + y |= 0x02 << KEY_DOWN; // DOWN + if (x & 0x02000000) + y |= 0x02 << KEY_EXIT; // EXIT + if (PIOB->PIO_PDSR & 0x000000020) + y |= 0x02 << KEY_MENU; // MENU +#endif + + return y ; +} + +uint32_t readTrims() +{ + uint32_t trims; + uint32_t trima; + + trims = 0; + + trima = PIOA->PIO_PDSR; + +// TRIM_LH_DOWN PA7 (PA23) +#if defined(REVA) + if ( ( trima & 0x0080 ) == 0 ) +#else + if ((trima & 0x00800000) == 0) +#endif + { + trims |= 1; + } + +// TRIM_LV_DOWN PA27 (PA24) +#if defined(REVA) + if ( ( trima & 0x08000000 ) == 0 ) +#else + if ((trima & 0x01000000) == 0) +#endif + { + trims |= 4; + } + +// TRIM_RV_UP PA30 (PA1) +#if defined(REVA) + if ( ( trima & 0x40000000 ) == 0 ) +#else + if ((trima & 0x00000002) == 0) +#endif + { + trims |= 0x20; + } + +// TRIM_RH_DOWN PA29 (PA0) +#if defined(REVA) + if ( ( trima & 0x20000000 ) == 0 ) +#else + if ((trima & 0x00000001) == 0) +#endif + { + trims |= 0x40; + } + +// TRIM_LH_UP PB4 + if ((PIOB->PIO_PDSR & 0x10) == 0) { + trims |= 2; + } + + trima = PIOC->PIO_PDSR; +// TRIM_LV_UP PC28 + if ((trima & 0x10000000) == 0) { + trims |= 8; + } + +// TRIM_RV_DOWN PC10 + if ((trima & 0x00000400) == 0) { + trims |= 0x10; + } + +// TRIM_RH_UP PC9 + if ((trima & 0x00000200) == 0) { + trims |= 0x80; + } + + return trims; +} + +uint8_t keyDown() +{ + return ~readKeys() & 0x7E ; +} + +void readKeysAndTrims() +{ + register uint32_t i; + +#if defined(ROTARY_ENCODERS) + keys[BTN_REa].input(!(PIOB->PIO_PDSR & 0x40), BTN_REa); +#endif + + uint8_t enuk = KEY_MENU; + uint8_t in = ~readKeys(); + for (i = 1; i < 7; i++) { + keys[enuk].input(in & (1 << i), (EnumKeys) enuk); + ++enuk; + } + + in = readTrims(); + + for (i = 1; i < 256; i <<= 1) { + keys[enuk].input(in & i, (EnumKeys) enuk); + ++enuk; + } +} diff --git a/src/sky9x/pulses_driver.cpp b/src/sky9x/pulses_driver.cpp new file mode 100644 index 000000000..344f87343 --- /dev/null +++ b/src/sky9x/pulses_driver.cpp @@ -0,0 +1,108 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "../open9x.h" + +// TODO illogical in the driver :( +void setupPulsesPPM(); + +void init_main_ppm( uint32_t period, uint32_t out_enable ) +{ + register Pio *pioptr ; + register Pwm *pwmptr ; + + setupPulsesPPM() ; + + if ( out_enable ) + { + pioptr = PIOA ; + pioptr->PIO_ABCDSR[0] &= ~PIO_PA17 ; // Peripheral C + pioptr->PIO_ABCDSR[1] |= PIO_PA17 ; // Peripheral C + pioptr->PIO_PDR = PIO_PA17 ; // Disable bit A17 Assign to peripheral + } + + pwmptr = PWM ; + // PWM3 for PPM output + pwmptr->PWM_CH_NUM[3].PWM_CMR = 0x0000000B ; // CLKA + if (g_model.pulsePol) + pwmptr->PWM_CH_NUM[3].PWM_CMR |= 0x00000200 ; // CPOL + pwmptr->PWM_CH_NUM[3].PWM_CPDR = period ; // Period in half uS + pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period ; // Period in half uS + pwmptr->PWM_CH_NUM[3].PWM_CDTY = g_model.ppmDelay*100+600; // Duty in half uS + pwmptr->PWM_CH_NUM[3].PWM_CDTYUPD = g_model.ppmDelay*100+600; // Duty in half uS + pwmptr->PWM_ENA = PWM_ENA_CHID3 ; // Enable channel 3 + + NVIC_EnableIRQ(PWM_IRQn) ; + pwmptr->PWM_IER1 = PWM_IER1_CHID3 ; +} + +void disable_main_ppm() +{ + register Pio *pioptr ; + + pioptr = PIOA ; + pioptr->PIO_PER = PIO_PA17 ; // Assign A17 to PIO + + PWM->PWM_IDR1 = PWM_IDR1_CHID3 ; + NVIC_DisableIRQ(PWM_IRQn) ; +} + +// Initialise the SSC to allow PXX output. +// TD is on PA17, peripheral A +void init_ssc() +{ + register Ssc *sscptr ; + + PMC->PMC_PCER0 |= 0x00400000L ; // Enable peripheral clock to SSC + + configure_pins( PIO_PA17, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ; + + sscptr = SSC ; + sscptr->SSC_CMR = Master_frequency / (125000*2) ; // 8uS per bit + sscptr->SSC_TCMR = 0 ; // 0000 0000 0000 0000 0000 0000 0000 0000 + sscptr->SSC_TFMR = 0x00000027 ; // 0000 0000 0000 0000 0000 0000 1010 0111 (8 bit data, lsb) + sscptr->SSC_CR = SSC_CR_TXEN ; +} + +void disable_ssc() +{ + register Pio *pioptr ; + register Ssc *sscptr ; + + // Revert back to pwm output + pioptr = PIOA ; + pioptr->PIO_PER = PIO_PA17 ; // Assign A17 to PIO + + sscptr = SSC ; + sscptr->SSC_CR = SSC_CR_TXDIS ; +} diff --git a/src/sky9x/sound_driver.h b/src/sky9x/sound_driver.h deleted file mode 100644 index a0373a75a..000000000 --- a/src/sky9x/sound_driver.h +++ /dev/null @@ -1,76 +0,0 @@ -/**************************************************************************** -* Copyright (c) 2011 by Michael Blandford. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* 1. Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* 2. Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* 3. Neither the name of the author nor the names of its contributors may -* be used to endorse or promote products derived from this software -* without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL -* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -* SUCH DAMAGE. -* -**************************************************************************** -* History: -* -****************************************************************************/ - -#ifndef sound_driver_h -#define sound_driver_h - -#define NUM_VOL_LEVELS 24 - -extern void startSound( void ) ; -extern void buzzer_on( void ) ; -extern void buzzer_off( void ) ; -extern void buzzer_sound( uint8_t time ) ; -extern void setFrequency( uint32_t frequency ) ; -extern uint32_t getFrequency(); -extern void start_timer1( void ) ; -extern void initDac( void ) ; -extern void end_sound( void ) ; -extern void write_coprocessor( uint8_t *ptr, uint32_t count ) ; -extern void read_coprocessor( bool onlytemp=false ) ; -extern uint8_t Coproc_read ; -extern int8_t Coproc_valid ; -extern int8_t Coproc_temp ; -extern int8_t Coproc_maxtemp ; - -extern uint16_t *nextAudioData; -extern uint16_t nextAudioSize; - -inline void toneStart() -{ - PMC->PMC_PCER0 |= 0x40000000L ; // Enable peripheral clock to DAC - DACC->DACC_IER = DACC_IER_ENDTX ; -} - -inline void toneStop() -{ - DACC->DACC_IDR = DACC_IDR_ENDTX ; // Disable interrupt -} - -extern volatile uint8_t Buzzer_count ; - -extern void init_twi( void ) ; -extern void setVolume( register uint8_t volume ) ; -extern "C" void TWI0_IRQHandler (void) ; - -#endif diff --git a/src/statistics_views.cpp b/src/statistics_views.cpp index c0863564e..e22ca0332 100644 --- a/src/statistics_views.cpp +++ b/src/statistics_views.cpp @@ -97,7 +97,9 @@ void menuStatisticsDebug(uint8_t event) g_eeGeneral.mAhUsed = 0; g_eeGeneral.globalTimer = 0; eeDirty(EE_GENERAL); +#if defined(PCBSKY9X) Current_used = 0; +#endif sessionTimer = 0; killEvents(event); AUDIO_KEYPAD_UP(); @@ -120,8 +122,7 @@ void menuStatisticsDebug(uint8_t event) return; } -#if defined(CPUARM) -#if !defined(REVA) +#if defined(PCBSKY9X) && !defined(REVA) lcd_putsLeft(1*FH, STR_CPU_CURRENT); putsTelemetryValue(MENU_DEBUG_COL_OFS, 1*FH, getCurrent(), UNIT_MILLIAMPS, 0); uint32_t current_scale = 488 + g_eeGeneral.currentCalib; @@ -131,21 +132,32 @@ void menuStatisticsDebug(uint8_t event) putsTelemetryValue(MENU_DEBUG_COL_OFS, 2*FH, g_eeGeneral.mAhUsed + Current_used*current_scale/8192/36, UNIT_MAH, PREC1); putsTime(17*FW, 2*FH, g_eeGeneral.globalTimer + sessionTimer, 0, 0); #endif + +#if defined(CPUARM) lcd_putsLeft(3*FH, STR_CPU_TEMP); putsTelemetryValue(MENU_DEBUG_COL_OFS, 3*FH, getTemperature(), UNIT_DEGREES, 0); putsTelemetryValue(20*FW+2, 3*FH, maxTemperature+g_eeGeneral.temperatureCalib, UNIT_DEGREES, 0); +#endif + +#if defined(PCBSKY9X) lcd_putsLeft(4*FH, STR_COPROC_TEMP); + if (Coproc_read==0) { lcd_putsAtt(9*FW+2, 4*FH, PSTR("Co Proc NACK"),INVERS); - } else if (Coproc_read==0x81) { + } + else if (Coproc_read==0x81) { lcd_putsAtt(9*FW+2, 4*FH, PSTR("Inst.TinyApp"),INVERS); - } else if (Coproc_read<3) { + } + else if (Coproc_read<3) { lcd_putsAtt(9*FW+2, 4*FH, PSTR("Upgr.TinyApp"),INVERS); - } else { + } + else { putsTelemetryValue(MENU_DEBUG_COL_OFS, 4*FH, Coproc_temp, UNIT_DEGREES, 0); putsTelemetryValue(20*FW+2, 4*FH, Coproc_maxtemp, UNIT_DEGREES, 0); } +#endif +#if defined(CPUARM) lcd_putsLeft(5*FH, STR_TMIXMAXMS); lcd_outdezAtt(MENU_DEBUG_COL_OFS, 5*FH, (maxMixerDuration)/20, PREC2); @@ -167,6 +179,7 @@ void menuStatisticsDebug(uint8_t event) lcd_putsLeft(5*FH, STR_FREESTACKMINB); lcd_outdezAtt(14*FW, 5*FH, stack_free(), UNSIGN) ; #endif + lcd_puts(3*FW, 7*FH+1, STR_MENUTORESET); lcd_status_line(); } diff --git a/src/stock/audio.h b/src/stock/audio.h index 3894acd83..2b6ee4b5e 100644 --- a/src/stock/audio.h +++ b/src/stock/audio.h @@ -31,6 +31,9 @@ * */ +#ifndef audio_h +#define audio_h + #if defined(PCBSTD) #define SPEAKER_ON BUZZER_ON #define SPEAKER_OFF toneFreq=0; BUZZER_OFF @@ -107,46 +110,51 @@ extern audioQueue audio; void audioDefevent(uint8_t e); -#define AUDIO_KEYPAD_UP() audioDefevent(AU_KEYPAD_UP) -#define AUDIO_KEYPAD_DOWN() audioDefevent(AU_KEYPAD_DOWN) -#define AUDIO_MENUS() audioDefevent(AU_MENUS) -#define AUDIO_WARNING1() audioDefevent(AU_WARNING1) -#define AUDIO_WARNING2() audioDefevent(AU_WARNING2) -#define AUDIO_ERROR() audioDefevent(AU_ERROR) +#define AUDIO_KEYPAD_UP() audioDefevent(AU_KEYPAD_UP) +#define AUDIO_KEYPAD_DOWN() audioDefevent(AU_KEYPAD_DOWN) +#define AUDIO_MENUS() audioDefevent(AU_MENUS) +#define AUDIO_WARNING1() audioDefevent(AU_WARNING1) +#define AUDIO_WARNING2() audioDefevent(AU_WARNING2) +#define AUDIO_ERROR() audioDefevent(AU_ERROR) #if defined(VOICE) -#define AUDIO_TADA() pushPrompt(PROMPT_SYSTEM_BASE+AU_TADA) +#define AUDIO_TADA() pushPrompt(PROMPT_SYSTEM_BASE+AU_TADA) #define AUDIO_TX_BATTERY_LOW() pushPrompt(PROMPT_SYSTEM_BASE+AU_TX_BATTERY_LOW) -#define AUDIO_INACTIVITY() pushPrompt(PROMPT_SYSTEM_BASE+AU_INACTIVITY) +#define AUDIO_INACTIVITY() pushPrompt(PROMPT_SYSTEM_BASE+AU_INACTIVITY) #define AUDIO_ERROR_MESSAGE(e) pushPrompt(PROMPT_SYSTEM_BASE+(e)) -#define AUDIO_TIMER_30() pushPrompt(PROMPT_SYSTEM_BASE+AU_TIMER_30) -#define AUDIO_TIMER_20() pushPrompt(PROMPT_SYSTEM_BASE+AU_TIMER_20) -#define AUDIO_TIMER_10() pushPrompt(PROMPT_SYSTEM_BASE+AU_TIMER_10) -#define AUDIO_TIMER_LT3(x) pushPrompt(PROMPT_SYSTEM_BASE+AU_TIMER_LT3) +#define AUDIO_TIMER_30() pushPrompt(PROMPT_SYSTEM_BASE+AU_TIMER_30) +#define AUDIO_TIMER_20() pushPrompt(PROMPT_SYSTEM_BASE+AU_TIMER_20) +#define AUDIO_TIMER_10() pushPrompt(PROMPT_SYSTEM_BASE+AU_TIMER_10) +#define AUDIO_TIMER_LT3(x) pushPrompt(PROMPT_SYSTEM_BASE+AU_TIMER_LT3) #else #define AUDIO_TADA() #define AUDIO_TX_BATTERY_LOW() audioDefevent(AU_TX_BATTERY_LOW) -#define AUDIO_INACTIVITY() audioDefevent(AU_INACTIVITY) +#define AUDIO_INACTIVITY() audioDefevent(AU_INACTIVITY) #define AUDIO_ERROR_MESSAGE(e) audioDefevent(AU_ERROR) -#define AUDIO_TIMER_30() audioDefevent(AU_TIMER_30) -#define AUDIO_TIMER_20() audioDefevent(AU_TIMER_20) -#define AUDIO_TIMER_10() audioDefevent(AU_TIMER_10) -#define AUDIO_TIMER_LT3(x) audioDefevent(AU_TIMER_LT3) +#define AUDIO_TIMER_30() audioDefevent(AU_TIMER_30) +#define AUDIO_TIMER_20() audioDefevent(AU_TIMER_20) +#define AUDIO_TIMER_10() audioDefevent(AU_TIMER_10) +#define AUDIO_TIMER_LT3(x) audioDefevent(AU_TIMER_LT3) #endif -#define AUDIO_MINUTE_BEEP() audioDefevent(AU_WARNING1) -#define AUDIO_MIX_WARNING_1() audioDefevent(AU_MIX_WARNING_1) -#define AUDIO_MIX_WARNING_2() audioDefevent(AU_MIX_WARNING_2) -#define AUDIO_MIX_WARNING_3() audioDefevent(AU_MIX_WARNING_3) +#define AUDIO_MINUTE_BEEP() audioDefevent(AU_WARNING1) +#define AUDIO_MIX_WARNING_1() audioDefevent(AU_MIX_WARNING_1) +#define AUDIO_MIX_WARNING_2() audioDefevent(AU_MIX_WARNING_2) +#define AUDIO_MIX_WARNING_3() audioDefevent(AU_MIX_WARNING_3) #define AUDIO_POT_STICK_MIDDLE() audioDefevent(AU_POT_STICK_MIDDLE) -#define AUDIO_VARIO_UP() audioDefevent(AU_KEYPAD_UP) -#define AUDIO_VARIO_DOWN() audioDefevent(AU_KEYPAD_DOWN) -#define AUDIO_TRIM_MIDDLE(f) audio.event(AU_TRIM_MIDDLE, f) -#define AUDIO_TRIM_END(f) AUDIO_TRIM_MIDDLE(f) -#define AUDIO_TRIM(event, f) audio.event(AU_TRIM_MOVE, f) -#define AUDIO_PLAY(p) audio.event(p) -#define AUDIO_VARIO(f, t) audio.play(f, t, 0, PLAY_BACKGROUND) +#define AUDIO_VARIO_UP() audioDefevent(AU_KEYPAD_UP) +#define AUDIO_VARIO_DOWN() audioDefevent(AU_KEYPAD_DOWN) +#define AUDIO_TRIM_MIDDLE(f) audio.event(AU_TRIM_MIDDLE, f) +#define AUDIO_TRIM_END(f) AUDIO_TRIM_MIDDLE(f) +#define AUDIO_TRIM(event, f) audio.event(AU_TRIM_MOVE, f) +#define AUDIO_PLAY(p) audio.event(p) +#define AUDIO_VARIO(f, t) audio.play(f, t, 0, PLAY_BACKGROUND) -#define AUDIO_DRIVER() audio.driver() -#define AUDIO_HEARTBEAT() audio.heartbeat() -#define IS_AUDIO_BUSY() audio.busy() +#define AUDIO_DRIVER() audio.driver() +#define AUDIO_HEARTBEAT() audio.heartbeat() +#define IS_AUDIO_BUSY() audio.busy() #define AUDIO_RESET() + +#define PLAY_PHASE_OFF(phase) +#define PLAY_PHASE_ON(phase) + +#endif diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf new file mode 100644 index 000000000..e04afaee6 Binary files /dev/null and b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf differ diff --git a/src/x9d/stm32f2xx.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h similarity index 98% rename from src/x9d/stm32f2xx.h rename to src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h index e0470a703..774f6abd9 100644 --- a/src/x9d/stm32f2xx.h +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h @@ -52,7 +52,10 @@ #ifndef __STM32F2xx_H #define __STM32F2xx_H -//#include "stm32f2xx_conf.h" + +// TODO added by BSS +#define assert_param(xx) + #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ @@ -94,7 +97,7 @@ can define the HSE value in your toolchain compiler preprocessor. */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)12000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /** @@ -6919,7 +6922,6 @@ typedef struct /** * @} */ -//±àÒëÆ÷ÉèÖÃÖÐdefine #ifdef USE_STDPERIPH_DRIVER #include "stm32f2xx_conf.h" diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h new file mode 100644 index 000000000..427b22255 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h @@ -0,0 +1,105 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.h + * @author MCD Application Team + * @version V1.1.3 + * @date 05-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F2XX_H +#define __SYSTEM_STM32F2XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F2xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F2xx_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F2XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Release_Notes.html b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Release_Notes.html new file mode 100644 index 000000000..c3d97b13f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Release_Notes.html @@ -0,0 +1,146 @@ + + + + + + + +Release Notes for STM32F2xx CMSIS + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
Back to Release page
+

Release +Notes for STM32F2xx CMSIS

+

Copyright 2012 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F2xx CMSIS +update History
    2. +
  2. License
    3. +
+ +

STM32F2xx CMSIS +update History

V1.1.3 / 05-March-2012

+

Main +Changes

+ +
  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V1.1.2 / 28-December-2011

Main +Changes

+
  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f2xx.h
    • Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST

V1.1.1 / 14-November-2011

Main +Changes

+
  • stm32f2xx.h
    • Add missing bits definition for DAC CR register
    • Add missing bits definition for FSMC BTR1, BTR2, BTR3, BWTR1, BWTR2, BWTR3 and BWTR4 registers
  • Add startup file for TASKING toolchain

V1.1.0 / 23-September-2011

Main +Changes

+
  • stm32f2xx.h
    • Add define for Cortex-M3 revision __CM3_REV
    • Allow +modification of some constants by the application code, definition of +these constants is now bracketed by              #if !defined. The concerned constant are HSE_VALUE, HSI_VALUE and HSE_STARTUP_TIMEOUT.
    • Fix include of stm32f2xx_conf.h file, change "stm32f2xx_conf.h " by "stm32f2xx_conf.h"
    • Correct MII_RMII_SEL bit (in SYSCFG_PMC register) value to 0x00800000
    • Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
    • Correct some bits definition to be in line with naming used in the Reference Manual (RM0033)
      • GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
      • GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
      • SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
      • RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
      • DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
    • GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28

V1.0.0 / 18-April-2011

Main +Changes

+
  • First official release for STM32F2xx devices
  • stm32f2xx.h
    • Add SYSCFG CMPCR register and bits definition 
    • Peripheral register's definitions: add description and address offset of each register
  • Add startup_stm32f2xx.s startup files for "gcc_ride7" and "TrueSTUDIO" compilers

V1.0.0RC1 / 11-March-2011

Main +Changes

+
  • Official version (V1.0.0) Release Candidate 1
  • stm32f2xx.h
    • Update file's header comments
    • Change "RNG_CR_IM" by "RNG_CR_IE"
    • Update "ETH_MACMIIAR_CR" bits definition
  • system_stm32f2xx.c
    • Implement SystemInit_ExtMemCtl() function
    • Change everywhere "STM3220F_EVAL" by "STM322xG_EVAL"
      • Update SystemCoreClockUpdate() function's header comments
+ +
    +
+

License

+ + +

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License. +
+
+

For +complete documentation on STM32 Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/TASKING/cstart_thumb2.asm b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/TASKING/cstart_thumb2.asm new file mode 100644 index 000000000..28f43aab0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/TASKING/cstart_thumb2.asm @@ -0,0 +1,140 @@ + + +;; NOTE: To allow the use of this file for both ARMv6M and ARMv7M, +;; we will only use 16-bit Thumb intructions. + + .extern _lc_ub_stack ; usr/sys mode stack pointer + .extern _lc_ue_stack ; symbol required by debugger + .extern _lc_ub_table ; ROM to RAM copy table + .extern main + .extern _Exit + .extern exit + .weak exit + .global __get_argcv + .weak __get_argcv + .extern __argcvbuf + .weak __argcvbuf + ;;.extern __init_hardware + .extern SystemInit + + .if @defined('__PROF_ENABLE__') + .extern __prof_init + .endif + .if @defined('__POSIX__') + .extern posix_main + .extern _posix_boot_stack_top + .endif + + .global _START + + .section .text.cstart + + .thumb +_START: + ;; anticipate possible ROM/RAM remapping + ;; by loading the 'real' program address + ldr r1,=_Next + bx r1 +_Next: + ;; initialize the stack pointer + ldr r1,=_lc_ub_stack ; TODO: make this part of the vector table + mov sp,r1 + + ;; call a user function which initializes function. + bl SystemInit + + ;; copy initialized sections from ROM to RAM + ;; and clear uninitialized data sections in RAM + + ldr r3,=_lc_ub_table + movs r0,#0 +cploop: + ldr r4,[r3,#0] ; load type + ldr r5,[r3,#4] ; dst address + ldr r6,[r3,#8] ; src address + ldr r7,[r3,#12] ; size + + cmp r4,#1 + beq copy + cmp r4,#2 + beq clear + b done + +copy: + subs r7,r7,#1 + ldrb r1,[r6,r7] + strb r1,[r5,r7] + bne copy + + adds r3,r3,#16 + b cploop + +clear: + subs r7,r7,#1 + strb r0,[r5,r7] + bne clear + + adds r3,r3,#16 + b cploop + +done: + + .if @defined('__POSIX__') + + ;; posix stack buffer for system upbringing + ldr r0,=_posix_boot_stack_top + ldr r0, [r0] + mov sp,r0 + + .else + + ;; load r10 with end of USR/SYS stack, which is + ;; needed in case stack overflow checking is on + ;; NOTE: use 16-bit instructions only, for ARMv6M + ldr r0,=_lc_ue_stack + mov r10,r0 + + .endif + + .if @defined('__PROF_ENABLE__') + bl __prof_init + .endif + + .if @defined('__POSIX__') + ;; call posix_main with no arguments + bl posix_main + .else + ;; retrieve argc and argv (default argv[0]==NULL & argc==0) + bl __get_argcv + ldr r1,=__argcvbuf + ;; call main + bl main + .endif + + ;; call exit using the return value from main() + ;; Note. Calling exit will also run all functions + ;; that were supplied through atexit(). + bl exit + +__get_argcv: ; weak definition + movs r0,#0 + bx lr + + .ltorg + .endsec + + .calls '_START', ' ' + .calls '_START','__init_vector_table' + .if @defined('__PROF_ENABLE__') + .calls '_START','__prof_init' + .endif + .if @defined('__POSIX__') + .calls '_START','posix_main' + .else + .calls '_START','__get_argcv' + .calls '_START','main' + .endif + .calls '_START','exit' + .calls '_START','',0 + + .end diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/TrueSTUDIO/startup_stm32f2xx.s b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/TrueSTUDIO/startup_stm32f2xx.s new file mode 100644 index 000000000..20fd155c6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/TrueSTUDIO/startup_stm32f2xx.s @@ -0,0 +1,514 @@ +/** + ****************************************************************************** + * @file startup_stm32f2xx.s + * @author MCD Application Team + * @version V1.1.3 + * @date 05-March-2012 + * @brief STM32F2xx Devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock and the external SRAM mounted on + * STM322xG-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f2xx.s b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f2xx.s new file mode 100644 index 000000000..95ac1fe1f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f2xx.s @@ -0,0 +1,429 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f2xx.s +;* Author : MCD Application Team +;* Version : V1.1.3 +;* Date : 05-March-2012 +;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the system clock and the external SRAM mounted on +;* STM322xG-EVAL board to be used as data memory (optional, +;* to be enabled by user) +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s new file mode 100644 index 000000000..65757dd85 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc_ride7/startup_stm32f2xx.s @@ -0,0 +1,512 @@ +/** + ****************************************************************************** + * @file startup_stm32f2xx.s + * @author MCD Application Team + * @version V1.1.3 + * @date 05-March-2012 + * @brief STM32F2xx Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the system clock and the external SRAM mounted on + * STM322xG-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f2xx.s b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f2xx.s new file mode 100644 index 000000000..ba2457912 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f2xx.s @@ -0,0 +1,629 @@ +;/******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f2xx.s +;* Author : MCD Application Team +;* Version : V1.1.3 +;* Date : 05-March-2012 +;* Description : STM32F2xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock and the external SRAM mounted on +;* STM322xG-EVAL board to be used as data memory (optional, +;* to be enabled by user) +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:REORDER(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c new file mode 100644 index 000000000..cdc57fbd6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.3 + * @date 05-March-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd new file mode 100644 index 000000000..17ace6a5e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd @@ -0,0 +1,274 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_CM4_SIMD.htm b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_CM4_SIMD.htm new file mode 100644 index 000000000..7275e0ef2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_CM4_SIMD.htm @@ -0,0 +1,3809 @@ + + + + CMSIS: Cortex-M4 SIMD Instructions + + + + + + +

CMSIS Support for Cortex-M4 SIMD Instructions

+ +

This file describes the Cortex-M4 SIMD instructions supported by CMSIS.

+

Version: 1.00 - 25. November 2010

+ +

Information in this file, the accompany manuals, and software is
+ Copyright © ARM Ltd.
All rights reserved. +

+ +
+ +

Revision History

+
    +
  • Revision 0.01 - January 2010: Initial version
    • +
  • Revision 0.02 - June 2010: added __QADD, __QSUB
    • +
  • Revision 1.00 - November 2010:
    • +
+ +
+ +

Contents

+ +
    +
  1. About
    2. +
  2. Cortex-M4 SIMD instruction support
    3. +
  3. Examples
    4. +
+ + + +

 

+

About

+

+ CMSIS provides for the Cortex-M4 a set of functions supporting Cortex-M4 SIMD instructions. +

+ +

 

+

Cortex-M4 SIMD instruction support

+

CMSIS supports the following functions for Cortex-M4 instructions: +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameMnemonicDescription
__SADD8SADD8GE setting quad 8-bit signed addition
__QADD8QADD8Q setting quad 8-bit saturating addition
__SHADD8SHADD8Quad 8-bit signed addition with halved results
__UADD8UADD8GE setting quad 8-bit unsigned addition
__UQADD8UQADD8Quad 8-bit unsigned saturating addition
__UHADD8UHADD8Quad 8-bit unsigned addition with halved results
__SSUB8SSUB8GE setting quad 8-bit signed subtraction
__QSUB8QSUB8Q setting quad 8-bit saturating subtract
__SHSUB8SHSUB8Quad 8-bit signed subtraction with halved results
__USUB8USUB8GE setting quad 8-bit unsigned subtract
__UQSUB8UQSUB8Quad 8-bit unsigned saturating subtraction
__UHSUB8UHSUB8Quad 8-bit unsigned subtraction with halved results
__SADD16SADD16GE setting dual 16-bit signed addition
__QADD16QADD16Q setting dual 16-bit saturating addition
__SHADD16SHADD16Dual 16-bit signed addition with halved results
__UADD16UADD16GE setting dual 16-bit unsigned addition
__UQADD16UQADD16Dual 16-bit unsigned saturating addition
__UHADD16UHADD16Dual 16-bit unsigned addition with halved results
__SSUB16SSUB16GE setting dual 16-bit signed subtraction
__QSUB16QSUB16Q setting dual 16-bit saturating subtract
__SHSUB16SHSUB16Dual 16-bit signed subtraction with halved results
__USUB16USUB16GE setting dual 16-bit unsigned subtract
__UQSUB16UQSUB16Dual 16-bit unsigned saturating subtraction
__UHSUB16UHSUB16Dual 16-bit unsigned subtraction with halved results
__SASXSASXGE setting dual 16-bit addition and subtraction with exchange
__QASXQASXQ setting dual 16-bit add and subtract with exchange
__SHASXSHASXDual 16-bit signed addition and subtraction with halved results
__UASXUASXGE setting dual 16-bit unsigned addition and subtraction with exchange
__UQASXUQASXDual 16-bit unsigned saturating addition and subtraction with exchange
__UHASXUHASXDual 16-bit unsigned addition and subtraction with halved results and exchange
__SSAXSSAXGE setting dual 16-bit signed subtraction and addition with exchange
__QSAXQSAXQ setting dual 16-bit subtract and add with exchange
__SHSAXSHSAXDual 16-bit signed subtraction and addition with halved results
__USAXUSAXGE setting dual 16-bit unsigned subtract and add with exchange
__UQSAXUQSAXDual 16-bit unsigned saturating subtraction and addition with exchange
__UHSAXUHSAXDual 16-bit unsigned subtraction and addition with halved results and exchange
__USAD8USAD8Unsigned sum of quad 8-bit unsigned absolute difference
__USADA8USADA8Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate
__SSAT16SSAT16Q setting dual 16-bit saturate
__USAT16USAT16Q setting dual 16-bit unsigned saturate
__UXTB16UXTB16Dual extract 8-bits and zero-extend to 16-bits
__UXTAB16UXTAB16Extracted 16-bit to 32-bit unsigned addition
__SXTB16SXTB16Dual extract 8-bits and sign extend each to 16-bits
__SXTAB16SXTAB16Dual extracted 8-bit to 16-bit signed addition
__SMUADSMUADQ setting sum of dual 16-bit signed multiply
__SMUADXSMUADXQ setting sum of dual 16-bit signed multiply with exchange
__SMLADSMLADQ setting dual 16-bit signed multiply with single 32-bit accumulator
__SMLADXSMLADXQ setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator
__SMLALDSMLALDDual 16-bit signed multiply with single 64-bit accumulator
__SMLALDXSMLALDXDual 16-bit signed multiply with exchange with single 64-bit accumulator
__SMUSDSMUSDDual 16-bit signed multiply returning difference
__SMUSDXSMUSDXDual 16-bit signed multiply with exchange returning difference
__SMLSDSMLSDQ setting dual 16-bit signed multiply subtract with 32-bit accumulate
__SMLSDXSMLSDXQ setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate
__SMLSLDSMLSLDQ setting dual 16-bit signed multiply subtract with 64-bit accumulate
__SMLSLDXSMLSLDXQ setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate
__SELSELSelect bytes based on GE bits
__QADDQADDQ setting saturating add
__QSUBQSUB/td> + Q setting saturating subtract
+ + + + +

Function __SADD8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SADD8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four 8-bit signed integer additions.
+ The GE bits in the APSR are set according to the results of the additions. +
Parameter +
    +
  • val1: first four 8-bit summands.
    • +
  • val2: second four 8-bit summands.
    • +
+
Return Value +

The function returns:

+
    +
  • the addition of the first bytes from each operand, in the first byte of the return value.
    • +
  • the addition of the second bytes of each operand, in the second byte of the return value.
    • +
  • the addition of the third bytes of each operand, in the third byte of the return value.
    • +
  • the addition of the fourth bytes of each operand, in the fourth byte of the return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation.
+ If res is the return value, then: +

+
    +
  • if res[7:0] ≥ 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0
    • +
+
Operation + 
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]
+
+ +

Function __QADD8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __QADD8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four 8-bit integer additions, saturating the results to + the 8-bit signed integer range -27 ≤ x ≤ 27 - 1. +
Parameter +
    +
  • val1: first four 8-bit summands.
    • +
  • val2: second four 8-bit summands.
    • +
+
Return Value +

The function returns:

+
    +
  • the saturated addition of the first byte of each operand in the first byte of the return value.
    • +
  • the saturated addition of the second byte of each operand in the second byte of the return value.
    • +
  • the saturated addition of the third byte of each operand in the third byte of the return value.
    • +
  • the saturated addition of the fourth byte of each operand in the fourth byte of the return value.
    • +
+

The returned results are saturated to the 16-bit signed integer range -27 ≤ x ≤ 27 - 1. +

+
Operation + 
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]
+
+ +

Function __SHADD8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SHADD8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four signed 8-bit integer additions, halving the results. +
Parameter +
    +
  • val1: first four 8-bit summands.
    • +
  • val2: second four 8-bit summands.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved addition of the first bytes from each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes from each operand, in the second byte of the return value.
    • +
  • the halved addition fo the third bytes from each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • +
+
Operation + 
+res[7:0]   = (val1[7:0]   + val2[7:0])   >> 1
+res[15:8]  = (val1[15:8]  + val2[15:8])  >> 1
+res[23:16] = (val1[23:16] + val2[23:16]) >> 1
+res[31:24] = (val1[31:24] + val2[31:24]) >> 1
+
+ +

Function __UADD8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UADD8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four unsigned 8-bit integer additions.
+ The GE bits in the APSR are set according to the results. +
Parameter +
    +
  • val1: first four 8-bit summands for each addition.
    • +
  • val2: second four 8-bit summands for each addition.
    • +
+
Return Value +

The function returns:

+
    +
  • the addition of the first bytes in each operand, in the first byte of the return value.
    • +
  • the addition of the second bytes in each operand, in the second byte of the return value.
    • +
  • the addition of the third bytes in each operand, in the third byte of the return value.
    • +
  • the addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation.
+ If res is the return value, then: +

+
    +
  • if res[7:0] ≥ 0x100 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] ≥ 0x100 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] ≥ 0x100 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] ≥ 0x100 then APSR.GE[3] = 1 else 0
    • +
+
Operation + 
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]
+
+ +

Function __UQADD8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UQADD8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four unsigned 8-bit integer additions, saturating the + results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1. +
Parameter +
    +
  • val1: first four 8-bit summands.
    • +
  • val2: second four 8-bit summands.
    • +
+
Return Value +

The function returns:

+
    +
  • the addition of the first bytes in each operand, in the first byte of the return value.
    • +
  • the addition of the second bytes in each operand, in the second byte of the return value.
    • +
  • the addition of the third bytes in each operand, in the third byte of the return value.
    • +
  • the addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • +
+

The results are saturated to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1. +

+
Operation + 
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]
+
+ +

Function __UHADD8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UHADD8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four unsigned 8-bit integer additions, halving the results. +
Parameter +
    +
  • val1: first four 8-bit summands.
    • +
  • val2: second four 8-bit summands.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved addition of the first bytes in each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes in each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes in each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • +
+
Operation + 
+res[7:0]   = (val1[7:0]   + val2[7:0])   >> 1
+res[15:8]  = (val1[15:8]  + val2[15:8])  >> 1
+res[23:16] = (val1[23:16] + val2[23:16]) >> 1
+res[31:24] = (val1[31:24] + val2[31:24]) >> 1
+
+ +

Function __SSUB8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SSUB8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four 8-bit signed integer subtractions.
+ The GE bits in the APSR are set according to the results. +
Parameter +
    +
  • val1: first four 8-bit operands of each subtraction.
    • +
  • val2: second four 8-bit operands of each subtraction.
    • +
+
Return Value +

The function returns:

+
    +
  • the subtraction of the first byte in the second operand from the first byte in the + first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in + the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the + first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in + the first operand, in the fourth byte of the return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation. If res is the return value, then: +

+
    +
  • if res[8:0] ≥ 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0
    • +
+
Operation + 
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]
+
+ +

Function __QSUB8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __QADD8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four 8-bit integer subtractions, saturating the results + to the 8-bit signed integer range -27 ≤ x ≤ 27 - 1. +
Parameter +
    +
  • val1: first four 8-bit operands.
    • +
  • val2: second four 8-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the subtraction of the first byte in the second operand from the first byte in the + first operand, in the first byte of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in + the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the + first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in + the first operand, in the fourth byte of the return value.
    • +
+

The returned results are saturated to the 8-bit signed integer range -27 ≤ x ≤ 27 - 1. +

+
Operation + 
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]
+
+ +

Function __SHSUB8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SHSUB8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four signed 8-bit integer subtractions, halving the + results. +
Parameter +
    +
  • val1: first four 8-bit operands.
    • +
  • val2: second four 8-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved subtraction of the first byte in the second operand from the first byte + in the first operand, in the first byte of the return value.
    • +
  • the halved subtraction of the second byte in the second operand from the second + byte in the first operand, in the second byte of the return value.
    • +
  • the halved subtraction of the third byte in the second operand from the third byte + in the first operand, in the third byte of the return value.
    • +
  • the halved subtraction of the fourth byte in the second operand from the fourth + byte in the first operand, in the fourth byte of the return value.
    • +
+
Operation + 
+res[7:0]   = (val1[7:0]   - val2[7:0])  >> 1
+res[15:8]  = (val1[15:8]  - val2[15:8]) >> 1
+res[23:16] = (val1[23:16] - val2[23:16] >> 1
+res[31:24] = (val1[31:24] - val2[31:24] >> 1
+
+ +

Function __USUB8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __USUB8(uint32_t val1, uint32_t val2);
+
DescriptionThis function It enables you to perform four 8-bit unsigned integer subtractions.
+ The GE bits in the APSR are set according to the results. +
Parameter +
    +
  • val1: first four 8-bit operands.
    • +
  • val2: second four 8-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the subtraction of the first byte in the second operand from the first byte in the + first operand, in the first byte of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in + the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the + first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in + the first operand, in the fourth byte of the return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation.
+ If res is the return value, then: +

+
    +
  • if res[7:0] ≥ 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0
    • +
+
Operation + 
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]
+
+ +

Function __UQSUB8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UQSUB8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four unsigned 8-bit integer subtractions, saturating + the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1. +
Parameter +
    +
  • val1: first four 8-bit operands.
    • +
  • val2: second four 8-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the subtraction of the first byte in the second operand from the first byte in the + first operand, in the first byte of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in + the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the + first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in + the first operand, in the fourth byte of the return value.
    • +
+

The results are saturated to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1. +

+
Operation + 
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]
+
+ +

Function __UHSUB8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UHSUB8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four unsigned 8-bit integer subtractions, halving the + results. +
Parameter +
    +
  • val1: first four 8-bit operands.
    • +
  • val2: second four 8-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved subtraction of the first byte in the second operand from the first byte + in the first operand, in the first byte of the return value.
    • +
  • the halved subtraction of the second byte in the second operand from the second + byte in the first operand, in the second byte of the return value.
    • +
  • the halved subtraction of the third byte in the second operand from the third byte + in the first operand, in the third byte of the return value.
    • +
  • the halved subtraction of the fourth byte in the second operand from the fourth + byte in the first operand, in the fourth byte of the return value.
    • +
+
Operation + 
+res[7:0]   = (val1[7:0]   - val2[7:0])   >> 1
+res[15:8]  = (val1[15:8]  - val2[15:8])  >> 1
+res[23:16] = (val1[23:16] - val2[23:16]) >> 1
+res[31:24] = (val1[31:24] - val2[31:24]) >> 1
+
+ +

Function __SADD16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SADD16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two 16-bit signed integer additions.
+ The GE bits in the APSR are set according to the results of the additions. +
Parameter +
    +
  • val1: first two 16-bit summands.
    • +
  • val2: second two 16-bit summands.
    • +
+
Return Value +

The function returns:

+
    +
  • the addition of the low halfwords in the low halfword of the return value.
    • +
  • the addition of the high halfwords in the high halfword of the return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation.
+ If res is the return value, then: +

+
    +
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • +
+
Operation + 
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]
+
+ +

Function __QADD16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __QADD16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two 16-bit integer arithmetic additions in parallel, + saturating the results to the 16-bit signed integer range -215 ≤ x ≤ 215 - 1. +
Parameter +
    +
  • val1: first two 16-bit summands.
    • +
  • val2: second two 16-bit summands.
    • +
+
Return Value +

The function returns:

+
    +
  • the saturated addition of the low halfwords in the low halfword of the return value.
    • +
  • the saturated addition of the high halfwords in the high halfword of the return value.
    • +
+

The returned results are saturated to the 16-bit signed integer + range -215 ≤ x ≤ 215 - 1 +

+
Operation + 
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[16:31] = val1[31:16] + val2[31:16]
+
+ +

Function __SHADD16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SHADD16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two signed 16-bit integer additions, halving the + results. +
Parameter +
    +
  • val1: first two 16-bit summands.
    • +
  • val2: second two 16-bit summands.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved addition of the low halfwords from each operand, in the low halfword + of the return value.
    • +
  • the halved addition of the high halfwords from each operand, in the high halfword + of the return value.
    • +
+
Operation + 
+res[15:0]  = (val1[15:0]  + val2[15:0])  >> 1
+res[31:16] = (val1[31:16] + val2[31:16]) >> 1
+
+ +

Function __UADD16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UADD16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two 16-bit unsigned integer additions.
+ The GE bits in the APSR are set according to the results. +
Parameter +
    +
  • val1: first two 16-bit summands for each addition.
    • +
  • val2: second two 16-bit summands for each addition.
    • +
+
Return Value +

The function returns:

+
    +
  • the addition of the low halfwords in each operand, in the low halfword of the + return value.
    • +
  • the addition of the high halfwords in each operand, in the high halfword of the + return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation.
+ If res is the return value, then: +

+
    +
  • if res[15:0] ≥ 0x10000 then APSR.GE[0] = 11 else 00
    • +
  • if res[31:16] ≥ 0x10000 then APSR.GE[1] = 11 else 00
    • +
+
Operation + 
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]
+
+ +

Function __UQADD16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UQADD16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two unsigned 16-bit integer additions, saturating the + results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1. +
Parameter +
    +
  • val1: first two 16-bit summands.
    • +
  • val2: second two 16-bit summands.
    • +
+
Return Value +

The function returns:

+
    +
  • the addition of the low halfword in the first operand and the low halfword in the + second operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the high halfword in the + second operand, in the high halfword of the return value.
    • +
+

The results are saturated to the 16-bit unsigned integer + range 0 ≤ x ≤ 216 - 1. +

+
Operation + 
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]
+
+ +

Function __UHADD16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UHADD16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two unsigned 16-bit integer additions, halving the + results. +
Parameter +
    +
  • val1: first two 16-bit summands.
    • +
  • val2: second two 16-bit summands.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved addition of the low halfwords in each operand, in the low halfword of + the return value.
    • +
  • the halved addition of the high halfwords in each operand, in the high halfword + of the return value.
    • +
+
Operation + 
+res[15:0]  = (val1[15:0]  + val2[15:0])  >> 1
+res[31:16] = (val1[31:16] + val2[31:16]) >> 1
+
+ +

Function __SSUB16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SSUB16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two 16-bit signed integer subtractions.
+ The GE bits in the APSR are set according to the results. +
Parameter +
    +
  • val1: first two 16-bit operands of each subtraction.
    • +
  • val2: second two 16-bit operands of each subtraction.
    • +
+
Return Value +

The function returns:

+
    +
  • the subtraction of the low halfword in the second operand from the low halfword + in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword + in the first operand, in the high halfword of the return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation.
+ If res is the return value, then: +

+
    +
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • +
+
Operation + 
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]
+
+ +

Function __QSUB16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __QSUB16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two 16-bit integer subtractions, saturating the + results to the 16-bit signed integer range -215 ≤ x ≤ 215 - 1. +
Parameter +
    +
  • val1: first two 16-bit operands.
    • +
  • val2: second two 16-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the saturated subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the returned result.
    • +
  • the saturated subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the returned result.
    • +
+

The returned results are saturated to the 16-bit signed integer + range -215 ≤ x ≤ 215 - 1. +

+
Operation + 
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]
+
+ +

Function __SHSUB16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SHSUB16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two signed 16-bit integer subtractions, halving the + results. +
Parameter +
    +
  • val1: first two 16-bit operands.
    • +
  • val2: second two 16-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value.
    • +
+
Operation + 
+res[15:0]  = (val1[15:0]  - val2[15:0])  >> 1
+res[31:16] = (val1[31:16] - val2[31:16]) >> 1
+
+ +

Function __USUB16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __USUB16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two 16-bit unsigned integer subtractions.
+ The GE bits in the APSR are set according to the results. +
Parameter +
    +
  • val1: first two 16-bit operands.
    • +
  • val2: second two 16-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the subtraction of the low halfword in the second operand from the low halfword + in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword + in the first operand, in the high halfword of the return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation.
+ If res is the return value, then: +

+
    +
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • +
+
Operation + 
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]
+
+ +

Function __UQSUB16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UQSUB16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two unsigned 16-bit integer subtractions, saturating + the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1. +
Parameter +
    +
  • val1: first two 16-bit operands for each subtraction.
    • +
  • val2: second two 16-bit operands for each subtraction.
    • +
+
Return Value +

The function returns:

+
    +
  • the subtraction of the low halfword in the second operand from the low halfword + in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword + in the first operand, in the high halfword of the return value.
    • +
+

The results are saturated to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1. +

+
Operation + 
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]
+
+ +

Function __UHSUB16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UHSUB16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two unsigned 16-bit integer subtractions, halving + the results. +
Parameter +
    +
  • val1: first two 16-bit operands.
    • +
  • val2: second two 16-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved subtraction of the low halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the high halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value.
    • +
+
Operation + 
+res[15:0]  = (val1[15:0]  - val2[15:0])  >> 1
+res[31:16] = (val1[31:16] - val2[31:16]) >> 1
+
+ +

Function __SASX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SASX(uint32_t val1, uint32_t val2);
+
DescriptionThis function inserts an SASX instruction into the instruction stream generated by the + compiler. It enables you to exchange the halfwords of the second operand, add the high + halfwords and subtract the low halfwords.
+ The GE bits in the APRS are set according to the results. +
Parameter +
    +
  • val1: first operand for the subtraction in the low halfword, and the + first operand for the addition in the high halfword.
    • +
  • val2: second operand for the subtraction in the high halfword, and the + second operand for the addition in the low halfword.
    • +
+
Return Value +

The function returns:

+
    +
  • the subtraction of the high halfword in the second operand from the low halfword + in the first operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the low halfword in the + second operand, in the high halfword of the return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation.
+ If res is the return value, then: +

+
    +
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • +
+
Operation + 
+res[15:0]  = val1[15:0] - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]
+
+ +

Function __QASX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __QASX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to exchange the halfwords of the one operand, then add the high + halfwords and subtract the low halfwords, saturating the results to the 16-bit signed + integer range -215 ≤ x ≤ 215 - 1. +
Parameter +
    +
  • val1: first operand for the subtraction in the low halfword, and the + first operand for the addition in the high halfword.
    • +
  • val2: second operand for the subtraction in the high halfword, and the + second operand for the addition in the low halfword.
    • +
+
Return Value +

The function returns:

+
    +
  • the saturated subtraction of the high halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value.
    • +
  • the saturated addition of the high halfword in the first operand and the low + halfword in the second operand, in the high halfword of the return value.
    • +
+

The returned results are saturated to the 16-bit signed integer + range -215 ≤ x ≤ 215 - 1. +

+
Operation + 
+res[15:0]  = val1[15:0]  - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]
+
+ +

Function __SHASX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SHASX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to exchange the two halfwords of one operand, perform one + signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results. +
Parameter +
    +
  • val1: first 16-bit operands.
    • +
  • val2: second 16-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved subtraction of the high halfword in the second operand from the low + halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value.
    • +
+
Operation + 
+res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0])  >> 1
+
+ +

Function __UASX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UASX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to exchange the two halfwords of the second operand, add the + high halfwords and subtract the low halfwords.
+ The GE bits in the APSR are set according to the results. +
Parameter +
    +
  • val1: first operand for the subtraction in the low halfword, and the + first operand for the addition in the high halfword.
    • +
  • val2: second operand for the subtraction in the high halfword and the + second operand for the addition in the low halfword.
    • +
+
Return Value +

The function returns:

+
    +
  • the subtraction of the high halfword in the second operand from the low halfword + in the first operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the low halfword in the + second operand, in the high halfword of the return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation.
+ If res is the return value, then: +

+
    +
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] ≥ 0x10000 then APSR.GE[3:2] = 11 else 00
    • +
+
Operation + 
+res[15:0]  = val1[15:0]  - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]
+
+ +

Function __UQASX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UQASX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to exchange the halfwords of the second operand and perform + one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the + results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1. +
Parameter +
    +
  • val1: first two 16-bit operands.
    • +
  • val2: second two 16-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the subtraction of the high halfword in the second operand from the low halfword + in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword + in the first operand, in the high halfword of the return value.
    • +
+

The results are saturated to the 16-bit unsigned integer + range 0 ≤ x ≤ 216 - 1. +

+
Operation + 
+res[15:0]  = val1[15:0]  - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]
+
+ +

Function __UHASX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UHASX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to exchange the halfwords of the second operand, add the high + halfwords and subtract the low halfwords, halving the results. +
Parameter +
    +
  • val1: first operand for the subtraction in the low halfword, and the + first operand for the addition in the high halfword.
    • +
  • val2: second operand for the subtraction in the high halfword, and the + second operand for the addition in the low halfword.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved subtraction of the high halfword in the second operand from the low + halfword in the first operand.
    • +
  • the halved addition of the high halfword in the first operand and the low halfword + in the second operand.
    • +
+
Operation + 
+res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1
+res[31:16] = (val1[31:16] + val2[15:0])  >> 1
+
+ +

Function __SSAX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SSAX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to exchange the two halfwords of one operand and perform one + 16-bit integer subtraction and one 16-bit addition.
+ The GE bits in the APSR are set according to the results. +
Parameter +
    +
  • val1: first operand for the addition in the low halfword, and the first + operand for the subtraction in the high halfword.
    • +
  • val2: second operand for the addition in the high halfword, and the + second operand for the subtraction in the low halfword.
    • +
+
Return Value +

The function returns:

+
    +
  • the addition of the low halfword in the first operand and the high halfword in the + second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword + in the first operand, in the high halfword of the return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation.
+ If res is the return value, then: +

+
    +
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • +
+
Operation + 
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]
+
+ +

Function __QSAX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __QSAX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to exchange the halfwords of one operand, then subtract the + high halfwords and add the low halfwords, saturating the results to the 16-bit signed + integer range -215 ≤ x ≤ 215 - 1. +
Parameter +
    +
  • val1: first operand for the addition in the low halfword, and the first + operand for the subtraction in the high halfword.
    • +
  • val2: second operand for the addition in the high halfword, and the + second operand for the subtraction in the low halfword.
    • +
+
Return Value +

The function returns:

+
    +
  • the saturated addition of the low halfword of the first operand and the high + halfword of the second operand, in the low halfword of the return value.
    • +
  • the saturated subtraction of the low halfword of the second operand from the high + halfword of the first operand, in the high halfword of the return value.
    • +
+

The returned results are saturated to the 16-bit signed integer + range -215 ≤ x ≤ 215 - 1. +

+
Operation + 
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]
+
+ +

Function __SHSAX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SHSAX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to exchange the two halfwords of one operand, perform one + signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results. +
Parameter +
    +
  • val1: first 16-bit operands.
    • +
  • val2: second 16-bit operands.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved addition of the low halfword in the first operand and the high halfword + in the second operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value.
    • +
+
Operation + 
+res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0])  >> 1
+
+ +

Function __USAX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __USAX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to exchange the halfwords of the second operand, subtract the + high halfwords and add the low halfwords.
+ The GE bits in the APSR are set according to the results. +
Parameter +
    +
  • val1: first operand for the addition in the low halfword, and the first + operand for the subtraction in the high halfword.
    • +
  • val2: second operand for the addition in the high halfword, and the + second operand for the subtraction in the low halfword.
    • +
+
Return Value +

The function returns:

+
    +
  • the addition of the low halfword in the first operand and the high halfword in the + second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword + in the first operand, in the high halfword of the return value.
    • +
+

Each bit in APSR.GE is set or cleared for each byte in the return value, depending on + the results of the operation.
+ If res is the return value, then: +

+
    +
  • if res[15:0] ≥ 0x10000 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • +
+
Operation + 
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]
+
+ +

Function __UQSAX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UQSAX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to exchange the halfwords of the second operand and perform + one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the + results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1. +
Parameter +
    +
  • val1: first 16-bit operand for the addition in the low halfword, and the + first 16-bit operand for the subtraction in the high halfword.
    • +
  • val2: second 16-bit halfword for the addition in the high halfword, + and the second 16-bit halfword for the subtraction in the low halfword.
    • +
+
Return Value +

The function returns:

+
    +
  • the addition of the low halfword in the first operand and the high halfword in the + second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword + in the first operand, in the high halfword of the return value.
    • +
+

The results are saturated to the 16-bit unsigned integer + range 0 ≤ x ≤ 216 - 1. +

+
Operation + 
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]
+
+ +

Function __UHSAX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UHSAX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to exchange the halfwords of the second operand, subtract the + high halfwords and add the low halfwords, halving the results. +
Parameter +
    +
  • val1: first operand for the addition in the low halfword, and the first + operand for the subtraction in the high halfword.
    • +
  • val2: second operand for the addition in the high halfword, and the + second operand for the subtraction in the low halfword.
    • +
+
Return Value +

The function returns:

+
    +
  • the halved addition of the high halfword in the second operand and the low + halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high + halfword in the first operand, in the high halfword of the return value.
    • +
+
Operation + 
+res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0])  >> 1
+
+ +

Function __USAD8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __USAD8(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform four unsigned 8-bit subtractions, and add the + absolute values of the differences together, returning the result as a single unsigned + integer. +
Parameter +
    +
  • val1: first four 8-bit operands for the subtractions.
    • +
  • val2: second four 8-bit operands for the subtractions.
    • +
+
Return Value +

The function returns the sum of the absolute differences of:

+
    +
  • the subtraction of the first byte in the second operand from the first byte in the + first operand.
    • +
  • the subtraction of the second byte in the second operand from the second byte in + the first operand.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the + first operand.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in + the first operand.
    • +
+

The sum is returned as a single unsigned integer.

+
Operation + 
+absdiff1  = val1[7:0]   - val2[7:0]
+absdiff2  = val1[15:8]  - val2[15:8]
+absdiff3  = val1[23:16] - val2[23:16]
+absdiff4  = val1[31:24] - val2[31:24]
+res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4
+
+ +

Function __USADA8

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __USADA8(uint32_t val1, uint32_t val2, uint32_t val3);
+
DescriptionThis function enables you to perform four unsigned 8-bit subtractions, and add the + absolute values of the differences to a 32-bit accumulate operand. +
Parameter +
    +
  • val1: first four 8-bit operands for the subtractions.
    • +
  • val2: second four 8-bit operands for the subtractions.
    • +
  • val3: accumulation value.
    • +
+
Return Value +

The function returns the sum of the absolute differences of the following + bytes, added to the accumulation value:

+
    +
  • the subtraction of the first byte in the second operand from the first byte in the + first operand.
    • +
  • the subtraction of the second byte in the second operand from the second byte in + the first operand.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the + first operand.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in + the first operand.
    • +
+
Operation + 
+absdiff1  = val1[7:0]   - val2[7:0]
+absdiff2  = val1[15:8]  - val2[15:8]
+absdiff3  = val1[23:16] - val2[23:16]
+absdiff4  = val1[31:24] - val2[31:24]
+sum       = absdiff1 + absdiff2 + absdiff3 + absdiff4
+res[31:0] = sum[31:0] + val3[31:0]
+
+ +

Function __SSAT16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SSAT16(uint32_t val1, const uint32_t val2);
+
DescriptionThis function enables you to saturate two signed 16-bit values to a selected signed range.
+ The Q bit is set if either operation saturates. +
Parameter +
    +
  • val1: two signed 16-bit values to be saturated.
    • +
  • val2: bit position for saturation, an integral constant expression in the + range 1 to 16.
    • +
+
Return Value +

The function returns:

+
    +
  • the signed saturation of the low halfword in val1, saturated to the bit position + specified in val2 and returned in the low halfword of the return value.
    • +
  • the signed saturation of the high halfword in val1, saturated to the bit position + specified in val2 and returned in the high halfword of the return value.
    • +
+
Operation + 
+Saturate halfwords in val1 to the signed range specified by the bit position in val2
+
+ +

Function __USAT16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __USAT16(uint32_t val1, const uint32_t val2);
+
DescriptionThis function enables you to saturate two signed 16-bit values to a selected unsigned + range.
+ The Q bit is set if either operation saturates. +
Parameter +
    +
  • val1: two 16-bit values that are to be saturated.
    • +
  • val2: bit position for saturation, and must be an integral constant + expression in the range 0 to 15.
    • +
+
Return Value +

The function returns the saturation of the two signed 16-bit values, as non-negative values.

+
    +
  • the saturation of the low halfword in val1, saturated to the bit position + specified in val2 and returned in the low halfword of the return value.
    • +
  • the saturation of the high halfword in val1, saturated to the bit position + specified in val2 and returned in the high halfword of the return value.
    • +
+
Operation + 
+Saturate halfwords in val1 to the unsigned range specified by the bit position in val2
+
+ +

Function __UXTB16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UXTB16(uint32_t val);
+
DescriptionThis function enables you to extract two 8-bit values from an operand and zero-extend + them to 16 bits each. +
Parameter +
    +
  • val1: two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
    • +
+
Return Value +

The function returns the 8-bit values zero-extended to 16-bit values.

+
    +
  • zero-extended value of val[7:0] in the low halfword of the return value.
    • +
  • zero-extended value of val[23:16] in the high halfword of the return value.
    • +
+
Operation + 
+res[15:0]  = ZeroExtended(val[7:0]  )
+res[31:16] = ZeroExtended(val[23:16])
+
+ +

Function __UXTAB16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __UXTAB16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to extract two 8-bit values from one operand, zero-extend them + to 16 bits each, and add the results to two 16-bit values from another operand. +
Parameter +
    +
  • val1: value added to the zero-extended to 16-bit values.
    • +
  • val2: two 8-bit values to be extracted and zero-extended.
    • +
+
Return Value +

The function returns the 8-bit values in val2, zero-extended to 16-bit values + and added to val1.

+
Operation + 
+res[15:0]  = ZeroExt(val2[7:0]   to 16 bits) + val1[15:0]
+res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
+
+ +

Function __SXTB16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SXTB16(uint32_t val);
+
DescriptionThis function enables you to extract two 8-bit values from an operand and sign-extend + them to 16 bits each. +
Parameter +
    +
  • val1: two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
    • +
+
Return Value +

The function returns the 8-bit values sign-extended to 16-bit values.

+
    +
  • sign-extended value of val[7:0] in the low halfword of the return value.
    • +
  • sign-extended value of val[23:16] in the high halfword of the return value.
    • +
+
Operation + 
+res[15:0]  = SignExtended(val[7:0]
+res[31:16] = SignExtended(val[23:16]
+
+ +

Function __SXTAB16

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SXTAB16(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to extract two 8-bit values from the second operand (at bit + positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the + first operand. +
Parameter +
    +
  • val1: values added to the zero-extended to 16-bit values.
    • +
  • val2: two 8-bit values to be extracted and zero-extended.
    • +
+
Return Value +

The function returns the addition of val1 and val2, where the 8-bit values in + val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.

+
Operation + 
+res[15:0]  = val1[15:0]  + SignExtended(val2[7:0])
+res[31:16] = val1[31:16] + SignExtended(val2[23:16])
+
+ +

Function __SMUAD

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SMUAD(uint32_t val1, uint32_t val2);
+
DescriptionThis function It enables you to perform two 16-bit signed multiplications, adding the + products together.
+ The Q bit is set if the addition overflows. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
+
Return Value +

The function returns the sum of the products of the two 16-bit signed multiplications.

+
Operation + 
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 + p2
+
+ +

Function __SMUADX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SMUADX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two 16-bit signed multiplications with exchanged + halfwords of the second operand, adding the products together.
+ The Q bit is set if the addition overflows. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
+
Return Value +

The function returns the sum of the products of the two 16-bit signed multiplications with exchanged + halfwords of the second operand.

+
Operation + 
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 + p2
+
+ +

Function __SMLAD

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SMLAD(uint32_t val1, uint32_t val2, uint32_t val3);
+
DescriptionThis function enables you to perform two signed 16-bit multiplications, adding both + results to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
  • val2: accumulate value.
    • +
+
Return Value +

The function returns the product of each multiplication added to the accumulate + value, as a 32-bit integer.

+
Operation + 
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 + p2 + val3[31:0]
+
+ +

Function __SMLADX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SMLADX(uint32_t val1, uint32_t val2, uint32_t val3);
+
DescriptionThis function enables you to perform two signed 16-bit multiplications with exchanged + halfwords of the second operand, adding both results to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
  • val2: accumulate value.
    • +
+
Return Value +

The function returns the product of each multiplication with exchanged + halfwords of the second operand added to the accumulate value, as a 32-bit integer.

+
Operation + 
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 + p2 + val3[31:0]
+
+ +

Function __SMLALD

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint64_t __SMLALD(uint32_t val1, uint32_t val2, uint64_t val3);
+
DescriptionThis function enables you to perform two signed 16-bit multiplications, adding both + results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit + addition. This overflow is not detected if it occurs. Instead, the result wraps around + modulo264. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
  • val2: accumulate value.
    • +
+
Return Value +

The function returns the product of each multiplication added to the accumulate value.

+
Operation + 
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+sum = p1 + p2 + val3[63:32][31:0]
+res[63:32] = sum[63:32]
+res[31:0]  = sum[31:0]
+
+ +

Function __SMLALDX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+unsigned long long __SMLALDX(uint32_t val1, uint32_t val2, unsigned long long val3);
+
DescriptionThis function enables you to exchange the halfwords of the second operand, and perform + two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. + Overflow is only possible as a result of the 64-bit addition. This overflow is not detected + if it occurs. Instead, the result wraps around modulo264. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
  • val2: accumulate value.
    • +
+
Return Value +

The function returns the product of each multiplication added to the accumulate value.

+
Operation + 
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+sum = p1 + p2 + val3[63:32][31:0]
+res[63:32] = sum[63:32]
+res[31:0] = sum[31:0]
+
+ +

Function __SMUSD

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SMUSD(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two 16-bit signed multiplications, taking the + difference of the products by subtracting the high halfword product from the low + halfword product. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
+
Return Value +

The function returns the difference of the products of the two 16-bit signed multiplications.

+
Operation + 
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 - p2
+
+ +

Function __SMUSDX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SMUSDX(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to perform two 16-bit signed multiplications, subtracting one + of the products from the other. The halfwords of the second operand are exchanged + before performing the arithmetic. This produces top * bottom and bottom * top + multiplication. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
+
Return Value +

The function returns the difference of the products of the two 16-bit signed multiplications.

+
Operation + 
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 - p2
+
+ +

Function __SMLSD

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SMLSD(uint32_t val1, uint32_t val2, uint32_t val3);
+
DescriptionThis function enables you to perform two 16-bit signed multiplications, take the + difference of the products, subtracting the high halfword product from the low halfword + product, and add the difference to a 32-bit accumulate operand.
+ The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the + subtraction. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
  • val3: accumulate value.
    • +
+
Return Value +

The function returns the difference of the product of each multiplication, added + to the accumulate value.

+
Operation + 
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 - p2 + val3[31:0]
+
+ +

Function __SMLSDX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SMLSDX(uint32_t val1, uint32_t val2, uint32_t val3);
+
DescriptionThis function enables you to exchange the halfwords in the second operand, then perform + two 16-bit signed multiplications. The difference of the products is added to a 32-bit + accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
  • val3: accumulate value.
    • +
+
Return Value +

The function returns the difference of the product of each multiplication, added + to the accumulate value.

+
Operation + 
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 - p2 + val3[31:0]
+
+ +

Function __SMLSLD

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint64_t __SMLSLD(uint32_t val1, uint32_t val2, uint64_t val3);
+
DescriptionThis function It enables you to perform two 16-bit signed multiplications, take the + difference of the products, subtracting the high halfword product from the low halfword + product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur + during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit + addition, and this overflow is not detected. Instead, the result wraps round to + modulo264. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
  • val3: accumulate value.
    • +
+
Return Value +

The function returns the difference of the product of each multiplication, + added to the accumulate value.

+
Operation + 
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[63:0] = p1 - p2 + val3[63:0]
+
+ +

Function __SMLSLDX

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+unsigned long long __SMLSLDX(uint32_t val1, uint32_t val2, unsigned long long val3);
+
DescriptionThis function enables you to exchange the halfwords of the second operand, perform two + 16-bit multiplications, adding the difference of the products to a 64-bit accumulate + operand. Overflow cannot occur during the multiplications or the subtraction. Overflow + can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, + the result wraps round to modulo264. +
Parameter +
    +
  • val1: first 16-bit operands for each multiplication.
    • +
  • val2: second 16-bit operands for each multiplication.
    • +
  • val3: accumulate value.
    • +
+
Return Value +

The function returns the difference of the product of each multiplication, + added to the accumulate value.

+
Operation + 
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[63:0] = p1 - p2 + val3[63:0]
+
+ + +

Function __SEL

+ + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __SEL(uint32_t val1, uint32_t val2);
+
DescriptionThis function inserts a SEL instruction into the instruction stream generated by the + compiler. It enables you to select bytes from the input parameters, whereby the bytes + that are selected depend upon the results of previous SIMD instruction function. The + results of previous SIMD instruction function are represented by the Greater than or + Equal flags in the Application Program Status Register (APSR). + The __SEL function works equally well on both halfword and byte operand function + results. This is because halfword operand operations set two (duplicate) GE bits per + value. +
Parameter +
    +
  • val1: four selectable 8-bit values.
    • +
  • val2: four selectable 8-bit values.
    • +
+
Return Value +

The function selects bytes from the input parameters and returns them in the + return value, res, according to the following criteria:

+
    +
  • if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0]
    • +
  • if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8]
    • +
  • if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16]
    • +
  • if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24]
    • +
+
+ +

Function __QADD

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __QADD(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to obtain the saturating add of two integers.
+ The Q bit is set if the operation saturates. +
Parameter +
    +
  • val1: first summand of the saturating add operation.
    • +
  • val2: second summand of the saturating add operation.
    • +
+
Return Value +

The function returns the saturating addition of val1 and val2.

+
Operation + 
+res[31:0] = SAT(val1 + SAT(val2 * 2))
+
+ +

Function __QSUB

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary + 
+uint32_t __QSUB(uint32_t val1, uint32_t val2);
+
DescriptionThis function enables you to obtain the saturating subtraction of two integers.
+ The Q bit is set if the operation saturates. +
Parameter +
    +
  • val1: minuend of the saturating subtraction operation.
    • +
  • val2: subtrahend of the saturating subtraction operation.
    • +
+
Return Value +

The function returns the saturating subtraction of val1 and val2.

+
Operation + 
+res[31:0] = SAT(val1 - SAT(val2 * 2))
+
+ + + +

 

+

Examples

+

Following are some coding examples using the SIMD functions: +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameDescription
AdditionAdd two values using SIMD function
SubtractionSubtract two values using SIMD function
MultiplicationPerforming a multiplication using SIMD function
+ + +

Addition

+ + + + + + + +
Example + 
+uint32_t add_halfwords(uint32_t val1, uint32_t val2)
+{
+   uint32_t res;
+   res = __SADD16(val1, val2);
+   return res;
+}
+
+ +

Subtraction

+ + + + + + + +
Example + 
+uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
+{
+  uint32_t res;
+  res = __SSUB16(val1, val2);
+  return res;
+}
+
+ +

Multiplication

+ + + + + + + +
Example + 
+uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
+{
+  uint32_t res;
+  res = __SMUAD(val1, val2);
+  return res;
+}
+
+ + + + \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_Core.htm b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_Core.htm new file mode 100644 index 000000000..aff81c9bc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_Core.htm @@ -0,0 +1,1470 @@ + + + + CMSIS: Cortex Microcontroller Software Interface Standard + + + +

Cortex Microcontroller Software Interface Standard

+ +

This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).

+

Version: 2.10 - July 2011

+ +

Information in this file, the accompany manuals, and software is
+ Copyright © ARM Ltd.
All rights reserved. +

+ +
+ +

Revision History

+
    +
  • Version 1.00: initial release.
    • +
  • Version 1.01: added __LDREXx, __STREXx, and __CLREX.
    • +
  • Version 1.02: added Cortex-M0.
    • +
  • Version 1.10: second review.
    • +
  • Version 1.20: third review.
    • +
  • Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.
    • +
  • Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.
    • +
  • Version 1.30: updated Device Support Packages.
    • +
  • Version 2.00: added Cortex-M4 support.
    • +
  • Version 2.01: internal review.
    • +
  • Version 2.02: updated Device Specific Defines
    • +
  • Version 2.10: reworked core include files
    • +
+ +
+ +

Contents

+ +
    +
  1. About
    2. +
  2. Coding Rules and Conventions
    3. +
  3. CMSIS Files
    4. +
  4. Core Peripheral Access Layer
    5. +
  5. CMSIS Example
    6. +
  6. CMSIS MISRA-C:2004 Compliance Exceptions
    7. +
+ +

About

+ +

+ The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges + that are faced when software components are deployed to physical microcontroller devices based on a + Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M + processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation + with various silicon and software vendors and provides a common approach to interface to peripherals, + real-time operating systems, and middleware components. +

+ +

ARM provides as part of the CMSIS the following software layers that are +available for various compiler implementations:

+
    +
  • Core Peripheral Access Layer: contains name definitions, + address definitions and helper functions to + access core registers and peripherals. It defines also a device + independent interface for RTOS Kernels that includes debug channel + definitions.
    • +
+ +

These software layers are expanded by Silicon partners with:

+
    +
  • Device Peripheral Access Layer: provides definitions + for all device peripherals
    • +
  • Access Functions for Peripherals (optional): provides + additional helper functions for peripherals
    • +
+ +

CMSIS defines for a Cortex-M Microcontroller System:

+
    +
  • A common way to access peripheral registers + and a common way to define exception vectors.
    • +
  • The register names of the Core + Peripherals and the names of the Core + Exception Vectors.
    • +
  • An device independent interface for RTOS Kernels including a debug + channel.
    • +
+ +

+ By using CMSIS compliant software components, the user can easier re-use template code. + CMSIS is intended to enable the combination of software components from multiple middleware vendors. +

+ +

Coding Rules and Conventions

+ +

+ The following section describes the coding rules and conventions used in the CMSIS + implementation. It contains also information about data types and version number information. +

+ +

Essentials

+
    +
  • The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, + there are disable and enable sequences for PC-LINT inserted.
    • +
  • ANSI standard data types defined in the ANSI C header file + <stdint.h> are used.
    • +
  • #define constants that include expressions must be enclosed by + parenthesis.
    • +
  • Variables and parameters have a complete data type.
    • +
  • All functions in the Core Peripheral Access Layer are + re-entrant.
    • +
  • The Core Peripheral Access Layer has no blocking code + (which means that wait/query loops are done at other software layers).
    • +
  • For each exception/interrupt there is definition for: +
      +
    • an exception/interrupt handler with the postfix _Handler + (for exceptions) or _IRQHandler (for interrupts).
      • +
    • a default exception/interrupt handler (weak definition) that contains an endless loop.
      • +
    • a #define of the interrupt number with the postfix _IRQn.
      • +
    • +
+ +

Recommendations

+ +

The CMSIS recommends the following conventions for identifiers.

+
    +
  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
    • +
  • CamelCase names to identify peripherals access functions and interrupts.
    • +
  • PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
    • +
  • Doxygen comments for all functions are included as described under Function Comments below.
    • +
+ +Comments + +
    +
  • Comments use the ANSI C90 style (/* comment */) or C++ style + (// comment). It is assumed that the programming tools support today + consistently the C++ comment style.
    • +
  • Function Comments provide for each function the following information: +
      +
    • one-line brief function overview.
      • +
    • detailed parameter explanation.
      • +
    • detailed information about return values.
      • +
    • detailed description of the actual function.
      • +
    +

    Doxygen Example:

    + 
    +/** 
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ * @param  IRQn  interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */
    +
    • +
+ +

Data Types and IO Type Qualifiers

+ +

+ The Cortex-M HAL uses the standard types from the standard ANSI C header file + <stdint.h>. IO Type Qualifiers are used to specify the access + to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of + debug information of peripheral registers. +

+ + + + + + + + + + + + + + + + + + + + + + + + +
IO Type Qualifier#defineDescription
__Ivolatile constRead access only
__OvolatileWrite access only
__IOvolatileRead and write access
+ +

CMSIS Version Number

+

+ File core_cm4.h contains the version number of the CMSIS with the following define: +

+ +
+#define __CM4_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
+#define __CM4_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB)
+ +

+ File core_cm3.h contains the version number of the CMSIS with the following define: +

+ +
+#define __CM3_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
+#define __CM3_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)
+ +

+ File core_cm0.h contains the version number of the CMSIS with the following define: +

+ +
+#define __CM0_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
+#define __CM0_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)
+ + +

CMSIS Cortex Core

+

+ File core_cm4.h contains the type of the CMSIS Cortex-M with the following define: +

+ +
+#define __CORTEX_M                (0x04)
+ +

+ File core_cm3.h contains the type of the CMSIS Cortex-M with the following define: +

+ +
+#define __CORTEX_M                (0x03)
+ +

+ File core_cm0.h contains the type of the CMSIS Cortex-M with the following define: +

+ +
+#define __CORTEX_M                (0x00)
+ + +

CMSIS Files

+

+ This section describes the Files provided in context with the CMSIS to access the Cortex-M + hardware and peripherals. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FileProviderDescription
device.hDevice specific (provided by silicon partner)Defines the peripherals for the actual device. The file may use + several other include files to define the peripherals of the actual device.
core_cm0.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
core_cm3.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
core_cm4.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M4 CPU and core peripherals.
core_cm4_simd.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the Cortex-M4 Core SIMD functions.
core_cmFunc.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the Cortex-M Core Register access functions.
core_cmInstr.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the Cortex-M Core instructions.
startup_deviceARM (adapted by compiler partner / silicon partner)Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
system_deviceARM (adapted by silicon partner)Provides a device specific configuration file for the device. It configures the device initializes + typically the oscillator (PLL) that is part of the microcontroller device
+ +

device.h

+ +

+ The file device.h is provided by the silicon vendor and is the + central include file that the application programmer is using in + the C source code. This file contains: +

+
    +
  • +

    Interrupt Number Definition: provides interrupt numbers + (IRQn) for all core and device specific exceptions and interrupts.

    +
    • +
  • +

    Configuration for core_cm0.h / core_cm3.h / core_cm4.h: reflects the + actual configuration of the Cortex-M processor that is part of the actual + device. As such the file core_cm0.h / core_cm3.h / core_cm4.h is included that + implements access to processor registers and core peripherals.

    +
    • +
  • +

    Device Peripheral Access Layer: provides definitions + for all device peripherals. It contains all data structures and the address + mapping for the device specific peripherals.

    +
    • +
  • Access Functions for Peripherals (optional): provides + additional helper functions for peripherals that are useful for programming + of these peripherals. Access Functions may be provided as inline functions + or can be extern references to a device specific library provided by the + silicon vendor.
    • +
+ + +

Interrupt Number Definition

+ +

To access the device specific interrupts the device.h file defines IRQn +numbers for the complete device using a enum typedef as shown below:

+
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
+  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
+  HardFault_IRQn                  = -13,      /*!< 3 Cortex-M3 Hard Fault Interrupt                      */
+  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
+  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
+  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
+  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
+  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
+  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
+  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */
+/******  STM32 specific Interrupt Numbers ****************************************************************/
+  WWDG_STM_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
+  PVD_STM_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
+  :
+  :
+  } IRQn_Type;
+ + +

Device Specific Defines

+

+ The following device implementation specific defines are set in the device header file and are + used for the Cortex-M core configuration options. Some configuration options are reflected + in the CMSIS layer using the #define settings described below. +

+

+ Several features in core_cm#.h are configured by the following defines + that must be defined before #include <core_cm#.h> + preprocessor command. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#defineCoreValueDescription
__CM0_REVM00x0000Core revision number ([15:8] revision number, [7:0] patch number)
__CM3_REVM30x0101 | 0x0200Core revision number ([15:8] revision number, [7:0] patch number)
__CM4_REVM40x0000Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITSM0, M3, M42 .. 8Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENTM0, M3, M40 | 1Defines if a MPU is present or not
__FPU_PRESENTM40 | 1Defines if a FPU is present or not
__Vendor_SysTickConfigM0, M3, M40 | 1When this define is setup to 1, the SysTickConfig function + in core_cm3.h is excluded. In this case the device.h + file must contain a vendor specific implementation of this function.
+ + +

Device Peripheral Access Layer

+

+ Each peripheral uses a prefix which consists of <device abbreviation>_ + and <peripheral name>_ to identify peripheral registers that access this + specific peripheral. The intention of this is to avoid name collisions caused + due to short names. If more than one peripheral of the same type exists, + identifiers have a postfix (digit or letter). For example: +

+
    +
  • <device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device. + 
    +typedef struct
+{
+  union {
+  __I  uint8_t  RBR;                     /*!< Offset: 0x000 (R/ )  Receiver Buffer Register    */
+  __O  uint8_t  THR;                     /*!< Offset: 0x000 ( /W)  Transmit Holding Register   */
+  __IO uint8_t  DLL;                     /*!< Offset: 0x000 (R/W)  Divisor Latch LSB           */
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;                     /*!< Offset: 0x004 (R/W)  Divisor Latch MSB           */
+  __IO uint32_t IER;                     /*!< Offset: 0x004 (R/W)  Interrupt Enable Register   */
+  };
+  union {
+  __I  uint32_t IIR;                     /*!< Offset: 0x008 (R/ )  Interrupt ID Register       */
+  __O  uint8_t  FCR;                     /*!< Offset: 0x008 ( /W)  FIFO Control Register       */
+  };
+  __IO uint8_t  LCR;                     /*!< Offset: 0x00C (R/W)  Line Control Register       */
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;                     /*!< Offset: 0x014 (R/ )  Line Status Register        */
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;                     /*!< Offset: 0x01C (R/W)  Scratch Pad Register        */
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;                     /*!< Offset: 0x020 (R/W)  Autobaud Control Register   */
+  __IO uint8_t  ICR;                     /*!< Offset: 0x024 (R/W)  IrDA Control Register       */
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;                     /*!< Offset: 0x028 (R/W)  Fractional Divider Register */
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;                     /*!< Offset: 0x030 (R/W)  Transmit Enable Register    */
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058 (R/ )  FIFO Level Register         */
+} LPC_UART_TypeDef;
    +
    • +
  • <device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. + For example UART1->THR is the transmit holding register of UART1. + 
    +#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
    +
    • +
+ +
Minimal Requiements
+

+ To access the peripheral registers and related function in a device the files device.h + and core_cm0.h / core_cm3.h defines as a minimum: +

+
    +
  • The Register Layout Typedef for each peripheral that defines all register names. + Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of + the peripheral registers. For example: + 
    +typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
    +
    • + +
  • + Base Address for each peripheral (in case of multiple peripherals + that use the same register layout typedef multiple base addresses are defined). For example: + 
    +#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */
    +
    • + +
  • + Access Definition for each peripheral (in case of multiple peripherals that use + the same register layout typedef multiple access definitions exist, i.e. LPC_UART0, + LPC_UART2). For Example: + 
    +#define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */
    +
    • +
+ +

+ These definitions allow to access the peripheral registers from user code with simple assignments like: +

+
SysTick->CTRL = 0;
+ +
Optional Features
+

In addition the device.h file may define:

+
    +
  • + #define constants that simplify access to the peripheral registers. + These constant define bit-positions or other specific patterns are that required for the + programming of the peripheral registers. The identifiers used start with + <device abbreviation>_ and <peripheral name>_. + It is recommended to use CAPITAL letters for such #define constants. +
    • +
  • + Functions that perform more complex functions with the peripheral (i.e. status query before + a sending register is accessed). Again these function start with + <device abbreviation>_ and <peripheral name>_. +
    • +
+ +

core_cm0.h

+

+ File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does + the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers + and core peripherals with efficient functions (defined as static inline). +

+

This file implement the Core Peripheral Access Layer for a Cortex-M0.

+

The define __CMSIS_GENERIC allows to use core_cm0.h in generic + library projects that are device independent. Only core relevant types and defines are used.

+ +

core_cm3.h

+

+ File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does + the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers + and core peripherals with efficient functions (defined as static inline). +

+

This file implement the Core Peripheral Access Layer for a Cortex-M3.

+

The define __CMSIS_GENERIC allows to use core_cm3.h in generic + library projects that are device independent. Only core relevant types and defines are used.

+ +

core_cm4.h, core_cm4_simd.h

+

+ File core_cm4.h describes the data structures for the Cortex-M4 core peripherals and does + the address mapping of this structures. It also provides basic access to the Cortex-M4 core registers + and core peripherals with efficient functions (defined as static inline). +

+

+ File core_cm4_simd.h defines Cortex-M4 SIMD instructions. +

+

Together these files implement the Core Peripheral Access Layer for a Cortex-M4.

+

The define __CMSIS_GENERIC allows to use core_cm4.h in generic + library projects that are device independent. Only core relevant types and defines are used.

+ +

core_cmFunc.h and core_cmInstr.h

+

+ File core_cmFunc.h defines the Cortex-M Core Register access functions (defined as static inline). +

+

+ File core_cmInstr.h defines the Cortex-M Core instructions (defined as static inline). +

+

These files are part of the Core Peripheral Access Layer for a Cortex-M.

+ +

startup_device

+

+ A template file for startup_device is provided by ARM for each supported + compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific + interrupt handlers. Each interrupt handler is defined as weak function + to an dummy handler. Therefore the interrupt handler can be directly used in application software + without any requirements to adapt the startup_device file. +

+

+ The following exception names are fixed and define the start of the vector table for a Cortex-M0: +

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+ +

+ The following exception names are fixed and define the start of the vector table for a Cortex-M3: +

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+ +

+ In the following examples for device specific interrupts are shown: +

+
+; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler         ; Tamper
+ +

+ Device specific interrupts must have a dummy function that can be overwritten in user code. + Below is an example for this dummy function. +

+
+Default_Handler PROC
+                EXPORT WWDG_IRQHandler   [WEAK]
+                EXPORT PVD_IRQHandler    [WEAK]
+                EXPORT TAMPER_IRQHandler [WEAK]
+                :
+                :
+                WWDG_IRQHandler
+                PVD_IRQHandler
+                TAMPER_IRQHandler
+                :
+                :
+                B .
+                ENDP
+ +

+ The user application may simply define an interrupt handler function by using the handler name + as shown below. +

+
+void WWDG_IRQHandler(void)
+{
+  :
+  :
+}
+ + +

system_device.c

+

+ A template file for system_device.c is provided by ARM but adapted by + the silicon vendor to match their actual device. As a minimum requirement + this file must provide a device specific system configuration function and a global variable + that contains the system frequency. It configures the device and initializes typically the + oscillator (PLL) that is part of the microcontroller device. +

+

+ The file system_device.c must provide + as a minimum requirement the SystemInit function as shown below. +

+ + + + + + + + + + + + + + + + +
Function DefinitionDescription
void SystemInit (void)Setup the microcontroller system. Typically this function configures the + oscillator (PLL) that is part of the microcontroller device. For systems + with variable clock speed it also updates the variable SystemCoreClock.
+ SystemInit is called from startup_device file.
void SystemCoreClockUpdate (void)Updates the variable SystemCoreClock and must be called whenever the + core clock is changed during program execution. SystemCoreClockUpdate() + evaluates the clock register settings and calculates the current core clock. +
+ +

+ Also part of the file system_device.c + is the variable SystemCoreClock which contains the current CPU clock speed shown below. +

+ + + + + + + + + + + + +
Variable DefinitionDescription
uint32_t SystemCoreClockContains the system core clock (which is the system clock frequency supplied + to the SysTick timer and the processor core clock). This variable can be + used by the user application to setup the SysTick timer or configure other + parameters. It may also be used by debugger to query the frequency of the + debug timer or configure the trace clock speed.
+ SystemCoreClock is initialized with a correct predefined value.

+ The compiler must be configured to avoid the removal of this variable in + case that the application program is not using it. It is important for + debug systems that the variable is physically present in memory so that + it can be examined to configure the debugger.
+ +

Note

+
    +

  • The above definitions are the minimum requirements for the file + system_device.c. This + file may export more functions or variables that provide a more flexible + configuration of the microcontroller system.

    +
    • +
+ + +

Core Peripheral Access Layer

+ +

Cortex-M Core Register Access

+

+ The following functions are defined in core_cm0.h / core_cm3.h + and provide access to Cortex-M core registers. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Function DefinitionCoreCore RegisterDescription
void __enable_irq (void)M0, M3, M4PRIMASK = 0Global Interrupt enable (using the instruction CPSIE i)
void __disable_irq (void)M0, M3, M4PRIMASK = 1Global Interrupt disable (using the instruction CPSID i)
uint32_t __get_CONTROL (void)M0, M3, M4return CONTROLReturn Control Register Value (using the instruction MRS)
void __set_CONTROL (uint32_t value)M0, M3, M4CONTROL = valueSet CONTROL register value (using the instruction MSR)
uint32_t __get_IPSR (void)M0, M3, M4return IPSRReturn IPSR Register Value (using the instruction MRS)
uint32_t __get_APSR (void)M0, M3, M4return APSRReturn APSR Register Value (using the instruction MRS)
uint32_t __get_xPSR (void)M0, M3, M4return xPSRReturn xPSR Register Value (using the instruction MRS)
uint32_t __get_PSP (void)M0, M3, M4return PSPReturn Process Stack Pointer (using the instruction MRS)
void __set_PSP (uint32_t TopOfProcStack)>M0, M3, M4PSP = TopOfProcStackSet Process Stack Pointer value (using the instruction MSR)
uint32_t __get_MSP (void)M0, M3, M4return MSPReturn Main Stack Pointer (using the instruction MRS)
void __set_MSP (uint32_t TopOfMainStack)M0, M3, M4MSP = TopOfMainStackSet Main Stack Pointer (using the instruction MSR)
uint32_t __get_PRIMASK (void)M0, M3, M4return PRIMASKReturn Priority Mask Register (using the instruction MRS)
void __set_PRIMASK (uint32_t value)M0, M3, M4PRIMASK = valueAssign value to Priority Mask Register (using the instruction MSR)
void __enable_fault_irq (void)M3, M4FAULTMASK = 0Global Fault exception and Interrupt enable (using the instruction CPSIE f)
void __disable_fault_irq (void)M3, M4FAULTMASK = 1Global Fault exception and Interrupt disable (using the instruction CPSID f)
uint32_t __get_BASEPRI (void)M3, M4return BASEPRIReturn Base Priority (using the instruction MRS)
void __set_BASEPRI (uint32_t value)M3, M4BASEPRI = valueSet Base Priority (using the instruction MSR)
uint32_t __get_FAULTMASK (void)M3, M4return FAULTMASKReturn Fault Mask Register (using the instruction MRS)
void __set_FAULTMASK (uint32_t value)M3, M4FAULTMASK = valueAssign value to Fault Mask Register (using the instruction MSR)
uint32_t __get_FPSCR (void)M4return FPSCRReturn Floating Point Status / Control Register
void __set_FPSCR (uint32_t value)M4FPSCR = valueAssign value to Floating Point Status / Control Register
+ +

Cortex-M Instruction Access

+

+ The following functions are defined in core_cm0.h / core_cm3.hand + generate specific Cortex-M instructions. The functions are implemented in the file + core_cm0.c / core_cm3.c. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameCoreGenerated CPU InstructionDescription
void __NOP (void)M0, M3, M4NOPNo Operation
void __WFI (void)M0, M3, M4WFIWait for Interrupt
void __WFE (void)M0, M3, M4WFEWait for Event
void __SEV (void)M0, M3, M4SEVSet Event
void __ISB (void)M0, M3, M4ISBInstruction Synchronization Barrier
void __DSB (void)M0, M3, M4DSBData Synchronization Barrier
void __DMB (void)M0, M3, M4DMBData Memory Barrier
uint32_t __REV (uint32_t value)M0, M3, M4REVReverse byte order in integer value.
uint32_t __REV16 (uint16_t value)M0, M3, M4REV16Reverse byte order in unsigned short value.
sint32_t __REVSH (sint16_t value)M0, M3, M4REVSHReverse byte order in signed short value with sign extension to integer.
uint32_t __RBIT (uint32_t value)M3, M4RBITReverse bit order of value
uint8_t __LDREXB (uint8_t *addr)M3, M4LDREXBLoad exclusive byte
uint16_t __LDREXH (uint16_t *addr)M3, M4LDREXHLoad exclusive half-word
uint32_t __LDREXW (uint32_t *addr)M3, M4LDREXWLoad exclusive word
uint8_t __STREXB (uint8_t value, uint8_t *addr)M3, M4STREXBStore exclusive byte
uint16_t __STREXH (uint16_t value, uint16_t *addr)M3, M4STREXHStore exclusive half-word
uint32_t __STREXW (uint32_t value, uint32_t *addr)M3, M4STREXWStore exclusive word
void __CLREX (void)M3, M4CLREXRemove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW
void __SSAT (void)M3, M4SSATsaturate a signed value
void __USAT (void)M3, M4USATsaturate an unsigned value
+ + +

NVIC Access Functions

+

+ The CMSIS provides access to the NVIC via the register interface structure and several helper + functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to + identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative + IRQn values are used for processor core exceptions. +

+

+ For the IRQn values of core exceptions the file device.h provides + the following enum names. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Core Exception enum ValueCoreIRQnDescription
NonMaskableInt_IRQnM0, M3, M4-14Cortex-M Non Maskable Interrupt
HardFault_IRQnM0, M3, M4-13Cortex-M Hard Fault Interrupt
MemoryManagement_IRQnM3, M4-12Cortex-M Memory Management Interrupt
BusFault_IRQnM3, M4-11Cortex-M Bus Fault Interrupt
UsageFault_IRQnM3, M4-10Cortex-M Usage Fault Interrupt
SVCall_IRQnM0, M3, M4-5Cortex-M SV Call Interrupt
DebugMonitor_IRQnM3, M4-4Cortex-M Debug Monitor Interrupt
PendSV_IRQnM0, M3, M4-2Cortex-M Pend SV Interrupt
SysTick_IRQnM0, M3, M4-1Cortex-M System Tick Interrupt
+ +

The following functions simplify the setup of the NVIC. +The functions are defined as static inline.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameCoreParameterDescription
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)M3, M4Priority Grouping ValueSet the Priority Grouping (Groups . Subgroups)
uint32_t NVIC_GetPriorityGrouping (void)M3, M4(void)Get the Priority Grouping (Groups . Subgroups)
void NVIC_EnableIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberEnable IRQn
void NVIC_DisableIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberDisable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberReturn 1 if IRQn is pending else 0
void NVIC_SetPendingIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberSet IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberClear IRQn Pending Status
uint32_t NVIC_GetActive (IRQn_Type IRQn)M3, M4IRQ NumberReturn 1 if IRQn is active else 0
void NVIC_SetPriority (
+   IRQn_Type IRQn,
+   uint32_t priority)		M0, M3, M4IRQ Number, PrioritySet Priority for IRQn
+ (not threadsafe for Cortex-M0)
uint32_t NVIC_GetPriority (IRQn_Type IRQn)M0, M3, M4IRQ NumberGet Priority for IRQn
uint32_t NVIC_EncodePriority (
+   uint32_t PriorityGroup,
+   uint32_t PreemptPriority,
+   uint32_t SubPriority)		M3, M4IRQ Number,
+ Priority Group,
+ Preemptive Priority,
+ Sub Priority		Encode priority for given group, preemptive and sub priority
void NVIC_DecodePriority (
+   uint32_t Priority,
+   uint32_t PriorityGroup,
+   uint32_t* pPreemptPriority,
+   uint32_t* pSubPriority)		M3, M4
+ Priority,
+ Priority Group,
+ pointer to Preempt. Priority,
+ pointer to Sub Priority		Decode given priority to group, preemptive and sub priority
void NVIC_SystemReset (void)M0, M3, M4(void)Resets the System
+

Note

+
    +

  • The processor exceptions have negative enum values. Device specific interrupts + have positive enum values and start with 0. The values are defined in + device.h file. +

    +
    • +

  • The values for PreemptPriority and SubPriority + used in functions NVIC_EncodePriority and NVIC_DecodePriority + depend on the available __NVIC_PRIO_BITS implemented in the NVIC. +

    +
    • +
+ + +

SysTick Configuration Function

+ +

The following function is used to configure the SysTick timer and start the +SysTick interrupt.

+ + + + + + + + + + + + + + +
NameParameterDescription
uint32_t SysTickConfig (uint32_t ticks)ticks is SysTick counter reload valueSetup the SysTick timer and enable the SysTick interrupt. After this + call the SysTick timer creates interrupts with the specified time interval.

+ Return: 0 when successful, 1 on failure.
+
+ + +

Cortex-M3 / Cortex-M4 ITM Debug Access

+ +

The Cortex-M3 / Cortex-M4 incorporates the Instrumented Trace Macrocell (ITM) that +provides together with the Serial Viewer Output trace capabilities for the +microcontroller system. The ITM has 32 communication channels; two ITM +communication channels are used by CMSIS to output the following information:

+
    +
  • ITM Channel 0: implements the ITM_SendChar function + which can be used for printf-style output via the debug interface.
    • +
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for + kernel awareness debugging.
    • +
+

Note

+
    +

  • The ITM channel 31 is selected for the RTOS kernel since some kernels + may use the Privileged level for program execution. ITM + channels have 4 groups with 8 channels each, whereby each group can be + configured for access rights in the Unprivileged level. The ITM channel 0 + may be therefore enabled for the user task whereas ITM channel 31 may be + accessible only in Privileged level from the RTOS kernel itself.

    +
    • +
+ +

The prototype of the ITM_SendChar routine is shown in the +table below.

+ + + + + + + + + + + + + + +
NameParameterDescription
void uint32_t ITM_SendChar(uint32_t chr)character to outputThe function outputs a character via the ITM channel 0. The + function returns when no debugger is connected that has booked the + output. It is blocking when a debugger is connected, but the + previous character send is not transmitted.

+ Return: the input character 'chr'. +
+ +

+ Example for the usage of the ITM Channel 31 for RTOS Kernels: +

+
+  // check if debugger connected and ITM channel enabled for tracing
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+  (ITM->TCR & ITM_TCR_ITMENA) &&
+  (ITM->TER & (1UL << 31))) {
+    // transmit trace data
+    while (ITM->PORT31_U32 == 0);
+    ITM->PORT[31].u8 = task_id;      // id of next task
+    while (ITM->PORT[31].u32 == 0);
+    ITM->PORT[31].u32 = task_status; // status information
+  }
+ + +

Cortex-M3 additional Debug Access

+ +

CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access. +Data can be transmitted via a certain global buffer variable towards the target system.

+ +

The buffer variable and the prototypes of the additional functions are shown in the +table below.

+ + + + + + + + + + + + + + + + + + + + + + + + +
NameParameterDescription
extern volatile int ITM_RxBuffer Buffer to transmit data towards debug system.

+ Value 0x5AA55AA5 indicates that buffer is empty.
int ITM_ReceiveChar (void)noneThe nonblocking functions returns the character stored in + ITM_RxBuffer.

+ Return: -1 indicates that no character was received.
int ITM_CheckChar (void)noneThe function checks if a character is available in ITM_RxBuffer.

+ Return: 1 indicates that a character is available, 0 indicates that + no character is available.
+ + +

CMSIS Example

+

+ The following section shows a typical example for using the CMSIS layer in user applications. + The example is based on a STM32F10x Device. +

+
+#include "stm32f10x.h"
+
+volatile uint32_t msTicks;                       /* timeTicks counter */
+
+void SysTick_Handler(void) {
+  msTicks++;                                     /* increment timeTicks counter */
+}
+
+__INLINE static void Delay (uint32_t dlyTicks) {
+  uint32_t curTicks = msTicks;
+
+  while ((msTicks - curTicks) < dlyTicks);
+}
+
+__INLINE static void LED_Config(void) {
+  ;                                              /* Configure the LEDs */
+}
+
+__INLINE static void LED_On (uint32_t led) {
+  ;                                              /* Turn On  LED */
+}
+
+__INLINE static void LED_Off (uint32_t led) {
+  ;                                              /* Turn Off LED */
+}
+
+int main (void) {
+  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
+    ;                                            /* Handle Error */
+    while (1);
+  }
+  
+  LED_Config();                                  /* configure the LEDs */                            
+ 
+  while(1) {
+    LED_On (0x100);                              /* Turn  on the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+    LED_Off (0x100);                             /* Turn off the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+  }
+}
+ + +

CMSIS MISRA-C:2004 Compliance Exceptions

+

+ CMSIS violates following MISRA-C2004 Rules: +

+
    +
  • Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'.
    • + +
  • Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers.
    • + +
  • Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code.
    • +
+ +

  

+ + \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_DebugSupport.htm b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_DebugSupport.htm new file mode 100644 index 000000000..96cc60ddb --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_DebugSupport.htm @@ -0,0 +1,240 @@ + + + +CMSIS Debug Support + + + + + + + + +

CMSIS Debug Support

+

This file describes the CMSIS Debug support available with CMSIS (starting V1.30).

+

Version: 1.02 - 25. July 2011

+ +

Information in this file, the accompany manuals, and software is
+ Copyright © ARM Ltd.
All rights reserved. +

+ +
+ +

Revision History

+
    +
  • Version 1.00: Initial Release.
    • +
  • Version 1.01: Internal Review.
    • +
  • Version 1.02: Removed product specific information.
    • +
+ +
+ +

Contents

+ +
    +
  1. About
    2. +
  2. Cortex-M3 / Cortex-M4 ITM Debug Access
    3. +
  3. Debug IN / OUT functions
    4. +
  4. ITM Debug Support in Debugger
    5. +
+ +

 

+

About

+

+ CMSIS provides for Cortex-M3 / Cortex-M4 processor based microcontrollers debug support via the Instrumented Trace Macrocell (ITM). + This document describes the available CMSIS Debug functions and the used methods. +

+ +

 

+

Cortex-M3 / Cortex-M4 ITM Debug Access

+

+ The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with + the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has + 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM + communication channels are used by CMSIS to output the following information: +

+
    +
  • ITM Channel 0: used for printf-style output via the debug interface.
    • +
  • ITM Channel 31: is reserved for RTOS kernel awareness debugging.
    • +
+ +

 

+

Debug IN / OUT functions

+

CMSIS provides following debug functions:

+
    +
  • ITM_SendChar (uses ITM channel 0)
    • +
  • ITM_ReceiveChar (uses global variable)
    • +
  • ITM_CheckChar (uses global variable)
    • +
+ +

ITM_SendChar

+

+ ITM_SendChar is used to transmit a character over ITM channel 0 from + the microcontroller system to the debug system.
+ Only a 8 bit value is transmitted. +

+
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  /* check if debugger connected and ITM channel enabled for tracing */
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&
+      (ITM->TCR & ITM_TCR_ITMENA)                  &&
+      (ITM->TER & (1UL << 0))  ) 
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }  
+  return (ch);
+}
+ +

ITM_ReceiveChar

+

+ ITM communication channel is only capable for OUT direction. For IN direction + a global variable is used. A simple mechanism detects if a character is received. + The project to test need to be build with debug information. +

+ +

+ The global variable ITM_RxBuffer is used to transmit a 8 bit value from debug system + to microcontroller system. ITM_RxBuffer is 32 bit wide to + ensure a proper handshake. +

+
+extern volatile int32_t ITM_RxBuffer;                    /* variable to receive characters                             */
+
+

+ A dedicated bit pattern is used to determine if ITM_RxBuffer is empty + or contains a valid value. +

+
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
+
+

+ ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking. + It returns the received character or '-1' if no character was available. +

+
+static __INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                               /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+  
+  return (ch); 
+}
+
+ +

ITM_CheckChar

+

+ ITM_CheckChar is used to check if a character is received. +

+
+static __INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+ + +

 

+

ITM Debug Support in a Debugger

+

+ The Debugger shall offer a dedicated console window for printf style debug input and output using the CMSIS defined ITM methods described above. +

+

Direction: Microcontroller -> Debugger:

+
    +
  • + at the beginning of a debug session the debugger shall enable ITM trace on channel 0 and continuously snoop for channel 0 data on the ITM trace + stream it receives from the Microcontroller's CoreSight ITM unit +
    • +
  • + data received via the ITM communication channel 0 is interpreted as charater and gets redirected into the dedicated Console Window +
    • +
+ +

Direction: Debugger -> Microcontroller:

+
    +
  • + at the beginning of a debug session the debugger shall seek for the presence of the global variable named ITM_RxBuffer in the debug + information of the application being loaded +
    • +
  • + strings entered into the Console Window are written by the debugger as a stream of char values via the variable ITM_RxBuffer. +
    • +
  • + the debugger writes the next character into the ITM_RxBuffer only once the value has been read and the ITM_RXBUFFER_EMPTY value being set. + (refer to: ITM_ReceiveChar()). +
+ + + + \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_History.htm b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_History.htm new file mode 100644 index 000000000..a906ae99c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_History.htm @@ -0,0 +1,472 @@ + + + +CMSIS Version History + + + + + + + + +

CMSIS Version History

+

This document describes the changes between the different CMSIS versions.

+

Version: 2.10 - July 2011

+ +

Information in this file, the accompany manuals, and software is
+ Copyright © ARM Ltd.
All rights reserved. +

+ +
+ + +

Contents

+ +
    +
  1. Used Toolchains
    2. +
  2. Changes to version V2.00
    3. +
  3. Changes to version V1.30
    4. +
  4. Changes to version V1.20
    5. +
  5. Open Points
    6. +
  6. Limitations
    7. +
+ + +

Used Toolchains

+

+ Following toolchains have been used for test / verification:. +

+
    +
  • ARM: MDK-ARM Version 4.21
    • +
  • GNU: Sourcery G++ Lite Edition for ARM 2010.09-51
    • +
  • IAR: IAR Embedded Workbench Kickstart Edition V6.10
    • +
+ + +

Changes to version V2.00

+ +

Added CMSIS DSP Software Library support for Cortex-M0 based MCUs

+

+ The CMSIS DSP Software Library provides now also libraries and examples for Cortex-M0. +

+

+ For more information refer to CMSIS DSP Library documentation. +

+ +

Added big endian support for DSP library

+

+ The CMSIS DSP Software Library provides now also pre-build libraries + and projects for big endian devices. +

+

+ For more information refer to CMSIS DSP Library documentation. +

+ + +

Simplified folder structure for CMSIS include files

+

+ All CMSIS core include files as well as the DSP-Library header files are located in + a single folder ./CMSIS/Include. +

+ +

Changed folder structure for Device Support packages

+

+ Device Support packages are expected to be in folder ./Device located at the + same level as ./CMSIS. +

+

The new Device folder contains the following subfolders:

+
    +
  • Device
    • +
      +
    • <Vendor> +
        +
      • <Device> | <Device Series> +
          +
        • Include
          + <device>.h
          + system_<device>.h
          +
          • +
        • Source +
            +
          • Templates
            + system_<device>.c
            +
              +
            • <Toolchain>
              + startup_<device>.s
              +
              • +
            • <Toolchain>
              • +
            • ...
              • +
            +
            • +
          +
          • +
        +
      • <Device> | <Device Series>
        • +
      • ...
        • +
      +
      • +
    • <Vendor>
      • +
    • ...
      • +
    + +
+

Template files are application specific files and are required to be copied to the project prior to use!

+ +

Removed CMSIS core source files

+

+ The CMSIS core source files core_cm0.c, core_cm3.c, core_cm4.c + containing helper functions for older ARM compiler versions got removed. +

+

+ For the ARM Compiler Toolchain version V4.0.677 or later is + required!

+ + +

Changes to version V1.30

+ +

Added CMSIS DSP Software Library

+

+ The CMSIS DSP Software Library is a suite of common signal processing functions targeted + to Cortex-M processor based microcontrollers. Even though the code has been specifically + optimized towards using the extended DSP instruction set of the Cortex-M4 processor, + the library can be compiled for any Cortex-M processor. +

+

+ For more information see CMSIS DSP Library documentation. +

+ +

Added CMSIS System View Description

+

+ The CMSIS System View Description answers the challenges of accurate, detailed and + timely device aware peripheral debugging support for Cortex Microcontroller based + devices by the software development tools vendor community. +

+

+ Silicon vendors shall create and maintain a formalized description of the debug view + for all the peripherals contained in their Cortex Microcontroller based devices. + Tool vendors use such descriptions to establish device specific debug support in + their debugging tools. +

+

+ A standardized System View Description shall provide a common approach to + capturing peripheral debug related information in a machine readable files. +

+

+ For more information see CMSIS System View Description. +

+ +

Added Cortex-M4 Core Support

+

+ Additional folder CM4, containing the Cortex-M4 core support files, has been added. +

+
    +
  • CM0
    • +
  • CM3
    • +
  • CM4 +
      +
    • CoreSupport
      • +
    • DeviceSupport
      • +
    +
    • +
+ +

New naming for Core Support Files

+

+ The new Core Support Files are: +

+
    +
  • core_cm#.h (# = 0, 3, 4)
    • +
  • core_cmFunc.h (Cortex-M Core Register access functions)
    • +
  • core_cmInstr.h (Cortex-M Core instructions)
    • +
  • core_cm4_simd.h (Cortex-M4 SIMD instructions)
    • +
+ +

Changes to version V1.20

+ +

Removed CMSIS Middelware packages

+

+ CMSIS Middleware is removed and no longer focus of CMSIS. +

+ +

SystemFrequency renamed to SystemCoreClock

+

+ The variable name SystemCoreClock is more precise than SystemFrequency + because the variable holds the clock value at which the core is running. +

+ +

Changed startup concept

+

+ The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit + from main) has the weakness that it does not work for controllers which need a already + configuerd clock system to configure the external memory controller. +

+ +
Changed startup concept
+
    +
  • + SystemInit() is called from startup file before premain. +
    • +
  • + SystemInit() configures the clock system and also configures + an existing external memory controller. +
    • +
  • + SystemInit() must not use global variables. +
    • +
  • + SystemCoreClock is initialized with a correct predefined value. +
    • +
  • + Additional function void SystemCoreClockUpdate (void) is provided.
    + SystemCoreClockUpdate() updates the variable SystemCoreClock + and must be called whenever the core clock is changed.
    + SystemCoreClockUpdate() evaluates the clock register settings and calculates + the current core clock. +
    • +
+ + +

Advanced Debug Functions

+

+ ITM communication channel is only capable for OUT direction. To allow also communication for + IN direction a simple concept is provided. +

+
    +
  • + Global variable volatile int ITM_RxBuffer used for IN data. +
    • +
  • + Function int ITM_CheckChar (void) checks if a new character is available. +
    • +
  • + Function int ITM_ReceiveChar (void) retrieves the new character. +
    • +
+ +

+ For detailed explanation see file CMSIS debug support.htm. +

+ + +

Core Register Bit Definitions

+

+ Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the + defines correspond with the Cortex-M Technical Reference Manual. +

+

+ e.g. SysTick structure with bit definitions +

+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+ +

DoxyGen Tags

+

+ DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation + using DoxyGen. +

+ +

Folder Structure

+

+ The folder structure is changed to differentiate the single support packages. +

+ +
    +
  • CM0
    • +
  • CM3 +
      +
    • CoreSupport
      • +
    • DeviceSupport
      • +
        +
      • Vendor +
          +
        • Device +
            +
          • Startup +
              +
            • Toolchain
              • +
            • Toolchain
              • +
            • ...
              • +
            +
            • +
          +
          • +
        • Device
          • +
        • ...
          • +
        +
        • +
      • Vendor
        • +
      • ...
        • +
      + +
    • Example (optional) +
        +
      • Toolchain +
          +
        • Device
          • +
        • Device
          • +
        • ...
          • +
        +
        • +
      • Toolchain
        • +
      • ...
        • +
      +
      • +
    +
    • + +
  • Documentation
    • +
+ +

Open Points

+

+ Following points need to be clarified and solved: +

+
    +
  • +

    + Equivalent C and Assembler startup files. +

    +

    + Is there a need for having C startup files although assembler startup files are + very efficient and do not need to be changed? +

    +

    • +
  • +

    + Placing of HEAP in external RAM. +

    +

    + It must be possible to place HEAP in external RAM if the device supports an + external memory controller. +

    +
    • +
  • +

    + Placing of STACK /HEAP. +

    +

    + STACK should always be placed at the end of internal RAM. +

    +

    + If HEAP is placed in internal RAM than it should be placed after RW ZI section. +

    +
    • +
+ + +

Limitations

+

+ The following limitations are not covered with the current CMSIS version: +

+
    +
  • + No C startup files are available. +
    • +
+ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_Logo_Final.jpg b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_Logo_Final.jpg new file mode 100644 index 000000000..e04560175 Binary files /dev/null and b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_Logo_Final.jpg differ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_System_View_Description.htm b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_System_View_Description.htm new file mode 100644 index 000000000..fe5d71f88 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Documentation/CMSIS_System_View_Description.htm @@ -0,0 +1,1157 @@ + + + + CMSIS - SVD: Cortex Microcontroller Software Interface Standard - System View Description + + + + + + +

Cortex Microcontroller Software Interface Standard
+System View Description

+ +

This file describes the Cortex Microcontroller Software +Interface Standard - System View Description (CMSIS - SVD) concept and syntax.

+

Version: 1.02 - 27. July 2011

+ +

Information in this file, the accompany manuals, and software is
+ Copyright © ARM Ltd.
All rights reserved. +

+ +
+ +

Revision History

+
    +
  • Version 0.91: initial proposal.
    • +
  • Version 0.92: revised proposal considering forum feedback (e.g. consider + IP-XACT constructs and naming scheme)
    • +
  • Version 1.0: new elements: peripheral version, vendor specific + extension section, interrupt mapping information, global peripheral disable + condition, naming of register arrays, enhanced naming schemes, etc.
    • +
  • Version 1.0: SVD versioning and updated schema file
    • +
  • Version 1.01: Error corrections in the example code. "include" has been removed. Restricted to one device per file.
    • +
  • Version 1.02: Adding the use case of device header file generation.
    • +
+ +

 

+ +
+ +

Contents

+ +
    +
  1. About
    2. +
  2. Motivation
    3. +
  3. Requirements
    4. +
  4. Format
    5. +
  5. Example
    6. +
  6. Questions & Answers
    7. +
+ +

About

+ +

+ The Cortex Microcontroller Software Interface Standard - System View + Description (CMSIS - SVD) answers the challenges + of accurate, detailed and timely device aware peripheral debugging support for Cortex + Microcontroller based devices by the software development + tools vendor community. +

+

+ Silicon vendors shall create and maintain a formalized description of the + debug view for all the peripherals contained in their Cortex + Microcontroller based devices. Tool vendors use such descriptions to + establish device specific debug support in their debugging tools with minimal turn around times and + manageable effort. Device support across many development tools  is + essential for silicon provider in order to promote new devices and device + variants entering the market. Device aware debug views provide fast and + convenient access to all registers and fields as well as a detailed + description. This enables software developer to + develop and debug code most efficiently and adopt new devices early and + quickly.

+

+ A standardized System View Description shall provide a common approach to + capturing peripheral debug related information in a machine readable files. + The scope of the contained information is agreed to match the level usually + provided by silicon vendors in their device reference manuals, however in a + formalized XML based format. There + are other description languages already available. IP-XACT from the SPIRIT + consortium is a prominent example. IP-XACT covers the register description + sufficiently, however it comprises many other aspects of the devices like + ports, bus-protocols, modeling, tool flows, etc. making a direct use of + IP-XACT too complex. The design of the SVD language is + taking some guidance from IP-XACT thus allowing straight forward conversion + from IP-XACT to CMSIS-SVD where IP-XACT device information is already + available.

+

+ In a second step the CMSIS-SVD description shall be used for automatically + generating CMSIS compliant a device header file. This enables the + information in the header file to be consistent with what the debugger will + display and CMSIS compliant by construction. The header file generation will + require some additional pieces of information and therefore a future version + of the description will need to include some extensions for this purpose.

+

+ Device aware debugging support is only one aspect of device + support essential to software development environments, however it is one of + the most time consuming and error prone ones.

+

Motivation

+

+ +The software developer of microcontroller devices is faced with a growing number +of devices with an ever increasing number of peripheral blocks providing a wide +range of distinct and complex functionality. The development of drivers for +these peripherals is in the critical path of every project. Modern debuggers are supporting the software developer in getting the +software to run according to the requirements. A debugger providing peripheral awareness improves the +ability to access and interpret complex configuration and status information of +peripherals. Even though this is only one aspect of device support within microcontroller +development environments it is essential for the successful and timely adoption +of development tools and the device by the market.

+

Today software development environments address device aware +debugging in various ways. They either use documents or proprietary file formats +as input for providing peripheral views in the debuggers. +Extracting peripheral information from written documentation is a very time +consuming, tedious and error prone task. Having a file containing peripheral specific information to generate peripheral views +is going to make device support more affordable, reliable and timely. +The challenge for the tool providers is the support of many +different and incompatible file formats from a growing number of silicon vendors. +For silicon vendors it is time consuming and costly to engage with many tool +provider in order to achieve device support in a wide range of development +environments.

+

Standardizing on a System View Description aims to ease this challenge +by agreeing on a formal XML-based file format. In conjunction with supporting web server infrastructure silicon partner +shall upload and maintain such descriptions in a tool vendor agnostic device +database, hosted e.g. by the web server infrastructure + +cmsis.arm.com . Access control to sensitive information is managed on a per user +basis. This allows silicon vendors to upload information for devices that have +not been made public. 

+

Such an approach provides benefits for silicon and tool vendors as well as +software developers of Cortex-M based microcontroller devices

+
    +
  • timely and accurate device support provided by a whole range of tool providers
    • +
  • tool providers become more efficient in supporting a multitude of devices + and device variants
    • +
  • less interaction required between silicon vendors and the + tool providers
    • +
  • silicon provider has control over and maintains the System View + Description during the life cycle of the device
    • +
  • high quality device support in terms of completeness and correctness of + device aware debugging
    • +
  • improved productivity and user experience for the software developer
    • +
+

Requirements

+

The debug description shall capture the information about all +the peripherals contained in a specific device. This section describes which +items of information are deemed relevant for a debugger. Silicon vendors are expected to +provide the System View Description for their devices, matching the information +contained in device reference manuals. The System View Description shall be suitable for straight forward +generation from existing databases like IP-XACT descriptions or SIDSC. The size +of device description is a concern and therefore redundancy in the description +shall be avoided. The size of SVD files affects the efficiency of +distribution as well as the loading time by the development tools. Last but not least manual editing of SVD files shall be possible for +the purpose of customization by SW developers.

+

Required content of the description

+

From a programmer's perspective a peripheral can be seen as a set of registers +with unique names being mapped to fixed addresses allocated +within a defined range of an address space.

+

From a debugger's point of view read accesses to a physical register need to be +executed in order to display its current value. The debugger executes a write +access to a register when a user edits its value. For this purpose the debugger +needs to know about the following additional attributes:

+
    +
  • minimal addressable unit = smallest series of bits + identified by a unique address (e.g. byte-addressable memory)
    • +
  • register size = number of bits forming a register (ARM Cortex-M usually + 32 bits)
    • +
  • access permission = read and write, read only, + write only
    • +
  • access side effects = accesses by the debugger must + be avoided if it has side effects. Some side effects may be + reversed by the debugger to compensate for the side effect
    • +
+

In many cases peripheral registers are partitioned into chunks of bits of +distinct functionality. In this document these chunks are referred to as +field. Each +register that consists of fields shall  be described by a list +of uniquely named fields (Note: field names are not required to be +unique across registers). In order for a debugger to extract the +value of a field from the corresponding register the following attributes are required:

+
    +
  • most significant bit = highest bit position of the + bit-field in the corresponding register
    • +
  • least significant bit = lowest bit position of the + bit-field within the corresponding register
    • +
  • access permission = read and write, read only, + write only
    • +
+

An enumerated value maps a number to a specific descriptive string +representing the semantics of the value of a field. The debugger displays the +descriptive string rather than the number to simplify the access to the +information thus +avoiding the necessity of a look-up in the device reference manual. Each item of +an enumerated value has the following attributes:

+
    +
  • value = value of the bit-field that corresponds to + the string attribute
    • +
  • name = short string that describes the semantics of a + field when the corresponding value is set
    • +
  • description = detailed description of the semantics + of the field when the corresponding value is set
    • +
+

The hierarchical structure of the description looks like this:

+

Device =

+
    +
  • +

     Peripherals

    +
      +
    • +

      Peripheral

      +
        +
      • +

        Registers

        +
          +
        • +

          + Register

          +
            +
          • +

            + Fields

            +
              +
            • +

              Field

              +
                +
              • +

                Enumerated Values

                +
                  +
                • +

                  Enumerated Value

                  +
                  • +
                +
                • +
              +
              • +
            +
            • +
          +
          • +
        +
        • +
      +
      • +
    +
    • +
+ +

One file can only contain a description for a single device or device family +sharing the identical description. Devices consists of a one or more peripherals. +Each peripheral contains +one or more registers, where each register may consist of one or more fields. +The values of a field maybe represented through descriptive strings and detailed +descriptions, the enumerated values.

+

In many cases there are multiple +instances of the same peripheral in a device (e.g. Timer0, Timer1, etc.). For +this reason the description has the concept of deriving a peripheral from a peripheral +that has already been described. The attribute derivedFrom specifies +such a relationship. +Similarly registers or fields can be reused within the device description. The +grouping of  peripherals providing +similar functionality (e.g. Simple Timer, Complex Timer) is controlled via the element groupName. +All peripherals associated with the same group name are collectively listed under this group +in the order they have been specified in the file. +Collecting  +similar or related peripherals into peripheral groups helps structuring the list +of peripherals e.g. in a drop down menu (tool dependent). Devices with a large +set of peripherals will benefit from this additional level of structure.

+

Each of the items (i.e. Device, Peripheral, Register and +Field) owns an description element containing verbose information about +the respective element. The description field plays +an important part in improving the software development productivity. Instead of +searching through the reference manual the detailed explanation from the manual +could become immediately accessible from within the development environment.

+

Details about the exact display format and layout of the peripheral view are +considered beyond the scope of the description. It is up to the tool vendor to +visualize the contained information appropriately. The +silicon vendor provides details about the device's peripherals that is commonly available.

+

System View Description files need to be validated for:

+
    +
  1. syntactical correctness using XML-Schema checking utilities
    2. +
  2. consistency  of the provided information (e.g. multiple registers mapped to the same address, + all registers located within the specified address ranges of a + peripheral, all fields are within the range of the register + size, etc.) by a utility developed by ARM (SVDConv.exe)
    3. +
  3.  semantical correctness of the System View Description + against the silicon specification executed by the silicon vendor
    4. +
+

The SVD description format was extended by numerous elements during the +review period targeting version 1.0 and new extensions are expected for future +versions of this format. A new section named "vendorExtensions" has been added +to the end of the top level to allow silicon vendors and tool partners to +innovate and expand the description in order to overcome limitations of the +current specification until these can be incorporated into new versions of +CMSIS-SVD.
+

+ +

 Format

+ +

+ The following section describes the SVD file format in detail. Each subsection + defines a single hierarchy level of the description and lists all mandatory + and optional language elements for that specific level including type + information for each element. Each element is discussed in more detail and a + brief snippet is provided as an example. The sequence of elements shown + below is binding. Optional elements are highlighted in green, blue elements + are mandatory unless they have been already specified globally on a higher + level.

+

+ An XML-schema file is provided alongside this document for syntactical + checking of descriptions being developed.

+

<device schemaVersion="xs:decimal" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">

+

   <name>xs:Name</name>
+   <version>xs:string</version>
+   <description>xs:string</description>
+   <addressUnitBits>scaledNonNegativeInteger</addressUnitBits>
+   <width>scaledNonNegativeInteger </width>
+
+   <size>scaledNonNegativeInteger</size>
+   <access>accessType</access>
+   <resetValue>scaledNonNegativeInteger</resetValue>
+   <resetMask>scaledNonNegativeInteger</resetMask>

+

   <peripherals>
+      ...
+   </peripherals>
+   <vendorExtensions>
+      ...
+    </vendorExtensions>

+

</device>

+

The device provides the outermost frame of the description. All other +elements like peripherals, registers and fields are described inside of this scope. A device contains one or more peripherals. +The optional elements size, access, resetValue and resetMask are used as default values throughout the +device description unless they get overruled on a lower level of the description +(e.g. peripheral or register).

+

Mandatory items:

+

name = the unique name string is used to identify the device. +All devices of a silicon vendor are required to have a unique name. In case an +SVD description covers a family or series of devices, the name of the series or +family is placed here. The device names of the members of the series or family +are listed in <memberDevices>

+

description = string describing main features of a device +(e.g. CPU, clock frequency, peripheral overview, etc.)

+

version = the string is defining the version of the +description for this device. Silicon vendors will maintain the description +throughout the lifecycle of the device and need to ensure that all updated and +released copies have a unique version string indicating the order in which. Note: this must not be used for +detailing the version of the device.

+

 

+

addressUnitBits = defines the number of data bits for each address +increment. The value for Cortex-M based devices is  8 (byte-addressable).

+

width = defines the number of bits for the maximum single +transfer size allowed by the bus interface hence the maximum size of a single +register that can be defined for the address space. This information is relevant +for debuggers when determining the size of debug transfers. The expected value +for Cortex-M based devices is 32.

+

peripherals = next level of description (see next section +for details)

+

Optional Items:

+

size = defines the default bit-width of registers contained +in the device. This element can be overruled by re-specifying the size element on a lower level of the +description.

+

access = defines the default access permissions for all +registers in the device. The allowed tokens are:
+  - read-only: read access is permitted. Write operations have an undefined +result.
+  - write-only: write access is permitted. Read operations have an +undefined result.
+  -read-write: both read and write accesses are permitted. Writes affect +the state of the register and reads return a value related to the register
+  -writeOnce: only the first write after reset has an effect on the +register. Read operations deliver undefined results
+  -read-writeOnce: Read operations deliver a result related to the register +content. Only the first write access to this register after a reset will have an +effect on the register content.

+

resetValue = defines the default value of all registers +after a reset. There are scenarios where SW developers need to know, what the +reset value of a register or field is. Even though listed as optional on this +level of the description, silicon vendors should ensure that this information is +provided for all registers.

+

resetMask = defines those bit positions set to one to be +taken from resetValue element. All other elements are undefined. If a register +does not have a defined reset value the resetMask needs to be set to 0.

+

vendorExtensions = the content and format of this section of +the description is unspecified. Silicon vendors may choose to provide additional +information. The assumption is that by default this section is completely +ignored by the debugger. It is up to the silicon vendor to specify the content +of this section and share the specification with the tool vendors. The new +elements shall be considered for a future version of the description format.

+

Example:

+
<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
+  <name>CMSIS_Cortex-M3</name>
+  <version>0.1</version>
+  <description>ARM Cortex-M3 based Microcontroller demonstration device</description>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0</resetValue>
+  <resetMask>0xffffffff</resetMask>
+
  <peripherals>
+    ...
+  </peripherals>
+</device>
+

The device description above is at version 0.1 and uniquely identifies the +device by the name "CMSIS_Cortex-M3". The peripherals are memory mapped in a +byte-addressable address space with a bus width of 32 bits. The default size of +the registers contained in the peripherals is set to 32 bits. Unless redefined +for specific peripherals, registers or fields all registers are read-write +accessible. A reset value of 0 valid for all 32 bits as specified by the reset +mask is set for all registers unless overruled at a lower level of the description.

+
+

<peripherals>

+

   <peripheral>
+     ...
+   </peripheral>

+

     ...

+

   <peripheral>
+     ...
+   </peripheral>

+

</peripherals>

+

This construct sets the frame for all peripherals and peripheral groups contained in a device. This +creates a container element which ease-up processing with languages like Java.

+
+

<peripheral derivedFrom="xs:Name">

+

   <name>xs:Name</name>
+   <version>xs:string</name>
+   <description>xs:string </description>
+   <groupName>xs:string</groupName>
+   <prependToName>xs:string</prependToName>
+   <appendToName>xs:string</appendToName>
+   <disableCondition>xs:string</disableCondition>
+   <baseAddress>scaledNonNegativeInteger</baseAddress>
+   <size>scaledNonNegativeInteger</size>
+   <access>accessType</access>
+   <resetValue>scaledNonNegativeInteger</resetValue>
+   <resetMask>scaledNonNegativeInteger</resetMask>

+

   <addressBlock>
+      <offset>scaledNonNegativeInteger</offset>
+      <size>scaledNonNegativeInteger</size>
+      <usage>usageType</usage>
+   </addressBlock>
+   ...
+  <addressBlock>
+      <offset>scaledNonNegativeInteger</offset>
+      <size>scaledNonNegativeInteger</size>
+      <usage>usageType</usage>
+   </addressBlock>
+   <interrupt>
+      <name>xs:string</name>
+      <value>scaledNonNegativeInteger</value>
+   </interrupt>
+   <registers>
+   ...
+   </registers>

+

</peripheral>

+

A peripheral encloses the description of one or more registers belonging to +this named peripheral. The address range allocated in the address space for this +peripheral is defined through one or more address ranges. An address range is +specified relative to the base address of the peripheral. This information +allows to display a memory map overview for all peripherals. Please note that +such a memory map does not contain any information for memories and unoccupied +address ranges.

+

Mandatory items:

+

name = name string used to identify the peripheral. Peripheral +names are required to be unique within the scope of a device.

+

baseAddress = lowest address reserved or used by the peripheral

+

description = string providing an overview of the purpose +and functionality of the peripheral

+

addressBlock = a peripheral may occupy one or more disparate +blocks in the address space. An addressBlock is a complex element consisting of +the mandatory elements:
+    offset: specifying the start address of an address block. It +is calculated from the sum of baseAddress and offset
+    size: specifying the number of addressUnitBits being covered +by this address block. The end address of an address block is the sum of start +address and the size - 1.
+    usage: the usage element is of usageType specifying +if the addresses within the specified address block is used for +registers or buffer or is reserved. +
+Note: registers must not be allocated +to an address within a reserved or buffer address range.

+

registers = next lower level of description (see next section +for details)

+

Optional items:

+

derivedFrom = this attribute specifies the name of a peripheral +that has already been described for this device. The description of that device +will be copied. It is mandatory to overwrite the name as well as the +addressOffset. All other specified information will overwrite the respective +elements in the copy.

+

version = the string specifies the version of this +peripheral description.

+

disableCondition = C language compliant logical expression +resulting in a true or false result. If "true" the refresh of the display +for this peripheral is disabled +and related accesses by the debugger are suppressed. Only constants and references to other registers +contained in the description are allowed:  +<peripheral>-><register>-><field> (e.g.: (System->ClockControl->apbEnable == 0)). +Only the following operators are allowed [&&,||, ==, !=, >>, <<, &, |]. Warning! +This feature must only be use in case accesses from the debugger to registers of +un-clocked peripherals result in severe debugging failures. SVD is intended to +be fully static information and not include any run-time computation or +functions such capabilities may be added by the tools but is considered beyond +the scope of this description language.

+

prependToName = all register names of this peripheral have +their names prepended with the string specified

+

appendToName = all register names of this peripheral have +their names appended with the string specified

+

size = defines the default bit-width of registers contained +in the device. This element can be overruled by re-specifying the size element on a lower level of the +description.

+

access = defines the default access permissions for all +registers in the peripheral. The value can be reset on a lower level of the +description. The allowed tokens are:
+  - read-only: read access is permitted. Write operations have an undefined +result.
+  - write-only: write access is permitted. Read operations have an +undefined result.
+  -read-write: both read and write accesses are permitted. Writes affect +the state of the register and reads return a value related to the register
+  -writeOnce: only the first write after reset has an effect on the +register. Read operations deliver undefined results
+  -read-writeOnce: Read operations deliver a result related to the register +content. Only the first write access to this register after a reset will have an +effect on the register content.

+

resetValue = defines the default value of all registers +after a reset but can be set for individual registers and fields on a lower +level of the description.

+

resetMask = defines those bit positions set to one to be +taken from resetValue element. All other elements are undefined. This is the +default value for the whole peripheral but can be readjusted on lower levels. If +a register does not have a defined reset value the resetMask needs to be set to +0.

+

interrupt = is a complex type that consists of the name of +the interrupt and the associated enumeration value. A peripheral can also have +multiple associated interrupts. This entry is mainly intended for information +only purposes in order to display the interrupts and respective interrupt +numbers associated with a peripheral.

+

Example:

+
... 
+    <peripheral>
+       <name>Timer0</name>
+       <version>1.0.32</version>
+       <description>Timer 0 is a simple 16 bit timer counting down ... </description>
+       <baseAddress>0x40000000</baseAddress>
+       <addressBlock>
+         <offset>0x0</offset>
+         <size>0x400</size>
+         <usage>registers</usage>
+       </addressBlock>
+       <interrupt><name>TIM0_INT</name><value>34</value></interrupt>
+       <registers>
+         ...
+       </registers>
+    </peripheral>
+    <peripheral derivedFrom="Timer0">
+      <name>Timer1</name>
+      <baseAddress>0x40000400</baseAddress>
+    </peripheral>
+
+...
+
+

<registers> ... </registers>

+

This construct sets the frame for all registers contained in a peripheral. +This creates container elements which ease-up processing with languages like Java.

+
+

<register derivedFrom=xs:Name>

+

   <dim>scaledNonNegativeInteger</dim>
+   <dimIncrement>scaledNonNegativeInteger</dimIncrement>
+   <dimIndex>xs:string</dimIndex>
+   <name>xs:Name</name>
+   <displayName>xs:string</displayName>
+   <description>xs:string</description>
+   <alternateGroup>xs:Name</alternateGroup>
+   <addressOffset>scaledNonNegativeInteger +</addressOffset>
+    <size>scaledNonNegativeInteger</size>
+   <access>accessType</access>
+   <resetValue>scaledNonNegativeInteger</resetValue>
+   <resetMask>scaledNonNegativeInteger</resetMask>
+ +   <modifiedWriteValues>writeValueType</modifiedWriteValues>
+   <writeConstraint>writeConstraintType</writeConstraint>
+   <readAction>readActionType </readAction>
+   <fields>
+      ...
+   </fields>

+

</register>

+

The definition of registers is the central part of the description. A +register may use its complete size for a single purpose and therefore not +consist of fields. Otherwise the description +of fields is mandatory.

+

Mandatory items:
+

+

name = name string used to identify the register. Register +names are required to be unique within the scope of a peripheral.

+

description = string describing the details of the register.

+

addressOffset = value defining the address of the register relative to +the baseAddress defined by the peripheral the register belongs to.
+

+

The following elements can be omitted if the corresponding value has been set +on a higher level of the description and matches the value required for this register:

+

size =value defining the bit-width of the register

+

access = predefined tokens: read-only, write-only, read-write, +writeOnce, read-writeOnce strings defining the allowed +accesses for this register.

+

resetValue = element defining the value of the register +immediately after a reset.

+

resetMask= element specifying those bits of the resetValue that +are defined (bit positions containing a 0 bit are ignored, bit +positions containing a 1 bit are taken from the corresponding bit position of +the resetValue). If a register does not have a defined reset value the resetMask +needs to be set to 0.

+

Optional items:

+

dim = if this field is specified the value defines the +number of elements in an array of registers.

+

dimIncrement = if dim is specified this element becomes +mandatory and specifies the address increment in between +two neighboring registers of the register array in the address map.

+

dimIndex = this element specifies the substrings within the +register array names that will replace the %s within the register name. By +default the index is a decimal value starting with 0 for the first register. +Examples:
+   <dim>6</dim> <dimIncrement>4</dimIncrement> <dimIndex>A,B,C,D,E,Z</dimIndex> +<name>GPIO_%s_CTRL</name> ...
+   => GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL, +GPIO_Z_CTRL
+   <dim>4</dim> <dimIncrement>4</dimIncrement> <dimIndex>3-6</dimIndex> +<name>IRQ%s</name> ...
+   => IRQ3, IRQ4, IRQ5, IRQ6                 

+

displayName = when used, this is the string being used by a +graphical frontend to visualize the register otherwise the name element is used. +Note: the display name may contain special characters and white spaces. It also +uses "%s" as the place holder for the dimIndex substring.

+

alternateGroup = when used, this element specifies a name of +a group that all alternate register with the same name a associated with. At the +same time it indicates that there is a register description allocating the same +absolute address in the address space.

+

modifiedWriteValues = element to describe the manipulation of +data written to a register. If not specified the value written to the field is the +value stored in the field. The other options are bitwise operations:
+  oneToClear: write data bits of one shall clear (set to zero) the +corresponding bit in the register
+  oneToSet: write data bits of one shall set (set to one) the +corresponding bit in the register
+  oneToToggle: write data bits of one shall toggle (invert) the +corresponding bit in the register
+  zeroToClear: write data bits of zero shall clear (set to zero) +the corresponding bit in the register
+  zeroToSet: write data bits of zero shall set (set to one) the +corresponding bit in the register
+  zeroToToggle: write data bits of zero shall toggle (invert) the +corresponding bit in the register
+  clear: after a write operation all bits in the field are cleared (set to +zero)
+  set: after a write operation all bits in the field are set (set to one)
+  modify: after a write operation all bit in the field may be modified +(default)

+

writeConstraint: has a set of options:
+  writeAsRead = if true only the last read value can be written
+  useEnumeratedValues = if true only those values listed in the +enumeratedValues list are considered valid write values
+  minimum = specifies the smallest number to be written to the +register
+  maximum = specifies the largest number to be written to the +register

+

readAction: if set it specifies the side effect following +read operations. If not set the register is not modified following a read +operations. The defined side effects are:
+  clear: indicates that the register is cleared (set to zero) +following a read operation
+  set: indicates that the register is set (set to ones) following a +read operation
+  modify: indicates that the register is modified in some way +after a read operation
+  modifyExternal: indicates that one or more dependent resources +other than the current register +are immediately affected by a read (it is recommended that the register +description specifies these dependencies). Debuggers are not expected to read +this register location unless explicitly instructed by user.

+

fields = next lower level of description (see next section +for details).

+

Optional attribute:

+

derivedFrom = specifies the name of the register to be +replicated. Elements being specified underneath will override the values specified +from the register being derived from. Note that it is mandatory to overwrite at +least name and addressOffset.

+

Example:

+
... 
+       <register>
+         <name>TimerCtrl0</name>
+         <description>Timer Control Register</description>
+         <addressOffset>0x0</addressOffset>
+         <access>read-write</access>
+         <resetValue>0x00008001</resetValue>
+         <resetMask>0x0000ffff</resetMask>
+         <size>32<size>
+         <fields>
+           ...
+         </fields>
+       </register>
+       <register derivedFrom="TimerCtrl0">
+         <name>TimerCtrl1</name>
+         <addressOffset>0x4<addressOffset>
+       </register>
+...
+
+

<fields> ... </fields>

+

This construct sets the frame for all fields contained in a register. +This creates container elements which ease-up processing with languages like Java.

+
+

 <field derivedFrom="xs:Name">

+

   <name>xs:Name</name>
+   <description>xs:string</description>
+   +<bitOffset>scaledNonNegativeInteger</bitOffset> +<bitWidth>scaledNonNegativeInteger</bitWidth>
+   or
+   <lsb>scaledNonNegativeInteger</lsb> <msb>scaledNonNegativeInteger</msb>
+   or
+   <bitRange>pattern</bitRange>
+   <access>accessType</access>
+   <modifiedWriteValues>writeValueType</modifiedWriteValues>
+   <writeConstraint>writeConstraintType</writeConstraint>
+   <readAction>readActionType </readAction>
+   <enumeratedValues>
+      ...
+   </enumeratedValues>

+

</field>

+

A bit-field has a name that is unique for the register it belongs to. The +position and size within the register is either described by the combination of +the least significant bit's position (lsb) and the most significant bit's +position (msb) or the lsb and the size, specifying the bit-width of the +field.  A field may define an enumeratedValue in order to make the display +more intuitive to read.

+

Mandatory items:

+

name = name string used to identify the field. Field names +are required to be unique within the scope of a register.
+

+

description = string describing the details of the register.
+

+

There are 3 ways to describe a field to be used mutually exclusive:
+a) specifying bitOffset and bitWidth (IP-XACT like)
+b) specifying lsb and msb of the field.
+c) specifying a bit range in the format "[<msb>:<lsb>]"

+

bitOffset = value defining the position of the least significant bit +of the field within the register it belongs to.
+bitWidth = value defining the bit-width of the bitfield within the +register it belongs to.
+

+

+lsb = value defining the bit position of the least significant +bit within the register it belongs to.
+msb = value defining the bit position of the most significant +bit within the register it belongs to. +

+

bitRange = a string in the format: [<msb>:<lsb>]
+

+

Optional items:

+

derivedFrom = the field is cloned +from a previously defined field with a unique name.

+

access = predefined strings defining the allowed +accesses for this register: read-only, write-only, read-write, writeOnce, +read-writeOnce. Can be omitted if it matches the access permission set for the parent register.

+

enumeratedValues = next lower level of description (see next section +for details)

+

modifiedWriteValues = element to describe the manipulation of +data written to a field. If not specified the value written to the field is the +value stored in the field. The other options are bitwise operations:
+  oneToClear: write data bit of one shall clear (set to zero) the +corresponding bit in the field
+  oneToSet: write data bit of one shall set (set to one) the corresponding +bit in the field
+  oneToToggle: write data bit of one shall toggle (invert) the +corresponding bit in the field
+  zeroToClear: write data bit of zero shall clear (set to zero) the +corresponding bit in the field
+  zeroToSet: write data bit of zero shall set (set to one) the +corresponding bit in the field
+  zeroToToggle: write data bit of zero shall toggle (invert) the +corresponding bit in the field
+  clear: after a write operation all bits in the field are cleared (set to +zero)
+  set: after a write operation all bits in the field are set (set to one)
+  modify: after a write operation all bit in the field may be modified +(default)

+

writeConstraint: has a set of options:
+  writeAsRead = if true only the last read value can be written
+  useEnumeratedValues = if true only those values listed in the +enumeratedValues list are considered valid write values
+  minimum = specifies the smallest number to be written to the field
+  maximum = specifies the largest number to be written to the field

+

readAction: if set it specifies the side effect following +read operations. If not set the field is not modified following a read +operations. The defined side effects are:
+  clear: indicates that the field is cleared (set to zero) +following a read operation
+  set: indicates that the field is set (set to ones) following a +read operation
+  modify: indicates that the field is modified in some way after a +read operation  +
+  modifyExternal: indicates that one or more dependent resources +other than this field are immediately affected by a read (it is recommended that +the field description specifies these dependencies). Debuggers are not expected +to read the field unless explicitly instructed by user.

+

Example:

+
...
+         <field>
+           <name>TimerCtrl0_IntSel</name>
+           <description>Select interrupt line that is triggered by timer overflow.</description>
+	   <bitOffset>1</bitOffset>
+           <bitWidth>3</bitWidth>
+           <access>read-write</access>
+	   <resetValue>0x0</resetValue>
+           <modifiedWriteValues>oneToSet</modifiedWriteValues>
+           <writeConstraint>
+              <range>
+                <minimum>0</minimum>
+                <maximum>5</maximum>
+              </range>
+           </writeConstraint>
+           <readAction>clear</readAction>
+ 
+           <enumeratedValues>
+              ...
+           </enumeratedValues>
+         </field>
+...
+
+

<enumeratedValues +derivedFrom="xs:Name">

+

   <name>xs:Name</name>
+   <usage>usageType</usage>
+   <enumeratedValue>
+      ...
+   </enumeratedValue>

+

      ... 

+

   <enumeratedValue>
+      ...
+   </enumeratedValue>

+

</enumeratedValues>

+

An enumerated value provides one or more enumeration items (enumeratedValue), defining a map +between all possible values of the bit-field it belongs to and the corresponding +human readable semantics of that value.

+

Mandatory items:
+enumeratedValue = next lower level of description (see next section +for details)

+

Optional items:
+derivedFrom = the enumeratedValues can be copied or derived +from a previously defined enumeratedValue that has been given a unique name.
+name = name string to identify an enumeratedValue. Named +enumeratedValues need to be unique in the scope of a device in order to be reusable +throughout the description of a device.
+usage = possible values are read, write or +read-write. This allows to specify two different enumerated values +depending whether it is to be used for a read or a write access. If not specified the enueratedValues are valid for read and write.

+

Example:

+
...
+           <enumeratedValues>
+              <name>TimerIntSelect</name>
+              <usage>read-write</usage>
+              <enumeratedValue>
+                <name>disabled</name>
+                <description>disabled bit</description>
+                <value>0</value>
+              </enumeratedValue>
+              ...
+              <enumeratedValue>
+                <name>reserved</name>
+	        <description>reserved values. Do not use</description>
+                <isDefault>true</isDefault>
+              </enumeratedValue>
+           </enumeratedValues>
+...
+
+

<enumeratedValue>

+

   <name>xs:name</name>
+   <description>xs:string</description>
+   <value>scaledNonNegativeInteger</value>
+   +or
+   <isDefault>xs:boolean</isDefault>
+

+

</enumeratedValue>

+

An enumeratedValue defines a map between a value and the string reading the +corresponding human readable semantics for that value in a brief and a detailed +version

+

Mandatory items:

+

name= brief string verbally describing the semantics of the value +defined for this enumeratedValue. E.g. used for display in visualization of a bit-field +instead of the value.

+

+value = defines the constant of the bit-field that the name +corresponds to.

+

isDefault = defines the name and description for all other +values that are not explicitly listed

+

Optional item:

+

description = extended string verbally describing the semantics +of the value defined for this enumeratedValue in full detail.

+

Example:

+
...
+         <enumeratedValue>
+            <name>disabled</name>
+            <description>Timer does not generate interrupts</description>
+            <value>0</value>
+         </enumeratedValue>
+         ...
+         <enumeratedValue>
+            <name>enabled</name>
+            <description>Timer does not generate interrupts</description>
+            <isDefault>true</isDefault>
+         </enumeratedValue>
+
+...
+
+

Names

+

Names shall comply with ANSI C variable naming restrictions.

+

Constants

+

Number constants shall be entered in hexadecimal, decimal or binary format.

+
    +
  • hexadecimal is indicated by a leading "0x"
    • +
  • binary format is indicated by a leading  "#"
    • +
  • all other formats are interpreted as decimal numbers
    • +
  • the value tag in enumeratedValue accepts do not care bits + represented by "x"
    • +
+

Comments

+

Comments have the standard XML format "<!--" starts a comment + "-->" terminates a comment

+

Example

+
+<?xml version="1.0" encoding="utf-8"?>
+ 
+<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
+  <name>Cortex_M3_Sample</name>
+  <version>0.1</version>
+  <description>ARM Cortex-M3 based Microcontroller dummy device</description>
+  <!-- Bus Interface Properties -->
+  <!-- Cortex-M3 is byte addressable -->
+  <addressUnitBits>8</addressUnitBits>
+  <!-- the maximum data bit width accessible within a single transfer is 32bits -->
+  <width>32</width>
+
+  <!-- Register Default Properties -->
+  <!-- the size of the registers is set to a bit width of 32. This can be overruled for individual peripherals and/or registers -->
+  <size>32</size>
+  <!-- the access to all registers is set to be readable and writeable. This can be overruled for individual peripherals and/or registers -->
+  <access>read-write</access>
+  <!-- for demonstration purposes the resetValue for all registers of the device is set to be 0. This can be overruled within the description -->
+  <resetValue>0</resetValue>
+  <!-- the resetMask = 0 specifies that by default no register of this device has a defined reset value -->
+  <resetMask>0</resetMask>
+
+  <peripherals>
+    <peripheral>
+      <name>Timer0</name>
+      <description>A simple 16 bit timer counting down ... </description>
+      <groupName>Timer</groupName>
+      <baseAddress>0x40000000</baseAddress>
+      <!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <addressBlock>
+        <offset>0x8</offset>
+        <size>0x3f8</size>
+        <usage>reserved</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIM0_IRQn</name>
+        <value>34</value>
+      </interrupt>
+      <registers>
+        <register> 
+          <name>TimerCtrl0</name>
+          <!-- the display name is an unrestricted string. -->
+          <displayName>Timer Ctrl 0</displayName>
+          <description>Timer Control Register</description>
+          <addressOffset>0x0</addressOffset>
+          <!-- size=32, access=read-write, resetValue=0x0, resetMask=0xffffffff, volatile=false -->
+          <fields>
+            <field>
+              <name>TimerCtrl0_En</name>
+              <description>Enable Bit activates the timer.</description>
+              <!-- Spirit like bit range description: [0:0] -->
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <!-- Writing 1 enables, writing 0 has no effect -->
+	      <modifiedWriteValues>oneToSet</modifiedWriteValues>
+              <!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed -->
+              <writeConstraint>
+                <useEnumeratedValues>true</useEnumeratedValues>
+              </writeConstraint>
+              <!-- there is no side effect on reads, therefore <readAction> is not set -->
+              <!-- oneBitEnable named enumeration that can be reused in other parts of the description -->
+              <enumeratedValues>
+                <name>oneBitEnable</name>
+                <!-- the same enumerated Values are used for read and write. This default is assumed when this tag is missing -->
+                <usage>read-write</usage>
+                <enumeratedValue>
+                  <name>enabled</name>
+                  <description>Timer is enabled and active</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>disabled</name>
+                  <description>Timer is disabled and inactive</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TimerCtrl0_Dis</name>
+              <description>Disable Bit deactivates the timer.</description>
+              <!-- Spirit like bit range description: [1:1] -->
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <!-- Writing 1 sets, writing 0 has no effect -->
+	      <modifiedWriteValues>oneToSet</modifiedWriteValues>
+              <!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed -->
+              <writeConstraint>
+                <useEnumeratedValues>true</useEnumeratedValues>
+              </writeConstraint>
+              <!-- there is no side effect on reads, therefore <readAction> is not set -->
+              <!-- oneBitEnable named enumeration that can be reused in other parts of the description -->
+              <enumeratedValues derivedFrom="oneBitEnable"></enumeratedValues>
+            </field>
+            <field>
+              <name>TimerCtrl0_Int</name>
+              <description>Select interrupt line that is triggered by timer overflow.</description>
+              <!-- the position of the bit field is described in the bitRange style. -->
+              <bitRange>[4:2]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>disabled</name>
+                  <description>Timer does not generate interrupts</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 0</name>
+                  <description>Timer does generate interrupts on interrupt line 0</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 1</name>
+                  <description>Timer does generate interrupts on interrupt line 1</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 2</name>
+                  <description>Timer does generate interrupts on interrupt line 2</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 3</name>
+                  <description>Timer does generate interrupts on interrupt line 3</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 4</name>
+                  <description>Timer does generate interrupts on interrupt line 4</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <!-- this is the default element. All the valid value not listed above (6,7) have the following name and description -->
+                <enumeratedValue>
+                  <name>reserved</name>
+                  <description>Timer is configured incorrectly and the functionality is considered unpredictable</description>
+                  <isDefault>true</isDefault>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TimerCounter0</name>
+          <description>Timer0 16 Bit Counter Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>16</size>
+        </register>
+        <!-- a copy of the counter register TimerCounter0 with the name="TimerCounter1" and the addressOffset="0x8" -->
+        <register derivedFrom="TimerCounter0">
+          <name>TimerCounter1</name>
+          <addressOffset>0x6</addressOffset>
+        </register>
+        <!-- ... this is a restricted demo example and a real timer peripheral would have more register to be complete -->
+      </registers>
+    </peripheral>
+    <!-- a copy of Timer0 with the name="Timer1 and the baseAddress="0x40000400" -->
+    <peripheral derivedFrom="Timer0">
+      <name>Timer1</name>
+      <baseAddress>0x40000400</baseAddress>
+      <interrupt>
+        <name>TIM1_IRQn</name>
+        <value>35</value>
+      </interrupt>
+    </peripheral>
+  </peripherals>
+</device>
+ +

Questions & Answers

+

Is there any relation between the System View Description and the CMSIS +standard?

+

Initiallly there was no immediate link but both initiatives had a common goal: +Create a sound software development eco-system for Cortex-M based +Microcontroller, giving the customers the free choice of devices and software +development environments and all resources required for a successful product +development in a single location. Meanwhile we have started to generate +CMSIS compliant device header files from the same CMSIS-SVD description. We will +introduce a small number of additional description tags in the next version of +the specification. The benefit is the synchronization between symbols used in +the application and the symbols displayed by the debugger. 

+

Why does the format not provide constructs like macros and +conditional statements?

+

It is assumed that the description is generated from other sources and +therefore such concepts would only complicate the language unnecessarily. It is +recommended to use a standard C pre-processor to generate the debug description +format from a redundancy optimized description.

+

Do we need to consider endianess in the description?

+

This should be specified on a device configuration level and is not specific +to the visualization of peripheral details in a System View. Endianess becomes +relevant when using bit fields in the CMSIS compliant device header file.

+

Is the System View Description limited to Cortex-M based devices ?

+ + +

There may have been assumptions made about the structure of the device due to +it being developed around a Cortex-M processor. E.g. that all peripherals are +assumed to be memory mapped and to reside in a single address space. It is quite +likely that the description format may also serve other architectures +sufficiently. There is no intent to limit the format to Cortex-M +processor based devices.

+ + + \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_common_tables.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_common_tables.h new file mode 100644 index 000000000..34f910f9b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,35 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 11. November 2010 +* $Revision: V1.0.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern uint16_t armBitRevTable[256]; +extern q15_t armRecipTableQ15[64]; +extern q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_math.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_math.h new file mode 100644 index 000000000..d8901db15 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_math.h @@ -0,0 +1,7051 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * $Date: 15. July 2011 + * $Revision: V1.0.10 + * + * Project: CMSIS DSP Library + * Title: arm_math.h + * + * Description: Public header file for CMSIS DSP Library + * + * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 + * + * Version 1.0.10 2011/7/15 + * Big Endian support added and Merged M0 and M3/M4 Source code. + * + * Version 1.0.3 2010/11/29 + * Re-organized the CMSIS folders and updated documentation. + * + * Version 1.0.2 2010/11/11 + * Documentation updated. + * + * Version 1.0.1 2010/10/05 + * Production release and review comments incorporated. + * + * Version 1.0.0 2010/09/20 + * Production release and review comments incorporated. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of modules each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Processor Support + * + * The library is completely written in C and is fully CMSIS compliant. + * High performance is achieved through maximum use of Cortex-M4 intrinsics. + * + * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, + * with the DSP intrinsics being emulated through software. + * + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.21. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * Each library project have differant pre-processor macros. + * + * ARM_MATH_CMx: + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target. + * + * ARM_MATH_BIG_ENDIAN: + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * ARM_MATH_MATRIX_CHECK: + * Define macro for checking on the input and output sizes of matrices + * + * ARM_MATH_ROUNDING: + * Define macro for rounding on support functions + * + * __FPU_PRESENT: + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. + * + * Copyright Notice + * + * Copyright (C) 2010 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the #define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" + #include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#define PI 3.14159265358979f + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#define __SIMD32(addr) (*(int32_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ(q31_t data); + + + static __INLINE uint32_t __CLZ(q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return(count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0 */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (char) x; + s = (char) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (char) x; + s = (char) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t)(((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t)(((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + + +#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t *pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t *pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t *pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + #ifdef ARM_MATH_CM0 + q15_t A1; + q15_t A2; + #else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ + #endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; + float32_t x1; + float32_t xSpacing; + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + /** + * @brief Processing function for the Q15 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Initialization function for the Q15 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Initialization function for the Q31 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point CFFT/CIFFT. + * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Initialization function for the floating-point CFFT/CIFFT. + * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + + /*---------------------------------------------------------------------- + * Internal functions prototypes FFT function + ----------------------------------------------------------------------*/ + + /** + * @brief Core function for the floating-point CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to the twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the floating-point CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @param[in] onebyfftLen value of 1/fftLen. + * @return none. + */ + + void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftSize length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. + * @param[in] *pBitRevTab points to the bit reversal table. + * @return none. + */ + + void arm_bitreversal_f32( + float32_t *pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Core function for the Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q31( + q31_t *pSrc, + uint32_t fftLen, + q31_t *pCoef, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the Q31 CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Core function for the Q15 CFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q15( + q15_t *pSrc16, + uint32_t fftLen, + q15_t *pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the Q15 CIFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q15( + q15_t *pSrc16, + uint32_t fftLen, + q15_t *pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + /** + * @brief Processing function for the Q15 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Initialization function for the Q15 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Initialization function for the Q31 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Initialization function for the floating-point RFFT/RIFFT. + * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point RFFT/RIFFT. + * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t *pkCoeffs, + float32_t *pvCoeffs, + float32_t *pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t *pkCoeffs, + q31_t *pvCoeffs, + q31_t *pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t *pkCoeffs, + q15_t *pvCoeffs, + q15_t *pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t *pSinVal, + float32_t *pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t *pSinVal, + q31_t *pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + + /* Implementation of PID controller */ + + #ifdef ARM_MATH_CM0 + + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0 )* in ; + + #else + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + #endif + + #ifdef ARM_MATH_CM0 + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0] ; + acc += (q31_t) S->A2 * S->state[1] ; + + #else + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); + + #endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (x - S->x1) / xSpacing; + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if(i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues-1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i +1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, + q31_t x, uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, float32_t *pOut) + { + if(in > 0) + { + +// #if __FPU_USED + #if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, q31_t *pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, q15_t *pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) + { + return(0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex-1) * S->numCols ; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex-1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm0.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 000000000..edd522173 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,665 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + + +/** \mainpage CMSIS Cortex-M0 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks */ +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP + and not via processor. Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm3.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 000000000..c15e10ae2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1236 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + + +/** \mainpage CMSIS Cortex-M3 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks */ +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB + Type definitions for the Cortex-M System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ +#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 000000000..76bf8292a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,1378 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + + +/** \mainpage CMSIS Cortex-M4 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + - Cortex-M SIMD instructions + + The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks to define __FPU_USED */ + #define __FPU_USED 0 +#endif + +#include /*!< standard types definitions */ +#include /*!< Core Instruction Access */ +#include /*!< Core Function Access */ +#include /*!< Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB + Type definitions for the Cortex-M System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ +#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU CMSIS FPU + Type definitions for the Cortex-M Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4_simd.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4_simd.h new file mode 100644 index 000000000..479188696 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4_simd.h @@ -0,0 +1,701 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/ +/* intrinsic __SADD8 see intrinsics.h */ +/* intrinsic __QADD8 see intrinsics.h */ +/* intrinsic __SHADD8 see intrinsics.h */ +/* intrinsic __UADD8 see intrinsics.h */ +/* intrinsic __UQADD8 see intrinsics.h */ +/* intrinsic __UHADD8 see intrinsics.h */ +/* intrinsic __SSUB8 see intrinsics.h */ +/* intrinsic __QSUB8 see intrinsics.h */ +/* intrinsic __SHSUB8 see intrinsics.h */ +/* intrinsic __USUB8 see intrinsics.h */ +/* intrinsic __UQSUB8 see intrinsics.h */ +/* intrinsic __UHSUB8 see intrinsics.h */ +/* intrinsic __SADD16 see intrinsics.h */ +/* intrinsic __QADD16 see intrinsics.h */ +/* intrinsic __SHADD16 see intrinsics.h */ +/* intrinsic __UADD16 see intrinsics.h */ +/* intrinsic __UQADD16 see intrinsics.h */ +/* intrinsic __UHADD16 see intrinsics.h */ +/* intrinsic __SSUB16 see intrinsics.h */ +/* intrinsic __QSUB16 see intrinsics.h */ +/* intrinsic __SHSUB16 see intrinsics.h */ +/* intrinsic __USUB16 see intrinsics.h */ +/* intrinsic __UQSUB16 see intrinsics.h */ +/* intrinsic __UHSUB16 see intrinsics.h */ +/* intrinsic __SASX see intrinsics.h */ +/* intrinsic __QASX see intrinsics.h */ +/* intrinsic __SHASX see intrinsics.h */ +/* intrinsic __UASX see intrinsics.h */ +/* intrinsic __UQASX see intrinsics.h */ +/* intrinsic __UHASX see intrinsics.h */ +/* intrinsic __SSAX see intrinsics.h */ +/* intrinsic __QSAX see intrinsics.h */ +/* intrinsic __SHSAX see intrinsics.h */ +/* intrinsic __USAX see intrinsics.h */ +/* intrinsic __UQSAX see intrinsics.h */ +/* intrinsic __UHSAX see intrinsics.h */ +/* intrinsic __USAD8 see intrinsics.h */ +/* intrinsic __USADA8 see intrinsics.h */ +/* intrinsic __SSAT16 see intrinsics.h */ +/* intrinsic __USAT16 see intrinsics.h */ +/* intrinsic __UXTB16 see intrinsics.h */ +/* intrinsic __SXTB16 see intrinsics.h */ +/* intrinsic __UXTAB16 see intrinsics.h */ +/* intrinsic __SXTAB16 see intrinsics.h */ +/* intrinsic __SMUAD see intrinsics.h */ +/* intrinsic __SMUADX see intrinsics.h */ +/* intrinsic __SMLAD see intrinsics.h */ +/* intrinsic __SMLADX see intrinsics.h */ +/* intrinsic __SMLALD see intrinsics.h */ +/* intrinsic __SMLALDX see intrinsics.h */ +/* intrinsic __SMUSD see intrinsics.h */ +/* intrinsic __SMUSDX see intrinsics.h */ +/* intrinsic __SMLSD see intrinsics.h */ +/* intrinsic __SMLSDX see intrinsics.h */ +/* intrinsic __SMLSLD see intrinsics.h */ +/* intrinsic __SMLSLDX see intrinsics.h */ +/* intrinsic __SEL see intrinsics.h */ +/* intrinsic __QADD see intrinsics.h */ +/* intrinsic __QSUB see intrinsics.h */ +/* intrinsic __PKHBT see intrinsics.h */ +/* intrinsic __PKHTB see intrinsics.h */ + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmFunc.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmFunc.h new file mode 100644 index 000000000..c999b1c83 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,609 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V2.10 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmInstr.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmInstr.h new file mode 100644 index 000000000..ceb4f8756 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,585 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/README.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/README.txt new file mode 100644 index 000000000..cc69e2ca2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/README.txt @@ -0,0 +1,34 @@ +* ------------------------------------------------------------------- +* Copyright (C) 2011 ARM Limited. All rights reserved. +* +* Date: 25 July 2011 +* Revision: V2.10 +* +* Project: Cortex Microcontroller Software Interface Standard (CMSIS) +* Title: Release Note for CMSIS +* +* ------------------------------------------------------------------- + + +NOTE - Open the index.html file to access CMSIS documentation + + +The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all +Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects +and reduces time-to-market for new embedded applications. + +CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf"). +Any user of the software package is bound to the terms and conditions of the end user license agreement. + + +You will find the following sub-directories: + +Documentation - Contains CMSIS documentation. + +DSP_Lib - MDK project files, Examples and source files etc.. to build the + CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors. + +Include - CMSIS Core Support and CMSIS DSP Include Files. + +Lib - CMSIS DSP Binaries +--- \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/index.htm b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/index.htm new file mode 100644 index 000000000..40e52b373 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/index.htm @@ -0,0 +1,115 @@ + + + +CMSIS Release Notes + + + + + + + + +

CMSIS Release Notes

+

Release Notes for CMSIS V2.00

+

November 2010

+ +

Information in this file, the accompany manuals, and software is
+ Copyright © ARM Ltd.
All rights reserved. +

+

+ +
+ +

Contents

+ + + + + + + \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/Release_Notes.html b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/Release_Notes.html new file mode 100644 index 000000000..2fea2a827 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/Release_Notes.html @@ -0,0 +1,968 @@ + + + + + + + + +Release Notes for STM32F2xx Standard Peripherals Library Drivers + + + + + +
+ +

 

+ +
+ + + + + +
+ + + + + + + +
+

Back to Release page

+
+

Release Notes for STM32F2xx Standard + Peripherals Library Drivers

+

Copyright + 2012 STMicroelectronics

+

+
+

 

+ + + + +
+

Contents

+
    +
  1. STM32F2xx Standard Peripherals Library Drivers + update History
    2. +
  2. License
    3. +
+

STM32F2xx + Standard Peripherals Library Drivers  update History

V1.1.2 / 05-March-2012

+

Main +Changes

+ +
  • All source files: license disclaimer text update and add link to the License file on ST Internet.
  • stm32f2xx_dcmi.c
    • DCMI_GetFlagStatus() function: fix test condition on RISR register, use if (dcmireg == 0x00) instead of if (dcmireg == 0x01)
  • stm32f2xx_pwr.c
    • PWR_PVDLevelConfig() +function: remove value of the voltage threshold corresponding to each +PVD detection level, user should refer to the electrical +characteristics of the STM32 device datasheet to have the correct +value

V1.1.1 / 28-December-2011

Main +Changes

+
  • All source files: update disclaimer to add reference to the new license agreement

V1.1.0 / 07-October-2011

Main +Changes

+
  • stm32f2xx_sdio.h/.c
    • SDIO_SetPowerState() function: fix POWER register configuration, only one access (for read or write) is allowed
  • stm32f2xx_usart.h/.c
    • Update procedure to check on overrun error interrupt pending bit, defines for the following flag are added:
      • USART_IT_ORE_RX: this flag is set if overrun error interrupt occurs and RXNEIE bit is set
      • USART_IT_ORE_ER: this flag is set if overrun error interrupt occurs and EIE bit is set
  • stm32f2xx_i2c.h
    • Add test on I2C3 in IS_I2C_ALL_PERIPH() macro
  • stm32f2xx_tim.c
    • TIM_UpdateRequestConfig(): correct function header's comment 
    • TIM_ICInit(): add assert macros to test if the passed TIM parameter has channel 2, 3 or 4
  • stm32f2xx_rtc.c
    • Remove useless code from RTC_GetDate() function

V1.0.0 / 18-April-2011

Main +Changes

+
  • First official release for STM32F2xx devices
  • All drivers
    • Update file and function's header comments to add more explanation and fix Doxygen tags formatting
  • stm32f2xx_syscfg.h/.c
    • Add 2 functions for Compensation Cell management:
      void SYSCFG_CompensationCellCmd(FunctionalState NewState);
      FlagStatus SYSCFG_GetCompensationCellStatus(void);
  • stm32f2xx_rtc.h
    • RTC_DateTypeDef structure: change RTC_Month and RTC_WeekDay members size to 8bit (instead of 32bit)

V1.0.0RC1 / 18-March-2011

Main +Changes

+
  • Official version (V1.0.0) Release Candidate 1
  • All drivers
    • Add more comments and information about how to use the driver and the functions API
    • Delete registers definition from stm32f2xx_ppp.c and use defines within stm32f2xx.h file
  • stm32f2xx_rcc.h/.c
    • RCC_PLLConfig() function updated to support only Silicon RevisionB and RevisionY (PLLR parameter removed)
  • stm32f2xx_spi.c
    • I2S_Init() function updated to support only the I2S clock scheme available in Silicon RevisionB and RevisionY
  • stm32f2xx_can.h/.c
    • Add 5 new functions
      • 3 +new functions controlling the counter errors: CAN_GetLastErrorCode(), +CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter()
      • 1 new function to select the CAN operating mode: CAN_OperatingModeRequest()
      • 1 new function to support CAN TT mode: CAN_TTComModeCmd()
        +
    • CAN_TransmitStatus() function updated to support all CAN transmit intermediate states
  • stm32f2xx_adc.h/.c
    • Name of the possible values of ADC_DMAAccessMode parameter modified as below:
      ADC_DMAAccessMode_HalfWord        -> ADC_DMAAccessMode_1 
      ADC_DMAAccessMode_TwoHalfWords -> ADC_DMAAccessMode_2
      ADC_DMAAccessMode_TwoBytes       -> ADC_DMAAccessMode_3
    • ADC_MultiModeDMARequestAfterLastTransferCmd(): the 1st parameter ADCx removed 
  • stm32f2xx_cryp.h/.c
    • CRYP_GetITStatus() function coding updated
    • Add 2 functions for CRYP Context swapping:
      ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
      void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
    • Name of the possible values of CRYP_DMAReq parameter modified as below:
      CRYP_DMAReq_Rx -> CRYP_DMAReq_DataIN
      CRYP_DMAReq_Tx -> CRYP_DMAReq_DataOUT 
  • Add three drivers to provide high level functions for AES, DES and TDES:
    • stm32f2xx_cryp_aes.c: provides high level functions to encrypt and decrypt an input message using AES in ECB/CBC/CTR modes
    • stm32f2xx_cryp_des.c: provides high level functions to encrypt and decrypt an input message using DES in ECB/CBC modes
    • stm32f2xx_cryp_tdes.c: provides high level functions to encrypt and decrypt an input message using TDES in ECB/CBC modes
    • These drivers uses the stm32f2xx_cryp.c/.h driver to access the STM32F2xx CRYP peripheral
  • stm32f2xx_hash.h/.c
    • HASH_GetITStatus() function coding updated
    • Add 2 functions for HASH Context swapping:
      void HASH_ContextSaving(HASH_Context* HASH_ContextSave);
      void HASH_ContextRestoring(HASH_Context* HASH_ContextRestore)
  • Add two drivers to provide high level functions for SHA1 and MD5:
    • stm32f2xx_hash_sha1.c: provides high level functions to compute the HASH SHA1 and HMAC SHA1 Digest of an input message
    • stm32f2xx_hash_md5.c: provides high level functions to compute the HASH MD5 and HMAC MD5 Digest of an input message
    • These drivers uses the stm32f2xx_hash.c/.h driver to access the STM32F2xx HASH peripheral
  • stm32f2xx_rng.h/.c
    • RNG_GetITStatus() function coding updated
    • Add new function:
      void RNG_ClearFlag(uint8_t RNG_FLAG);
  • stm32f2xx_gpio.h
    • Change the name of the parameter GPIO_Mode_AIN by GPIO_Mode_AN
  • stm32f2xx_rtc.h/.c
    • Rename the function RTC_DigitalCalibConfig() to RTC_CoarseCalibConfig() (no change on the parameter name)
    • Rename the function RTC_DigitalCalibCmd() to RTC_CoarseCalibCmd() (no change on the parameter name)
    • Add 3 functions:
      void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
      void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
      void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);       
  • stm32f2xx_flash.h/.c
    • Name of the possible values of OB_BOR parameter modified as below:
      OB_BOR_Level_3    -> OB_BOR_LEVEL3
      OB_BOR_Level_2    -> OB_BOR_LEVEL2
      OB_BOR_Level_1    -> OB_BOR_LEVEL1
      OB_BOR_Level_Off  -> OB_BOR_OFF
    • FLASH_OB_GetBOR() function updated to return the BOR level value as defined in OPTCR register
  • stm32f2xx_i2c.h/.c
    • Add 1 new function:
      • I2C_NACKPositionConfig(): +This function configures the same bit (POS) as I2C_PECPositionConfig() +but is intended to be used in I2C mode while I2C_PECPositionConfig() is +intended to used in SMBUS mode.
  • stm32f2xx_tim.h
    • Change the TIM_DMABurstLength_xBytes definitions to TIM_DMABurstLength_xTansfers
+

License

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License.
+
+
+

For + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32

+
+

+
+ +
+ +

 

+ +
+ + \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h new file mode 100644 index 000000000..aec4c361b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h @@ -0,0 +1,178 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be an enumerator of @ref IRQn_Type + enumeration (For the complete STM32 Devices IRQ Channels + list, please refer to stm32f2xx.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup MISC_Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup MISC_System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup MISC_Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup MISC_SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h new file mode 100644 index 000000000..e8a52b318 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h @@ -0,0 +1,649 @@ +/** + ****************************************************************************** + * @file stm32f2xx_adc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the ADC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_ADC_H +#define __STM32F2xx_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief ADC Init structure definition + */ +typedef struct +{ + uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. + This parameter can be a value of @ref ADC_resolution */ + FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion + is performed in Scan (multichannels) + or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion + is performed in Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and + enable the trigger of a regular group. + This parameter can be a value of + @ref ADC_external_trigger_edge_for_regular_channels_conversion */ + uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger + the start of conversion of a regular group. + This parameter can be a value of + @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment + is left or right. This parameter can be + a value of @ref ADC_data_align */ + uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions + that will be done using the sequencer for + regular channel group. + This parameter must range from 1 to 16. */ +}ADC_InitTypeDef; + +/** + * @brief ADC Common Init structure definition + */ +typedef struct +{ + uint32_t ADC_Mode; /*!< Configures the ADC to operate in + independent or multi mode. + This parameter can be a value of @ref ADC_Common_mode */ + uint32_t ADC_Prescaler; /*!< Select the frequency of the clock + to the ADC. The clock is common for all the ADCs. + This parameter can be a value of @ref ADC_Prescaler */ + uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access + mode for multi ADC mode. + This parameter can be a value of + @ref ADC_Direct_memory_access_mode_for_multi_mode */ + uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. + This parameter can be a value of + @ref ADC_delay_between_2_sampling_phases */ + +}ADC_CommonInitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants + * @{ + */ +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) + +/** @defgroup ADC_Common_mode + * @{ + */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) +#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) +#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) +#define ADC_DualMode_RegSimult ((uint32_t)0x00000006) +#define ADC_DualMode_Interl ((uint32_t)0x00000007) +#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) +#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) +#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) +#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) +#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) +#define ADC_TripleMode_Interl ((uint32_t)0x00000017) +#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ + ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_DualMode_InjecSimult) || \ + ((MODE) == ADC_DualMode_RegSimult) || \ + ((MODE) == ADC_DualMode_Interl) || \ + ((MODE) == ADC_DualMode_AlterTrig) || \ + ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ + ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_TripleMode_InjecSimult) || \ + ((MODE) == ADC_TripleMode_RegSimult) || \ + ((MODE) == ADC_TripleMode_Interl) || \ + ((MODE) == ADC_TripleMode_AlterTrig)) +/** + * @} + */ + + +/** @defgroup ADC_Prescaler + * @{ + */ +#define ADC_Prescaler_Div2 ((uint32_t)0x00000000) +#define ADC_Prescaler_Div4 ((uint32_t)0x00010000) +#define ADC_Prescaler_Div6 ((uint32_t)0x00020000) +#define ADC_Prescaler_Div8 ((uint32_t)0x00030000) +#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ + ((PRESCALER) == ADC_Prescaler_Div4) || \ + ((PRESCALER) == ADC_Prescaler_Div6) || \ + ((PRESCALER) == ADC_Prescaler_Div8)) +/** + * @} + */ + + +/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode + * @{ + */ +#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ +#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ +#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ +#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ +#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ + ((MODE) == ADC_DMAAccessMode_1) || \ + ((MODE) == ADC_DMAAccessMode_2) || \ + ((MODE) == ADC_DMAAccessMode_3)) + +/** + * @} + */ + + +/** @defgroup ADC_delay_between_2_sampling_phases + * @{ + */ +#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) +#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) +#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) +#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) +#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) +#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) +#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) +#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) +#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) +#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) +#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) +#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) +#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) +#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) +#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) +#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) +#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ + ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) + +/** + * @} + */ + + +/** @defgroup ADC_resolution + * @{ + */ +#define ADC_Resolution_12b ((uint32_t)0x00000000) +#define ADC_Resolution_10b ((uint32_t)0x01000000) +#define ADC_Resolution_8b ((uint32_t)0x02000000) +#define ADC_Resolution_6b ((uint32_t)0x03000000) +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ + ((RESOLUTION) == ADC_Resolution_10b) || \ + ((RESOLUTION) == ADC_Resolution_8b) || \ + ((RESOLUTION) == ADC_Resolution_6b)) + +/** + * @} + */ + + +/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion + * @{ + */ +#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) +#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) +#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) +#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) +#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) +/** + * @} + */ + + +/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion + * @{ + */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) +#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) +#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) +#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) +/** + * @} + */ + + +/** @defgroup ADC_data_align + * @{ + */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + + +/** @defgroup ADC_channels + * @{ + */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) +#define ADC_Channel_18 ((uint8_t)0x12) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) +#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ + ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || \ + ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || \ + ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || \ + ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || \ + ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || \ + ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || \ + ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || \ + ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || \ + ((CHANNEL) == ADC_Channel_17) || \ + ((CHANNEL) == ADC_Channel_18)) +/** + * @} + */ + + +/** @defgroup ADC_sampling_times + * @{ + */ +#define ADC_SampleTime_3Cycles ((uint8_t)0x00) +#define ADC_SampleTime_15Cycles ((uint8_t)0x01) +#define ADC_SampleTime_28Cycles ((uint8_t)0x02) +#define ADC_SampleTime_56Cycles ((uint8_t)0x03) +#define ADC_SampleTime_84Cycles ((uint8_t)0x04) +#define ADC_SampleTime_112Cycles ((uint8_t)0x05) +#define ADC_SampleTime_144Cycles ((uint8_t)0x06) +#define ADC_SampleTime_480Cycles ((uint8_t)0x07) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ + ((TIME) == ADC_SampleTime_15Cycles) || \ + ((TIME) == ADC_SampleTime_28Cycles) || \ + ((TIME) == ADC_SampleTime_56Cycles) || \ + ((TIME) == ADC_SampleTime_84Cycles) || \ + ((TIME) == ADC_SampleTime_112Cycles) || \ + ((TIME) == ADC_SampleTime_144Cycles) || \ + ((TIME) == ADC_SampleTime_480Cycles)) +/** + * @} + */ + + +/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion + * @{ + */ +#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) +#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) +#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) +#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ + ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) + +/** + * @} + */ + + +/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion + * @{ + */ +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) +#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) +#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) +#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) +#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) +/** + * @} + */ + + +/** @defgroup ADC_injected_channel_selection + * @{ + */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) +/** + * @} + */ + + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** + * @} + */ + + +/** @defgroup ADC_interrupts_definition + * @{ + */ +#define ADC_IT_EOC ((uint16_t)0x0205) +#define ADC_IT_AWD ((uint16_t)0x0106) +#define ADC_IT_JEOC ((uint16_t)0x0407) +#define ADC_IT_OVR ((uint16_t)0x201A) +#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) +/** + * @} + */ + + +/** @defgroup ADC_flags_definition + * @{ + */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) +#define ADC_FLAG_OVR ((uint8_t)0x20) + +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ + ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || \ + ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT) || \ + ((FLAG)== ADC_FLAG_OVR)) +/** + * @} + */ + + +/** @defgroup ADC_thresholds + * @{ + */ +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) +/** + * @} + */ + + +/** @defgroup ADC_injected_offset + * @{ + */ +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) +/** + * @} + */ + + +/** @defgroup ADC_injected_length + * @{ + */ +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) +/** + * @} + */ + + +/** @defgroup ADC_injected_rank + * @{ + */ +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) +/** + * @} + */ + + +/** @defgroup ADC_regular_length + * @{ + */ +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + + +/** @defgroup ADC_regular_rank + * @{ + */ +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) +/** + * @} + */ + + +/** @defgroup ADC_regular_discontinuous_mode_number + * @{ + */ +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the ADC configuration to the default reset state *****/ +void ADC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); +void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +/* Analog Watchdog configuration functions ************************************/ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); + +/* Temperature Sensor, Vrefint and VBAT management functions ******************/ +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +void ADC_VBATCmd(FunctionalState NewState); + +/* Regular Channels Configuration functions ***********************************/ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetMultiModeConversionValue(void); + +/* Regular Channels DMA Configuration functions *******************************/ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); + +/* Injected channels Configuration functions **********************************/ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); +void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); + +/* Interrupts and flags management functions **********************************/ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_can.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_can.h new file mode 100644 index 000000000..42cfdedf8 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_can.h @@ -0,0 +1,644 @@ +/** + ****************************************************************************** + * @file stm32f2xx_can.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the CAN firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CAN_H +#define __STM32F2xx_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ + ((PERIPH) == CAN2)) + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_InitTypeDef; + +/** + * @brief CAN filter init structure definition + */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Constants + * @{ + */ + +/** @defgroup CAN_InitStatus + * @{ + */ + +#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ + + +/* Legacy defines */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +/** + * @} + */ + +/** @defgroup CAN_operating_mode + * @{ + */ + +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ + ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || \ + ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + + + /** + * @defgroup CAN_operating_mode + * @{ + */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ + + +#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ + ((MODE) == CAN_OperatingMode_Normal)|| \ + ((MODE) == CAN_OperatingMode_Sleep)) +/** + * @} + */ + +/** + * @defgroup CAN_operating_mode_status + * @{ + */ + +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ +#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ +#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler + * @{ + */ +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) +/** + * @} + */ + +/** @defgroup CAN_filter_number + * @{ + */ +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +/** + * @} + */ + +/** @defgroup CAN_filter_mode + * @{ + */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale + * @{ + */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO + * @{ + */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) + +/* Legacy defines */ +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +/** + * @} + */ + +/** @defgroup CAN_Start_bank_filter_for_slave_CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) +/** + * @} + */ + +/** @defgroup CAN_Tx + * @{ + */ +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) +/** + * @} + */ + +/** @defgroup CAN_identifier_type + * @{ + */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ + ((IDTYPE) == CAN_Id_Extended)) + +/* Legacy defines */ +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request + * @{ + */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) + +/* Legacy defines */ +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +/** + * @} + */ + +/** @defgroup CAN_transmit_constants + * @{ + */ +#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide + an empty mailbox */ +/* Legacy defines */ +#define CANTXFAILED CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +/** + * @} + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/* Legacy defines */ +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +/** + * @} + */ + +/** @defgroup CAN_wake_up_constants + * @{ + */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/* Legacy defines */ +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok +/** + * @} + */ + +/** + * @defgroup CAN_Error_Code_constants + * @{ + */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ +/** + * @} + */ + +/** @defgroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ + ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ + ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ + ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_SLAK )) + +#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ + ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + + +/** @defgroup CAN_interrupts + * @{ + */ +#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + + +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the CAN configuration to the default reset state *****/ +void CAN_DeInit(CAN_TypeDef* CANx); + +/* Initialization and Configuration functions *********************************/ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); + +/* CAN Frames Transmission functions ******************************************/ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); + +/* CAN Frames Reception functions *********************************************/ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); + +/* CAN Bus Error management functions *****************************************/ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_CAN_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_crc.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_crc.h new file mode 100644 index 000000000..725c581f5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_crc.h @@ -0,0 +1,83 @@ +/** + ****************************************************************************** + * @file stm32f2xx_crc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CRC_H +#define __STM32F2xx_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_CRC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_cryp.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_cryp.h new file mode 100644 index 000000000..893e92586 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_cryp.h @@ -0,0 +1,344 @@ +/** + ****************************************************************************** + * @file stm32f2xx_cryp.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the Cryptographic + * processor(CRYP) firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CRYP_H +#define __STM32F2xx_CRYP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRYP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief CRYP Init structure definition + */ +typedef struct +{ + uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a + value of @ref CRYP_Algorithm_Direction */ + uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, + AES-CBC, AES-CTR, AES-Key. This parameter can be + a value of @ref CRYP_Algorithm_Mode */ + uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string. + This parameter can be a value of @ref CRYP_Data_Type */ + uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit + key length. This parameter can be a value of + @ref CRYP_Key_Size_for_AES_only */ +}CRYP_InitTypeDef; + +/** + * @brief CRYP Key(s) structure definition + */ +typedef struct +{ + uint32_t CRYP_Key0Left; /*!< Key 0 Left */ + uint32_t CRYP_Key0Right; /*!< Key 0 Right */ + uint32_t CRYP_Key1Left; /*!< Key 1 left */ + uint32_t CRYP_Key1Right; /*!< Key 1 Right */ + uint32_t CRYP_Key2Left; /*!< Key 2 left */ + uint32_t CRYP_Key2Right; /*!< Key 2 Right */ + uint32_t CRYP_Key3Left; /*!< Key 3 left */ + uint32_t CRYP_Key3Right; /*!< Key 3 Right */ +}CRYP_KeyInitTypeDef; +/** + * @brief CRYP Initialization Vectors (IV) structure definition + */ +typedef struct +{ + uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */ + uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */ + uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */ + uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */ +}CRYP_IVInitTypeDef; + +/** + * @brief CRYP context swapping structure definition + */ +typedef struct +{ + /*!< Configuration */ + uint32_t CR_bits9to2; + /*!< KEY */ + uint32_t CRYP_IV0LR; + uint32_t CRYP_IV0RR; + uint32_t CRYP_IV1LR; + uint32_t CRYP_IV1RR; + /*!< IV */ + uint32_t CRYP_K0LR; + uint32_t CRYP_K0RR; + uint32_t CRYP_K1LR; + uint32_t CRYP_K1RR; + uint32_t CRYP_K2LR; + uint32_t CRYP_K2RR; + uint32_t CRYP_K3LR; + uint32_t CRYP_K3RR; +}CRYP_Context; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRYP_Exported_Constants + * @{ + */ + +/** @defgroup CRYP_Algorithm_Direction + * @{ + */ +#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000) +#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004) +#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \ + ((ALGODIR) == CRYP_AlgoDir_Decrypt)) + +/** + * @} + */ + +/** @defgroup CRYP_Algorithm_Mode + * @{ + */ + +/*!< TDES Modes */ +#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000) +#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008) + +/*!< DES Modes */ +#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010) +#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018) + +/*!< AES Modes */ +#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020) +#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028) +#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030) +#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038) + +#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ + ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ + ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \ + ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ + ((ALGOMODE) == CRYP_AlgoMode_AES_Key)) +/** + * @} + */ + +/** @defgroup CRYP_Data_Type + * @{ + */ +#define CRYP_DataType_32b ((uint16_t)0x0000) +#define CRYP_DataType_16b ((uint16_t)0x0040) +#define CRYP_DataType_8b ((uint16_t)0x0080) +#define CRYP_DataType_1b ((uint16_t)0x00C0) +#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \ + ((DATATYPE) == CRYP_DataType_16b)|| \ + ((DATATYPE) == CRYP_DataType_8b)|| \ + ((DATATYPE) == CRYP_DataType_1b)) +/** + * @} + */ + +/** @defgroup CRYP_Key_Size_for_AES_only + * @{ + */ +#define CRYP_KeySize_128b ((uint16_t)0x0000) +#define CRYP_KeySize_192b ((uint16_t)0x0100) +#define CRYP_KeySize_256b ((uint16_t)0x0200) +#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \ + ((KEYSIZE) == CRYP_KeySize_192b)|| \ + ((KEYSIZE) == CRYP_KeySize_256b)) +/** + * @} + */ + +/** @defgroup CRYP_flags_definition + * @{ + */ +#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently + processing a block of data + or a key preparation (for + AES decryption). */ +#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */ +#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */ +#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */ +#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw + interrupt status */ +#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */ +#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw + interrupt status */ + +#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \ + ((FLAG) == CRYP_FLAG_IFNF) || \ + ((FLAG) == CRYP_FLAG_OFNE) || \ + ((FLAG) == CRYP_FLAG_OFFU) || \ + ((FLAG) == CRYP_FLAG_BUSY) || \ + ((FLAG) == CRYP_FLAG_OUTRIS)|| \ + ((FLAG) == CRYP_FLAG_INRIS)) +/** + * @} + */ + +/** @defgroup CRYP_interrupts_definition + * @{ + */ +#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */ +#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */ +#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) +#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI)) + +/** + * @} + */ + +/** @defgroup CRYP_Encryption_Decryption_modes_definition + * @{ + */ +#define MODE_ENCRYPT ((uint8_t)0x01) +#define MODE_DECRYPT ((uint8_t)0x00) + +/** + * @} + */ + +/** @defgroup CRYP_DMA_transfer_requests + * @{ + */ +#define CRYP_DMAReq_DataIN ((uint8_t)0x01) +#define CRYP_DMAReq_DataOUT ((uint8_t)0x02) +#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the CRYP configuration to the default reset state ****/ +void CRYP_DeInit(void); + +/* CRYP Initialization and Configuration functions ****************************/ +void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct); +void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct); +void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); +void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); +void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); +void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); +void CRYP_Cmd(FunctionalState NewState); + +/* CRYP Data processing functions *********************************************/ +void CRYP_DataIn(uint32_t Data); +uint32_t CRYP_DataOut(void); +void CRYP_FIFOFlush(void); + +/* CRYP Context swapping functions ********************************************/ +ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, + CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); +void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); + +/* CRYP's DMA interface function **********************************************/ +void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); +ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); +FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); + +/* High Level AES functions **************************************************/ +ErrorStatus CRYP_AES_ECB(uint8_t Mode, + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_AES_CBC(uint8_t Mode, + uint8_t InitVectors[16], + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_AES_CTR(uint8_t Mode, + uint8_t InitVectors[16], + uint8_t *Key, uint16_t Keysize, + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +/* High Level TDES functions **************************************************/ +ErrorStatus CRYP_TDES_ECB(uint8_t Mode, + uint8_t Key[24], + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_TDES_CBC(uint8_t Mode, + uint8_t Key[24], + uint8_t InitVectors[8], + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +/* High Level DES functions **************************************************/ +ErrorStatus CRYP_DES_ECB(uint8_t Mode, + uint8_t Key[8], + uint8_t *Input, uint32_t Ilength, + uint8_t *Output); + +ErrorStatus CRYP_DES_CBC(uint8_t Mode, + uint8_t Key[8], + uint8_t InitVectors[8], + uint8_t *Input,uint32_t Ilength, + uint8_t *Output); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_CRYP_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dac.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dac.h new file mode 100644 index 000000000..f5e1c3355 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dac.h @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file stm32f2xx_dac.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_DAC_H +#define __STM32F2xx_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ + +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** @defgroup DAC_interrupts_definition + * @{ + */ +#define DAC_IT_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the DAC configuration to the default reset state *****/ +void DAC_DeInit(void); + +/* DAC channels configuration: trigger, output buffer, data format functions */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +/* DMA management functions ***************************************************/ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_DAC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h new file mode 100644 index 000000000..2a5baa58a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h @@ -0,0 +1,109 @@ +/** + ****************************************************************************** + * @file stm32f2xx_dbgmcu.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the DBGMCU firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_DBGMCU_H +#define __STM32F2xx_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) + +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) +#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040) +#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080) +#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100) +#define DBGMCU_RTC_STOP ((uint32_t)0x00000400) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) +#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000) +#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00)) + +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) +#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000) +#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_DBGMCU_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dcmi.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dcmi.h new file mode 100644 index 000000000..eb3212674 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dcmi.h @@ -0,0 +1,312 @@ +/** + ****************************************************************************** + * @file stm32f2xx_dcmi.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the DCMI firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_DCMI_H +#define __STM32F2xx_DCMI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DCMI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief DCMI Init structure definition + */ +typedef struct +{ + uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot. + This parameter can be a value of @ref DCMI_Capture_Mode */ + + uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. + This parameter can be a value of @ref DCMI_Synchronization_Mode */ + + uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. + This parameter can be a value of @ref DCMI_PIXCK_Polarity */ + + uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. + This parameter can be a value of @ref DCMI_VSYNC_Polarity */ + + uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. + This parameter can be a value of @ref DCMI_HSYNC_Polarity */ + + uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. + This parameter can be a value of @ref DCMI_Capture_Rate */ + + uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. + This parameter can be a value of @ref DCMI_Extended_Data_Mode */ +} DCMI_InitTypeDef; + +/** + * @brief DCMI CROP Init structure definition + */ +typedef struct +{ + uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture + will start. This parameter can be a value between 0x00 and 0x1FFF */ + + uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture. + This parameter can be a value between 0x00 and 0x3FFF */ + + uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point. + This parameter can be a value between 0x00 and 0x3FFF */ + + uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting + point on the same line. + This parameter can be a value between 0x00 and 0x3FFF */ +} DCMI_CROPInitTypeDef; + +/** + * @brief DCMI Embedded Synchronisation CODE Init structure definition + */ +typedef struct +{ + uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ + uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */ + uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */ + uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ +} DCMI_CodesInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DCMI_Exported_Constants + * @{ + */ + +/** @defgroup DCMI_Capture_Mode + * @{ + */ +#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously + into the destination memory through the DMA */ +#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of + frame and then transfers a single frame through the DMA */ +#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \ + ((MODE) == DCMI_CaptureMode_SnapShot)) +/** + * @} + */ + + +/** @defgroup DCMI_Synchronization_Mode + * @{ + */ +#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop) + is synchronized with the HSYNC/VSYNC signals */ +#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with + synchronization codes embedded in the data flow */ +#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \ + ((MODE) == DCMI_SynchroMode_Embedded)) +/** + * @} + */ + + +/** @defgroup DCMI_PIXCK_Polarity + * @{ + */ +#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */ +#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */ +#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \ + ((POLARITY) == DCMI_PCKPolarity_Rising)) +/** + * @} + */ + + +/** @defgroup DCMI_VSYNC_Polarity + * @{ + */ +#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */ +#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */ +#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \ + ((POLARITY) == DCMI_VSPolarity_High)) +/** + * @} + */ + + +/** @defgroup DCMI_HSYNC_Polarity + * @{ + */ +#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */ +#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */ +#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \ + ((POLARITY) == DCMI_HSPolarity_High)) +/** + * @} + */ + + +/** @defgroup DCMI_Capture_Rate + * @{ + */ +#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */ +#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */ +#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */ +#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \ + ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\ + ((RATE) == DCMI_CaptureRate_1of4_Frame)) +/** + * @} + */ + + +/** @defgroup DCMI_Extended_Data_Mode + * @{ + */ +#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */ +#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */ +#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */ +#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */ +#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \ + ((DATA) == DCMI_ExtendedDataMode_10b) ||\ + ((DATA) == DCMI_ExtendedDataMode_12b) ||\ + ((DATA) == DCMI_ExtendedDataMode_14b)) +/** + * @} + */ + + +/** @defgroup DCMI_interrupt_sources + * @{ + */ +#define DCMI_IT_FRAME ((uint16_t)0x0001) +#define DCMI_IT_OVF ((uint16_t)0x0002) +#define DCMI_IT_ERR ((uint16_t)0x0004) +#define DCMI_IT_VSYNC ((uint16_t)0x0008) +#define DCMI_IT_LINE ((uint16_t)0x0010) +#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000)) +#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \ + ((IT) == DCMI_IT_OVF) || \ + ((IT) == DCMI_IT_ERR) || \ + ((IT) == DCMI_IT_VSYNC) || \ + ((IT) == DCMI_IT_LINE)) +/** + * @} + */ + + +/** @defgroup DCMI_Flags + * @{ + */ +/** + * @brief DCMI SR register + */ +#define DCMI_FLAG_HSYNC ((uint16_t)0x2001) +#define DCMI_FLAG_VSYNC ((uint16_t)0x2002) +#define DCMI_FLAG_FNE ((uint16_t)0x2004) +/** + * @brief DCMI RISR register + */ +#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001) +#define DCMI_FLAG_OVFRI ((uint16_t)0x0002) +#define DCMI_FLAG_ERRRI ((uint16_t)0x0004) +#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008) +#define DCMI_FLAG_LINERI ((uint16_t)0x0010) +/** + * @brief DCMI MISR register + */ +#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001) +#define DCMI_FLAG_OVFMI ((uint16_t)0x1002) +#define DCMI_FLAG_ERRMI ((uint16_t)0x1004) +#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008) +#define DCMI_FLAG_LINEMI ((uint16_t)0x1010) +#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \ + ((FLAG) == DCMI_FLAG_VSYNC) || \ + ((FLAG) == DCMI_FLAG_FNE) || \ + ((FLAG) == DCMI_FLAG_FRAMERI) || \ + ((FLAG) == DCMI_FLAG_OVFRI) || \ + ((FLAG) == DCMI_FLAG_ERRRI) || \ + ((FLAG) == DCMI_FLAG_VSYNCRI) || \ + ((FLAG) == DCMI_FLAG_LINERI) || \ + ((FLAG) == DCMI_FLAG_FRAMEMI) || \ + ((FLAG) == DCMI_FLAG_OVFMI) || \ + ((FLAG) == DCMI_FLAG_ERRMI) || \ + ((FLAG) == DCMI_FLAG_VSYNCMI) || \ + ((FLAG) == DCMI_FLAG_LINEMI)) + +#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the DCMI configuration to the default reset state ****/ +void DCMI_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct); +void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct); +void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct); +void DCMI_CROPCmd(FunctionalState NewState); +void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct); +void DCMI_JPEGCmd(FunctionalState NewState); + +/* Image capture functions ****************************************************/ +void DCMI_Cmd(FunctionalState NewState); +void DCMI_CaptureCmd(FunctionalState NewState); +uint32_t DCMI_ReadData(void); + +/* Interrupts and flags management functions **********************************/ +void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState); +FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG); +void DCMI_ClearFlag(uint16_t DCMI_FLAG); +ITStatus DCMI_GetITStatus(uint16_t DCMI_IT); +void DCMI_ClearITPendingBit(uint16_t DCMI_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_DCMI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h new file mode 100644 index 000000000..94c7dff40 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h @@ -0,0 +1,609 @@ +/** + ****************************************************************************** + * @file stm32f2xx_dma.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_DMA_H +#define __STM32F2xx_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. + This parameter can be a value of @ref DMA_channel */ + + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ + + uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. + This memory is the default memory used when double buffer mode is + not enabled. */ + + uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_circular_normal_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. + This parameter can be a value of @ref DMA_fifo_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected Stream */ + + uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_fifo_threshold_level */ + + uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptable + transaction. This parameter can be a value of @ref DMA_memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptable + transaction. This parameter can be a value of @ref DMA_peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ + ((PERIPH) == DMA1_Stream1) || \ + ((PERIPH) == DMA1_Stream2) || \ + ((PERIPH) == DMA1_Stream3) || \ + ((PERIPH) == DMA1_Stream4) || \ + ((PERIPH) == DMA1_Stream5) || \ + ((PERIPH) == DMA1_Stream6) || \ + ((PERIPH) == DMA1_Stream7) || \ + ((PERIPH) == DMA2_Stream0) || \ + ((PERIPH) == DMA2_Stream1) || \ + ((PERIPH) == DMA2_Stream2) || \ + ((PERIPH) == DMA2_Stream3) || \ + ((PERIPH) == DMA2_Stream4) || \ + ((PERIPH) == DMA2_Stream5) || \ + ((PERIPH) == DMA2_Stream6) || \ + ((PERIPH) == DMA2_Stream7)) + +#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \ + ((CONTROLLER) == DMA2)) + +/** @defgroup DMA_channel + * @{ + */ +#define DMA_Channel_0 ((uint32_t)0x00000000) +#define DMA_Channel_1 ((uint32_t)0x02000000) +#define DMA_Channel_2 ((uint32_t)0x04000000) +#define DMA_Channel_3 ((uint32_t)0x06000000) +#define DMA_Channel_4 ((uint32_t)0x08000000) +#define DMA_Channel_5 ((uint32_t)0x0A000000) +#define DMA_Channel_6 ((uint32_t)0x0C000000) +#define DMA_Channel_7 ((uint32_t)0x0E000000) + +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ + ((CHANNEL) == DMA_Channel_1) || \ + ((CHANNEL) == DMA_Channel_2) || \ + ((CHANNEL) == DMA_Channel_3) || \ + ((CHANNEL) == DMA_Channel_4) || \ + ((CHANNEL) == DMA_Channel_5) || \ + ((CHANNEL) == DMA_Channel_6) || \ + ((CHANNEL) == DMA_Channel_7)) +/** + * @} + */ + + +/** @defgroup DMA_data_transfer_direction + * @{ + */ +#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) +#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) +#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ + ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ + ((DIRECTION) == DMA_DIR_MemoryToMemory)) +/** + * @} + */ + + +/** @defgroup DMA_data_buffer_size + * @{ + */ +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** + * @} + */ + + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000400) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_data_size + * @{ + */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + + +/** @defgroup DMA_memory_data_size + * @{ + */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word )) +/** + * @} + */ + + +/** @defgroup DMA_circular_normal_mode + * @{ + */ +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define DMA_Mode_Circular ((uint32_t)0x00000100) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \ + ((MODE) == DMA_Mode_Circular)) +/** + * @} + */ + + +/** @defgroup DMA_priority_level + * @{ + */ +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define DMA_Priority_Medium ((uint32_t)0x00010000) +#define DMA_Priority_High ((uint32_t)0x00020000) +#define DMA_Priority_VeryHigh ((uint32_t)0x00030000) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_VeryHigh)) +/** + * @} + */ + + +/** @defgroup DMA_fifo_direct_mode + * @{ + */ +#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) +#define DMA_FIFOMode_Enable ((uint32_t)0x00000004) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ + ((STATE) == DMA_FIFOMode_Enable)) +/** + * @} + */ + + +/** @defgroup DMA_fifo_threshold_level + * @{ + */ +#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) +#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) +#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) +#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ + ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ + ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ + ((THRESHOLD) == DMA_FIFOThreshold_Full)) +/** + * @} + */ + + +/** @defgroup DMA_memory_burst + * @{ + */ +#define DMA_MemoryBurst_Single ((uint32_t)0x00000000) +#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) +#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) +#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ + ((BURST) == DMA_MemoryBurst_INC4) || \ + ((BURST) == DMA_MemoryBurst_INC8) || \ + ((BURST) == DMA_MemoryBurst_INC16)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_burst + * @{ + */ +#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) +#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) +#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) +#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ + ((BURST) == DMA_PeripheralBurst_INC4) || \ + ((BURST) == DMA_PeripheralBurst_INC8) || \ + ((BURST) == DMA_PeripheralBurst_INC16)) +/** + * @} + */ + + +/** @defgroup DMA_fifo_status_level + * @{ + */ +#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) +#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) +#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) +#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) +#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) +#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) + +#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ + ((STATUS) == DMA_FIFOStatus_HalfFull) || \ + ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ + ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ + ((STATUS) == DMA_FIFOStatus_Full) || \ + ((STATUS) == DMA_FIFOStatus_Empty)) +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) +#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) +#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) +#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) +#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) +#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) +#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) +#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) +#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) +#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) +#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) +#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) +#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) +#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) +#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) +#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) +#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) +#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) +#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) +#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) +#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) +#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) +#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) +#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) +#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) +#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) +#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) +#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) +#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) +#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) +#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) +#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) +#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) +#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) +#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) +#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) +#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) +#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) +#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) +#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) + +#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ + (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ + ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ + ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ + ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ + ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ + ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ + ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ + ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ + ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ + ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ + ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ + ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ + ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ + ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ + ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ + ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ + ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ + ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ + ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ + ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions + * @{ + */ +#define DMA_IT_TC ((uint32_t)0x00000010) +#define DMA_IT_HT ((uint32_t)0x00000008) +#define DMA_IT_TE ((uint32_t)0x00000004) +#define DMA_IT_DME ((uint32_t)0x00000002) +#define DMA_IT_FE ((uint32_t)0x00000080) + +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + + +/** @defgroup DMA_interrupts_definitions + * @{ + */ +#define DMA_IT_FEIF0 ((uint32_t)0x90000001) +#define DMA_IT_DMEIF0 ((uint32_t)0x10001004) +#define DMA_IT_TEIF0 ((uint32_t)0x10002008) +#define DMA_IT_HTIF0 ((uint32_t)0x10004010) +#define DMA_IT_TCIF0 ((uint32_t)0x10008020) +#define DMA_IT_FEIF1 ((uint32_t)0x90000040) +#define DMA_IT_DMEIF1 ((uint32_t)0x10001100) +#define DMA_IT_TEIF1 ((uint32_t)0x10002200) +#define DMA_IT_HTIF1 ((uint32_t)0x10004400) +#define DMA_IT_TCIF1 ((uint32_t)0x10008800) +#define DMA_IT_FEIF2 ((uint32_t)0x90010000) +#define DMA_IT_DMEIF2 ((uint32_t)0x10041000) +#define DMA_IT_TEIF2 ((uint32_t)0x10082000) +#define DMA_IT_HTIF2 ((uint32_t)0x10104000) +#define DMA_IT_TCIF2 ((uint32_t)0x10208000) +#define DMA_IT_FEIF3 ((uint32_t)0x90400000) +#define DMA_IT_DMEIF3 ((uint32_t)0x11001000) +#define DMA_IT_TEIF3 ((uint32_t)0x12002000) +#define DMA_IT_HTIF3 ((uint32_t)0x14004000) +#define DMA_IT_TCIF3 ((uint32_t)0x18008000) +#define DMA_IT_FEIF4 ((uint32_t)0xA0000001) +#define DMA_IT_DMEIF4 ((uint32_t)0x20001004) +#define DMA_IT_TEIF4 ((uint32_t)0x20002008) +#define DMA_IT_HTIF4 ((uint32_t)0x20004010) +#define DMA_IT_TCIF4 ((uint32_t)0x20008020) +#define DMA_IT_FEIF5 ((uint32_t)0xA0000040) +#define DMA_IT_DMEIF5 ((uint32_t)0x20001100) +#define DMA_IT_TEIF5 ((uint32_t)0x20002200) +#define DMA_IT_HTIF5 ((uint32_t)0x20004400) +#define DMA_IT_TCIF5 ((uint32_t)0x20008800) +#define DMA_IT_FEIF6 ((uint32_t)0xA0010000) +#define DMA_IT_DMEIF6 ((uint32_t)0x20041000) +#define DMA_IT_TEIF6 ((uint32_t)0x20082000) +#define DMA_IT_HTIF6 ((uint32_t)0x20104000) +#define DMA_IT_TCIF6 ((uint32_t)0x20208000) +#define DMA_IT_FEIF7 ((uint32_t)0xA0400000) +#define DMA_IT_DMEIF7 ((uint32_t)0x21001000) +#define DMA_IT_TEIF7 ((uint32_t)0x22002000) +#define DMA_IT_HTIF7 ((uint32_t)0x24004000) +#define DMA_IT_TCIF7 ((uint32_t)0x28008000) + +#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ + (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ + (((IT) & 0x40820082) == 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \ + ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ + ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ + ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ + ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ + ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ + ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ + ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ + ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ + ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ + ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ + ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ + ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ + ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ + ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ + ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ + ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ + ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ + ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ + ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) +/** + * @} + */ + + +/** @defgroup DMA_peripheral_increment_offset + * @{ + */ +#define DMA_PINCOS_Psize ((uint32_t)0x00000000) +#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) + +#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ + ((SIZE) == DMA_PINCOS_WordAligned)) +/** + * @} + */ + + +/** @defgroup DMA_flow_controller_definitions + * @{ + */ +#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) +#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) + +#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ + ((CTRL) == DMA_FlowCtrl_Peripheral)) +/** + * @} + */ + + +/** @defgroup DMA_memory_targets_definitions + * @{ + */ +#define DMA_Memory_0 ((uint32_t)0x00000000) +#define DMA_Memory_1 ((uint32_t)0x00080000) + +#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the DMA configuration to the default reset state *****/ +void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx); + +/* Initialization and Configuration functions *********************************/ +void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); + +/* Optional Configuration functions *******************************************/ +void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos); +void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl); + +/* Data Counter functions *****************************************************/ +void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); +uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); + +/* Double Buffer mode functions ***********************************************/ +void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, + uint32_t DMA_CurrentMemory); +void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); +void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, + uint32_t DMA_MemoryTarget); +uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); + +/* Interrupts and flags management functions **********************************/ +FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); +uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); +FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); +void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); +void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); +ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); +void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_DMA_H */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h new file mode 100644 index 000000000..186e87f08 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h @@ -0,0 +1,183 @@ +/** + ****************************************************************************** + * @file stm32f2xx_exti.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the EXTI firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_EXTI_H +#define __STM32F2xx_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination value of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTITrigger_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ + +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) + +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ + ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ + ((LINE) == EXTI_Line22)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the EXTI configuration to the default reset state *****/ +void EXTI_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); + +/* Interrupts and flags management functions **********************************/ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_EXTI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h new file mode 100644 index 000000000..8ea12def4 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h @@ -0,0 +1,340 @@ +/** + ****************************************************************************** + * @file stm32f2xx_flash.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_FLASH_H +#define __STM32F2xx_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief FLASH Status + */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PGS, + FLASH_ERROR_PGP, + FLASH_ERROR_PGA, + FLASH_ERROR_WRP, + FLASH_ERROR_PROGRAM, + FLASH_ERROR_OPERATION, + FLASH_COMPLETE +}FLASH_Status; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ +#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ +#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ +#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ +#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ +#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ +#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2) || \ + ((LATENCY) == FLASH_Latency_3) || \ + ((LATENCY) == FLASH_Latency_4) || \ + ((LATENCY) == FLASH_Latency_5) || \ + ((LATENCY) == FLASH_Latency_6) || \ + ((LATENCY) == FLASH_Latency_7)) +/** + * @} + */ + +/** @defgroup FLASH_Voltage_Range + * @{ + */ +#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ +#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ + (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ +#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ +#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ +#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ +#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ +#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ +#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ +#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ +#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ +#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ +#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ +#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ +#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ +#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ + +#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_Read_Protection + * @{ + */ +#define OB_RDP_Level_0 ((uint8_t)0xAA) +#define OB_RDP_Level_1 ((uint8_t)0x55) +/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 + it's no more possible to go back to level 1 or 0 */ +#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ + ((LEVEL) == OB_RDP_Level_1))/*||\ + ((LEVEL) == OB_RDP_Level_2))*/ +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_IWatchdog + * @{ + */ +#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_nRST_STOP + * @{ + */ +#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) +/** + * @} + */ + + +/** @defgroup FLASH_Option_Bytes_nRST_STDBY + * @{ + */ +#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) +/** + * @} + */ + +/** @defgroup FLASH_BOR_Reset_Level + * @{ + */ +#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ + ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) +/** + * @} + */ + +/** @defgroup FLASH_Interrupts + * @{ + */ +#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ +#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ + ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ + ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ + ((FLAG) == FLASH_FLAG_BSY)) +/** + * @} + */ + +/** @defgroup FLASH_Program_Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) +#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) +#define FLASH_PSIZE_WORD ((uint32_t)0x00000200) +#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) +#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) +/** + * @} + */ + +/** @defgroup FLASH_Keys + * @{ + */ +#define RDP_KEY ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) +#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) +#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) +/** + * @} + */ + +/** + * @brief ACR register byte 0 (Bits[8:0]) base address + */ +#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) +/** + * @brief OPTCR register byte 3 (Bits[24:16]) base address + */ +#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) +#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) +#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* FLASH Interface configuration functions ************************************/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_PrefetchBufferCmd(FunctionalState NewState); +void FLASH_InstructionCacheCmd(FunctionalState NewState); +void FLASH_DataCacheCmd(FunctionalState NewState); +void FLASH_InstructionCacheReset(void); +void FLASH_DataCacheReset(void); + +/* FLASH Memory Programming functions *****************************************/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); +FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); +FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); + +/* Option Bytes Programming functions *****************************************/ +void FLASH_OB_Unlock(void); +void FLASH_OB_Lock(void); +void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); +void FLASH_OB_RDPConfig(uint8_t OB_RDP); +void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); +void FLASH_OB_BORConfig(uint8_t OB_BOR); +FLASH_Status FLASH_OB_Launch(void); +uint8_t FLASH_OB_GetUser(void); +uint16_t FLASH_OB_GetWRP(void); +FlagStatus FLASH_OB_GetRDP(void); +uint8_t FLASH_OB_GetBOR(void); + +/* Interrupts and flags management functions **********************************/ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_FLASH_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_fsmc.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_fsmc.h new file mode 100644 index 000000000..65ffc3269 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_fsmc.h @@ -0,0 +1,675 @@ +/** + ****************************************************************************** + * @file stm32f2xx_fsmc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the FSMC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_FSMC_H +#define __STM32F2xx_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note This parameter is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ +typedef struct +{ + uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank + * @{ + */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Bank + * @{ + */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FSMC_PCCARD_Bank + * @{ + */ +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +/** @defgroup FSMC_NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_AsynchronousWait + * @{ + */ +#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) +#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ + ((STATE) == FSMC_AsynchronousWait_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) +/** + * @} + */ + + +/** @defgroup FSMC_ECC + * @{ + */ +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* NOR/SRAM Controller functions **********************************************/ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); + +/* NAND Controller functions **************************************************/ +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); + +/* PCCARD Controller functions ************************************************/ +void FSMC_PCCARDDeInit(void); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_PCCARDCmd(FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h new file mode 100644 index 000000000..2300207eb --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h @@ -0,0 +1,411 @@ +/** + ****************************************************************************** + * @file stm32f2xx_gpio.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the GPIO firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_GPIO_H +#define __STM32F2xx_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG) || \ + ((PERIPH) == GPIOH) || \ + ((PERIPH) == GPIOI)) + +/** + * @brief GPIO Configuration Mode enumeration + */ +typedef enum +{ + GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ + GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ + GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ +}GPIOMode_TypeDef; +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ + ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) + +/** + * @brief GPIO Output type enumeration + */ +typedef enum +{ + GPIO_OType_PP = 0x00, + GPIO_OType_OD = 0x01 +}GPIOOType_TypeDef; +#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) + + +/** + * @brief GPIO Output Maximum frequency enumeration + */ +typedef enum +{ + GPIO_Speed_2MHz = 0x00, /*!< Low speed */ + GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ + GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ + GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) + +/** + * @brief GPIO Configuration PullUp PullDown enumeration + */ +typedef enum +{ + GPIO_PuPd_NOPULL = 0x00, + GPIO_PuPd_UP = 0x01, + GPIO_PuPd_DOWN = 0x02 +}GPIOPuPd_TypeDef; +#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ + ((PUPD) == GPIO_PuPd_DOWN)) + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIOOType_TypeDef */ + + GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIOPuPd_TypeDef */ +}GPIO_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) +/** + * @} + */ + + +/** @defgroup GPIO_Pin_sources + * @{ + */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) +/** + * @} + */ + +/** @defgroup GPIO_Alternat_function_selection_define + * @{ + */ +/** + * @brief AF 0 selection + */ +#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ +#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ + ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ + ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ + ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ + ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ + ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ + ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ + ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ + ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ + ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ + ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ + ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ + ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ + ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ + ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \ + ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \ + ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT)) +/** + * @} + */ + +/** @defgroup GPIO_Legacy + * @{ + */ + +#define GPIO_Mode_AIN GPIO_Mode_AN + +#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS +#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS +#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the GPIO configuration to the default reset state ****/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); + +/* Initialization and Configuration functions *********************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Read and Write functions **********************************************/ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Alternate functions configuration function ****************************/ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_GPIO_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_hash.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_hash.h new file mode 100644 index 000000000..62445fe33 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_hash.h @@ -0,0 +1,250 @@ +/** + ****************************************************************************** + * @file stm32f2xx_hash.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the HASH + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_HASH_H +#define __STM32F2xx_HASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup HASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HASH Init structure definition + */ +typedef struct +{ + uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value + of @ref HASH_Algo_Selection */ + uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value + of @ref HASH_processor_Algorithm_Mode */ + uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or + bit-string. This parameter can be a value of + @ref HASH_Data_Type */ + uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter + can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ +}HASH_InitTypeDef; + +/** + * @brief HASH message digest result structure definition + */ +typedef struct +{ + uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or + 4x 32bit words for MD5 */ +} HASH_MsgDigest; + +/** + * @brief HASH context swapping structure definition + */ +typedef struct +{ + uint32_t HASH_IMR; + uint32_t HASH_STR; + uint32_t HASH_CR; + uint32_t HASH_CSR[51]; +}HASH_Context; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HASH_Exported_Constants + * @{ + */ + +/** @defgroup HASH_Algo_Selection + * @{ + */ +#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */ +#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */ + +#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ + ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) +/** + * @} + */ + +/** @defgroup HASH_processor_Algorithm_Mode + * @{ + */ +#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */ +#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */ + +#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ + ((ALGOMODE) == HASH_AlgoMode_HMAC)) +/** + * @} + */ + +/** @defgroup HASH_Data_Type + * @{ + */ +#define HASH_DataType_32b ((uint16_t)0x0000) +#define HASH_DataType_16b ((uint16_t)0x0010) +#define HASH_DataType_8b ((uint16_t)0x0020) +#define HASH_DataType_1b ((uint16_t)0x0030) + +#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ + ((DATATYPE) == HASH_DataType_16b)|| \ + ((DATATYPE) == HASH_DataType_8b)|| \ + ((DATATYPE) == HASH_DataType_1b)) +/** + * @} + */ + +/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode + * @{ + */ +#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ +#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */ + +#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ + ((KEYTYPE) == HASH_HMACKeyType_LongKey)) +/** + * @} + */ + +/** @defgroup Number_of_valid_bits_in_last_word_of_the_message + * @{ + */ +#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F) + +/** + * @} + */ + +/** @defgroup HASH_interrupts_definition + * @{ + */ +#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/ +#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */ + +#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) +#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) + +/** + * @} + */ + +/** @defgroup HASH_flags_definition + * @{ + */ +#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/ +#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */ +#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ +#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */ +#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */ + +#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ + ((FLAG) == HASH_FLAG_DCIS) || \ + ((FLAG) == HASH_FLAG_DMAS) || \ + ((FLAG) == HASH_FLAG_BUSY) || \ + ((FLAG) == HASH_FLAG_DINNE)) + +#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \ + ((FLAG) == HASH_FLAG_DCIS)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the HASH configuration to the default reset state ****/ +void HASH_DeInit(void); + +/* HASH Configuration function ************************************************/ +void HASH_Init(HASH_InitTypeDef* HASH_InitStruct); +void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct); +void HASH_Reset(void); + +/* HASH Message Digest generation functions ***********************************/ +void HASH_DataIn(uint32_t Data); +uint8_t HASH_GetInFIFOWordsNbr(void); +void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); +void HASH_StartDigest(void); +void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); + +/* HASH Context swapping functions ********************************************/ +void HASH_SaveContext(HASH_Context* HASH_ContextSave); +void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); + +/* HASH's DMA interface function **********************************************/ +void HASH_DMACmd(FunctionalState NewState); + +/* HASH Interrupts and flags management functions *****************************/ +void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState); +FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG); +void HASH_ClearFlag(uint16_t HASH_FLAG); +ITStatus HASH_GetITStatus(uint8_t HASH_IT); +void HASH_ClearITPendingBit(uint8_t HASH_IT); + +/* High Level SHA1 functions **************************************************/ +ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); +ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, + uint8_t *Input, uint32_t Ilen, + uint8_t Output[20]); + +/* High Level MD5 functions ***************************************************/ +ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); +ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, + uint8_t *Input, uint32_t Ilen, + uint8_t Output[16]); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_HASH_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h new file mode 100644 index 000000000..bd3388845 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h @@ -0,0 +1,698 @@ +/** + ****************************************************************************** + * @file stm32f2xx_i2c.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the I2C firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_I2C_H +#define __STM32F2xx_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2) || \ + ((PERIPH) == I2C3)) +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ + ((CYCLE) == I2C_DutyCycle_2)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ + ((STATE) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_DR ((uint8_t)0x10) +#define I2C_Register_SR1 ((uint8_t)0x14) +#define I2C_Register_SR2 ((uint8_t)0x18) +#define I2C_Register_CCR ((uint8_t)0x1C) +#define I2C_Register_TRISE ((uint8_t)0x20) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_DR) || \ + ((REGISTER) == I2C_Register_SR1) || \ + ((REGISTER) == I2C_Register_SR2) || \ + ((REGISTER) == I2C_Register_CCR) || \ + ((REGISTER) == I2C_Register_TRISE)) +/** + * @} + */ + +/** @defgroup I2C_NACK_position + * @{ + */ + +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ + ((POSITION) == I2C_NACKPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) +#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ + ((ALERT) == I2C_SMBusAlert_High)) +/** + * @} + */ + +/** @defgroup I2C_PEC_position + * @{ + */ + +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ + ((POSITION) == I2C_PECPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ + ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ + ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ + ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +/** + * @brief SR2 register flags + */ + +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/** + * @brief SR1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ + ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ + ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ + ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ + ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ + ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ + ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ + ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_SB)) +/** + * @} + */ + +/** @defgroup I2C_Events + * @{ + */ + +/** + =============================================================================== + I2C Master Events (Events grouped in order of communication) + =============================================================================== + */ + +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateSTART() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* --EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_Send7bitAddress() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_ReceiveData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/** + =============================================================================== + I2C Slave Events (Events grouped in order of communication) + =============================================================================== + */ + + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_AcknowledgeConfig()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of transfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +/* + =============================================================================== + End of Events Description + =============================================================================== + */ + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ + ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @defgroup I2C_clock_speed + * @{ + */ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the I2C configuration to the default reset state *****/ +void I2C_DeInit(I2C_TypeDef* I2Cx); + +/* Initialization and Configuration functions *********************************/ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); + +/* PEC management functions ***************************************************/ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); + +/* DMA transfers management functions *****************************************/ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); + +/* Interrupts, events and flags management functions **************************/ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); + +/* + =============================================================================== + I2C State Monitoring Functions + =============================================================================== + This I2C driver provides three different ways for I2C state monitoring + depending on the application requirements and constraints: + + + 1. Basic state monitoring (Using I2C_CheckEvent() function) + ----------------------------------------------------------- + It compares the status registers (SR1 and SR2) content to a given event + (can be the combination of one or more flags). + It returns SUCCESS if the current status includes the given flags + and returns ERROR if one or more flags are missing in the current status. + + - When to use + - This function is suitable for most applications as well as for startup + activity since the events are fully described in the product reference + manual (RM0033). + - It is also suitable for users who need to define their own events. + + - Limitations + - If an error occurs (ie. error flags are set besides to the monitored + flags), the I2C_CheckEvent() function may return SUCCESS despite + the communication hold or corrupted real state. + In this case, it is advised to use error interrupts to monitor + the error events and handle them in the interrupt IRQ handler. + + Note + For error management, it is advised to use the following functions: + - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + Where x is the peripheral instance (I2C1, I2C2 ...) + - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the + I2Cx_ER_IRQHandler() function in order to determine which error occurred. + - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + and/or I2C_GenerateStop() in order to clear the error flag and source + and return to correct communication status. + + + 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) + -------------------------------------------------------------------- + Using the function I2C_GetLastEvent() which returns the image of both status + registers in a single word (uint32_t) (Status Register 2 value is shifted left + by 16 bits and concatenated to Status Register 1). + + - When to use + - This function is suitable for the same applications above but it + allows to overcome the mentioned limitation of I2C_GetFlagStatus() + function. + - The returned value could be compared to events already defined in + this file or to custom values defined by user. + This function is suitable when multiple flags are monitored at the + same time. + - At the opposite of I2C_CheckEvent() function, this function allows + user to choose when an event is accepted (when all events flags are + set and no other flags are set or just when the needed flags are set + like I2C_CheckEvent() function. + + - Limitations + - User may need to define his own events. + - Same remark concerning the error management is applicable for this + function if user decides to check only regular communication flags + (and ignores error flags). + + + 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) + ----------------------------------------------------------------------- + + Using the function I2C_GetFlagStatus() which simply returns the status of + one single flag (ie. I2C_FLAG_RXNE ...). + + - When to use + - This function could be used for specific applications or in debug + phase. + - It is suitable when only one flag checking is needed (most I2C + events are monitored through multiple flags). + - Limitations: + - When calling this function, the Status register is accessed. + Some flags are cleared when the status register is accessed. + So checking the status of one Flag, may clear other ones. + - Function may need to be called twice or more in order to monitor + one single event. + */ + +/* + =============================================================================== + 1. Basic state monitoring + =============================================================================== + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/* + =============================================================================== + 2. Advanced state monitoring + =============================================================================== + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/* + =============================================================================== + 3. Flag-based state monitoring + =============================================================================== + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_I2C_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_iwdg.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_iwdg.h new file mode 100644 index 000000000..e689bd763 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_iwdg.h @@ -0,0 +1,131 @@ +/** + ****************************************************************************** + * @file stm32f2xx_iwdg.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IWDG_H +#define __STM32F2xx_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Prescaler and Counter configuration functions ******************************/ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); + +/* IWDG activation function ***************************************************/ +void IWDG_Enable(void); + +/* Flag management function ***************************************************/ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h new file mode 100644 index 000000000..7a9cf3ec5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file stm32f2xx_pwr.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_PWR_H +#define __STM32F2xx_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level + * @{ + */ + +#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 + +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ + ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ + ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ + ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) +/** + * @} + */ + + +/** @defgroup PWR_Regulator_state_in_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower PWR_CR_LPDS +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_BRR PWR_CSR_BRR + +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the PWR configuration to the default reset state ******/ +void PWR_DeInit(void); + +/* Backup Domain Access function **********************************************/ +void PWR_BackupAccessCmd(FunctionalState NewState); + +/* PVD configuration functions ************************************************/ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_PVDCmd(FunctionalState NewState); + +/* WakeUp pins configuration functions ****************************************/ +void PWR_WakeUpPinCmd(FunctionalState NewState); + +/* Backup Regulator configuration functions ***********************************/ +void PWR_BackupRegulatorCmd(FunctionalState NewState); + +/* FLASH Power Down configuration functions ***********************************/ +void PWR_FlashPowerDownCmd(FunctionalState NewState); + +/* Low Power modes configuration functions ************************************/ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); + +/* Flags management functions *************************************************/ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_PWR_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h new file mode 100644 index 000000000..cfe0f0bc6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h @@ -0,0 +1,515 @@ +/** + ****************************************************************************** + * @file stm32f2xx_rcc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the RCC firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_RCC_H +#define __STM32F2xx_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup RCC_HSE_configuration + * @{ + */ +#define RCC_HSE_OFF ((uint8_t)0x00) +#define RCC_HSE_ON ((uint8_t)0x01) +#define RCC_HSE_Bypass ((uint8_t)0x05) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source + * @{ + */ +#define RCC_PLLSource_HSI ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE ((uint32_t)0x00400000) +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ + ((SOURCE) == RCC_PLLSource_HSE)) +#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) +#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) + +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source + * @{ + */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source + * @{ + */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source + * @{ + */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00001000) +#define RCC_HCLK_Div4 ((uint32_t)0x00001400) +#define RCC_HCLK_Div8 ((uint32_t)0x00001800) +#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_Source + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) +#define RCC_IT_CSS ((uint8_t)0x80) +#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLLI2SRDY)) +#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration + * @{ + */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source + * @{ + */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) +#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) +#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) +#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) +#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) +#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) +#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) +#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) +#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) +#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) +#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) +#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) +#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) +#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) +#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) +#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) +#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) +#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) +#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) +#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) +#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) +#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) +#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) +#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) +#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) +#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) +#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) +#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) +#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) +#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) +/** + * @} + */ + +/** @defgroup RCC_I2S_Clock_Source + * @{ + */ +#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) +#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) + +#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripherals + * @{ + */ +#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) +#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) +#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) +#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) +#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) +#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) +#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) +#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) +#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) +#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) +#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) +#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) +#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) +#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) +#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) +#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) +#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) +#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) +#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) +#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) +#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) +#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) +#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripherals + * @{ + */ +#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) +#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) +#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) +#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) +#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) +#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_AHB3_Peripherals + * @{ + */ +#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) +#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripherals + * @{ + */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripherals + * @{ + */ +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) +#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) +#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) +#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source_Prescaler + * @{ + */ +#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) +#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) +#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) +#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) +#define RCC_MCO1Div_1 ((uint32_t)0x00000000) +#define RCC_MCO1Div_2 ((uint32_t)0x04000000) +#define RCC_MCO1Div_3 ((uint32_t)0x05000000) +#define RCC_MCO1Div_4 ((uint32_t)0x06000000) +#define RCC_MCO1Div_5 ((uint32_t)0x07000000) +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ + ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) + +#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ + ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ + ((DIV) == RCC_MCO1Div_5)) +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source_Prescaler + * @{ + */ +#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) +#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) +#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) +#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) +#define RCC_MCO2Div_1 ((uint32_t)0x00000000) +#define RCC_MCO2Div_2 ((uint32_t)0x20000000) +#define RCC_MCO2Div_3 ((uint32_t)0x28000000) +#define RCC_MCO2Div_4 ((uint32_t)0x30000000) +#define RCC_MCO2Div_5 ((uint32_t)0x38000000) +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) + +#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ + ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ + ((DIV) == RCC_MCO2Div_5)) +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_BORRST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ + ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ + ((FLAG) == RCC_FLAG_PLLI2SRDY)) +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RCC clock configuration to the default reset state */ +void RCC_DeInit(void); + +/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ +void RCC_HSEConfig(uint8_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); + +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); +void RCC_PLLI2SCmd(FunctionalState NewState); + +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); +void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); + +/* System, AHB and APB busses clocks configuration functions ******************/ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); + +/* Peripheral clocks configuration functions **********************************/ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); + +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_RCC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rng.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rng.h new file mode 100644 index 000000000..c2b52e686 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rng.h @@ -0,0 +1,120 @@ +/** + ****************************************************************************** + * @file stm32f2xx_rng.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the Random + * Number Generator(RNG) firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_RNG_H +#define __STM32F2xx_RNG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RNG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RNG_Exported_Constants + * @{ + */ + +/** @defgroup RNG_flags_definition + * @{ + */ +#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ +#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ +#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ + +#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ + ((RNG_FLAG) == RNG_FLAG_CECS) || \ + ((RNG_FLAG) == RNG_FLAG_SECS)) +#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ + ((RNG_FLAG) == RNG_FLAG_SECS)) +/** + * @} + */ + +/** @defgroup RNG_interrupts_definition + * @{ + */ +#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ +#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ + +#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) +#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RNG configuration to the default reset state *****/ +void RNG_DeInit(void); + +/* Configuration function *****************************************************/ +void RNG_Cmd(FunctionalState NewState); + +/* Get 32 bit Random number function ******************************************/ +uint32_t RNG_GetRandomNumber(void); + +/* Interrupts and flags management functions **********************************/ +void RNG_ITConfig(FunctionalState NewState); +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); +void RNG_ClearFlag(uint8_t RNG_FLAG); +ITStatus RNG_GetITStatus(uint8_t RNG_IT); +void RNG_ClearITPendingBit(uint8_t RNG_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_RNG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h new file mode 100644 index 000000000..3cb7e2020 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h @@ -0,0 +1,650 @@ +/** + ****************************************************************************** + * @file stm32f2xx_rtc.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_RTC_H +#define __STM32F2xx_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be set to a value lower than 0x7F */ + + uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be set to a value lower than 0x1FFF */ +}RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. + This parameter must be set to a value in the 0-12 range + if the RTC_HourFormat_12 is selected or 0-23 range if + the RTC_HourFormat_24 is selected. */ + + uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ +}RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t RTC_Date; /*!< Specifies the RTC Date. + This parameter must be set to a value in the 1-31 range. */ + + uint8_t RTC_Year; /*!< Specifies the RTC Date Year. + This parameter must be set to a value in the 0-99 range. */ +}RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter + must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this + parameter can be a value of @ref RTC_WeekDay_Definitions */ +}RTC_AlarmTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + + +/** @defgroup RTC_Hour_Formats + * @{ + */ +#define RTC_HourFormat_24 ((uint32_t)0x00000000) +#define RTC_HourFormat_12 ((uint32_t)0x00000040) +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ + ((FORMAT) == RTC_HourFormat_24)) +/** + * @} + */ + +/** @defgroup RTC_Asynchronous_Predivider + * @{ + */ +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) + +/** + * @} + */ + + +/** @defgroup RTC_Synchronous_Predivider + * @{ + */ +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFF) + +/** + * @} + */ + +/** @defgroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) + +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_H12_AM ((uint8_t)0x00) +#define RTC_H12_PM ((uint8_t)0x40) +#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) + +/** + * @} + */ + +/** @defgroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) + +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_Month_January ((uint8_t)0x01) +#define RTC_Month_February ((uint8_t)0x02) +#define RTC_Month_March ((uint8_t)0x03) +#define RTC_Month_April ((uint8_t)0x04) +#define RTC_Month_May ((uint8_t)0x05) +#define RTC_Month_June ((uint8_t)0x06) +#define RTC_Month_July ((uint8_t)0x07) +#define RTC_Month_August ((uint8_t)0x08) +#define RTC_Month_September ((uint8_t)0x09) +#define RTC_Month_October ((uint8_t)0x10) +#define RTC_Month_November ((uint8_t)0x11) +#define RTC_Month_December ((uint8_t)0x12) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions + * @{ + */ + +#define RTC_Weekday_Monday ((uint8_t)0x01) +#define RTC_Weekday_Tuesday ((uint8_t)0x02) +#define RTC_Weekday_Wednesday ((uint8_t)0x03) +#define RTC_Weekday_Thursday ((uint8_t)0x04) +#define RTC_Weekday_Friday ((uint8_t)0x05) +#define RTC_Weekday_Saturday ((uint8_t)0x06) +#define RTC_Weekday_Sunday ((uint8_t)0x07) +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) +/** + * @} + */ + + +/** @defgroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmDateWeekDay_Definitions + * @{ + */ +#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) +#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ + ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_AlarmMask_None ((uint32_t)0x00000000) +#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) +#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) +#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) +#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) +#define RTC_AlarmMask_All ((uint32_t)0x80808080) +#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions + * @{ + */ +#define RTC_Alarm_A ((uint32_t)0x00000100) +#define RTC_Alarm_B ((uint32_t)0x00000200) +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) +#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup RTC_Wakeup_Timer_Definitions + * @{ + */ +#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) +#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) +#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) +#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) +#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) +#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ + ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ + ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ + ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +/** + * @} + */ + +/** @defgroup RTC_Time_Stamp_Edges_definitions + * @{ + */ +#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) +#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) +#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ + ((EDGE) == RTC_TimeStampEdge_Falling)) +/** + * @} + */ + +/** @defgroup RTC_Output_selection_Definitions + * @{ + */ +#define RTC_Output_Disable ((uint32_t)0x00000000) +#define RTC_Output_AlarmA ((uint32_t)0x00200000) +#define RTC_Output_AlarmB ((uint32_t)0x00400000) +#define RTC_Output_WakeUp ((uint32_t)0x00600000) + +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ + ((OUTPUT) == RTC_Output_AlarmA) || \ + ((OUTPUT) == RTC_Output_AlarmB) || \ + ((OUTPUT) == RTC_Output_WakeUp)) + +/** + * @} + */ + +/** @defgroup RTC_Output_Polarity_Definitions + * @{ + */ +#define RTC_OutputPolarity_High ((uint32_t)0x00000000) +#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ + ((POL) == RTC_OutputPolarity_Low)) +/** + * @} + */ + + +/** @defgroup RTC_Digital_Calibration_Definitions + * @{ + */ +#define RTC_CalibSign_Positive ((uint32_t)0x00000000) +#define RTC_CalibSign_Negative ((uint32_t)0x00000080) +#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ + ((SIGN) == RTC_CalibSign_Negative)) +#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) + +/** + * @} + */ + + +/** @defgroup RTC_DayLightSaving_Definitions + * @{ + */ +#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) +#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ + ((SAVE) == RTC_DayLightSaving_ADD1H)) + +#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) +#define RTC_StoreOperation_Set ((uint32_t)0x00040000) +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ + ((OPERATION) == RTC_StoreOperation_Set)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Trigger_Definitions + * @{ + */ +#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) +#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pins_Definitions + * @{ + */ +#define RTC_Tamper_1 RTC_TAFCR_TAMP1E +#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pin_Selection + * @{ + */ +#define RTC_TamperPin_PC13 ((uint32_t)0x00000000) +#define RTC_TamperPin_PI8 ((uint32_t)0x00010000) +#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ + ((PIN) == RTC_TamperPin_PI8)) +/** + * @} + */ + +/** @defgroup RTC_TimeStamp_Pin_Selection + * @{ + */ +#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) +#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) +#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ + ((PIN) == RTC_TimeStampPin_PI8)) +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT + * @{ + */ +#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) +#define RTC_OutputType_PushPull ((uint32_t)0x00040000) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ + ((TYPE) == RTC_OutputType_PushPull)) + +/** + * @} + */ + +/** @defgroup RTC_Backup_Registers_Definitions + * @{ + */ + +#define RTC_BKP_DR0 ((uint32_t)0x00000000) +#define RTC_BKP_DR1 ((uint32_t)0x00000001) +#define RTC_BKP_DR2 ((uint32_t)0x00000002) +#define RTC_BKP_DR3 ((uint32_t)0x00000003) +#define RTC_BKP_DR4 ((uint32_t)0x00000004) +#define RTC_BKP_DR5 ((uint32_t)0x00000005) +#define RTC_BKP_DR6 ((uint32_t)0x00000006) +#define RTC_BKP_DR7 ((uint32_t)0x00000007) +#define RTC_BKP_DR8 ((uint32_t)0x00000008) +#define RTC_BKP_DR9 ((uint32_t)0x00000009) +#define RTC_BKP_DR10 ((uint32_t)0x0000000A) +#define RTC_BKP_DR11 ((uint32_t)0x0000000B) +#define RTC_BKP_DR12 ((uint32_t)0x0000000C) +#define RTC_BKP_DR13 ((uint32_t)0x0000000D) +#define RTC_BKP_DR14 ((uint32_t)0x0000000E) +#define RTC_BKP_DR15 ((uint32_t)0x0000000F) +#define RTC_BKP_DR16 ((uint32_t)0x00000010) +#define RTC_BKP_DR17 ((uint32_t)0x00000011) +#define RTC_BKP_DR18 ((uint32_t)0x00000012) +#define RTC_BKP_DR19 ((uint32_t)0x00000013) +#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ + ((BKP) == RTC_BKP_DR1) || \ + ((BKP) == RTC_BKP_DR2) || \ + ((BKP) == RTC_BKP_DR3) || \ + ((BKP) == RTC_BKP_DR4) || \ + ((BKP) == RTC_BKP_DR5) || \ + ((BKP) == RTC_BKP_DR6) || \ + ((BKP) == RTC_BKP_DR7) || \ + ((BKP) == RTC_BKP_DR8) || \ + ((BKP) == RTC_BKP_DR9) || \ + ((BKP) == RTC_BKP_DR10) || \ + ((BKP) == RTC_BKP_DR11) || \ + ((BKP) == RTC_BKP_DR12) || \ + ((BKP) == RTC_BKP_DR13) || \ + ((BKP) == RTC_BKP_DR14) || \ + ((BKP) == RTC_BKP_DR15) || \ + ((BKP) == RTC_BKP_DR16) || \ + ((BKP) == RTC_BKP_DR17) || \ + ((BKP) == RTC_BKP_DR18) || \ + ((BKP) == RTC_BKP_DR19)) +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions + * @{ + */ +#define RTC_Format_BIN ((uint32_t)0x000000000) +#define RTC_Format_BCD ((uint32_t)0x000000001) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) + +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) +#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) +#define RTC_FLAG_TSF ((uint32_t)0x00000800) +#define RTC_FLAG_WUTF ((uint32_t)0x00000400) +#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) +#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) +#define RTC_FLAG_INITF ((uint32_t)0x00000040) +#define RTC_FLAG_RSF ((uint32_t)0x00000020) +#define RTC_FLAG_INITS ((uint32_t)0x00000010) +#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) +#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) +#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ + ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ + ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ + ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ + ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ + ((FLAG) == RTC_FLAG_TAMP1F)) +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFC0DF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions + * @{ + */ +#define RTC_IT_TS ((uint32_t)0x00008000) +#define RTC_IT_WUT ((uint32_t)0x00004000) +#define RTC_IT_ALRB ((uint32_t)0x00002000) +#define RTC_IT_ALRA ((uint32_t)0x00001000) +#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TAMP1 ((uint32_t)0x00020000) + +#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ + ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ + ((IT) == RTC_IT_TAMP1)) +#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup RTC_Legacy + * @{ + */ +#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig +#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the RTC configuration to the default reset state *****/ +ErrorStatus RTC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); +void RTC_WriteProtectionCmd(FunctionalState NewState); +ErrorStatus RTC_EnterInitMode(void); +void RTC_ExitInitMode(void); +ErrorStatus RTC_WaitForSynchro(void); +ErrorStatus RTC_RefClockCmd(FunctionalState NewState); + +/* Time and Date configuration functions **************************************/ +ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); +void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); + +/* Alarms (Alarm A and Alarm B) configuration functions **********************/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); + +/* WakeUp Timer configuration functions ***************************************/ +void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); +uint32_t RTC_GetWakeUpCounter(void); +ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); + +/* Daylight Saving configuration functions ************************************/ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void); + +/* Output pin Configuration function ******************************************/ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); + +/* Coarse Calibration configuration functions *********************************/ +ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); +ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); +void RTC_CalibOutputCmd(FunctionalState NewState); + +/* TimeStamp configuration functions ******************************************/ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, + RTC_DateTypeDef* RTC_StampDateStruct); + +/* Tampers configuration functions ********************************************/ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); + +/* Backup Data Registers configuration functions ******************************/ +void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); +uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); + +/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration + functions ******************************************************************/ +void RTC_TamperPinSelection(uint32_t RTC_TamperPin); +void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); +void RTC_OutputTypeConfig(uint32_t RTC_OutputType); + +/* Interrupts and flags management functions **********************************/ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +void RTC_ClearFlag(uint32_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint32_t RTC_IT); +void RTC_ClearITPendingBit(uint32_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_RTC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_sdio.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_sdio.h new file mode 100644 index 000000000..16efdeeb2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_sdio.h @@ -0,0 +1,536 @@ +/** + ****************************************************************************** + * @file stm32f2xx_sdio.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the SDIO firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_SDIO_H +#define __STM32F2xx_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_sources + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/* Function used to set the SDIO configuration to the default reset state ****/ +void SDIO_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); + +/* Command path state machine (CPSM) management functions *********************/ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); + +/* Data path state machine (DPSM) management functions ************************/ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); + +/* SDIO IO Cards mode management functions ************************************/ +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); + +/* CE-ATA mode management functions *******************************************/ +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); + +/* DMA transfers management functions *****************************************/ +void SDIO_DMACmd(FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_SDIO_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h new file mode 100644 index 000000000..594dfd631 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h @@ -0,0 +1,526 @@ +/** + ****************************************************************************** + * @file stm32f2xx_spi.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the SPI + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_SPI_H +#define __STM32F2xx_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx)|| \ + ((MODE) == I2S_Mode_MasterRx)) +/** + * @} + */ + + +/** @defgroup SPI_I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup SPI_I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ + ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define I2S_IT_UDR ((uint8_t)0x53) +#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) + +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) + +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) + +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) + +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ + ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ + ((IT) == SPI_I2S_IT_TIFRFE)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) + +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ + ((FLAG) == SPI_I2S_FLAG_TIFRFE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** @defgroup SPI_I2S_Legacy + * @{ + */ + +#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx +#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx +#define SPI_IT_TXE SPI_I2S_IT_TXE +#define SPI_IT_RXNE SPI_I2S_IT_RXNE +#define SPI_IT_ERR SPI_I2S_IT_ERR +#define SPI_IT_OVR SPI_I2S_IT_OVR +#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE +#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE +#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR +#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY +#define SPI_DeInit SPI_I2S_DeInit +#define SPI_ITConfig SPI_I2S_ITConfig +#define SPI_DMACmd SPI_I2S_DMACmd +#define SPI_SendData SPI_I2S_SendData +#define SPI_ReceiveData SPI_I2S_ReceiveData +#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus +#define SPI_ClearFlag SPI_I2S_ClearFlag +#define SPI_GetITStatus SPI_I2S_GetITStatus +#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the SPI configuration to the default reset state *****/ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); + +/* Initialization and Configuration functions *********************************/ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); + +/* Hardware CRC Calculation functions *****************************************/ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); + +/* DMA transfers management functions *****************************************/ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_SPI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h new file mode 100644 index 000000000..ab45e12a0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h @@ -0,0 +1,179 @@ +/** + ****************************************************************************** + * @file stm32f2xx_syscfg.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the SYSCFG firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_SYSCFG_H +#define __STM32F2xx_SYSCFG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SYSCFG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SYSCFG_Exported_Constants + * @{ + */ + +/** @defgroup SYSCFG_EXTI_Port_Sources + * @{ + */ +#define EXTI_PortSourceGPIOA ((uint8_t)0x00) +#define EXTI_PortSourceGPIOB ((uint8_t)0x01) +#define EXTI_PortSourceGPIOC ((uint8_t)0x02) +#define EXTI_PortSourceGPIOD ((uint8_t)0x03) +#define EXTI_PortSourceGPIOE ((uint8_t)0x04) +#define EXTI_PortSourceGPIOF ((uint8_t)0x05) +#define EXTI_PortSourceGPIOG ((uint8_t)0x06) +#define EXTI_PortSourceGPIOH ((uint8_t)0x07) +#define EXTI_PortSourceGPIOI ((uint8_t)0x08) + +#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOI)) +/** + * @} + */ + + +/** @defgroup SYSCFG_EXTI_Pin_Sources + * @{ + */ +#define EXTI_PinSource0 ((uint8_t)0x00) +#define EXTI_PinSource1 ((uint8_t)0x01) +#define EXTI_PinSource2 ((uint8_t)0x02) +#define EXTI_PinSource3 ((uint8_t)0x03) +#define EXTI_PinSource4 ((uint8_t)0x04) +#define EXTI_PinSource5 ((uint8_t)0x05) +#define EXTI_PinSource6 ((uint8_t)0x06) +#define EXTI_PinSource7 ((uint8_t)0x07) +#define EXTI_PinSource8 ((uint8_t)0x08) +#define EXTI_PinSource9 ((uint8_t)0x09) +#define EXTI_PinSource10 ((uint8_t)0x0A) +#define EXTI_PinSource11 ((uint8_t)0x0B) +#define EXTI_PinSource12 ((uint8_t)0x0C) +#define EXTI_PinSource13 ((uint8_t)0x0D) +#define EXTI_PinSource14 ((uint8_t)0x0E) +#define EXTI_PinSource15 ((uint8_t)0x0F) +#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ + ((PINSOURCE) == EXTI_PinSource1) || \ + ((PINSOURCE) == EXTI_PinSource2) || \ + ((PINSOURCE) == EXTI_PinSource3) || \ + ((PINSOURCE) == EXTI_PinSource4) || \ + ((PINSOURCE) == EXTI_PinSource5) || \ + ((PINSOURCE) == EXTI_PinSource6) || \ + ((PINSOURCE) == EXTI_PinSource7) || \ + ((PINSOURCE) == EXTI_PinSource8) || \ + ((PINSOURCE) == EXTI_PinSource9) || \ + ((PINSOURCE) == EXTI_PinSource10) || \ + ((PINSOURCE) == EXTI_PinSource11) || \ + ((PINSOURCE) == EXTI_PinSource12) || \ + ((PINSOURCE) == EXTI_PinSource13) || \ + ((PINSOURCE) == EXTI_PinSource14) || \ + ((PINSOURCE) == EXTI_PinSource15)) +/** + * @} + */ + + +/** @defgroup SYSCFG_Memory_Remap_Config + * @{ + */ +#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) +#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) +#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) +#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) + +#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ + ((REMAP) == SYSCFG_MemoryRemap_FSMC)) +/** + * @} + */ + + +/** @defgroup SYSCFG_ETHERNET_Media_Interface + * @{ + */ +#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) +#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) + +#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ + ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void SYSCFG_DeInit(void); +void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); +void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); +void SYSCFG_CompensationCellCmd(FunctionalState NewState); +FlagStatus SYSCFG_GetCompensationCellStatus(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_SYSCFG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h new file mode 100644 index 000000000..62590b64c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h @@ -0,0 +1,1150 @@ +/** + ****************************************************************************** + * @file stm32f2xx_tim.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the TIM firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_TIM_H +#define __STM32F2xx_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief TIM Time Base Init structure definition + * @note This structure is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_State */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief BDTR structure definition + * @note This structure is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10) || \ + ((PERIPH) == TIM11) || \ + ((PERIPH) == TIM12) || \ + (((PERIPH) == TIM13) || \ + ((PERIPH) == TIM14))) +/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10) || \ + ((PERIPH) == TIM11) || \ + ((PERIPH) == TIM12) || \ + ((PERIPH) == TIM13) || \ + ((PERIPH) == TIM14)) + +/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)) +/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) +/* LIST4: TIM1 and TIM8 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) +/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8)) +/* LIST6: TIM2, TIM5 and TIM11 */ +#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ + ((TIMx) == TIM5) || \ + ((TIMx) == TIM11)) + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) + +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_State + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_State + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)|| \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define TIM_DMABase_OR ((uint16_t)0x0013) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR) || \ + ((BASE) == TIM_DMABase_OR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ +/** @defgroup TIM_Remap + * @{ + */ + +#define TIM2_TIM8_TRGO ((uint16_t)0x0000) +#define TIM2_ETH_PTP ((uint16_t)0x0400) +#define TIM2_USBFS_SOF ((uint16_t)0x0800) +#define TIM2_USBHS_SOF ((uint16_t)0x0C00) + +#define TIM5_GPIO ((uint16_t)0x0000) +#define TIM5_LSI ((uint16_t)0x0040) +#define TIM5_LSE ((uint16_t)0x0080) +#define TIM5_RTC ((uint16_t)0x00C0) + +#define TIM11_GPIO ((uint16_t)0x0000) +#define TIM11_HSE ((uint16_t)0x0002) + +#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ + ((TIM_REMAP) == TIM2_ETH_PTP)||\ + ((TIM_REMAP) == TIM2_USBFS_SOF)||\ + ((TIM_REMAP) == TIM2_USBHS_SOF)||\ + ((TIM_REMAP) == TIM5_GPIO)||\ + ((TIM_REMAP) == TIM5_LSI)||\ + ((TIM_REMAP) == TIM5_LSE)||\ + ((TIM_REMAP) == TIM5_RTC)||\ + ((TIM_REMAP) == TIM11_GPIO)||\ + ((TIM_REMAP) == TIM11_HSE)) + +/** + * @} + */ +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_Legacy + * @{ + */ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* TimeBase management ********************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Output Compare management **************************************************/ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); + +/* Input Capture management ***************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); + +/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Interrupts, DMA and flags management ***************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Clocks management **********************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); + +/* Synchronization management *************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); + +/* Specific interface management **********************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Specific remapping management **********************************************/ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F2xx_TIM_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h new file mode 100644 index 000000000..dd27ac1f3 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h @@ -0,0 +1,429 @@ +/** + ****************************************************************************** + * @file stm32f2xx_usart.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_USART_H +#define __STM32F2xx_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 + Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ + + uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4) || \ + ((PERIPH) == UART5) || \ + ((PERIPH) == USART6)) + +#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == USART6)) + +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +/** @defgroup USART_Legacy + * @{ + */ +#define USART_IT_ORE USART_IT_ORE_ER +/** + * @} + */ + +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the USART configuration to the default reset state ***/ +void USART_DeInit(USART_TypeDef* USARTx); + +/* Initialization and Configuration functions *********************************/ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); + +/* Multi-Processor Communication functions ************************************/ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* LIN mode functions *********************************************************/ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendBreak(USART_TypeDef* USARTx); + +/* Half-duplex mode function **************************************************/ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Smartcard mode functions ***************************************************/ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); + +/* IrDA mode functions ********************************************************/ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* DMA transfers management functions *****************************************/ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_USART_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_wwdg.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_wwdg.h new file mode 100644 index 000000000..c4c1969dc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_wwdg.h @@ -0,0 +1,111 @@ +/** + ****************************************************************************** + * @file stm32f2xx_wwdg.h + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the WWDG firmware + * library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_WWDG_H +#define __STM32F2xx_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/* Function used to set the WWDG configuration to the default reset state ****/ +void WWDG_DeInit(void); + +/* Prescaler, Refresh window and Counter configuration functions **************/ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); + +/* WWDG activation function ***************************************************/ +void WWDG_Enable(uint8_t Counter); + +/* Interrupts and flags management functions **********************************/ +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c new file mode 100644 index 000000000..7555a3d89 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c @@ -0,0 +1,249 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + * + * @verbatim + * + * =================================================================== + * How to configure Interrupts using driver + * =================================================================== + * + * This section provide functions allowing to configure the NVIC interrupts (IRQ). + * The Cortex-M3 exceptions are managed by CMSIS functions. + * + * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() + * function according to the following table. + + * The table below gives the allowed values of the pre-emption priority and subpriority according + * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + * ========================================================================================================================== + * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + * ========================================================================================================================== + * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + * | | | 4 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + * | | | 3 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + * | | | 2 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + * | | | 1 bits for subpriority + * -------------------------------------------------------------------------------------------------------------------------- + * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + * | | | 0 bits for subpriority + * ========================================================================================================================== + * + * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() + * + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * + * @note IRQ priority order (sorted by highest to lowest priority): + * - Lowest pre-emption priority + * - Lowest subpriority + * - Lowest hardware priority (IRQ number) + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); + + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. + * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. + * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. + * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. + * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c new file mode 100644 index 000000000..e1d05597a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c @@ -0,0 +1,1748 @@ +/** + ****************************************************************************** + * @file stm32f2xx_adc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) peripheral: + * - Initialization and Configuration (in addition to ADC multi mode + * selection) + * - Analog Watchdog configuration + * - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT + * management + * - Regular Channels Configuration + * - Regular Channels DMA Configuration + * - Injected channels Configuration + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + + * 1. Enable the ADC interface clock using + * RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); + * + * 2. ADC pins configuration + * - Enable the clock for the ADC GPIOs using the following function: + * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + * - Configure these ADC pins in analog mode using GPIO_Init(); + * + * 3. Configure the ADC Prescaler, conversion resolution and data + * alignment using the ADC_Init() function. + * 4. Activate the ADC peripheral using ADC_Cmd() function. + * + * Regular channels group configuration + * ==================================== + * - To configure the ADC regular channels group features, use + * ADC_Init() and ADC_RegularChannelConfig() functions. + * - To activate the continuous mode, use the ADC_continuousModeCmd() + * function. + * - To configurate and activate the Discontinuous mode, use the + * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. + * - To read the ADC converted values, use the ADC_GetConversionValue() + * function. + * + * Multi mode ADCs Regular channels configuration + * =============================================== + * - Refer to "Regular channels group configuration" description to + * configure the ADC1, ADC2 and ADC3 regular channels. + * - Select the Multi mode ADC regular channels features (dual or + * triple mode) using ADC_CommonInit() function and configure + * the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() + * functions. + * - Read the ADCs converted values using the + * ADC_GetMultiModeConversionValue() function. + * + * DMA for Regular channels group features configuration + * ====================================================== + * - To enable the DMA mode for regular channels group, use the + * ADC_DMACmd() function. + * - To enable the generation of DMA requests continuously at the end + * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() + * function. + * + * Injected channels group configuration + * ===================================== + * - To configure the ADC Injected channels group features, use + * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() + * functions. + * - To activate the continuous mode, use the ADC_continuousModeCmd() + * function. + * - To activate the Injected Discontinuous mode, use the + * ADC_InjectedDiscModeCmd() function. + * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() + * function. + * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() + * function. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) + +/* ADC EXTEN mask */ +#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) + +/* ADC JEXTEN mask */ +#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_SET ((uint32_t)0x0000001F) +#define SQR2_SQ_SET ((uint32_t)0x0000001F) +#define SQR1_SQ_SET ((uint32_t)0x0000001F) + +/* ADC L Mask */ +#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_SET ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_SET ((uint32_t)0x00300000) +#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_SET ((uint32_t)0x00000007) +#define SMPR2_SMP_SET ((uint32_t)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_OFFSET ((uint8_t)0x28) + +/* ADC CDR register base address */ +#define CDR_ADDRESS ((uint32_t)0x40012308) + +/* ADC CCR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** @defgroup ADC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + This section provides functions allowing to: + - Initialize and configure the ADC Prescaler + - ADC Conversion Resolution (12bit..6bit) + - Scan Conversion Mode (multichannels or one channel) for regular group + - ADC Continuous Conversion Mode (Continuous or Single conversion) for + regular group + - External trigger Edge and source of regular group, + - Converted data alignment (left or right) + - The number of ADC conversions that will be done using the sequencer for + regular channel group + - Multi ADC mode selection + - Direct memory access mode selection for multi ADC mode + - Delay between 2 sampling phases (used in dual or triple interleaved modes) + - Enable or disable the ADC peripheral + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes all ADCs peripherals registers to their default reset + * values. + * @param None + * @retval None + */ +void ADC_DeInit(void) +{ + /* Enable all ADCs reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); + + /* Release all ADCs from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @note This function is used to configure the global features of the ADC ( + * Resolution and Data Alignment), however, the rest of the configuration + * parameters are specific to the regular channels group (scan mode + * activation, continuous mode activation, External trigger source and + * edge, number of conversion in the regular channels group sequencer). + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + + /* Clear RES and SCAN bits */ + tmpreg1 &= CR1_CLEAR_MASK; + + /* Configure ADCx: scan conversion mode and resolution */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + /* Set RES bit according to ADC_Resolution value */ + tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ + ADC_InitStruct->ADC_Resolution); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + + /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_MASK; + + /* Configure ADCx: external trigger event and edge, data alignment and + continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ + ADC_InitStruct->ADC_ExternalTrigConv | + ADC_InitStruct->ADC_ExternalTrigConvEdge | \ + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + + /* Clear L bits */ + tmpreg1 &= SQR1_L_RESET; + + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfConversion value */ + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); + tmpreg1 |= ((uint32_t)tmpreg2 << 20); + + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @note This function is used to initialize the global features of the ADC ( + * Resolution and Data Alignment), however, the rest of the configuration + * parameters are specific to the regular channels group (scan mode + * activation, continuous mode activation, External trigger source and + * edge, number of conversion in the regular channels group sequencer). + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; + + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + + /* Initialize the ADC_ExternalTrigConvEdge member */ + ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + + /* Initialize the ADC_NbrOfConversion member */ + ADC_InitStruct->ADC_NbrOfConversion = 1; +} + +/** + * @brief Initializes the ADCs peripherals according to the specified parameters + * in the ADC_CommonInitStruct. + * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure + * that contains the configuration information for All ADCs peripherals. + * @retval None + */ +void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) +{ + uint32_t tmpreg1 = 0; + /* Check the parameters */ + assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); + assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); + assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); + assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); + /*---------------------------- ADC CCR Configuration -----------------*/ + /* Get the ADC CCR value */ + tmpreg1 = ADC->CCR; + + /* Clear MULTI, DELAY, DMA and ADCPRE bits */ + tmpreg1 &= CR_CLEAR_MASK; + + /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, + and DMA access mode for multimode */ + /* Set MULTI bits according to ADC_Mode value */ + /* Set ADCPRE bits according to ADC_Prescaler value */ + /* Set DMA bits according to ADC_DMAAccessMode value */ + /* Set DELAY bits according to ADC_TwoSamplingDelay value */ + tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | + ADC_CommonInitStruct->ADC_Prescaler | + ADC_CommonInitStruct->ADC_DMAAccessMode | + ADC_CommonInitStruct->ADC_TwoSamplingDelay); + + /* Write to ADC CCR */ + ADC->CCR = tmpreg1; +} + +/** + * @brief Fills each ADC_CommonInitStruct member with its default value. + * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure + * which will be initialized. + * @retval None + */ +void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) +{ + /* Initialize the ADC_Mode member */ + ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; + + /* initialize the ADC_Prescaler member */ + ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; + + /* Initialize the ADC_DMAAccessMode member */ + ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + + /* Initialize the ADC_TwoSamplingDelay member */ + ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); + } +} +/** + * @} + */ + +/** @defgroup ADC_Group2 Analog Watchdog configuration functions + * @brief Analog Watchdog configuration functions + * +@verbatim + =============================================================================== + Analog Watchdog configuration functions + =============================================================================== + + This section provides functions allowing to configure the Analog Watchdog + (AWD) feature in the ADC. + + A typical configuration Analog Watchdog is done following these steps : + 1. the ADC guarded channel(s) is (are) selected using the + ADC_AnalogWatchdogSingleChannelConfig() function. + 2. The Analog watchdog lower and higher threshold are configured using the + ADC_AnalogWatchdogThresholdsConfig() function. + 3. The Analog watchdog is enabled and configured to enable the check, on one + or more channels, using the ADC_AnalogWatchdogCmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the analog watchdog on single/all regular or + * injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel + * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel + * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel + * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel + * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel + * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels + * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + + /* Clear AWDEN, JAWDEN and AWDSGL bits */ + tmpreg &= CR1_AWDMode_RESET; + + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12-bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12-bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_RESET; + + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} +/** + * @} + */ + +/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) + * and VBAT (Voltage BATtery) management functions + * @brief Temperature Sensor, Vrefint and VBAT management functions + * +@verbatim + =============================================================================== + Temperature Sensor, Vrefint and VBAT management functions + =============================================================================== + + This section provides functions allowing to enable/ disable the internal + connections between the ADC and the Temperature Sensor, the Vrefint and the + Vbat sources. + + A typical configuration to get the Temperature sensor and Vrefint channels + voltages is done following these steps : + 1. Enable the internal connection of Temperature sensor and Vrefint sources + with the ADC channels using ADC_TempSensorVrefintCmd() function. + 2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using + ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions + 3. Get the voltage values, using ADC_GetConversionValue() or + ADC_GetInjectedConversionValue(). + + A typical configuration to get the VBAT channel voltage is done following + these steps : + 1. Enable the internal connection of VBAT source with the ADC channel using + ADC_VBATCmd() function. + 2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or + ADC_InjectedChannelConfig() functions + 3. Get the voltage value, using ADC_GetConversionValue() or + ADC_GetInjectedConversionValue(). + +@endverbatim + * @{ + */ + + +/** + * @brief Enables or disables the temperature sensor and Vrefint channels. + * @param NewState: new state of the temperature sensor and Vrefint channels. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); + } +} + +/** + * @brief Enables or disables the VBAT (Voltage Battery) channel. + * @param NewState: new state of the VBAT channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_VBATCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the VBAT channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_VBATE; + } + else + { + /* Disable the VBAT channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group4 Regular Channels Configuration functions + * @brief Regular Channels Configuration functions + * +@verbatim + =============================================================================== + Regular Channels Configuration functions + =============================================================================== + + This section provides functions allowing to manage the ADC's regular channels, + it is composed of 2 sub sections : + + 1. Configuration and management functions for regular channels: This subsection + provides functions allowing to configure the ADC regular channels : + - Configure the rank in the regular group sequencer for each channel + - Configure the sampling time for each channel + - select the conversion Trigger for regular channels + - select the desired EOC event behavior configuration + - Activate the continuous Mode (*) + - Activate the Discontinuous Mode + Please Note that the following features for regular channels are configurated + using the ADC_Init() function : + - scan mode activation + - continuous mode activation (**) + - External trigger source + - External trigger edge + - number of conversion in the regular channels group sequencer. + + @note (*) and (**) are performing the same configuration + + 2. Get the conversion data: This subsection provides an important function in + the ADC peripheral since it returns the converted data of the current + regular channel. When the Conversion value is read, the EOC Flag is + automatically cleared. + + @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions + results data (in the selected multi mode) can be returned in the same + time using ADC_GetMultiModeConversionValue() function. + + +@endverbatim + * @{ + */ +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @param Rank: The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles + * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles + * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles + * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles + * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles + * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles + * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles + * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); + + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); + + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); + + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/** + * @brief Enables the selected ADC software start conversion of the regular channels. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Enable the selected ADC conversion for regular group */ + ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; +} + +/** + * @brief Gets the selected ADC Software start regular conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + + /* Return the SWSTART bit status */ + return bitstatus; +} + + +/** + * @brief Enables or disables the EOC on each regular channel conversion + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC EOC flag rising + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC EOC rising on each regular channel conversion */ + ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; + } + else + { + /* Disable the selected ADC EOC rising on each regular channel conversion */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); + } +} + +/** + * @brief Enables or disables the ADC continuous conversion mode + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC continuous conversion mode + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC continuous conversion mode */ + ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; + } + else + { + /* Disable the selected ADC continuous conversion mode */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); + } +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular group + * channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Number: specifies the discontinuous mode regular channel count value. + * This number must be between 1 and 8. + * @retval None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_RESET; + + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group channel + * for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode on + * regular group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results + * data in the selected multi mode. + * @param None + * @retval The Data conversion value. + * @note In dual mode, the value returned by this function is as following + * Data[15:0] : these bits contain the regular data of ADC1. + * Data[31:16]: these bits contain the regular data of ADC2. + * @note In triple mode, the value returned by this function is as following + * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. + * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. + */ +uint32_t ADC_GetMultiModeConversionValue(void) +{ + /* Return the multi mode conversion value */ + return (*(__IO uint32_t *) CDR_ADDRESS); +} +/** + * @} + */ + +/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions + * @brief Regular Channels DMA Configuration functions + * +@verbatim + =============================================================================== + Regular Channels DMA Configuration functions + =============================================================================== + + This section provides functions allowing to configure the DMA for ADC regular + channels. + Since converted regular channel values are stored into a unique data register, + it is useful to use DMA for conversion of more than one regular channel. This + avoids the loss of the data already stored in the ADC Data register. + + When the DMA mode is enabled (using the ADC_DMACmd() function), after each + conversion of a regular channel, a DMA request is generated. + + Depending on the "DMA disable selection for Independent ADC mode" + configuration (using the ADC_DMARequestAfterLastTransferCmd() function), + at the end of the last DMA transfer, two possibilities are allowed: + - No new DMA request is issued to the DMA controller (feature DISABLED) + - Requests can continue to be generated (feature ENABLED). + + Depending on the "DMA disable selection for multi ADC mode" configuration + (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), + at the end of the last DMA transfer, two possibilities are allowed: + - No new DMA request is issued to the DMA controller (feature DISABLED) + - Requests can continue to be generated (feature ENABLED). + +@endverbatim + * @{ + */ + + /** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); + } +} + +/** + * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC DMA request after last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; + } + else + { + /* Disable the selected ADC DMA request after last transfer */ + ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); + } +} + +/** + * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode + * @param NewState: new state of the selected ADC DMA request after last transfer. + * This parameter can be: ENABLE or DISABLE. + * @note if Enabled, DMA requests are issued as long as data are converted and + * DMA mode for multi ADC mode (selected using ADC_CommonInit() function + * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is + * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. + * @retval None + */ +void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + ADC->CCR |= (uint32_t)ADC_CCR_DDS; + } + else + { + /* Disable the selected ADC DMA request after last transfer */ + ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); + } +} +/** + * @} + */ + +/** @defgroup ADC_Group6 Injected channels Configuration functions + * @brief Injected channels Configuration functions + * +@verbatim + =============================================================================== + Injected channels Configuration functions + =============================================================================== + + This section provide functions allowing to configure the ADC Injected channels, + it is composed of 2 sub sections : + + 1. Configuration functions for Injected channels: This subsection provides + functions allowing to configure the ADC injected channels : + - Configure the rank in the injected group sequencer for each channel + - Configure the sampling time for each channel + - Activate the Auto injected Mode + - Activate the Discontinuous Mode + - scan mode activation + - External/software trigger source + - External trigger edge + - injected channels sequencer. + + 2. Get the Specified Injected channel conversion data: This subsection + provides an important function in the ADC peripheral since it returns the + converted data of the specific injected channel. + +@endverbatim + * @{ + */ +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @param Rank: The rank in the injected group sequencer. + * This parameter must be between 1 to 4. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles + * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles + * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles + * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles + * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles + * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles + * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles + * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); + /* Clear the old sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Length: The sequencer length. + * This parameter must be a number between 1 to 4. + * @retval None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + + /* Clear the old injected sequence length JL bits */ + tmpreg1 &= JSQR_JL_RESET; + + /* Set the injected sequence length JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @param Offset: the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t *) tmp = (uint32_t)Offset; +} + + /** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected + * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected + * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected + * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected + * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected + * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected + * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected + * @retval None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + + /* Get the old register value */ + tmpreg = ADCx->CR2; + + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_RESET; + + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Configures the ADCx external trigger edge for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge + * to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for + * injected conversion + * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge + * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge + * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising + * and falling edge + * @retval None + */ +void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external trigger edge for injected group */ + tmpreg &= CR2_JEXTEN_RESET; + /* Set the new external trigger edge for injected group */ + tmpreg |= ADC_ExternalTrigInjecConvEdge; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Enables the selected ADC software start conversion of the injected channels. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Enable the selected ADC conversion for injected group */ + ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode on injected + * group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); + } +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @retval The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDR_OFFSET; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} +/** + * @} + */ + +/** @defgroup ADC_Group7 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides functions allowing to configure the ADC Interrupts and + to get the status and clear flags and Interrupts pending bits. + + Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into + 3 groups: + + I. Flags and Interrupts for ADC regular channels + ================================================= + Flags : + ---------- + 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost + + 2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending + on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of: + ==> a regular CHANNEL conversion + ==> sequence of regular GROUP conversions . + + 3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL + conversion starts. + + Interrupts : + ------------ + 1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event. + 2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of + conversion event. + + + II. Flags and Interrupts for ADC Injected channels + ================================================= + Flags : + ---------- + 1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at + the end of injected GROUP conversion + + 2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when + injected GROUP conversion starts. + + Interrupts : + ------------ + 1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of + conversion event. + + III. General Flags and Interrupts for the ADC + ================================================= + Flags : + ---------- + 1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage + crosses the programmed thresholds values. + + Interrupts : + ------------ + 1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. + + + The user should identify which mode will be used in his application to manage + the ADC controller events: Polling mode or Interrupt mode. + + In the Polling Mode it is advised to use the following functions: + - ADC_GetFlagStatus() : to check if flags events occur. + - ADC_ClearFlag() : to clear the flags events. + + In the Interrupt Mode it is advised to use the following functions: + - ADC_ITConfig() : to enable or disable the interrupt source. + - ADC_GetITStatus() : to check if Interrupt occurs. + - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). +@endverbatim + * @{ + */ +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt enable + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint32_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + itmask = (uint32_t)0x01 << itmask; + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @arg ADC_FLAG_OVR: Overrun flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @arg ADC_FLAG_OVR: Overrun flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + + /* Clear the selected ADC flags */ + ADCx->SR = ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt mask + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; + + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @arg ADC_IT_OVR: Overrun interrupt mask + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(uint32_t)itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c new file mode 100644 index 000000000..5198acee5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c @@ -0,0 +1,1704 @@ +/** + ****************************************************************************** + * @file stm32f2xx_can.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Controller area network (CAN) peripheral: + * - Initialization and Configuration + * - CAN Frames Transmission + * - CAN Frames Reception + * - Operation modes switch + * - Error management + * - Interrupts and flags + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + + * 1. Enable the CAN controller interface clock using + * RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 + * and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 + * @note In case you are using CAN2 only, you have to enable the CAN1 clock. + * + * 2. CAN pins configuration + * - Enable the clock for the CAN GPIOs using the following function: + * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + * - Connect the involved CAN pins to AF9 using the following function + * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); + * - Configure these CAN pins in alternate function mode by calling + * the function GPIO_Init(); + * + * 3. Initialise and configure the CAN using CAN_Init() and + * CAN_FilterInit() functions. + * + * 4. Transmit the desired CAN frame using CAN_Transmit() function. + * + * 5. Check the transmission of a CAN frame using CAN_TransmitStatus() + * function. + * + * 6. Cancel the transmission of a CAN frame using CAN_CancelTransmit() + * function. + * + * 7. Receive a CAN frame using CAN_Recieve() function. + * + * 8. Release the receive FIFOs using CAN_FIFORelease() function. + * + * 9. Return the number of pending received frames using + * CAN_MessagePending() function. + * + * 10. To control CAN events you can use one of the following two methods: + * - Check on CAN flags using the CAN_GetFlagStatus() function. + * - Use CAN interrupts through the function CAN_ITConfig() at + * initialization phase and CAN_GetITStatus() function into + * interrupt routines to check if the event has occurred or not. + * After checking on a flag you should clear it using CAN_ClearFlag() + * function. And after checking on an interrupt event you should + * clear it using CAN_ClearITPendingBit() function. + * + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_can.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CAN + * @brief CAN driver modules + * @{ + */ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* CAN Master Control Register bits */ +#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSR register */ +#define CAN_FLAGS_TSR ((uint32_t)0x08000000) +/* Flags in RF1R register */ +#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) +/* Flags in RF0R register */ +#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) +/* Flags in MSR register */ +#define CAN_FLAGS_MSR ((uint32_t)0x01000000) +/* Flags in ESR register */ +#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/** @defgroup CAN_Private_Functions + * @{ + */ + +/** @defgroup CAN_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + This section provides functions allowing to + - Initialize the CAN peripherals : Prescaler, operating mode, the maximum number + of time quanta to perform resynchronization, the number of time quanta in + Bit Segment 1 and 2 and many other modes. + Refer to @ref CAN_InitTypeDef for more details. + - Configures the CAN reception filter. + - Select the start bank filter for slave CAN. + - Enables or disables the Debug Freeze mode for CAN + - Enables or disables the CAN Time Trigger Operation communication mode + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval None. + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if (CANx == CAN1) + { + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + /* Enable CAN2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains + * the configuration information for the CAN peripheral. + * @retval Constant indicates initialization succeed which will be + * CAN_InitStatus_Failed or CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* Exit from sleep mode */ + CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + CANx->MCR |= CAN_MCR_INRQ ; + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* Check acknowledge */ + if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->MCR |= CAN_MCR_TTCM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->MCR |= CAN_MCR_ABOM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->MCR |= CAN_MCR_AWUM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->MCR |= CAN_MCR_NART; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->MCR |= CAN_MCR_RFLM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->MCR |= CAN_MCR_TXFP; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + + /* Request leave initialisation */ + CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Wait the acknowledge */ + wait_ack = 0; + + while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that + * contains the configuration information. + * @retval None + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FA1R |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Fills each CAN_InitStruct member with its default value. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. + * @retval None + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/** + * @brief Select the start bank filter for slave CAN. + * @param CAN_BankNumber: Select the start slave bank filter from 1..27. + * @retval None + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); + + /* Enter Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Select the start slave bank */ + CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; + + /* Leave Initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFOs can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; + } +} + + +/** + * @brief Enables or disables the CAN Time TriggerOperation communication mode. + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. + * When enabled, Time stamp (TIME[15:0]) value is sent in the last two + * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] + * in data byte 7. + * @retval None + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCR |= CAN_MCR_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); + } +} +/** + * @} + */ + + +/** @defgroup CAN_Group2 CAN Frames Transmission functions + * @brief CAN Frames Transmission functions + * +@verbatim + =============================================================================== + CAN Frames Transmission functions + =============================================================================== + This section provides functions allowing to + - Initiate and transmit a CAN frame message (if there is an empty mailbox). + - Check the transmission status of a CAN Frame + - Cancel a transmit request + +@endverbatim + * @{ + */ + +/** + * @brief Initiates and transmits a CAN frame message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. + * @retval The number of the mailbox that is used for transmission or + * CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission status of a CAN Frame. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for transmission. + * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, + * CAN_TxStatus_Failed in an other case. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); + break; + case (CAN_TXMAILBOX_1): + state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); + break; + case (CAN_TXMAILBOX_2): + state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); + break; + default: + state = CAN_TxStatus_Failed; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): state = CAN_TxStatus_Pending; + break; + /* transmit failed */ + case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; + break; + /* transmit succeeded */ + case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; + break; + default: state = CAN_TxStatus_Failed; + break; + } + return (uint8_t) state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param Mailbox: Mailbox number. + * @retval None + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; + break; + case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; + break; + case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; + break; + default: + break; + } +} +/** + * @} + */ + + +/** @defgroup CAN_Group3 CAN Frames Reception functions + * @brief CAN Frames Reception functions + * +@verbatim + =============================================================================== + CAN Frames Reception functions + =============================================================================== + This section provides functions allowing to + - Receive a correct CAN frame + - Release a specified receive FIFO (2 FIFOs are available) + - Return the number of the pending received CAN frames + +@endverbatim + * @{ + */ + +/** + * @brief Receives a correct CAN frame. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive frame which contains CAN Id, + * CAN DLC, CAN data and FMI number. + * @retval None + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Releases the specified receive FIFO. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Returns the number of pending received messages. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval NbMessage : which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} +/** + * @} + */ + + +/** @defgroup CAN_Group4 CAN Operation modes functions + * @brief CAN Operation modes functions + * +@verbatim + =============================================================================== + CAN Operation modes functions + =============================================================================== + This section provides functions allowing to select the CAN Operation modes + - sleep mode + - normal mode + - initialization mode + +@endverbatim + * @{ + */ + + +/** + * @brief Selects the CAN Operation mode. + * @param CAN_OperatingMode: CAN Operating Mode. + * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. + * @retval status of the requested mode which can be + * - CAN_ModeStatus_Failed: CAN failed entering the specific mode + * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INAK_TIMEOUT; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + /* Request initialisation */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) + { + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + /* Request Sleep mode */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t) status; +} + +/** + * @brief Enters the Sleep (low power) mode. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) + { + /* Sleep mode not entered */ + sleepstatus = CAN_Sleep_Ok; + } + /* return sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode . + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Sleep mode status */ + while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) + { + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WakeUp_Ok; + } + /* return wakeup status */ + return (uint8_t)wakeupstatus; +} +/** + * @} + */ + + +/** @defgroup CAN_Group5 CAN Bus Error management functions + * @brief CAN Bus Error management functions + * +@verbatim + =============================================================================== + CAN Bus Error management functions + =============================================================================== + This section provides functions allowing to + - Return the CANx's last error code (LEC) + - Return the CANx Receive Error Counter (REC) + - Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). + + @note If TEC is greater than 255, The CAN is in bus-off state. + @note if REC or TEC are greater than 96, an Error warning flag occurs. + @note if REC or TEC are greater than 127, an Error Passive Flag occurs. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval Error code: + * - CAN_ERRORCODE_NoErr: No Error + * - CAN_ERRORCODE_StuffErr: Stuff Error + * - CAN_ERRORCODE_FormErr: Form Error + * - CAN_ERRORCODE_ACKErr : Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error + * - CAN_ERRORCODE_CRCErr: CRC Error + * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); + + /* Return the error code*/ + return errorcode; +} + +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} +/** + * @} + */ + +/** @defgroup CAN_Group6 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides functions allowing to configure the CAN Interrupts and + to get the status and clear flags and Interrupts pending bits. + + The CAN provides 14 Interrupts sources and 15 Flags: + + =============== + Flags : + =============== + The 15 flags can be divided on 4 groups: + + A. Transmit Flags + ----------------------- + CAN_FLAG_RQCP0, + CAN_FLAG_RQCP1, + CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags + Set when when the last request (transmit or abort) has + been performed. + + B. Receive Flags + ----------------------- + + CAN_FLAG_FMP0, + CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags + set to signal that messages are pending in the receive + FIFO. + These Flags are cleared only by hardware. + + CAN_FLAG_FF0, + CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags + set when three messages are stored in the selected + FIFO. + + CAN_FLAG_FOV0 + CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags + set when a new message has been received and passed + the filter while the FIFO was full. + + C. Operating Mode Flags + ----------------------- + CAN_FLAG_WKU : Wake up Flag + set to signal that a SOF bit has been detected while + the CAN hardware was in Sleep mode. + + CAN_FLAG_SLAK : Sleep acknowledge Flag + Set to signal that the CAN has entered Sleep Mode. + + D. Error Flags + ----------------------- + CAN_FLAG_EWG : Error Warning Flag + Set when the warning limit has been reached (Receive + Error Counter or Transmit Error Counter greater than 96). + This Flag is cleared only by hardware. + + CAN_FLAG_EPV : Error Passive Flag + Set when the Error Passive limit has been reached + (Receive Error Counter or Transmit Error Counter + greater than 127). + This Flag is cleared only by hardware. + + CAN_FLAG_BOF : Bus-Off Flag + set when CAN enters the bus-off state. The bus-off + state is entered on TEC overflow, greater than 255. + This Flag is cleared only by hardware. + + CAN_FLAG_LEC : Last error code Flag + set If a message has been transferred (reception or + transmission) with error, and the error code is hold. + + =============== + Interrupts : + =============== + The 14 interrupts can be divided on 4 groups: + + A. Transmit interrupt + ----------------------- + CAN_IT_TME : Transmit mailbox empty Interrupt + if enabled, this interrupt source is pending when + no transmit request are pending for Tx mailboxes. + + B. Receive Interrupts + ----------------------- + CAN_IT_FMP0, + CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts + if enabled, these interrupt sources are pending when + messages are pending in the receive FIFO. + The corresponding interrupt pending bits are cleared + only by hardware. + + CAN_IT_FF0, + CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts + if enabled, these interrupt sources are pending when + three messages are stored in the selected FIFO. + + CAN_IT_FOV0, + CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts + if enabled, these interrupt sources are pending when + a new message has been received and passed the filter + while the FIFO was full. + + C. Operating Mode Interrupts + ------------------------------- + CAN_IT_WKU : Wake-up Interrupt + if enabled, this interrupt source is pending when + a SOF bit has been detected while the CAN hardware was + in Sleep mode. + + CAN_IT_SLK : Sleep acknowledge Interrupt + if enabled, this interrupt source is pending when + the CAN has entered Sleep Mode. + + D. Error Interrupts + ----------------------- + CAN_IT_EWG : Error warning Interrupt + if enabled, this interrupt source is pending when + the warning limit has been reached (Receive Error + Counter or Transmit Error Counter=96). + + CAN_IT_EPV : Error passive Interrupt + if enabled, this interrupt source is pending when + the Error Passive limit has been reached (Receive + Error Counter or Transmit Error Counter>127). + + CAN_IT_BOF : Bus-off Interrupt + if enabled, this interrupt source is pending when + CAN enters the bus-off state. The bus-off state is + entered on TEC overflow, greater than 255. + This Flag is cleared only by hardware. + + CAN_IT_LEC : Last error code Interrupt + if enabled, this interrupt source is pending when + a message has been transferred (reception or + transmission) with error, and the error code is hold. + + CAN_IT_ERR : Error Interrupt + if enabled, this interrupt source is pending when + an error condition is pending. + + + Managing the CAN controller events : + ------------------------------------ + The user should identify which mode will be used in his application to manage + the CAN controller events: Polling mode or Interrupt mode. + + 1. In the Polling Mode it is advised to use the following functions: + - CAN_GetFlagStatus() : to check if flags events occur. + - CAN_ClearFlag() : to clear the flags events. + + + + 2. In the Interrupt Mode it is advised to use the following functions: + - CAN_ITConfig() : to enable or disable the interrupt source. + - CAN_GetITStatus() : to check if Interrupt occurs. + - CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). + @note This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts + pending bits since there are cleared only by hardware. + +@endverbatim + * @{ + */ +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->IER &= ~CAN_IT; + } +} +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag + * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag + * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @arg CAN_FLAG_LEC: Last error code Flag + * @retval The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + + if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag + * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag + * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_LEC: Last error code Flag + * @retval None + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ + { + /* Clear the selected CAN flags */ + CANx->ESR = (uint32_t)RESET; + } + else /* MSR or TSR or RF0R or RF1R */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF0R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF1R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSR = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSR = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @retval The current state of CAN_IT (SET or RESET). + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + + /* check the interrupt enable bit */ + if((CANx->IER & CAN_IT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_IT) + { + case CAN_IT_TME: + /* Check CAN_TSR_RQCPx bits */ + itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); + break; + case CAN_IT_FMP0: + /* Check CAN_RF0R_FMP0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); + break; + case CAN_IT_FF0: + /* Check CAN_RF0R_FULL0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); + break; + case CAN_IT_FOV0: + /* Check CAN_RF0R_FOVR0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); + break; + case CAN_IT_FMP1: + /* Check CAN_RF1R_FMP1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); + break; + case CAN_IT_FF1: + /* Check CAN_RF1R_FULL1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); + break; + case CAN_IT_FOV1: + /* Check CAN_RF1R_FOVR1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); + break; + case CAN_IT_WKU: + /* Check CAN_MSR_WKUI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); + break; + case CAN_IT_SLK: + /* Check CAN_MSR_SLAKI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); + break; + case CAN_IT_EWG: + /* Check CAN_ESR_EWGF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); + break; + case CAN_IT_EPV: + /* Check CAN_ESR_EPVF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); + break; + case CAN_IT_BOF: + /* Check CAN_ESR_BOFF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); + break; + case CAN_IT_LEC: + /* Check CAN_ESR_LEC bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); + break; + case CAN_IT_ERR: + /* Check CAN_MSR_ERRI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); + break; + default: + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_IT status */ + return itstatus; +} + +/** + * @brief Clears the CANx's interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty Interrupt + * @arg CAN_IT_FF0: FIFO 0 full Interrupt + * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt + * @arg CAN_IT_FF1: FIFO 1 full Interrupt + * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt + * @arg CAN_IT_WKU: Wake-up Interrupt + * @arg CAN_IT_SLK: Sleep acknowledge Interrupt + * @arg CAN_IT_EWG: Error warning Interrupt + * @arg CAN_IT_EPV: Error passive Interrupt + * @arg CAN_IT_BOF: Bus-off Interrupt + * @arg CAN_IT_LEC: Last error code Interrupt + * @arg CAN_IT_ERR: Error Interrupt + * @retval None + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_TME: + /* Clear CAN_TSR_RQCPx (rc_w1)*/ + CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; + break; + case CAN_IT_FF0: + /* Clear CAN_RF0R_FULL0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FULL0; + break; + case CAN_IT_FOV0: + /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FOVR0; + break; + case CAN_IT_FF1: + /* Clear CAN_RF1R_FULL1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FULL1; + break; + case CAN_IT_FOV1: + /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FOVR1; + break; + case CAN_IT_WKU: + /* Clear CAN_MSR_WKUI (rc_w1)*/ + CANx->MSR = CAN_MSR_WKUI; + break; + case CAN_IT_SLK: + /* Clear CAN_MSR_SLAKI (rc_w1)*/ + CANx->MSR = CAN_MSR_SLAKI; + break; + case CAN_IT_EWG: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_EPV: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_BOF: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ + break; + case CAN_IT_LEC: + /* Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + break; + case CAN_IT_ERR: + /*Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ + break; + default: + break; + } +} + /** + * @} + */ + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg: specifies the CAN interrupt register to check. + * @param It_Bit: specifies the interrupt source bit to check. + * @retval The new state of the CAN Interrupt (SET or RESET). + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c new file mode 100644 index 000000000..450875963 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c @@ -0,0 +1,133 @@ +/** + ****************************************************************************** + * @file stm32f2xx_crc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides all the CRC firmware functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_crc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DR). + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CRC_CR_RESET; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c new file mode 100644 index 000000000..d78bf55a8 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c @@ -0,0 +1,856 @@ +/** + ****************************************************************************** + * @file stm32f2xx_cryp.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Cryptographic processor (CRYP) peripheral: + * - Initialization and Configuration functions + * - Data treatment functions + * - Context swapping functions + * - DMA interface function + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable the CRYP controller clock using + * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. + * + * 2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if + * needed CRYP_IVInit(). + * + * 3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. + * + * 4. Enable the CRYP controller using the CRYP_Cmd() function. + * + * 5. If using DMA for Data input and output transfer, + * Activate the needed DMA Requests using CRYP_DMACmd() function + + * 6. If DMA is not used for data transfer, use CRYP_DataIn() and + * CRYP_DataOut() functions to enter data to IN FIFO and get result + * from OUT FIFO. + * + * 7. To control CRYP events you can use one of the following + * two methods: + * - Check on CRYP flags using the CRYP_GetFlagStatus() function. + * - Use CRYP interrupts through the function CRYP_ITConfig() at + * initialization phase and CRYP_GetITStatus() function into + * interrupt routines in processing phase. + * + * 8. Save and restore Cryptographic processor context using + * CRYP_SaveContext() and CRYP_RestoreContext() functions. + * + * + * =================================================================== + * Procedure to perform an encryption or a decryption + * =================================================================== + * + * Initialization + * =============== + * 1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and + * CRYP_IVInit functions: + * - Configure the key size (128-, 192- or 256-bit, in the AES only) + * - Enter the symmetric key + * - Configure the data type + * - In case of decryption in AES-ECB or AES-CBC, you must prepare + * the key: configure the key preparation mode. Then Enable the CRYP + * peripheral using CRYP_Cmd() function: the BUSY flag is set. + * Wait until BUSY flag is reset : the key is prepared for decryption + * - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the + * AES in ECB/CBC/CTR) + * - Configure the direction (encryption/decryption). + * - Write the initialization vectors (in CBC or CTR modes only) + * + * 2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function + * + * + * Basic Processing mode (polling mode) + * ==================================== + * 1. Enable the cryptographic processor using CRYP_Cmd() function. + * + * 2. Write the first blocks in the input FIFO (2 to 8 words) using + * CRYP_DataIn() function. + * + * 3. Repeat the following sequence until the complete message has been + * processed: + * + * a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() + * function), then read the OUT-FIFO using CRYP_DataOut() function + * (1 block or until the FIFO is empty) + * + * b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() + * function then write the IN FIFO using CRYP_DataIn() function + * (1 block or until the FIFO is full) + * + * 4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and + * both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is + * reset). You can disable the peripheral using CRYP_Cmd() function. + * + * Interrupts Processing mode + * =========================== + * In this mode, Processing is done when the data are transferred by the + * CPU during interrupts. + * + * 1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using + * CRYP_ITConfig() function. + * + * 2. Enable the cryptographic processor using CRYP_Cmd() function. + * + * 3. In the CRYP_IT_INI interrupt handler : load the input message into the + * IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a + * time, or load data until the IN FIFO is full. When the last word of + * the message has been entered into the IN FIFO, disable the CRYP_IT_INI + * interrupt (using CRYP_ITConfig() function). + * + * 4. In the CRYP_IT_OUTI interrupt handler : read the output message from + * the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or + * 4 words) at a time or read data until the FIFO is empty. + * When the last word has been read, INIM=0, BUSY=0 and both FIFOs are + * empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). + * You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() + * function) and you can disable the peripheral using CRYP_Cmd() function. + * + * DMA Processing mode + * ==================== + * In this mode, Processing is done when the DMA is used to transfer the + * data from/to the memory. + * + * 1. Configure the DMA controller to transfer the input data from the + * memory using DMA_Init() function. + * The transfer length is the length of the message. + * As message padding is not managed by the peripheral, the message + * length must be an entire number of blocks. The data are transferred + * in burst mode. The burst length is 4 words in the AES and 2 or 4 + * words in the DES/TDES. The DMA should be configured to set an + * interrupt on transfer completion of the output data to indicate that + * the processing is finished. + * Refer to DMA peripheral driver for more details. + * + * 2. Enable the cryptographic processor using CRYP_Cmd() function. + * Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT + * using CRYP_DMACmd() function. + * + * 3. All the transfers and processing are managed by the DMA and the + * cryptographic processor. The DMA transfer complete interrupt indicates + * that the processing is complete. Both FIFOs are normally empty and + * CRYP_FLAG_BUSY flag is reset. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define FLAG_MASK ((uint8_t)0x20) +#define MAX_TIMEOUT ((uint16_t)0xFFFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + This section provides functions allowing to + - Initialize the cryptographic Processor using CRYP_Init() function + - Encrypt or Decrypt + - mode : TDES-ECB, TDES-CBC, + DES-ECB, DES-CBC, + AES-ECB, AES-CBC, AES-CTR, AES-Key + - DataType : 32-bit data, 16-bit data, bit data or bit-string + - Key Size (only in AES modes) + - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function + - Configure the Initialization Vectors(IV) for CBC and CTR modes using + CRYP_IVInit() function. + - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. + - Enable or disable the CRYP Processor using CRYP_Cmd() function + + +@endverbatim + * @{ + */ +/** + * @brief Deinitializes the CRYP peripheral registers to their default reset values + * @param None + * @retval None + */ +void CRYP_DeInit(void) +{ + /* Enable CRYP reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE); + + /* Release CRYP from reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE); +} + +/** + * @brief Initializes the CRYP peripheral according to the specified parameters + * in the CRYP_InitStruct. + * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains + * the configuration information for the CRYP peripheral. + * @retval None + */ +void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode)); + assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType)); + assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir)); + + /* Select Algorithm mode*/ + CRYP->CR &= ~CRYP_CR_ALGOMODE; + CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode; + + /* Select dataType */ + CRYP->CR &= ~CRYP_CR_DATATYPE; + CRYP->CR |= CRYP_InitStruct->CRYP_DataType; + + /* select Key size (used only with AES algorithm) */ + if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) || + (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) || + (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) || + (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key)) + { + assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); + CRYP->CR &= ~CRYP_CR_KEYSIZE; + CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be + configured once the key has + been prepared */ + } + + /* Select data Direction */ + CRYP->CR &= ~CRYP_CR_ALGODIR; + CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir; +} + +/** + * @brief Fills each CRYP_InitStruct member with its default value. + * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct) +{ + /* Initialize the CRYP_AlgoDir member */ + CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + + /* initialize the CRYP_AlgoMode member */ + CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; + + /* initialize the CRYP_DataType member */ + CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b; + + /* Initialize the CRYP_KeySize member */ + CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b; +} + +/** + * @brief Initializes the CRYP Keys according to the specified parameters in + * the CRYP_KeyInitStruct. + * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that + * contains the configuration information for the CRYP Keys. + * @retval None + */ +void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) +{ + /* Key Initialisation */ + CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; + CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; + CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; + CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; + CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; + CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; + CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; + CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; +} + +/** + * @brief Fills each CRYP_KeyInitStruct member with its default value. + * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure + * which will be initialized. + * @retval None + */ +void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) +{ + CRYP_KeyInitStruct->CRYP_Key0Left = 0; + CRYP_KeyInitStruct->CRYP_Key0Right = 0; + CRYP_KeyInitStruct->CRYP_Key1Left = 0; + CRYP_KeyInitStruct->CRYP_Key1Right = 0; + CRYP_KeyInitStruct->CRYP_Key2Left = 0; + CRYP_KeyInitStruct->CRYP_Key2Right = 0; + CRYP_KeyInitStruct->CRYP_Key3Left = 0; + CRYP_KeyInitStruct->CRYP_Key3Right = 0; +} +/** + * @brief Initializes the CRYP Initialization Vectors(IV) according to the + * specified parameters in the CRYP_IVInitStruct. + * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains + * the configuration information for the CRYP Initialization Vectors(IV). + * @retval None + */ +void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) +{ + CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left; + CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right; + CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left; + CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right; +} + +/** + * @brief Fills each CRYP_IVInitStruct member with its default value. + * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization + * Vectors(IV) structure which will be initialized. + * @retval None + */ +void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) +{ + CRYP_IVInitStruct->CRYP_IV0Left = 0; + CRYP_IVInitStruct->CRYP_IV0Right = 0; + CRYP_IVInitStruct->CRYP_IV1Left = 0; + CRYP_IVInitStruct->CRYP_IV1Right = 0; +} + +/** + * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the + * FIFOs are reset) + * @note The FIFOs must be flushed only when BUSY flag is reset. + * @param None + * @retval None + */ +void CRYP_FIFOFlush(void) +{ + /* Reset the read and write pointers of the FIFOs */ + CRYP->CR |= CRYP_CR_FFLUSH; +} + +/** + * @brief Enables or disables the CRYP peripheral. + * @param NewState: new state of the CRYP peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRYP_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Cryptographic processor */ + CRYP->CR |= CRYP_CR_CRYPEN; + } + else + { + /* Disable the Cryptographic processor */ + CRYP->CR &= ~CRYP_CR_CRYPEN; + } +} +/** + * @} + */ + +/** @defgroup CRYP_Group2 CRYP Data processing functions + * @brief CRYP Data processing functions + * +@verbatim + =============================================================================== + CRYP Data processing functions + =============================================================================== + This section provides functions allowing the encryption and decryption + operations: + - Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. + - Get the data result from the OUT FIFO : using CRYP_DataOut() function. + +@endverbatim + * @{ + */ + +/** + * @brief Writes data in the Data Input register (DIN). + * @note After the DIN register has been read once or several times, + * the FIFO must be flushed (using CRYP_FIFOFlush() function). + * @param Data: data to write in Data Input register + * @retval None + */ +void CRYP_DataIn(uint32_t Data) +{ + CRYP->DR = Data; +} + +/** + * @brief Returns the last data entered into the output FIFO. + * @param None + * @retval Last data entered into the output FIFO. + */ +uint32_t CRYP_DataOut(void) +{ + return CRYP->DOUT; +} +/** + * @} + */ + +/** @defgroup CRYP_Group3 Context swapping functions + * @brief Context swapping functions + * +@verbatim + =============================================================================== + Context swapping functions + =============================================================================== + + This section provides functions allowing to save and store CRYP Context + + It is possible to interrupt an encryption/ decryption/ key generation process + to perform another processing with a higher priority, and to complete the + interrupted process later on, when the higher-priority task is complete. To do + so, the context of the interrupted task must be saved from the CRYP registers + to memory, and then be restored from memory to the CRYP registers. + + 1. To save the current context, use CRYP_SaveContext() function + 2. To restore the saved context, use CRYP_RestoreContext() function + + +@endverbatim + * @{ + */ + +/** + * @brief Saves the CRYP peripheral Context. + * @note This function stops DMA transfer before to save the context. After + * restoring the context, you have to enable the DMA again (if the DMA + * was previously used). + * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains + * the repository for current context. + * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that + * contains the configuration information for the CRYP Keys. + * @retval None + */ +ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, + CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) +{ + __IO uint32_t timeout = 0; + uint32_t ckeckmask = 0, bitstatus; + ErrorStatus status = ERROR; + + /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */ + CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN; + + /* Wait until both the IN and OUT FIFOs are empty + (IFEM=1 and OFNE=0 in the CRYP_SR register) and the + BUSY bit is cleared. */ + + if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */ + { + ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ; + } + else /* AES or DES */ + { + ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE; + } + + do + { + bitstatus = CRYP->SR & ckeckmask; + timeout++; + } + while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM)); + + if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM) + { + status = ERROR; + } + else + { + /* Stop DMA transfers on the OUT FIFO by + - writing the DOEN bit to 0 in the CRYP_DMACR register + - and clear the CRYPEN bit. */ + + CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; + CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; + + /* Save the current configuration (bits [9:2] in the CRYP_CR register) */ + CRYP_ContextSave->CR_bits9to2 = CRYP->CR & (CRYP_CR_KEYSIZE | + CRYP_CR_DATATYPE | + CRYP_CR_ALGOMODE | + CRYP_CR_ALGODIR); + + /* and, if not in ECB mode, the initialization vectors. */ + CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; + CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR; + CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR; + CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR; + + /* save The key value */ + CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; + CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; + CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; + CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; + CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; + CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; + CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; + CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; + + /* When needed, save the DMA status (pointers for IN and OUT messages, + number of remaining bytes, etc.) */ + + status = SUCCESS; + } + + return status; +} + +/** + * @brief Restores the CRYP peripheral Context. + * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function, + * after restoring the context, you have to enable the DMA again (if the + * DMA was previously used). + * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains + * the repository for saved context. + * @note The data that were saved during context saving must be rewrited into + * the IN FIFO. + * @retval None + */ +void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) +{ + + /* Configure the processor with the saved configuration */ + CRYP->CR = CRYP_ContextRestore->CR_bits9to2; + + /* restore The key value */ + CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; + CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR; + CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR; + CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR; + CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR; + CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR; + CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR; + CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR; + + /* and the initialization vectors. */ + CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR; + CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR; + CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; + CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; + + /* Enable the cryptographic processor */ + CRYP->CR |= CRYP_CR_CRYPEN; +} +/** + * @} + */ + +/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function + * @brief CRYP's DMA interface Configuration function + * +@verbatim + =============================================================================== + CRYP's DMA interface Configuration function + =============================================================================== + + This section provides functions allowing to configure the DMA interface for + CRYP data input and output transfer. + + When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be + transferred: + - From memory to the CRYP IN FIFO using the DMA peripheral by enabling + the CRYP_DMAReq_DataIN request. + - From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling + the CRYP_DMAReq_DataOUT request. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the CRYP DMA interface. + * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer + * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer + * @param NewState: new state of the selected CRYP DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CRYP DMA request */ + CRYP->DMACR |= CRYP_DMAReq; + } + else + { + /* Disable the selected CRYP DMA request */ + CRYP->DMACR &= (uint8_t)~CRYP_DMAReq; + } +} +/** + * @} + */ + +/** @defgroup CRYP_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides functions allowing to configure the CRYP Interrupts and + to get the status and Interrupts pending bits. + + The CRYP provides 2 Interrupts sources and 7 Flags: + + Flags : + ------- + + 1. CRYP_FLAG_IFEM : Set when Input FIFO is empty. + This Flag is cleared only by hardware. + + 2. CRYP_FLAG_IFNF : Set when Input FIFO is not full. + This Flag is cleared only by hardware. + + + 3. CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending + it gives the raw interrupt state prior to masking + of the input FIFO service interrupt. + This Flag is cleared only by hardware. + + 4. CRYP_FLAG_OFNE : Set when Output FIFO not empty. + This Flag is cleared only by hardware. + + 5. CRYP_FLAG_OFFU : Set when Output FIFO is full. + This Flag is cleared only by hardware. + + 6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending + it gives the raw interrupt state prior to masking + of the output FIFO service interrupt. + This Flag is cleared only by hardware. + + 7. CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a + block of data or a key preparation (for AES + decryption). + This Flag is cleared only by hardware. + To clear it, the CRYP core must be disabled and the + last processing has completed. + + Interrupts : + ------------ + + 1. CRYP_IT_INI : The input FIFO service interrupt is asserted when there + are less than 4 words in the input FIFO. + This interrupt is associated to CRYP_FLAG_INRIS flag. + + @note This interrupt is cleared by performing write operations + to the input FIFO until it holds 4 or more words. The + input FIFO service interrupt INMIS is enabled with the + CRYP enable bit. Consequently, when CRYP is disabled, the + INMIS signal is low even if the input FIFO is empty. + + + + 2. CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there + is one or more (32-bit word) data items in the output FIFO. + This interrupt is associated to CRYP_FLAG_OUTRIS flag. + + @note This interrupt is cleared by reading data from the output + FIFO until there is no valid (32-bit) word left (that is, + the interrupt follows the state of the OFNE (output FIFO + not empty) flag). + + + Managing the CRYP controller events : + ------------------------------------ + The user should identify which mode will be used in his application to manage + the CRYP controller events: Polling mode or Interrupt mode. + + 1. In the Polling Mode it is advised to use the following functions: + - CRYP_GetFlagStatus() : to check if flags events occur. + + @note The CRYPT flags do not need to be cleared since they are cleared as + soon as the associated event are reset. + + + 2. In the Interrupt Mode it is advised to use the following functions: + - CRYP_ITConfig() : to enable or disable the interrupt source. + - CRYP_GetITStatus() : to check if Interrupt occurs. + + @note The CRYPT interrupts have no pending bits, the interrupt is cleared as + soon as the associated event is reset. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified CRYP interrupts. + * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CRYP_IT_INI: Input FIFO interrupt + * @arg CRYP_IT_OUTI: Output FIFO interrupt + * @param NewState: new state of the specified CRYP interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CRYP_CONFIG_IT(CRYP_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CRYP interrupt */ + CRYP->IMSCR |= CRYP_IT; + } + else + { + /* Disable the selected CRYP interrupt */ + CRYP->IMSCR &= (uint8_t)~CRYP_IT; + } +} + +/** + * @brief Checks whether the specified CRYP interrupt has occurred or not. + * @note This function checks the status of the masked interrupt (i.e the + * interrupt should be previously enabled). + * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check. + * This parameter can be one of the following values: + * @arg CRYP_IT_INI: Input FIFO interrupt + * @arg CRYP_IT_OUTI: Output FIFO interrupt + * @retval The new state of CRYP_IT (SET or RESET). + */ +ITStatus CRYP_GetITStatus(uint8_t CRYP_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_CRYP_GET_IT(CRYP_IT)); + + /* Check the status of the specified CRYP interrupt */ + if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET) + { + /* CRYP_IT is set */ + bitstatus = SET; + } + else + { + /* CRYP_IT is reset */ + bitstatus = RESET; + } + /* Return the CRYP_IT status */ + return bitstatus; +} + +/** + * @brief Checks whether the specified CRYP flag is set or not. + * @param CRYP_FLAG: specifies the CRYP flag to check. + * This parameter can be one of the following values: + * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag. + * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag. + * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag. + * @arg CRYP_FLAG_OFFU: Output FIFO Full flag. + * @arg CRYP_FLAG_BUSY: Busy flag. + * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag. + * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag. + * @retval The new state of CRYP_FLAG (SET or RESET). + */ +FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tempreg = 0; + + /* Check the parameters */ + assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG)); + + /* check if the FLAG is in RISR register */ + if ((CRYP_FLAG & FLAG_MASK) != 0x00) + { + tempreg = CRYP->RISR; + } + else /* The FLAG is in SR register */ + { + tempreg = CRYP->SR; + } + + + /* Check the status of the specified CRYP flag */ + if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET) + { + /* CRYP_FLAG is set */ + bitstatus = SET; + } + else + { + /* CRYP_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the CRYP_FLAG status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c new file mode 100644 index 000000000..25520e8f8 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c @@ -0,0 +1,644 @@ +/** + ****************************************************************************** + * @file stm32f2xx_cryp_aes.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides high level functions to encrypt and decrypt an + * input message using AES in ECB/CBC/CTR modes. + * It uses the stm32f2xx_cryp.c/.h drivers to access the STM32F2xx CRYP + * peripheral. + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable The CRYP controller clock using + * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. + * + * 2. Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() + * function. + * + * 3. Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() + * function. + * + * 4. Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() + * function. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_cryp.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group6 High Level AES functions + * @brief High Level AES functions + * +@verbatim + =============================================================================== + High Level AES functions + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Encrypt and decrypt using AES in ECB Mode + * @param Mode: encryption or decryption Mode. + * This parameter can be one of the following values: + * @arg MODE_ENCRYPT: Encryption + * @arg MODE_DECRYPT: Decryption + * @param Key: Key used for AES algorithm. + * @param Keysize: length of the Key, must be a 128, 192 or 256. + * @param Input: pointer to the Input buffer. + * @param Ilength: length of the Input buffer, must be a multiple of 16. + * @param Output: pointer to the returned buffer. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Operation done + * - ERROR: Operation failed + */ +ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize, + uint8_t* Input, uint32_t Ilength, uint8_t* Output) +{ + CRYP_InitTypeDef AES_CRYP_InitStructure; + CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t keyaddr = (uint32_t)Key; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + uint32_t i = 0; + + /* Crypto structures initialisation*/ + CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); + + switch(Keysize) + { + case 128: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + case 192: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; + AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + case 256: + AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; + AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + break; + default: + break; + } + + /*------------------ AES Decryption ------------------*/ + if(Mode == MODE_DECRYPT) /* AES decryption */ + { + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Crypto Init for Key preparation for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; + CRYP_Init(&AES_CRYP_InitStructure); + + /* Key Initialisation */ + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + /* wait until the Busy flag is RESET */ + do + { + busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); + counter++; + }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); + + if (busystatus != RESET) + { + status = ERROR; + } + else + { + /* Crypto Init for decryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + } + } + /*------------------ AES Encryption ------------------*/ + else /* AES encryption */ + { + + CRYP_KeyInit(&AES_CRYP_KeyInitStructure); + + /* Crypto Init for Encryption process */ + AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + } + + AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; + AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&AES_CRYP_InitStructure); + + /* Flush IN/OUT FIFOs */ + CRYP_FIFOFlush(); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_cryp.h" + + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group8 High Level DES functions + * @brief High Level DES functions + * +@verbatim + =============================================================================== + High Level DES functions + =============================================================================== +@endverbatim + * @{ + */ + +/** + * @brief Encrypt and decrypt using DES in ECB Mode + * @param Mode: encryption or decryption Mode. + * This parameter can be one of the following values: + * @arg MODE_ENCRYPT: Encryption + * @arg MODE_DECRYPT: Decryption + * @param Key: Key used for DES algorithm. + * @param Ilength: length of the Input buffer, must be a multiple of 8. + * @param Input: pointer to the Input buffer. + * @param Output: pointer to the returned buffer. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Operation done + * - ERROR: Operation failed + */ +ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, + uint32_t Ilength, uint8_t *Output) +{ + CRYP_InitTypeDef DES_CRYP_InitStructure; + CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t keyaddr = (uint32_t)Key; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + uint32_t i = 0; + + /* Crypto structures initialisation*/ + CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure); + + /* Crypto Init for Encryption process */ + if( Mode == MODE_ENCRYPT ) /* DES encryption */ + { + DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + } + else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */ + { + DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + } + + DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB; + DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&DES_CRYP_InitStructure); + + /* Key Initialisation */ + DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + CRYP_KeyInit(& DES_CRYP_KeyInitStructure); + + /* Flush IN/OUT FIFO */ + CRYP_FIFOFlush(); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_cryp.h" + + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRYP + * @brief CRYP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup CRYP_Private_Functions + * @{ + */ + +/** @defgroup CRYP_Group7 High Level TDES functions + * @brief High Level TDES functions + * +@verbatim + =============================================================================== + High Level TDES functions + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Encrypt and decrypt using TDES in ECB Mode + * @param Mode: encryption or decryption Mode. + * This parameter can be one of the following values: + * @arg MODE_ENCRYPT: Encryption + * @arg MODE_DECRYPT: Decryption + * @param Key: Key used for TDES algorithm. + * @param Ilength: length of the Input buffer, must be a multiple of 8. + * @param Input: pointer to the Input buffer. + * @param Output: pointer to the returned buffer. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Operation done + * - ERROR: Operation failed + */ +ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, + uint32_t Ilength, uint8_t *Output) +{ + CRYP_InitTypeDef TDES_CRYP_InitStructure; + CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t keyaddr = (uint32_t)Key; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + uint32_t i = 0; + + /* Crypto structures initialisation*/ + CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure); + + /* Crypto Init for Encryption process */ + if(Mode == MODE_ENCRYPT) /* TDES encryption */ + { + TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + } + else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */ + { + TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + } + + TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; + TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; + CRYP_Init(&TDES_CRYP_InitStructure); + + /* Key Initialisation */ + TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); + keyaddr+=4; + TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); + CRYP_KeyInit(& TDES_CRYP_KeyInitStructure); + + /* Flush IN/OUT FIFO */ + CRYP_FIFOFlush(); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_dac.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* CR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** @defgroup DAC_Group1 DAC channels configuration + * @brief DAC channels configuration: trigger, output buffer, data format + * +@verbatim + =============================================================================== + DAC channels configuration: trigger, output buffer, data format + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified parameters + * in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains + * the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); + +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, + wave generation, mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ + DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @note When the DAC channel is enabled the trigger source can no more be modified. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= (DAC_CR_EN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_SET; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignment for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel DAC. + * @param DAC_Align: Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} +/** + * @} + */ + +/** @defgroup DAC_Group2 DMA management functions + * @brief DMA management functions + * +@verbatim + =============================================================================== + DMA management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, + * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be + * already configured. + * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be + * already configured. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); + } +} +/** + * @} + */ + +/** @defgroup DAC_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} + +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's pending flags. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's interrupt pending bits. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before the + * acknowledgement for the first external trigger is received (first request). + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c new file mode 100644 index 000000000..08000ceaf --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c @@ -0,0 +1,180 @@ +/** + ****************************************************************************** + * @file stm32f2xx_dbgmcu.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides all the DBGMCU firmware functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_dbgmcu.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); +} + +/** + * @brief Configures low power mode behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @param NewState: new state of the specified low power mode in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/** + * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB1 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted + * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @arg DBGMCU_RTC_STOP: RTC Wakeup counter stopped when Core is halted. + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB1FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB1FZ &= ~DBGMCU_Periph; + } +} + +/** + * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB2 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted + * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted + * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted + * @param NewState: new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB2FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB2FZ &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c new file mode 100644 index 000000000..09685a624 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c @@ -0,0 +1,540 @@ +/** + ****************************************************************************** + * @file stm32f2xx_dcmi.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the DCMI peripheral: + * - Initialization and Configuration + * - Image capture functions + * - Interrupts and flags management + * + * @verbatim + * + * + * =================================================================== + * How to use this driver + * =================================================================== + * + * The sequence below describes how to use this driver to capture image + * from a camera module connected to the DCMI Interface. + * This sequence does not take into account the configuration of the + * camera module, which should be made before to configure and enable + * the DCMI to capture images. + * + * 1. Enable the clock for the DCMI and associated GPIOs using the following functions: + * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); + * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + * + * 2. DCMI pins configuration + * - Connect the involved DCMI pins to AF13 using the following function + * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); + * - Configure these DCMI pins in alternate function mode by calling the function + * GPIO_Init(); + * + * 3. Declare a DCMI_InitTypeDef structure, for example: + * DCMI_InitTypeDef DCMI_InitStructure; + * and fill the DCMI_InitStructure variable with the allowed values + * of the structure member. + * + * 4. Initialize the DCMI interface by calling the function + * DCMI_Init(&DCMI_InitStructure); + * + * 5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR + * register to the destination memory buffer. + * + * 6. Enable DCMI interface using the function + * DCMI_Cmd(ENABLE); + * + * 7. Start the image capture using the function + * DCMI_CaptureCmd(ENABLE); + * + * 8. At this stage the DCMI interface waits for the first start of frame, + * then a DMA request is generated continuously/once (depending on the + * mode used, Continuous/Snapshot) to transfer the received data into + * the destination memory. + * + * @note If you need to capture only a rectangular window from the received + * image, you have to use the DCMI_CROPConfig() function to configure + * the coordinates and size of the window to be captured, then enable + * the Crop feature using DCMI_CROPCmd(ENABLE); + * In this case, the Crop configuration should be made before to enable + * and start the DCMI interface. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DCMI + * @brief DCMI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DCMI_Private_Functions + * @{ + */ + +/** @defgroup DCMI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DCMI registers to their default reset values. + * @param None + * @retval None + */ +void DCMI_DeInit(void) +{ + DCMI->CR = 0x0; + DCMI->IER = 0x0; + DCMI->ICR = 0x1F; + DCMI->ESCR = 0x0; + DCMI->ESUR = 0x0; + DCMI->CWSTRTR = 0x0; + DCMI->CWSIZER = 0x0; +} + +/** + * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. + * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains + * the configuration information for the DCMI. + * @retval None + */ +void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct) +{ + uint32_t temp = 0x0; + + /* Check the parameters */ + assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode)); + assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode)); + assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity)); + assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity)); + assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity)); + assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate)); + assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode)); + + /* The DCMI configuration registers should be programmed correctly before + enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */ + DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE); + + /* Reset the old DCMI configuration */ + temp = DCMI->CR; + + temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL | + DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | + DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); + + /* Sets the new configuration of the DCMI peripheral */ + temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode | + DCMI_InitStruct->DCMI_SynchroMode | + DCMI_InitStruct->DCMI_PCKPolarity | + DCMI_InitStruct->DCMI_VSPolarity | + DCMI_InitStruct->DCMI_HSPolarity | + DCMI_InitStruct->DCMI_CaptureRate | + DCMI_InitStruct->DCMI_ExtendedDataMode); + + DCMI->CR = temp; +} + +/** + * @brief Fills each DCMI_InitStruct member with its default value. + * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct) +{ + /* Set the default configuration */ + DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous; + DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware; + DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; + DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low; + DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low; + DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; + DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; +} + +/** + * @brief Initializes the DCMI peripheral CROP mode according to the specified + * parameters in the DCMI_CROPInitStruct. + * @note This function should be called before to enable and start the DCMI interface. + * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that + * contains the configuration information for the DCMI peripheral CROP mode. + * @retval None + */ +void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct) +{ + /* Sets the CROP window coordinates */ + DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount | + ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16)); + + /* Sets the CROP window size */ + DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount | + ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16)); +} + +/** + * @brief Enables or disables the DCMI Crop feature. + * @note This function should be called before to enable and start the DCMI interface. + * @param NewState: new state of the DCMI Crop feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_CROPCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI Crop feature */ + DCMI->CR |= (uint32_t)DCMI_CR_CROP; + } + else + { + /* Disable the DCMI Crop feature */ + DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; + } +} + +/** + * @brief Sets the embedded synchronization codes + * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that + * contains the embedded synchronization codes for the DCMI peripheral. + * @retval None + */ +void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct) +{ + DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode | + ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)| + ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)| + ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24)); +} + +/** + * @brief Enables or disables the DCMI JPEG format. + * @note The Crop and Embedded Synchronization features cannot be used in this mode. + * @param NewState: new state of the DCMI JPEG format. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_JPEGCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI JPEG format */ + DCMI->CR |= (uint32_t)DCMI_CR_JPEG; + } + else + { + /* Disable the DCMI JPEG format */ + DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG; + } +} +/** + * @} + */ + +/** @defgroup DCMI_Group2 Image capture functions + * @brief Image capture functions + * +@verbatim + =============================================================================== + Image capture functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the DCMI interface. + * @param NewState: new state of the DCMI interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI by setting ENABLE bit */ + DCMI->CR |= (uint32_t)DCMI_CR_ENABLE; + } + else + { + /* Disable the DCMI by clearing ENABLE bit */ + DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE; + } +} + +/** + * @brief Enables or disables the DCMI Capture. + * @param NewState: new state of the DCMI capture. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_CaptureCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DCMI Capture */ + DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE; + } + else + { + /* Disable the DCMI Capture */ + DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE; + } +} + +/** + * @brief Reads the data stored in the DR register. + * @param None + * @retval Data register value + */ +uint32_t DCMI_ReadData(void) +{ + return DCMI->DR; +} +/** + * @} + */ + +/** @defgroup DCMI_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the DCMI interface interrupts. + * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVF: Overflow interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @param NewState: new state of the specified DCMI interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DCMI_CONFIG_IT(DCMI_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + DCMI->IER |= DCMI_IT; + } + else + { + /* Disable the Interrupt sources */ + DCMI->IER &= (uint16_t)(~DCMI_IT); + } +} + +/** + * @brief Checks whether the DCMI interface flag is set or not. + * @param DCMI_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask + * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask + * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask + * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask + * @arg DCMI_FLAG_LINERI: Line Raw flag mask + * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask + * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask + * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask + * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask + * @arg DCMI_FLAG_LINEMI: Line Masked flag mask + * @arg DCMI_FLAG_HSYNC: HSYNC flag mask + * @arg DCMI_FLAG_VSYNC: VSYNC flag mask + * @arg DCMI_FLAG_FNE: Fifo not empty flag mask + * @retval The new state of DCMI_FLAG (SET or RESET). + */ +FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t dcmireg, tempreg = 0; + + /* Check the parameters */ + assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG)); + + /* Get the DCMI register index */ + dcmireg = (((uint16_t)DCMI_FLAG) >> 12); + + if (dcmireg == 0x00) /* The FLAG is in RISR register */ + { + tempreg= DCMI->RISR; + } + else if (dcmireg == 0x02) /* The FLAG is in SR register */ + { + tempreg = DCMI->SR; + } + else /* The FLAG is in MISR register */ + { + tempreg = DCMI->MISR; + } + + if ((tempreg & DCMI_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the DCMI_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DCMI's pending flags. + * @param DCMI_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask + * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask + * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask + * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask + * @arg DCMI_FLAG_LINERI: Line Raw flag mask + * @retval None + */ +void DCMI_ClearFlag(uint16_t DCMI_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG)); + + /* Clear the flag by writing in the ICR register 1 in the corresponding + Flag position*/ + + DCMI->ICR = DCMI_FLAG; +} + +/** + * @brief Checks whether the DCMI interrupt has occurred or not. + * @param DCMI_IT: specifies the DCMI interrupt source to check. + * This parameter can be one of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVF: Overflow interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @retval The new state of DCMI_IT (SET or RESET). + */ +ITStatus DCMI_GetITStatus(uint16_t DCMI_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itstatus = 0; + + /* Check the parameters */ + assert_param(IS_DCMI_GET_IT(DCMI_IT)); + + itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */ + + if ((itstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the DCMI's interrupt pending bits. + * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVF: Overflow interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @retval None + */ +void DCMI_ClearITPendingBit(uint16_t DCMI_IT) +{ + /* Clear the interrupt pending Bit by writing in the ICR register 1 in the + corresponding pending Bit position*/ + + DCMI->ICR = DCMI_IT; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c new file mode 100644 index 000000000..9e8ec04cf --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c @@ -0,0 +1,1289 @@ +/** + ****************************************************************************** + * @file stm32f2xx_dma.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access controller (DMA): + * - Initialization and Configuration + * - Data Counter + * - Double Buffer mode configuration and command + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) + * function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) + * function for DMA2. + * + * 2. Enable and configure the peripheral to be connected to the DMA Stream + * (except for internal SRAM / FLASH memories: no initialization is + * necessary). + * + * 3. For a given Stream, program the required configuration through following parameters: + * Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination + * data formats, Circular or Normal mode, Stream Priority level, Source and Destination + * Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or + * Destination (if needed) using the DMA_Init() function. + * To avoid filling un-nesecessary fields, you can call DMA_StructInit() function + * to initialize a given structure with default values (reset values), the modify + * only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats). + * + * 4. Enable the NVIC and the corresponding interrupt(s) using the function + * DMA_ITConfig() if you need to use DMA interrupts. + * + * 5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring + * the second Memory address and the first Memory to be used through the function + * DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function + * DMA_DoubleBufferModeCmd(). These operations must be done before step 6. + * + * 6. Enable the DMA stream using the DMA_Cmd() function. + * + * 7. Activate the needed Stream Request using PPP_DMACmd() function for + * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) + * The function allowing this operation is provided in each PPP peripheral + * driver (ie. SPI_DMACmd for SPI peripheral). + * Once the Stream is enabled, it is not possible to modify its configuration + * unless the stream is stopped and disabled. + * After enabling the Stream, it is advised to monitor the EN bit status using + * the function DMA_GetCmdStatus(). In case of configuration errors or bus errors + * this bit will remain reset and all transfers on this Stream will remain on hold. + * + * 8. Optionally, you can configure the number of data to be transferred + * when the Stream is disabled (ie. after each Transfer Complete event + * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). + * And you can get the number of remaining data to be transferred using + * the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is + * enabled and running). + * + * 9. To control DMA events you can use one of the following + * two methods: + * a- Check on DMA Stream flags using the function DMA_GetFlagStatus(). + * b- Use DMA interrupts through the function DMA_ITConfig() at initialization + * phase and DMA_GetITStatus() function into interrupt routines in + * communication phase. + * After checking on a flag you should clear it using DMA_ClearFlag() + * function. And after checking on an interrupt event you should + * clear it using DMA_ClearITPendingBit() function. + * + * 10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify + * the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that + * the Memory Address to be modified is not the one currently in use by DMA Stream. + * This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). + * + * 11. Optionally, Pause-Resume operations may be performed: + * The DMA_Cmd() function may be used to perform Pause-Resume operation. When a + * transfer is ongoing, calling this function to disable the Stream will cause the + * transfer to be paused. All configuration registers and the number of remaining + * data will be preserved. When calling again this function to re-enable the Stream, + * the transfer will be resumed from the point where it was paused. + * + * @note Memory-to-Memory transfer is possible by setting the address of the memory into + * the Peripheral registers. In this mode, Circular mode and Double Buffer mode + * are not allowed. + * + * @note The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + * possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + * Half-Word data size for the peripheral to access its data register and set Word data size + * for the Memory to gain in access time. Each two Half-words will be packed and written in + * a single access to a Word in the Memory). + * + * @note When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + * and Destination. In this case the Peripheral Data Size will be applied to both Source + * and Destination. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_dma.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Masks Definition */ +#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \ + DMA_SxCR_TEIE | DMA_SxCR_DMEIE) + +#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \ + DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \ + DMA_LISR_TCIF0) + +#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6) +#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16) +#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22) +#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000) +#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000) +#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000) +#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000) +#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C +#define HIGH_ISR_MASK (uint32_t)0x20000000 +#define RESERVED_MASK (uint32_t)0x0F7D0F7D + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** @defgroup DMA_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + + This subsection provides functions allowing to initialize the DMA Stream source + and destination addresses, incrementation and data sizes, transfer direction, + buffer size, circular/normal mode selection, memory-to-memory mode selection + and Stream priority value. + + The DMA_Init() function follows the DMA configuration procedures as described in + reference manual (RM0033) except the first point: waiting on EN bit to be reset. + This condition should be checked by user application using the function DMA_GetCmdStatus() + before calling the DMA_Init() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the DMAy Streamx registers to their default reset values. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval None + */ +void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Disable the selected DMAy Streamx */ + DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN); + + /* Reset DMAy Streamx control register */ + DMAy_Streamx->CR = 0; + + /* Reset DMAy Streamx Number of Data to Transfer register */ + DMAy_Streamx->NDTR = 0; + + /* Reset DMAy Streamx peripheral address register */ + DMAy_Streamx->PAR = 0; + + /* Reset DMAy Streamx memory 0 address register */ + DMAy_Streamx->M0AR = 0; + + /* Reset DMAy Streamx memory 1 address register */ + DMAy_Streamx->M1AR = 0; + + /* Reset DMAy Streamx FIFO control register */ + DMAy_Streamx->FCR = (uint32_t)0x00000021; + + /* Reset interrupt pending bits for the selected stream */ + if (DMAy_Streamx == DMA1_Stream0) + { + /* Reset interrupt pending bits for DMA1 Stream0 */ + DMA1->LIFCR = DMA_Stream0_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream1) + { + /* Reset interrupt pending bits for DMA1 Stream1 */ + DMA1->LIFCR = DMA_Stream1_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream2) + { + /* Reset interrupt pending bits for DMA1 Stream2 */ + DMA1->LIFCR = DMA_Stream2_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream3) + { + /* Reset interrupt pending bits for DMA1 Stream3 */ + DMA1->LIFCR = DMA_Stream3_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream4) + { + /* Reset interrupt pending bits for DMA1 Stream4 */ + DMA1->HIFCR = DMA_Stream4_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream5) + { + /* Reset interrupt pending bits for DMA1 Stream5 */ + DMA1->HIFCR = DMA_Stream5_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream6) + { + /* Reset interrupt pending bits for DMA1 Stream6 */ + DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK; + } + else if (DMAy_Streamx == DMA1_Stream7) + { + /* Reset interrupt pending bits for DMA1 Stream7 */ + DMA1->HIFCR = DMA_Stream7_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream0) + { + /* Reset interrupt pending bits for DMA2 Stream0 */ + DMA2->LIFCR = DMA_Stream0_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream1) + { + /* Reset interrupt pending bits for DMA2 Stream1 */ + DMA2->LIFCR = DMA_Stream1_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream2) + { + /* Reset interrupt pending bits for DMA2 Stream2 */ + DMA2->LIFCR = DMA_Stream2_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream3) + { + /* Reset interrupt pending bits for DMA2 Stream3 */ + DMA2->LIFCR = DMA_Stream3_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream4) + { + /* Reset interrupt pending bits for DMA2 Stream4 */ + DMA2->HIFCR = DMA_Stream4_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream5) + { + /* Reset interrupt pending bits for DMA2 Stream5 */ + DMA2->HIFCR = DMA_Stream5_IT_MASK; + } + else if (DMAy_Streamx == DMA2_Stream6) + { + /* Reset interrupt pending bits for DMA2 Stream6 */ + DMA2->HIFCR = DMA_Stream6_IT_MASK; + } + else + { + if (DMAy_Streamx == DMA2_Stream7) + { + /* Reset interrupt pending bits for DMA2 Stream7 */ + DMA2->HIFCR = DMA_Stream7_IT_MASK; + } + } +} + +/** + * @brief Initializes the DMAy Streamx according to the specified parameters in + * the DMA_InitStruct structure. + * @note Before calling this function, it is recommended to check that the Stream + * is actually disabled using the function DMA_GetCmdStatus(). + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel)); + assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode)); + assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst)); + + /*------------------------- DMAy Streamx CR Configuration ------------------*/ + /* Get the DMAy_Streamx CR value */ + tmpreg = DMAy_Streamx->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR)); + + /* Configure DMAy Streamx: */ + /* Set CHSEL bits according to DMA_CHSEL value */ + /* Set DIR bits according to DMA_DIR value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PL bits according to DMA_Priority value */ + /* Set MBURST bits according to DMA_MemoryBurst value */ + /* Set PBURST bits according to DMA_PeripheralBurst value */ + tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority | + DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst; + + /* Write to DMAy Streamx CR register */ + DMAy_Streamx->CR = tmpreg; + + /*------------------------- DMAy Streamx FCR Configuration -----------------*/ + /* Get the DMAy_Streamx FCR value */ + tmpreg = DMAy_Streamx->FCR; + + /* Clear DMDIS and FTH bits */ + tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Configure DMAy Streamx FIFO: + Set DMDIS bits according to DMA_FIFOMode value + Set FTH bits according to DMA_FIFOThreshold value */ + tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold; + + /* Write to DMAy Streamx CR */ + DMAy_Streamx->FCR = tmpreg; + + /*------------------------- DMAy Streamx NDTR Configuration ----------------*/ + /* Write to DMAy Streamx NDTR register */ + DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize; + + /*------------------------- DMAy Streamx PAR Configuration -----------------*/ + /* Write to DMAy Streamx PAR */ + DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + + /*------------------------- DMAy Streamx M0AR Configuration ----------------*/ + /* Write to DMAy Streamx M0AR */ + DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ + /*-------------- Reset DMA init structure parameters values ----------------*/ + /* Initialize the DMA_Channel member */ + DMA_InitStruct->DMA_Channel = 0; + + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + + /* Initialize the DMA_Memory0BaseAddr member */ + DMA_InitStruct->DMA_Memory0BaseAddr = 0; + + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory; + + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + + /* Initialize the DMA_FIFOMode member */ + DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable; + + /* Initialize the DMA_FIFOThreshold member */ + DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; + + /* Initialize the DMA_MemoryBurst member */ + DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single; + + /* Initialize the DMA_PeripheralBurst member */ + DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single; +} + +/** + * @brief Enables or disables the specified DMAy Streamx. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param NewState: new state of the DMAy Streamx. + * This parameter can be: ENABLE or DISABLE. + * + * @note This function may be used to perform Pause-Resume operation. When a + * transfer is ongoing, calling this function to disable the Stream will + * cause the transfer to be paused. All configuration registers and the + * number of remaining data will be preserved. When calling again this + * function to re-enable the Stream, the transfer will be resumed from + * the point where it was paused. + * + * @note After configuring the DMA Stream (DMA_Init() function) and enabling the + * stream, it is recommended to check (or wait until) the DMA Stream is + * effectively enabled. A Stream may remain disabled if a configuration + * parameter is wrong. + * After disabling a DMA Stream, it is also recommended to check (or wait + * until) the DMA Stream is effectively disabled. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * + * @retval None + */ +void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Streamx by setting EN bit */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN; + } + else + { + /* Disable the selected DMAy Streamx by clearing EN bit */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN; + } +} + +/** + * @brief Configures, when the PINC (Peripheral Increment address mode) bit is + * set, if the peripheral address should be incremented with the data + * size (configured with PSIZE bits) or by a fixed offset equal to 4 + * (32-bit aligned addresses). + * + * @note This function has no effect if the Peripheral Increment mode is disabled. + * + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_Pincos: specifies the Peripheral increment offset size. + * This parameter can be one of the following values: + * @arg DMA_PINCOS_Psize: Peripheral address increment is done + * accordingly to PSIZE parameter. + * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is + * fixed to 4 (32-bit aligned addresses). + * @retval None + */ +void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos)); + + /* Check the needed Peripheral increment offset */ + if(DMA_Pincos != DMA_PINCOS_Psize) + { + /* Configure DMA_SxCR_PINCOS bit with the input parameter */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; + } + else + { + /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; + } +} + +/** + * @brief Configures, when the DMAy Streamx is disabled, the flow controller for + * the next transactions (Peripheral or Memory). + * + * @note Before enabling this feature, check if the used peripheral supports + * the Flow Controller mode or not. + * + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_FlowCtrl: specifies the DMA flow controller. + * This parameter can be one of the following values: + * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is + * the DMA controller. + * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller + * is the peripheral. + * @retval None + */ +void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl)); + + /* Check the needed flow controller */ + if(DMA_FlowCtrl != DMA_FlowCtrl_Memory) + { + /* Configure DMA_SxCR_PFCTRL bit with the input parameter */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; + } + else + { + /* Clear the PFCTRL bit: Memory is the flow controller */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; + } +} +/** + * @} + */ + +/** @defgroup DMA_Group2 Data Counter functions + * @brief Data Counter functions + * +@verbatim + =============================================================================== + Data Counter functions + =============================================================================== + + This subsection provides function allowing to configure and read the buffer size + (number of data to be transferred). + + The DMA data counter can be written only when the DMA Stream is disabled + (ie. after transfer complete event). + + The following function can be used to write the Stream data counter value: + - void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); + +@note It is advised to use this function rather than DMA_Init() in situations where + only the Data buffer needs to be reloaded. + +@note If the Source and Destination Data Sizes are different, then the value written in + data counter, expressing the number of transfers, is relative to the number of + transfers from the Peripheral point of view. + ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value + to be configured in the data counter is the number of Half-Words to be transferred + from/to the peripheral. + + The DMA data counter can be read to indicate the number of remaining transfers for + the relative DMA Stream. This counter is decremented at the end of each data + transfer and when the transfer is complete: + - If Normal mode is selected: the counter is set to 0. + - If Circular mode is selected: the counter is reloaded with the initial value + (configured before enabling the DMA Stream) + + The following function can be used to read the Stream data counter value: + - uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); + +@endverbatim + * @{ + */ + +/** + * @brief Writes the number of data units to be transferred on the DMAy Streamx. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param Counter: Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @note In Memory-to-Memory transfer mode, the memory buffer pointed by + * DMAy_SxPAR register is considered as Peripheral. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Write the number of data units to be transferred */ + DMAy_Streamx->NDTR = (uint16_t)Counter; +} + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Return the number of remaining data units for DMAy Streamx */ + return ((uint16_t)(DMAy_Streamx->NDTR)); +} +/** + * @} + */ + +/** @defgroup DMA_Group3 Double Buffer mode functions + * @brief Double Buffer mode functions + * +@verbatim + =============================================================================== + Double Buffer mode functions + =============================================================================== + + This subsection provides function allowing to configure and control the double + buffer mode parameters. + + The Double Buffer mode can be used only when Circular mode is enabled. + The Double Buffer mode cannot be used when transferring data from Memory to Memory. + + The Double Buffer mode allows to set two different Memory addresses from/to which + the DMA controller will access alternatively (after completing transfer to/from target + memory 0, it will start transfer to/from target memory 1). + This allows to reduce software overhead for double buffering and reduce the CPU + access time. + + Two functions must be called before calling the DMA_Init() function: + - void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, + uint32_t DMA_CurrentMemory); + - void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); + + DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first + Memory target from/to which the transfer will start after enabling the DMA Stream. + Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable + it when it should not be used). + + + Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is + stopped) to modify on of the target Memories addresses or to check wich Memory target is currently + used: + - void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, + uint32_t DMA_MemoryTarget); + - uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); + + DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories. + The Memory of which the base address will be modified must not be currently be used by the DMA Stream + (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address + of target Memory 0 and vice versa). + To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which + returns the index of the Memory target currently in use by the DMA Stream. + +@endverbatim + * @{ + */ + +/** + * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode + * and the current memory target. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) + * @param DMA_CurrentMemory: specifies which memory will be first buffer for + * the transactions when the Stream will be enabled. + * This parameter can be one of the following values: + * @arg DMA_Memory_0: Memory 0 is the current buffer. + * @arg DMA_Memory_1: Memory 1 is the current buffer. + * + * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init(). + * + * @retval None + */ +void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, + uint32_t DMA_CurrentMemory) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory)); + + if (DMA_CurrentMemory != DMA_Memory_0) + { + /* Set Memory 1 as current memory address */ + DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); + } + else + { + /* Set Memory 0 as current memory address */ + DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); + } + + /* Write to DMAy Streamx M1AR */ + DMAy_Streamx->M1AR = Memory1BaseAddr; +} + +/** + * @brief Enables or disables the double buffer mode for the selected DMA stream. + * @note This function can be called only when the DMA Stream is disabled. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param NewState: new state of the DMAy Streamx double buffer mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Configure the Double Buffer mode */ + if (NewState != DISABLE) + { + /* Enable the Double buffer mode */ + DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM; + } + else + { + /* Disable the Double buffer mode */ + DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM; + } +} + +/** + * @brief Configures the Memory address for the next buffer transfer in double + * buffer mode (for dynamic use). This function can be called when the + * DMA Stream is enabled and when the transfer is ongoing. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param MemoryBaseAddr: The base address of the target memory buffer + * @param DMA_MemoryTarget: Next memory target to be used. + * This parameter can be one of the following values: + * @arg DMA_Memory_0: To use the memory address 0 + * @arg DMA_Memory_1: To use the memory address 1 + * + * @note It is not allowed to modify the Base Address of a target Memory when + * this target is involved in the current transfer. ie. If the DMA Stream + * is currently transferring to/from Memory 1, then it not possible to + * modify Base address of Memory 1, but it is possible to modify Base + * address of Memory 0. + * To know which Memory is currently used, you can use the function + * DMA_GetCurrentMemoryTarget(). + * + * @retval None + */ +void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, + uint32_t DMA_MemoryTarget) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget)); + + /* Check the Memory target to be configured */ + if (DMA_MemoryTarget != DMA_Memory_0) + { + /* Write to DMAy Streamx M1AR */ + DMAy_Streamx->M1AR = MemoryBaseAddr; + } + else + { + /* Write to DMAy Streamx M0AR */ + DMAy_Streamx->M0AR = MemoryBaseAddr; + } +} + +/** + * @brief Returns the current memory target used by double buffer transfer. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval The memory target number: 0 for Memory0 or 1 for Memory1. + */ +uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Get the current memory target */ + if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0) + { + /* Current memory buffer used is Memory 1 */ + tmp = 1; + } + else + { + /* Current memory buffer used is Memory 0 */ + tmp = 0; + } + return tmp; +} +/** + * @} + */ + +/** @defgroup DMA_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This subsection provides functions allowing to + - Check the DMA enable status + - Check the FIFO status + - Configure the DMA Interrupts sources and check or clear the flags or pending bits status. + + 1. DMA Enable status: + After configuring the DMA Stream (DMA_Init() function) and enabling the stream, + it is recommended to check (or wait until) the DMA Stream is effectively enabled. + A Stream may remain disabled if a configuration parameter is wrong. + After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA + Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, + the current data will be transferred and the Stream will be effectively disabled only after + this data transfer completion. + To monitor this state it is possible to use the following function: + - FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); + + 2. FIFO Status: + It is possible to monitor the FIFO status when a transfer is ongoing using the following + function: + - uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); + + 3. DMA Interrupts and Flags: + The user should identify which mode will be used in his application to manage the + DMA controller events: Polling mode or Interrupt mode. + + Polling Mode + ============= + Each DMA stream can be managed through 4 event Flags: + (x : DMA Stream number ) + 1. DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. + 2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. + 3. DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. + 4. DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. + 5. DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . + + In this Mode it is advised to use the following functions: + - FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); + - void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); + + Interrupt Mode + =============== + Each DMA Stream can be managed through 4 Interrupts: + + Interrupt Source + ---------------- + 1. DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. + 2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. + 3. DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. + 4. DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. + 5. DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. + + In this Mode it is advised to use the following functions: + - void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); + - ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); + - void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); + +@endverbatim + * @{ + */ + +/** + * @brief Returns the status of EN bit for the specified DMAy Streamx. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * + * @note After configuring the DMA Stream (DMA_Init() function) and enabling + * the stream, it is recommended to check (or wait until) the DMA Stream + * is effectively enabled. A Stream may remain disabled if a configuration + * parameter is wrong. + * After disabling a DMA Stream, it is also recommended to check (or wait + * until) the DMA Stream is effectively disabled. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer + * of this single data is finished. + * + * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). + */ +FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx) +{ + FunctionalState state = DISABLE; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0) + { + /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */ + state = ENABLE; + } + else + { + /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + state = DISABLE; + } + return state; +} + +/** + * @brief Returns the current DMAy Streamx FIFO filled level. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + + /* Get the FIFO level bits */ + tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS)); + + return tmpreg; +} + +/** + * @brief Checks whether the specified DMAy Streamx flag is set or not. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag + * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag + * @arg DMA_FLAG_TEIFx: Streamx transfer error flag + * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag + * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag + * Where x can be 0 to 7 to select the DMA Stream. + * @retval The new state of DMA_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + DMA_TypeDef* DMAy; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if the flag is in HISR or LISR */ + if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Get DMAy HISR register value */ + tmpreg = DMAy->HISR; + } + else + { + /* Get DMAy LISR register value */ + tmpreg = DMAy->LISR; + } + + /* Mask the reserved bits */ + tmpreg &= (uint32_t)RESERVED_MASK; + + /* Check the status of the specified DMA flag */ + if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Streamx's pending flags. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag + * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag + * @arg DMA_FLAG_TEIFx: Streamx transfer error flag + * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag + * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag + * Where x can be 0 to 7 to select the DMA Stream. + * @retval None + */ +void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) +{ + DMA_TypeDef* DMAy; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if LIFCR or HIFCR register is targeted */ + if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Set DMAy HIFCR register clear flag bits */ + DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); + } + else + { + /* Set DMAy LIFCR register clear flag bits */ + DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); + } +} + +/** + * @brief Enables or disables the specified DMAy Streamx interrupts. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @arg DMA_IT_FE: FIFO error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Check if the DMA_IT parameter contains a FIFO interrupt */ + if ((DMA_IT & DMA_IT_FE) != 0) + { + if (NewState != DISABLE) + { + /* Enable the selected DMA FIFO interrupts */ + DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE; + } + else + { + /* Disable the selected DMA FIFO interrupts */ + DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; + } + } + + /* Check if the DMA_IT parameter contains a Transfer interrupt */ + if (DMA_IT != DMA_IT_FE) + { + if (NewState != DISABLE) + { + /* Enable the selected DMA transfer interrupts */ + DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); + } + else + { + /* Disable the selected DMA transfer interrupts */ + DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); + } + } +} + +/** + * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_IT: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt + * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt + * @arg DMA_IT_TEIFx: Streamx transfer error interrupt + * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt + * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt + * Where x can be 0 to 7 to select the DMA Stream. + * @retval The new state of DMA_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) +{ + ITStatus bitstatus = RESET; + DMA_TypeDef* DMAy; + uint32_t tmpreg = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if the interrupt enable bit is in the CR or FCR register */ + if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET) + { + /* Get the interrupt enable position mask in CR register */ + tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); + + /* Check the enable bit in CR register */ + enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg); + } + else + { + /* Check the enable bit in FCR register */ + enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); + } + + /* Check if the interrupt pending flag is in LISR or HISR */ + if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Get DMAy HISR register value */ + tmpreg = DMAy->HISR ; + } + else + { + /* Get DMAy LISR register value */ + tmpreg = DMAy->LISR ; + } + + /* mask all reserved bits */ + tmpreg &= (uint32_t)RESERVED_MASK; + + /* Check the status of the specified DMA interrupt */ + if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Streamx's interrupt pending bits. + * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 + * to 7 to select the DMA Stream. + * @param DMA_IT: specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt + * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt + * @arg DMA_IT_TEIFx: Streamx transfer error interrupt + * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt + * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt + * Where x can be 0 to 7 to select the DMA Stream. + * @retval None + */ +void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) +{ + DMA_TypeDef* DMAy; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Determine the DMA to which belongs the stream */ + if (DMAy_Streamx < DMA2_Stream0) + { + /* DMAy_Streamx belongs to DMA1 */ + DMAy = DMA1; + } + else + { + /* DMAy_Streamx belongs to DMA2 */ + DMAy = DMA2; + } + + /* Check if LIFCR or HIFCR register is targeted */ + if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) + { + /* Set DMAy HIFCR register clear interrupt bits */ + DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); + } + else + { + /* Set DMAy LIFCR register clear interrupt bits */ + DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c new file mode 100644 index 000000000..2964a84a6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c @@ -0,0 +1,312 @@ +/** + ****************************************************************************** + * @file stm32f2xx_exti.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the EXTI peripheral: + * - Initialization and Configuration + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * EXTI features + * =================================================================== + * + * External interrupt/event lines are mapped as following: + * 1- All available GPIO pins are connected to the 16 external + * interrupt/event lines from EXTI0 to EXTI15. + * 2- EXTI line 16 is connected to the PVD Output + * 3- EXTI line 17 is connected to the RTC Alarm event + * 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event + * 5- EXTI line 19 is connected to the Ethernet Wakeup event + * 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event + * 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events + * 8- EXTI line 22 is connected to the RTC Wakeup event + * + * =================================================================== + * How to use this driver + * =================================================================== + * + * In order to use an I/O pin as an external interrupt source, follow + * steps below: + * 1- Configure the I/O in input mode using GPIO_Init() + * 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() + * 3- Select the mode(interrupt, event) and configure the trigger + * selection (Rising, falling or both) using EXTI_Init() + * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() + * + * @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx + * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_exti.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** @defgroup EXTI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x007FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param EXTI_Line: specifies the EXTI line on which the software interrupt + * will be generated. + * This parameter can be any combination of EXTI_Linex where x can be (0..22) + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @} + */ + +/** @defgroup EXTI_Group2 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be EXTI_Linex where x can be(0..22) + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..22) + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be EXTI_Linex where x can be(0..22) + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..22) + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c new file mode 100644 index 000000000..59a2c8d5b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c @@ -0,0 +1,1060 @@ +/** + ****************************************************************************** + * @file stm32f2xx_flash.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * - FLASH Interface configuration + * - FLASH Memory Programming + * - Option Bytes Programming + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * + * This driver provides functions to configure and program the FLASH + * memory of all STM32F2xx devices. + * These functions are split in 4 groups: + * + * 1. FLASH Interface configuration functions: this group includes the + * management of the following features: + * - Set the latency + * - Enable/Disable the prefetch buffer + * - Enable/Disable the Instruction cache and the Data cache + * - Reset the Instruction cache and the Data cache + * + * 2. FLASH Memory Programming functions: this group includes all needed + * functions to erase and program the main memory: + * - Lock and Unlock the FLASH interface + * - Erase function: Erase sector, erase all sectors + * - Program functions: byte, half word, word and double word + * + * 3. Option Bytes Programming functions: this group includes all needed + * functions to manage the Option Bytes: + * - Set/Reset the write protection + * - Set the Read protection Level + * - Set the BOR level + * - Program the user Option Bytes + * - Launch the Option Bytes loader + * + * 4. Interrupts and flags management functions: this group + * includes all needed functions to: + * - Enable/Disable the FLASH interrupt sources + * - Get flags status + * - Clear flags + * - Get FLASH operation status + * - Wait for last FLASH operation + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_flash.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SECTOR_MASK ((uint32_t)0xFFFFFF07) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** @defgroup FLASH_Group1 FLASH Interface configuration functions + * @brief FLASH Interface configuration functions + * + +@verbatim + =============================================================================== + FLASH Interface configuration functions + =============================================================================== + + This group includes the following functions: + - void FLASH_SetLatency(uint32_t FLASH_Latency) + To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| + |***************|****************|****************|*****************|*****************|*****************************+ + | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | + |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| + |Max Parallelism| x32 | x16 | x8 | x64 | + |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| + |PSIZE[1:0] | 10 | 01 | 00 | 11 | + +-------------------------------------------------------------------------------------------------------------------+ + + - void FLASH_PrefetchBufferCmd(FunctionalState NewState) + - void FLASH_InstructionCacheCmd(FunctionalState NewState) + - void FLASH_DataCacheCmd(FunctionalState NewState) + - void FLASH_InstructionCacheReset(void) + - void FLASH_DataCacheReset(void) + + The unlock sequence is not needed for these functions. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the code latency value. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @arg FLASH_Latency_2: FLASH Two Latency cycles + * @arg FLASH_Latency_3: FLASH Three Latency cycles + * @arg FLASH_Latency_4: FLASH Four Latency cycles + * @arg FLASH_Latency_5: FLASH Five Latency cycles + * @arg FLASH_Latency_6: FLASH Six Latency cycles + * @arg FLASH_Latency_7: FLASH Seven Latency cycles + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */ + *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @param NewState: new state of the Prefetch Buffer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_PrefetchBufferCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Enable or disable the Prefetch Buffer */ + if(NewState != DISABLE) + { + FLASH->ACR |= FLASH_ACR_PRFTEN; + } + else + { + FLASH->ACR &= (~FLASH_ACR_PRFTEN); + } +} + +/** + * @brief Enables or disables the Instruction Cache feature. + * @param NewState: new state of the Instruction Cache. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_InstructionCacheCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + FLASH->ACR |= FLASH_ACR_ICEN; + } + else + { + FLASH->ACR &= (~FLASH_ACR_ICEN); + } +} + +/** + * @brief Enables or disables the Data Cache feature. + * @param NewState: new state of the Data Cache. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_DataCacheCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + FLASH->ACR |= FLASH_ACR_DCEN; + } + else + { + FLASH->ACR &= (~FLASH_ACR_DCEN); + } +} + +/** + * @brief Resets the Instruction Cache. + * @note This function must be used only when the Instruction Cache is disabled. + * @param None + * @retval None + */ +void FLASH_InstructionCacheReset(void) +{ + FLASH->ACR |= FLASH_ACR_ICRST; +} + +/** + * @brief Resets the Data Cache. + * @note This function must be used only when the Data Cache is disabled. + * @param None + * @retval None + */ +void FLASH_DataCacheReset(void) +{ + FLASH->ACR |= FLASH_ACR_DCRST; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group2 FLASH Memory Programming functions + * @brief FLASH Memory Programming functions + * +@verbatim + =============================================================================== + FLASH Memory Programming functions + =============================================================================== + + This group includes the following functions: + - void FLASH_Unlock(void) + - void FLASH_Lock(void) + - FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) + - FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) + - FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) + - FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) + - FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) + - FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) + + Any operation of erase or program should follow these steps: + 1. Call the FLASH_Unlock() function to enable the FLASH control register access + + 2. Call the desired function to erase sector(s) or program data + + 3. Call the FLASH_Lock() function to disable the FLASH control register access + (recommended to protect the FLASH memory against possible unwanted operation) + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the FLASH control register access + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + if((FLASH->CR & FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + } +} + +/** + * @brief Locks the FLASH control register access + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + FLASH->CR |= FLASH_CR_LOCK; +} + +/** + * @brief Erases a specified FLASH Sector. + * + * @param FLASH_Sector: The Sector number to be erased. + * This parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11 + * + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0x0; + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(FLASH_Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == VoltageRange_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == VoltageRange_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == VoltageRange_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the sector */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR &= SECTOR_MASK; + FLASH->CR |= FLASH_CR_SER | FLASH_Sector; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the SER Bit */ + FLASH->CR &= (~FLASH_CR_SER); + FLASH->CR &= SECTOR_MASK; + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH Sectors. + * + * @param VoltageRange: The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0x0; + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == VoltageRange_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == VoltageRange_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == VoltageRange_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_CR_MER); + + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Programs a double word (64-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V and an External Vpp is present. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint64_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a word (32-bit) at a specified address. + * @param Address: specifies the address to be programmed. + * This parameter can be any address in Program memory zone or in OTP zone. + * @note This function must be used when the device voltage range is from 2.7V to 3.6V. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint32_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word (16-bit) at a specified address. + * @note This function must be used when the device voltage range is from 2.1V to 3.6V. + * @param Address: specifies the address to be programmed. + * This parameter can be any address in Program memory zone or in OTP zone. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_HALF_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a byte (8-bit) at a specified address. + * @note This function can be used within all the device supply voltage ranges. + * @param Address: specifies the address to be programmed. + * This parameter can be any address in Program memory zone or in OTP zone. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_BYTE; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint8_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + + /* Return the Program Status */ + return status; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group3 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + =============================================================================== + Option Bytes Programming functions + =============================================================================== + + This group includes the following functions: + - void FLASH_OB_Unlock(void) + - void FLASH_OB_Lock(void) + - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) + - void FLASH_OB_RDPConfig(uint8_t OB_RDP) + - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) + - void FLASH_OB_BORConfig(uint8_t OB_BOR) + - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) + - FLASH_Status FLASH_OB_Launch(void) + - uint32_t FLASH_OB_GetUser(void) + - uint8_t FLASH_OB_GetWRP(void) + - uint8_t FLASH_OB_GetRDP(void) + - uint8_t FLASH_OB_GetBOR(void) + + Any operation of erase or program should follow these steps: + 1. Call the FLASH_OB_Unlock() function to enable the FLASH option control register access + + 2. Call one or several functions to program the desired Option Bytes: + - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable + the desired sector write protection + - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level + - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure + the user Option Bytes. + - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level + + 3. Once all needed Option Bytes to be programmed are correctly written, call the + FLASH_OB_Launch() function to launch the Option Bytes programming process. + + @note When changing the IWDG mode from HW to SW or from SW to HW, a system + reset is needed to make the change effective. + + 4. Call the FLASH_OB_Lock() function to disable the FLASH option control register + access (recommended to protect the Option Bytes against possible unwanted operations) + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the FLASH Option Control Registers access. + * @param None + * @retval None + */ +void FLASH_OB_Unlock(void) +{ + if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) + { + /* Authorizes the Option Byte register programming */ + FLASH->OPTKEYR = FLASH_OPT_KEY1; + FLASH->OPTKEYR = FLASH_OPT_KEY2; + } +} + +/** + * @brief Locks the FLASH Option Control Registers access. + * @param None + * @retval None + */ +void FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; +} + +/** + * @brief Enables or disables the write protection of the desired sectors + * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 + * @arg OB_WRP_Sector_All + * @param Newstate: new state of the Write Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_WRP(OB_WRP)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + if(NewState != DISABLE) + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); + } + else + { + *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP; + } + } +} + +/** + * @brief Sets the read protection level. + * @param OB_RDP: specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_Level_0: No protection + * @arg OB_RDP_Level_1: Read protection of the memory + * @arg OB_RDP_Level_2: Full chip protection + * + * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * + * @retval None + */ +void FLASH_OB_RDPConfig(uint8_t OB_RDP) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_RDP(OB_RDP)); + + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; + + } +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param OB_IWDG: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval None + */ +void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) +{ + uint8_t optiontmp = 0xFF; + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + if(status == FLASH_COMPLETE) + { + /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); + + /* Update User Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); + } +} + +/** + * @brief Sets the BOR Level. + * @param OB_BOR: specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V + * @retval None + */ +void FLASH_OB_BORConfig(uint8_t OB_BOR) +{ + /* Check the parameters */ + assert_param(IS_OB_BOR(OB_BOR)); + + /* Set the BOR Level */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; + +} + +/** + * @brief Launch the option byte loading. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_OB_Launch(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Set the OPTSTRT bit in OPTCR register */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(); + + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @param None + * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)(FLASH->OPTCR >> 5); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes value. + * @param None + * @retval The FLASH Write Protection Option Bytes value + */ +uint16_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @param None + * @retval FLASH ReadOut Protection Status: + * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set + * - RESET, when OB_RDP_Level_0 is set + */ +FlagStatus FLASH_OB_GetRDP(void) +{ + FlagStatus readstatus = RESET; + + if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0)) + { + readstatus = SET; + } + else + { + readstatus = RESET; + } + return readstatus; +} + +/** + * @brief Returns the FLASH BOR level. + * @param None + * @retval The FLASH BOR level: + * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V + */ +uint8_t FLASH_OB_GetBOR(void) +{ + /* Return the FLASH BOR level */ + return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); +} + +/** + * @} + */ + +/** @defgroup FLASH_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERR: FLASH Error Interrupt + * @arg FLASH_IT_EOP: FLASH end of operation Interrupt + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR: FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); + + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR: FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +} + +/** + * @brief Returns the FLASH Status. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_PROGRAM; + } + else + { + if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) + { + flashstatus = FLASH_ERROR_OPERATION; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + } + /* Return the FLASH Status */ + return flashstatus; +} + +/** + * @brief Waits for a FLASH operation to complete. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, + * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(void) +{ + __IO FLASH_Status status = FLASH_COMPLETE; + + /* Check for the FLASH Status */ + status = FLASH_GetStatus(); + + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + while(status == FLASH_BUSY) + { + status = FLASH_GetStatus(); + } + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c new file mode 100644 index 000000000..84a38f064 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c @@ -0,0 +1,987 @@ +/** + ****************************************************************************** + * @file stm32f2xx_fsmc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the FSMC peripheral: + * - Interface with SRAM, PSRAM, NOR and OneNAND memories + * - Interface with NAND memories + * - Interface with 16-bit PC Card compatible memories + * - Interrupts and flags management + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup FSMC + * @brief FSMC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* --------------------- FSMC registers bit mask ---------------------------- */ +/* FSMC BCRx Mask */ +#define BCR_MBKEN_SET ((uint32_t)0x00000001) +#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_SET ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_SET ((uint32_t)0x00000004) +#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_SET ((uint32_t)0x00000040) +#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) +#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FSMC_Private_Functions + * @{ + */ + +/** @defgroup FSMC_Group1 NOR/SRAM Controller functions + * @brief NOR/SRAM Controller functions + * +@verbatim + =============================================================================== + NOR/SRAM Controller functions + =============================================================================== + + The following sequence should be followed to configure the FSMC to interface with + SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: + + 1. Enable the clock for the FSMC and associated GPIOs using the following functions: + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + 2. FSMC pins configuration + - Connect the involved FSMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); + - Configure these FSMC pins in alternate function mode by calling the function + GPIO_Init(); + + 3. Declare a FSMC_NORSRAMInitTypeDef structure, for example: + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + and fill the FSMC_NORSRAMInitStructure variable with the allowed values of + the structure member. + + 4. Initialize the NOR/SRAM Controller by calling the function + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + 5. Then enable the NOR/SRAM Bank, for example: + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); + + 6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @retval None + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure + * that contains the configuration information for the FSMC NOR/SRAM + * specified Banks. + * @retval None + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; + } + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/** + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; + } +} +/** + * @} + */ + +/** @defgroup FSMC_Group2 NAND Controller functions + * @brief NAND Controller functions + * +@verbatim + =============================================================================== + NAND Controller functions + =============================================================================== + + The following sequence should be followed to configure the FSMC to interface with + 8-bit or 16-bit NAND memory connected to the NAND Bank: + + 1. Enable the clock for the FSMC and associated GPIOs using the following functions: + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + 2. FSMC pins configuration + - Connect the involved FSMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); + - Configure these FSMC pins in alternate function mode by calling the function + GPIO_Init(); + + 3. Declare a FSMC_NANDInitTypeDef structure, for example: + FSMC_NANDInitTypeDef FSMC_NANDInitStructure; + and fill the FSMC_NANDInitStructure variable with the allowed values of + the structure member. + + 4. Initialize the NAND Controller by calling the function + FSMC_NANDInit(&FSMC_NANDInitStructure); + + 5. Then enable the NAND Bank, for example: + FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); + + 6. At this stage you can read/write from/to the memory connected to the NAND Bank. + +@note To enable the Error Correction Code (ECC), you have to use the function + FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); + and to get the current ECC value you have to use the function + ECCval = FSMC_GetECC(FSMC_Bank3_NAND); + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval None + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Initializes the FSMC NAND Banks according to the specified parameters + * in the FSMC_NANDInitStruct. + * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that + * contains the configuration information for the FSMC NAND specified Banks. + * @retval None + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MEMORYTYPE_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + + +/** + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which + * will be initialized. + * @retval None + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_SET; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_SET; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET; + } + } +} +/** + * @brief Enables or disables the FSMC NAND ECC feature. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_SET; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_SET; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} +/** + * @} + */ + +/** @defgroup FSMC_Group3 PCCARD Controller functions + * @brief PCCARD Controller functions + * +@verbatim + =============================================================================== + PCCARD Controller functions + =============================================================================== + + The following sequence should be followed to configure the FSMC to interface with + 16-bit PC Card compatible memory connected to the PCCARD Bank: + + 1. Enable the clock for the FSMC and associated GPIOs using the following functions: + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + + 2. FSMC pins configuration + - Connect the involved FSMC pins to AF12 using the following function + GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); + - Configure these FSMC pins in alternate function mode by calling the function + GPIO_Init(); + + 3. Declare a FSMC_PCCARDInitTypeDef structure, for example: + FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; + and fill the FSMC_PCCARDInitStructure variable with the allowed values of + the structure member. + + 4. Initialize the PCCARD Controller by calling the function + FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); + + 5. Then enable the PCCARD Bank: + FSMC_PCCARDCmd(ENABLE); + + 6. At this stage you can read/write from/to the memory connected to the PCCARD Bank. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FSMC PCCARD Bank according to the specified parameters + * in the FSMC_PCCARDInitStruct. + * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure + * that contains the configuration information for the FSMC PCCARD Bank. + * @retval None + */ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FSMC_PCCARDInitStruct member with its default value. + * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure + * which will be initialized. + * @retval None + */ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_SET; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET; + } +} +/** + * @} + */ + +/** @defgroup FSMC_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified FSMC interrupts. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @param NewState: new state of the specified FSMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FSMC flag is set or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. + * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. + * @retval The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FSMC's pending flags. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. + * @retval None + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/** + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FSMC's interrupt pending bits. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval None + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c new file mode 100644 index 000000000..aaf8dcb4d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c @@ -0,0 +1,566 @@ +/** + ****************************************************************************** + * @file stm32f2xx_gpio.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the GPIO peripheral: + * - Initialization and Configuration + * - GPIO Read and Write + * - GPIO Alternate functions configuration + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable the GPIO AHB clock using the following function + * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); + * + * 2. Configure the GPIO pin(s) using GPIO_Init() + * Four possible configuration are available for each pin: + * - Input: Floating, Pull-up, Pull-down. + * - Output: Push-Pull (Pull-up, Pull-down or no Pull) + * Open Drain (Pull-up, Pull-down or no Pull). + * In output mode, the speed is configurable: 2 MHz, 25 MHz, + * 50 MHz or 100 MHz. + * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) + * Open Drain (Pull-up, Pull-down or no Pull). + * - Analog: required mode when a pin is to be used as ADC channel + * or DAC output. + * + * 3- Peripherals alternate function: + * - For ADC and DAC, configure the desired pin in analog mode using + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; + * - For other peripherals (TIM, USART...): + * - Connect the pin to the desired peripherals' Alternate + * Function (AF) using GPIO_PinAFConfig() function + * - Configure the desired pin in alternate function mode using + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * + * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() + * + * 5. To set/reset the level of a pin configured in output mode use + * GPIO_SetBits()/GPIO_ResetBits() + * + * 6. During and just after reset, the alternate functions are not + * active and the GPIO pins are configured in input floating mode + * (except JTAG pins). + * + * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as + * general-purpose (PC14 and PC15, respectively) when the LSE + * oscillator is off. The LSE has priority over the GPIO function. + * + * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as + * general-purpose PH0 and PH1, respectively, when the HSE + * oscillator is off. The HSE has priority over the GPIO function. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** @defgroup GPIO_Group1 Initialization and Configuration + * @brief Initialization and Configuration + * +@verbatim + =============================================================================== + Initialization and Configuration + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); + } + else if (GPIOx == GPIOG) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); + } + else if (GPIOx == GPIOH) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); + } + else + { + if (GPIOx == GPIOI) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); + } + } +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + + /* -------------------------Configure the port pins---------------- */ + /*-- GPIO Mode Configuration --*/ + for (pinpos = 0x00; pinpos < 0x10; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); + GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); + + if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) + { + /* Check Speed mode parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + + /* Speed mode configuration */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); + GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); + + /* Check Output mode parameters */ + assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); + + /* Output mode configuration*/ + GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; + GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); + } + + /* Pull-up Pull down resistor configuration*/ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); + GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); + } + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; + GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group2 GPIO Read and Write + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + GPIO Read and Write + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @note This functions uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRL = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @note This functions uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRRH = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRRL = GPIO_Pin; + } + else + { + GPIOx->BSRRH = GPIO_Pin ; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Toggles the specified GPIO pins.. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR ^= GPIO_Pin; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function + * @brief GPIO Alternate functions configuration function + * +@verbatim + =============================================================================== + GPIO Alternate functions configuration function + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_PinSource: specifies the pin for the Alternate function. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @param GPIO_AFSelection: selects the pin to used as Alternate function. + * This parameter can be one of the following values: + * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) + * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) + * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) + * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) + * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) + * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 + * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 + * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 + * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 + * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 + * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 + * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 + * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 + * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 + * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 + * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 + * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 + * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 + * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 + * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 + * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 + * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 + * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 + * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 + * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 + * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 + * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 + * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 + * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 + * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 + * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 + * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 + * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 + * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 + * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 + * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 + * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 + * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 + * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 + * @retval None + */ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) +{ + uint32_t temp = 0x00; + uint32_t temp_2 = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + assert_param(IS_GPIO_AF(GPIO_AF)); + + temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; + temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; + GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c new file mode 100644 index 000000000..74ac28047 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c @@ -0,0 +1,706 @@ +/** + ****************************************************************************** + * @file stm32f2xx_hash.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the HASH / HMAC Processor (HASH) peripheral: + * - Initialization and Configuration functions + * - Message Digest generation functions + * - context swapping functions + * - DMA interface function + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * HASH operation : + * ---------------- + * 1. Enable the HASH controller clock using + * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. + * + * 2. Initialise the HASH using HASH_Init() function. + * + * 3 . Reset the HASH processor core, so that the HASH will be ready + * to compute he message digest of a new message by using + * HASH_Reset() function. + * + * 4. Enable the HASH controller using the HASH_Cmd() function. + * + * 5. if using DMA for Data input transfer, Activate the DMA Request + * using HASH_DMACmd() function + * + * 6. if DMA is not used for data transfer, use HASH_DataIn() function + * to enter data to IN FIFO. + * + * + * 7. Configure the Number of valid bits in last word of the message + * using HASH_SetLastWordValidBitsNbr() function. + * + * 8. if the message length is not an exact multiple of 512 bits, + * then the function HASH_StartDigest() must be called to + * launch the computation of the final digest. + * + * 9. Once computed, the digest can be read using HASH_GetDigest() + * function. + * + * 10. To control HASH events you can use one of the following + * two methods: + * a- Check on HASH flags using the HASH_GetFlagStatus() function. + * b- Use HASH interrupts through the function HASH_ITConfig() at + * initialization phase and HASH_GetITStatus() function into + * interrupt routines in hashing phase. + * After checking on a flag you should clear it using HASH_ClearFlag() + * function. And after checking on an interrupt event you should + * clear it using HASH_ClearITPendingBit() function. + * + * 11. Save and restore hash processor context using + * HASH_SaveContext() and HASH_RestoreContext() functions. + * + * + * + * HMAC operation : + * ---------------- + * The HMAC algorithm is used for message authentication, by + * irreversibly binding the message being processed to a key chosen + * by the user. + * For HMAC specifications, refer to "HMAC: keyed-hashing for message + * authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" + * + * Basically, the HMAC algorithm consists of two nested hash operations: + * HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] + * where: + * - "pad" is a sequence of zeroes needed to extend the key to the + * length of the underlying hash function data block (that is + * 512 bits for both the SHA-1 and MD5 hash algorithms) + * - "|" represents the concatenation operator + * + * + * To compute the HMAC, four different phases are required: + * + * 1. Initialise the HASH using HASH_Init() function to do HMAC + * operation. + * + * 2. The key (to be used for the inner hash function) is then given + * to the core. This operation follows the same mechanism as the + * one used to send the message in the hash operation (that is, + * by HASH_DataIn() function and, finally, + * HASH_StartDigest() function. + * + * 3. Once the last word has been entered and computation has started, + * the hash processor elaborates the key. It is then ready to + * accept the message text using the same mechanism as the one + * used to send the message in the hash operation. + * + * 4. After the first hash round, the hash processor returns "ready" + * to indicate that it is ready to receive the key to be used for + * the outer hash function (normally, this key is the same as the + * one used for the inner hash function). When the last word of + * the key is entered and computation starts, the HMAC result is + * made available using HASH_GetDigest() function. + * + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_hash.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup HASH + * @brief HASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HASH_Private_Functions + * @{ + */ + +/** @defgroup HASH_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + This section provides functions allowing to + - Initialize the HASH peripheral + - Configure the HASH Processor + - MD5/SHA1, + - HASH/HMAC, + - datatype + - HMAC Key (if mode = HMAC) + - Reset the HASH Processor + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the HASH peripheral registers to their default reset values + * @param None + * @retval None + */ +void HASH_DeInit(void) +{ + /* Enable HASH reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE); + /* Release HASH from reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE); +} + +/** + * @brief Initializes the HASH peripheral according to the specified parameters + * in the HASH_InitStruct structure. + * @note the hash processor is reset when calling this function so that the + * HASH will be ready to compute the message digest of a new message. + * There is no need to call HASH_Reset() function. + * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains + * the configuration information for the HASH peripheral. + * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only + * if the algorithm mode is HMAC. + * @retval None + */ +void HASH_Init(HASH_InitTypeDef* HASH_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection)); + assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType)); + assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode)); + + /* Configure the Algorithm used, algorithm mode and the datatype */ + HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE); + HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \ + HASH_InitStruct->HASH_DataType | \ + HASH_InitStruct->HASH_AlgoMode); + + /* if algorithm mode is HMAC, set the Key */ + if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) + { + assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType)); + HASH->CR &= ~HASH_CR_LKEY; + HASH->CR |= HASH_InitStruct->HASH_HMACKeyType; + } + + /* Reset the HASH processor core, so that the HASH will be ready to compute + the message digest of a new message */ + HASH->CR |= HASH_CR_INIT; +} + +/** + * @brief Fills each HASH_InitStruct member with its default value. + * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will + * be initialized. + * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1, + * Data type selected is 32b and HMAC Key Type is short key. + * @retval None + */ +void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct) +{ + /* Initialize the HASH_AlgoSelection member */ + HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1; + + /* Initialize the HASH_AlgoMode member */ + HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH; + + /* Initialize the HASH_DataType member */ + HASH_InitStruct->HASH_DataType = HASH_DataType_32b; + + /* Initialize the HASH_HMACKeyType member */ + HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; +} + +/** + * @brief Resets the HASH processor core, so that the HASH will be ready + * to compute the message digest of a new message. + * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation + * completion interrupt status) bit corresponding to HASH_IT_DCI + * interrupt and HASH_FLAG_DCIS flag. + * @param None + * @retval None + */ +void HASH_Reset(void) +{ + /* Reset the HASH processor core */ + HASH->CR |= HASH_CR_INIT; +} +/** + * @} + */ + +/** @defgroup HASH_Group2 Message Digest generation functions + * @brief Message Digest generation functions + * +@verbatim + =============================================================================== + Message Digest generation functions + =============================================================================== + This section provides functions allowing the generation of message digest: + - Push data in the IN FIFO : using HASH_DataIn() + - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() + - set the last word valid bits number using HASH_SetLastWordValidBitsNbr() + - start digest calculation : using HASH_StartDigest() + - Get the Digest message : using HASH_GetDigest() + +@endverbatim + * @{ + */ + + +/** + * @brief Configure the Number of valid bits in last word of the message + * @param ValidNumber: Number of valid bits in last word of the message. + * This parameter must be a number between 0 and 0x1F. + * - 0x00: All 32 bits of the last data written are valid + * - 0x01: Only bit [0] of the last data written is valid + * - 0x02: Only bits[1:0] of the last data written are valid + * - 0x03: Only bits[2:0] of the last data written are valid + * - ... + * - 0x1F: Only bits[30:0] of the last data written are valid + * @note The Number of valid bits must be set before to start the message + * digest competition (in Hash and HMAC) and key treatment(in HMAC). + * @retval None + */ +void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber) +{ + /* Check the parameters */ + assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber)); + + /* Configure the Number of valid bits in last word of the message */ + HASH->STR &= ~(HASH_STR_NBW); + HASH->STR |= ValidNumber; +} + +/** + * @brief Writes data in the Data Input FIFO + * @param Data: new data of the message to be processed. + * @retval None + */ +void HASH_DataIn(uint32_t Data) +{ + /* Write in the DIN register a new data */ + HASH->DIN = Data; +} + +/** + * @brief Returns the number of words already pushed into the IN FIFO. + * @param None + * @retval The value of words already pushed into the IN FIFO. + */ +uint8_t HASH_GetInFIFOWordsNbr(void) +{ + /* Return the value of NBW bits */ + return ((HASH->CR & HASH_CR_NBW) >> 8); +} + +/** + * @brief Provides the message digest result. + * @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used + * and is read as zero. + * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will + * hold the message digest result + * @retval None + */ +void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest) +{ + /* Get the data field */ + HASH_MessageDigest->Data[0] = HASH->HR[0]; + HASH_MessageDigest->Data[1] = HASH->HR[1]; + HASH_MessageDigest->Data[2] = HASH->HR[2]; + HASH_MessageDigest->Data[3] = HASH->HR[3]; + HASH_MessageDigest->Data[4] = HASH->HR[4]; +} + +/** + * @brief Starts the message padding and calculation of the final message + * @param None + * @retval None + */ +void HASH_StartDigest(void) +{ + /* Start the Digest calculation */ + HASH->STR |= HASH_STR_DCAL; +} +/** + * @} + */ + +/** @defgroup HASH_Group3 Context swapping functions + * @brief Context swapping functions + * +@verbatim + =============================================================================== + Context swapping functions + =============================================================================== + + This section provides functions allowing to save and store HASH Context + + It is possible to interrupt a HASH/HMAC process to perform another processing + with a higher priority, and to complete the interrupted process later on, when + the higher priority task is complete. To do so, the context of the interrupted + task must be saved from the HASH registers to memory, and then be restored + from memory to the HASH registers. + + 1. To save the current context, use HASH_SaveContext() function + 2. To restore the saved context, use HASH_RestoreContext() function + + +@endverbatim + * @{ + */ + +/** + * @brief Save the Hash peripheral Context. + * @note The context can be saved only when no block is currently being + * processed. So user must wait for DINIS = 1 (the last block has been + * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not + * full and no processing is ongoing). + * @param HASH_ContextSave: pointer to a HASH_Context structure that contains + * the repository for current context. + * @retval None + */ +void HASH_SaveContext(HASH_Context* HASH_ContextSave) +{ + uint8_t i = 0; + + /* save context registers */ + HASH_ContextSave->HASH_IMR = HASH->IMR; + HASH_ContextSave->HASH_STR = HASH->STR; + HASH_ContextSave->HASH_CR = HASH->CR; + for(i=0; i<=50;i++) + { + HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; + } +} + +/** + * @brief Restore the Hash peripheral Context. + * @note After calling this function, user can restart the processing from the + * point where it has been interrupted. + * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains + * the repository for saved context. + * @retval None + */ +void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) +{ + uint8_t i = 0; + + /* restore context registers */ + HASH->IMR = HASH_ContextRestore->HASH_IMR; + HASH->STR = HASH_ContextRestore->HASH_STR; + HASH->CR = HASH_ContextRestore->HASH_CR; + + /* Initialize the hash processor */ + HASH->CR |= HASH_CR_INIT; + + /* continue restoring context registers */ + for(i=0; i<=50;i++) + { + HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; + } +} +/** + * @} + */ + +/** @defgroup HASH_Group4 HASH's DMA interface Configuration function + * @brief HASH's DMA interface Configuration function + * +@verbatim + =============================================================================== + HASH's DMA interface Configuration function + =============================================================================== + + This section provides functions allowing to configure the DMA interface for + HASH/ HMAC data input transfer. + + When the DMA mode is enabled (using the HASH_DMACmd() function), data can be + sent to the IN FIFO using the DMA peripheral. + + + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the HASH DMA interface. + * @note The DMA is disabled by hardware after the end of transfer. + * @param NewState: new state of the selected HASH DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void HASH_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the HASH DMA request */ + HASH->CR |= HASH_CR_DMAE; + } + else + { + /* Disable the HASH DMA request */ + HASH->CR &= ~HASH_CR_DMAE; + } +} +/** + * @} + */ + +/** @defgroup HASH_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides functions allowing to configure the HASH Interrupts and + to get the status and clear flags and Interrupts pending bits. + + The HASH provides 2 Interrupts sources and 5 Flags: + + Flags : + ---------- + 1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO + which means that a new block (512 bit) can be entered + into the input buffer. + + 2. HASH_FLAG_DCIS : set when Digest calculation is complete + + 3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or + a transfer is ongoing. + This Flag is cleared only by hardware. + + 4. HASH_FLAG_BUSY : set when The hash core is processing a block of data + This Flag is cleared only by hardware. + + 5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that + the Data IN FIFO contains at least one word of data. + This Flag is cleared only by hardware. + + Interrupts : + ------------ + + 1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16 + locations are free in the Data IN FIFO which means that + a new block (512 bit) can be entered into the input buffer. + This interrupt source is cleared using + HASH_ClearITPendingBit(HASH_IT_DINI) function. + + 2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest + calculation is complete. + This interrupt source is cleared using + HASH_ClearITPendingBit(HASH_IT_DCI) function. + + Managing the HASH controller events : + ------------------------------------ + The user should identify which mode will be used in his application to manage + the HASH controller events: Polling mode or Interrupt mode. + + 1. In the Polling Mode it is advised to use the following functions: + - HASH_GetFlagStatus() : to check if flags events occur. + - HASH_ClearFlag() : to clear the flags events. + + 2. In the Interrupt Mode it is advised to use the following functions: + - HASH_ITConfig() : to enable or disable the interrupt source. + - HASH_GetITStatus() : to check if Interrupt occurs. + - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified HASH interrupts. + * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg HASH_IT_DINI: Data Input interrupt + * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt + * @param NewState: new state of the specified HASH interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_HASH_IT(HASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected HASH interrupt */ + HASH->IMR |= HASH_IT; + } + else + { + /* Disable the selected HASH interrupt */ + HASH->IMR &= (uint8_t) ~HASH_IT; + } +} + +/** + * @brief Checks whether the specified HASH flag is set or not. + * @param HASH_FLAG: specifies the HASH flag to check. + * This parameter can be one of the following values: + * @arg HASH_FLAG_DINIS: Data input interrupt status flag + * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag + * @arg HASH_FLAG_BUSY: Busy flag + * @arg HASH_FLAG_DMAS: DMAS Status flag + * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag + * @retval The new state of HASH_FLAG (SET or RESET) + */ +FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tempreg = 0; + + /* Check the parameters */ + assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); + + /* check if the FLAG is in CR register */ + if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET ) + { + tempreg = HASH->CR; + } + else /* The FLAG is in SR register */ + { + tempreg = HASH->SR; + } + + /* Check the status of the specified HASH flag */ + if ((tempreg & HASH_FLAG) != (uint16_t)RESET) + { + /* HASH is set */ + bitstatus = SET; + } + else + { + /* HASH_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the HASH_FLAG status */ + return bitstatus; +} +/** + * @brief Clears the HASH flags. + * @param HASH_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg HASH_FLAG_DINIS: Data Input Flag + * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag + * @retval None + */ +void HASH_ClearFlag(uint16_t HASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); + + /* Clear the selected HASH flags */ + HASH->SR = ~(uint32_t)HASH_FLAG; +} +/** + * @brief Checks whether the specified HASH interrupt has occurred or not. + * @param HASH_IT: specifies the HASH interrupt source to check. + * This parameter can be one of the following values: + * @arg HASH_IT_DINI: Data Input interrupt + * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt + * @retval The new state of HASH_IT (SET or RESET). + */ +ITStatus HASH_GetITStatus(uint8_t HASH_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_HASH_GET_IT(HASH_IT)); + + + /* Check the status of the specified HASH interrupt */ + tmpreg = HASH->SR; + + if (((HASH->IMR & tmpreg) & HASH_IT) != RESET) + { + /* HASH_IT is set */ + bitstatus = SET; + } + else + { + /* HASH_IT is reset */ + bitstatus = RESET; + } + /* Return the HASH_IT status */ + return bitstatus; +} + +/** + * @brief Clears the HASH interrupt pending bit(s). + * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear. + * This parameter can be any combination of the following values: + * @arg HASH_IT_DINI: Data Input interrupt + * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt + * @retval None + */ +void HASH_ClearITPendingBit(uint8_t HASH_IT) +{ + /* Check the parameters */ + assert_param(IS_HASH_IT(HASH_IT)); + + /* Clear the selected HASH interrupt pending bit */ + HASH->SR = (uint8_t)~HASH_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c new file mode 100644 index 000000000..6cb343737 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c @@ -0,0 +1,320 @@ +/** + ****************************************************************************** + * @file stm32f2xx_hash_md5.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides high level functions to compute the HASH MD5 and + * HMAC MD5 Digest of an input message. + * It uses the stm32f2xx_hash.c/.h drivers to access the STM32F2xx HASH + * peripheral. + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable The HASH controller clock using + * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. + * + * 2. Calculate the HASH MD5 Digest using HASH_MD5() function. + * + * 3. Calculate the HMAC MD5 Digest using HMAC_MD5() function. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_hash.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup HASH + * @brief HASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HASH_Private_Functions + * @{ + */ + +/** @defgroup HASH_Group7 High Level MD5 functions + * @brief High Level MD5 Hash and HMAC functions + * +@verbatim + =============================================================================== + High Level MD5 Hash and HMAC functions + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Compute the HASH MD5 digest. + * @param Input: pointer to the Input buffer to be treated. + * @param Ilen: length of the Input buffer. + * @param Output: the returned digest + * @retval An ErrorStatus enumeration value: + * - SUCCESS: digest computation done + * - ERROR: digest computation failed + */ +ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]) +{ + HASH_InitTypeDef MD5_HASH_InitStructure; + HASH_MsgDigest MD5_MessageDigest; + __IO uint16_t nbvalidbitsdata = 0; + uint32_t i = 0; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + + + /* Number of valid bits in last word of the Input data */ + nbvalidbitsdata = 8 * (Ilen % 4); + + /* HASH peripheral initialization */ + HASH_DeInit(); + + /* HASH Configuration */ + MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; + MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; + MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; + HASH_Init(&MD5_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the data */ + HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); + + /* Write the Input block in the IN FIFO */ + for(i=0; i 64) + { + /* HMAC long Key */ + MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; + } + else + { + /* HMAC short Key */ + MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; + } + HASH_Init(&MD5_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the Key */ + HASH_SetLastWordValidBitsNbr(nbvalidbitskey); + + /* Write the Key */ + for(i=0; i
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_hash.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup HASH + * @brief HASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HASH_Private_Functions + * @{ + */ + +/** @defgroup HASH_Group6 High Level SHA1 functions + * @brief High Level SHA1 Hash and HMAC functions + * +@verbatim + =============================================================================== + High Level SHA1 Hash and HMAC functions + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Compute the HASH SHA1 digest. + * @param Input: pointer to the Input buffer to be treated. + * @param Ilen: length of the Input buffer. + * @param Output: the returned digest + * @retval An ErrorStatus enumeration value: + * - SUCCESS: digest computation done + * - ERROR: digest computation failed + */ +ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) +{ + HASH_InitTypeDef SHA1_HASH_InitStructure; + HASH_MsgDigest SHA1_MessageDigest; + __IO uint16_t nbvalidbitsdata = 0; + uint32_t i = 0; + __IO uint32_t counter = 0; + uint32_t busystatus = 0; + ErrorStatus status = SUCCESS; + uint32_t inputaddr = (uint32_t)Input; + uint32_t outputaddr = (uint32_t)Output; + + /* Number of valid bits in last word of the Input data */ + nbvalidbitsdata = 8 * (Ilen % 4); + + /* HASH peripheral initialization */ + HASH_DeInit(); + + /* HASH Configuration */ + SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; + SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; + SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; + HASH_Init(&SHA1_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the data */ + HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); + + /* Write the Input block in the IN FIFO */ + for(i=0; i 64) + { + /* HMAC long Key */ + SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; + } + else + { + /* HMAC short Key */ + SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; + } + HASH_Init(&SHA1_HASH_InitStructure); + + /* Configure the number of valid bits in last word of the Key */ + HASH_SetLastWordValidBitsNbr(nbvalidbitskey); + + /* Write the Key */ + for(i=0; iGPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * Recommended configuration is Push-Pull, Pull-up, Open-Drain. + * Add an external pull up if necessary (typically 4.7 KOhm). + * + * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged + * Address using the I2C_Init() function. + * + * 5. Optionally you can enable/configure the following parameters without + * re-initialization (i.e there is no need to call again I2C_Init() function): + * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function + * - Enable the dual addressing mode using I2C_DualAddressCmd() function + * - Enable the general call using the I2C_GeneralCallCmd() function + * - Enable the clock stretching using I2C_StretchClockCmd() function + * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() + * function. + * - Configure the NACK position for Master Receiver mode in case of + * 2 bytes reception using the function I2C_NACKPositionConfig(). + * - Enable the PEC Calculation using I2C_CalculatePEC() function + * - For SMBus Mode: + * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function + * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function + * + * 6. Enable the NVIC and the corresponding interrupt using the function + * I2C_ITConfig() if you need to use interrupt mode. + * + * 7. When using the DMA mode + * - Configure the DMA using DMA_Init() function + * - Active the needed channel Request using I2C_DMACmd() or + * I2C_DMALastTransferCmd() function. + * @note When using DMA mode, I2C interrupts may be used at the same time to + * control the communication flow (Start/Stop/Ack... events and errors). + * + * 8. Enable the I2C using the I2C_Cmd() function. + * + * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the + * transfers. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TRISE */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral + input clock) must be a multiple of 10 MHz */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + + /* Test if CCR value is under 0x1*/ + if ((result & I2C_CCR_CCR) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= (uint16_t)(result | I2C_CCR_FS); + /* Set Maximum Rise Time for fast mode */ + I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= I2C_CR1_START; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= I2C_CR1_STOP; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); + } +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param Address: specifies the slave address which will be transmitted + * @param I2C_Direction: specifies whether the I2C device will be a Transmitter + * or a Receiver. + * This parameter can be one of the following values + * @arg I2C_Direction_Transmitter: Transmitter mode + * @arg I2C_Direction_Receiver: Receiver mode + * @retval None. + */ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= I2C_OAR1_ADD0; + } + else + { + /* Reset the address bit0 for write */ + Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= I2C_CR1_ACK; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param Address: specifies the 7bit I2C own address2. + * @retval None. + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); + + /* Set I2Cx Own address2 */ + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= I2C_OAR2_ENDUAL; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= I2C_CR1_ENGC; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); + } +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @note When software reset is enabled, the I2C IOs are released (this can + * be useful to recover from bus errors). + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= I2C_CR1_SWRST; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= I2C_CR1_NOSTRETCH; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_DutyCycle: specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 + * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @retval None + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + +/** + * @brief Selects the specified I2C NACK position in master receiver mode. + * @note This function is useful in I2C Master Receiver mode when the number + * of data to be received is equal to 2. In this case, this function + * should be called (with parameter I2C_NACKPosition_Next) before data + * reception starts,as described in the 2-byte reception procedure + * recommended in Reference Manual in Section: Master receiver. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_NACKPosition: specifies the NACK position. + * This parameter can be one of the following values: + * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last + * received byte. + * @arg I2C_NACKPosition_Current: indicates that current byte is the last + * received byte. + * + * @note This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * + * @retval None + */ +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); + + /* Check the input parameter */ + if (I2C_NACKPosition == I2C_NACKPosition_Next) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CR1 |= I2C_NACKPosition_Next; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CR1 &= I2C_NACKPosition_Current; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_SMBusAlert: specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low + * @arg I2C_SMBusAlert_High: SMBAlert pin driven high + * @retval None + */ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= I2C_CR1_ENARP; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); + } +} +/** + * @} + */ + +/** @defgroup I2C_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + Data transfers functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @} + */ + +/** @defgroup I2C_Group3 PEC management functions + * @brief PEC management functions + * +@verbatim + =============================================================================== + PEC management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= I2C_CR1_PEC; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_PECPosition: specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PECPosition_Next: indicates that the next byte is PEC + * @arg I2C_PECPosition_Current: indicates that current byte is PEC + * + * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() + * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() + * is intended to used in I2C mode. + * + * @retval None + */ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* Next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= I2C_CR1_ENPEC; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @retval The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->SR2) >> 8); +} + +/** + * @} + */ + +/** @defgroup I2C_Group4 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + DMA transfers management functions + =============================================================================== + This section provides functions allowing to configure the I2C DMA channels + requests. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); + } +} + +/** + * @brief Specifies that the next DMA transfer is the last one. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CR2 |= I2C_CR2_LAST; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); + } +} + +/** + * @} + */ + +/** @defgroup I2C_Group5 Interrupts events and flags management functions + * @brief Interrupts, events and flags management functions + * +@verbatim + =============================================================================== + Interrupts, events and flags management functions + =============================================================================== + This section provides functions allowing to configure the I2C Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + =============================================================================== + I2C State Monitoring Functions + =============================================================================== + This I2C driver provides three different ways for I2C state monitoring + depending on the application requirements and constraints: + + + 1. Basic state monitoring (Using I2C_CheckEvent() function) + ----------------------------------------------------------- + It compares the status registers (SR1 and SR2) content to a given event + (can be the combination of one or more flags). + It returns SUCCESS if the current status includes the given flags + and returns ERROR if one or more flags are missing in the current status. + + - When to use + - This function is suitable for most applications as well as for startup + activity since the events are fully described in the product reference + manual (RM0033). + - It is also suitable for users who need to define their own events. + + - Limitations + - If an error occurs (ie. error flags are set besides to the monitored + flags), the I2C_CheckEvent() function may return SUCCESS despite + the communication hold or corrupted real state. + In this case, it is advised to use error interrupts to monitor + the error events and handle them in the interrupt IRQ handler. + + @note + For error management, it is advised to use the following functions: + - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + Where x is the peripheral instance (I2C1, I2C2 ...) + - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the + I2Cx_ER_IRQHandler() function in order to determine which error occurred. + - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + and/or I2C_GenerateStop() in order to clear the error flag and source + and return to correct communication status. + + + 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) + -------------------------------------------------------------------- + Using the function I2C_GetLastEvent() which returns the image of both status + registers in a single word (uint32_t) (Status Register 2 value is shifted left + by 16 bits and concatenated to Status Register 1). + + - When to use + - This function is suitable for the same applications above but it + allows to overcome the mentioned limitation of I2C_GetFlagStatus() + function. + - The returned value could be compared to events already defined in + the library (stm32f2xx_i2c.h) or to custom values defined by user. + This function is suitable when multiple flags are monitored at the + same time. + - At the opposite of I2C_CheckEvent() function, this function allows + user to choose when an event is accepted (when all events flags are + set and no other flags are set or just when the needed flags are set + like I2C_CheckEvent() function. + + - Limitations + - User may need to define his own events. + - Same remark concerning the error management is applicable for this + function if user decides to check only regular communication flags + (and ignores error flags). + + + 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) + ----------------------------------------------------------------------- + + Using the function I2C_GetFlagStatus() which simply returns the status of + one single flag (ie. I2C_FLAG_RXNE ...). + + - When to use + - This function could be used for specific applications or in debug + phase. + - It is suitable when only one flag checking is needed (most I2C + events are monitored through multiple flags). + - Limitations: + - When calling this function, the Status register is accessed. + Some flags are cleared when the status register is accessed. + So checking the status of one Flag, may clear other ones. + - Function may need to be called twice or more in order to monitor + one single event. + + For detailed description of Events, please refer to section I2C_Events in + stm32f2xx_i2c.h file. + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_BUF: Buffer interrupt mask + * @arg I2C_IT_EVT: Event interrupt mask + * @arg I2C_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (uint16_t)~I2C_IT; + } +} + +/* + =============================================================================== + 1. Basic state monitoring + =============================================================================== + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9 + * + * @note For detailed description of Events, please refer to section I2C_Events + * in stm32f2xx_i2c.h file. + * + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/* + =============================================================================== + 2. Advanced state monitoring + =============================================================================== + */ + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * + * @note For detailed description of Events, please refer to section I2C_Events + * in stm32f2xx_i2c.h file. + * + * @retval The last event + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_MASK; + + /* Return status */ + return lastevent; +} + +/* + =============================================================================== + 3. Flag-based state monitoring + =============================================================================== + */ + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_FLAG_SB: Start bit flag (Master mode) + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_MASK; + + if(i2creg != 0) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx SR2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx SR2 register address */ + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @note STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * @note ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DR register. + * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * @note ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR + * register (I2C_SendData()). + * + * @retval None + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_MASK; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert flag + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_IT_PECERR: PEC error in reception flag + * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure flag + * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_IT_BERR: Bus error flag + * @arg I2C_IT_TXE: Data register empty flag (Transmitter) + * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag + * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) + * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_IT_BTF: Byte transfer finished flag + * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_IT_SB: Start bit flag (Master mode) + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_MASK; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's interrupt pending bits. + * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert interrupt + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt + * @arg I2C_IT_PECERR: PEC error in reception interrupt + * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure interrupt + * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) + * @arg I2C_IT_BERR: Bus error interrupt + * + * @note STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * @note ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DR register. + * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * @note ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * @note SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DR register (I2C_SendData()). + * @retval None + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_MASK; + + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c new file mode 100644 index 000000000..de89eac04 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c @@ -0,0 +1,269 @@ +/** + ****************************************************************************** + * @file stm32f2xx_iwdg.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Independent watchdog (IWDG) peripheral: + * - Prescaler and Counter configuration + * - IWDG activation + * - Flag management + * + * @verbatim + * + * =================================================================== + * IWDG features + * =================================================================== + * + * The IWDG can be started by either software or hardware (configurable + * through option byte). + * + * The IWDG is clocked by its own dedicated low-speed clock (LSI) and + * thus stays active even if the main clock fails. + * Once the IWDG is started, the LSI is forced ON and cannot be disabled + * (LSI cannot be disabled too), and the counter starts counting down from + * the reset value of 0xFFF. When it reaches the end of count value (0x000) + * a system reset is generated. + * The IWDG counter should be reloaded at regular intervals to prevent + * an MCU reset. + * + * The IWDG is implemented in the VDD voltage domain that is still functional + * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + * + * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG + * reset occurs. + * + * Min-max timeout value @32KHz (LSI): ~125us / ~32.7s + * The IWDG timeout may vary due to LSI frequency dispersion. STM32F2xx + * devices provide the capability to measure the LSI frequency (LSI clock + * connected internally to TIM5 CH4 input capture). The measured value + * can be used to have an IWDG timeout with an acceptable accuracy. + * For more information, please refer to the STM32F2xx Reference manual + * + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable write access to IWDG_PR and IWDG_RLR registers using + * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function + * + * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function + * + * 3. Configure the IWDG counter value using IWDG_SetReload() function. + * This value will be loaded in the IWDG counter each time the counter + * is reloaded, then the IWDG will start counting down from this value. + * + * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used + * in software mode (no need to enable the LSI, it will be enabled + * by hardware) + * + * 5. Then the application program must reload the IWDG counter at regular + * intervals during normal operation to prevent an MCU reset, using + * IWDG_ReloadCounter() function. + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_iwdg.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_RELOAD ((uint16_t)0xAAAA) +#define KR_KEY_ENABLE ((uint16_t)0xCCCC) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions + * @brief Prescaler and Counter configuration functions + * +@verbatim + =============================================================================== + Prescaler and Counter configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_RELOAD; +} + +/** + * @} + */ + +/** @defgroup IWDG_Group2 IWDG activation function + * @brief IWDG activation function + * +@verbatim + =============================================================================== + IWDG activation function + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_ENABLE; +} + +/** + * @} + */ + +/** @defgroup IWDG_Group3 Flag management function + * @brief Flag management function + * +@verbatim + =============================================================================== + Flag management function + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c new file mode 100644 index 000000000..1c84cf75d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c @@ -0,0 +1,620 @@ +/** + ****************************************************************************** + * @file stm32f2xx_pwr.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * - Backup Domain Access + * - PVD configuration + * - WakeUp pin configuration + * - Backup Regulator configuration + * - FLASH Power Down configuration + * - Low Power modes configuration + * - Flags management + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* Alias word address of FPDS bit */ +#define FPDS_BitNumber 0x09 +#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* Alias word address of BRE bit */ +#define BRE_BitNumber 0x09 +#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** @defgroup PWR_Group1 Backup Domain Access function + * @brief Backup Domain Access function + * +@verbatim + =============================================================================== + Backup Domain Access function + =============================================================================== + + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + - Enable the Power Controller (PWR) APB1 interface clock using the + RCC_APB1PeriphClockCmd() function. + - Enable access to RTC domain using the PWR_BackupAccessCmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @param NewState: new state of the access to the backup domain. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group2 PVD configuration functions + * @brief PVD configuration functions + * +@verbatim + =============================================================================== + PVD configuration functions + =============================================================================== + + - The PVD is used to monitor the VDD power supply by comparing it to a threshold + selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the + PVD threshold. This event is internally connected to the EXTI line16 + and can generate an interrupt if enabled through the EXTI registers. + - The PVD is stopped in Standby mode. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_0 + * @arg PWR_PVDLevel_1 + * @arg PWR_PVDLevel_2 + * @arg PWR_PVDLevel_3 + * @arg PWR_PVDLevel_4 + * @arg PWR_PVDLevel_5 + * @arg PWR_PVDLevel_6 + * @arg PWR_PVDLevel_7 + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + + tmpreg = PWR->CR; + + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_MASK; + + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group3 WakeUp pin configuration functions + * @brief WakeUp pin configuration functions + * +@verbatim + =============================================================================== + WakeUp pin configuration functions + =============================================================================== + + - WakeUp pin is used to wakeup the system from Standby mode. This pin is + forced in input pull down configuration and is active on rising edges. + - There is only one WakeUp pin: WakeUp Pin 1 on PA.00. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group4 Backup Regulator configuration functions + * @brief Backup Regulator configuration functions + * +@verbatim + =============================================================================== + Backup Regulator configuration functions + =============================================================================== + + - The backup domain includes 4 Kbytes of backup SRAM accessible only from the + CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained + even in Standby or VBAT mode when the low power backup regulator is enabled. + It can be considered as an internal EEPROM when VBAT is always present. + You can use the PWR_BackupRegulatorCmd() function to enable the low power + backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is + ready or not. + + - When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to + save battery life. + + - The backup SRAM is not mass erased by an tamper event. It is read protected + to prevent confidential data, such as cryptographic private key, from being + accessed. The backup SRAM can be erased only through the Flash interface when + a protection level change from level 1 to level 0 is requested. + Refer to the description of Read protection (RDP) in the Flash programming manual. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the Backup Regulator. + * @param NewState: new state of the Backup Regulator. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupRegulatorCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group5 FLASH Power Down configuration functions + * @brief FLASH Power Down configuration functions + * +@verbatim + =============================================================================== + FLASH Power Down configuration functions + =============================================================================== + + - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd() + function, the Flash memory also enters power down mode when the device enters + Stop mode. When the Flash memory is in power down mode, an additional startup + delay is incurred when waking up from Stop mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the Flash Power Down in STOP mode. + * @param NewState: new state of the Flash power mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_FlashPowerDownCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup PWR_Group6 Low Power modes configuration functions + * @brief Low Power modes configuration functions + * +@verbatim + =============================================================================== + Low Power modes configuration functions + =============================================================================== + + The devices feature 3 low-power modes: + - Sleep mode: Cortex-M3 core stopped, peripherals kept running. + - Stop mode: all clocks are stopped, regulator running, regulator in low power mode + - Standby mode: 1.2V domain powered off. + + Sleep mode + =========== + - Entry: + - The Sleep mode is entered by using the __WFI() or __WFE() functions. + - Exit: + - Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + Stop mode + ========== + In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption In Stop mode, FLASH can be powered off before + entering the Stop mode. It can be switched on again by software after exiting + the Stop mode using the PWR_FlashPowerDownCmd() function. + + - Entry: + - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) + function with regulator in LowPower or with Regulator ON. + - Exit: + - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + Standby mode + ============ + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. + The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby + circuitry. + + The voltage regulator is OFF. + + - Entry: + - The Standby mode is entered using the PWR_EnterSTANDBYMode() function. + - Exit: + - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + Auto-wakeup (AWU) from low-power mode + ===================================== + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event, a time-stamp event, or a comparator event, + without depending on an external interrupt (Auto-wakeup mode). + + - RTC auto-wakeup (AWU) from the Stop mode + ---------------------------------------- + + - To wake up from the Stop mode with an RTC alarm event, it is necessary to: + - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function + - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + - To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to: + - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function + - Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: + - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function + - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), + RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + + - RTC auto-wakeup (AWU) from the Standby mode + ------------------------------------------- + - To wake up from the Standby mode with an RTC alarm event, it is necessary to: + - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function + - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + - To wake up from the Standby mode with an RTC Tamper or time stamp event, it + is necessary to: + - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function + - Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: + - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function + - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), + RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enters STOP mode. + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDSR bits */ + tmpreg &= CR_DS_MASK; + + /* Set LPDSR bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters STANDBY mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. + * - WKUP pin 1 (PA0) if enabled. + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wakeup flag */ + PWR->CR |= PWR_CR_CWUF; + + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @} + */ + +/** @defgroup PWR_Group7 Flags management functions + * @brief Flags management functions + * +@verbatim + =============================================================================== + Flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A + * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c new file mode 100644 index 000000000..a668c5a37 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c @@ -0,0 +1,1817 @@ +/** + ****************************************************************************** + * @file stm32f2xx_rcc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Reset and clock control (RCC) peripheral: + * - Internal/external clocks, PLL, CSS and MCO configuration + * - System, AHB and APB busses clocks configuration + * - Peripheral clocks configuration + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * RCC specific features + * =================================================================== + * + * After reset the device is running from Internal High Speed oscillator + * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + * and I-Cache are disabled, and all peripherals are off except internal + * SRAM, Flash and JTAG. + * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; + * all peripherals mapped on these busses are running at HSI speed. + * - The clock for all peripherals is switched off, except the SRAM and FLASH. + * - All GPIOs are in input floating state, except the JTAG pins which + * are assigned to be used for debug purpose. + * + * Once the device started from reset, the user application has to: + * - Configure the clock source to be used to drive the System clock + * (if the application needs higher frequency/performance) + * - Configure the System clock frequency and Flash settings + * - Configure the AHB and APB busses prescalers + * - Enable the clock for the peripheral(s) to be used + * - Configure the clock source(s) for peripherals which clocks are not + * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) +/* Alias word address of PLLI2SON bit */ +#define PLLI2SON_BitNumber 0x1A +#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) + +/* --- CFGR Register ---*/ +/* Alias word address of I2SSRC bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x08) +#define I2SSRC_BitNumber 0x17 +#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) + +/* --- BDCR Register ---*/ +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x70) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x74) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) +/* ---------------------- RCC registers bit mask ------------------------ */ +/* CFGR register bit mask */ +#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) +#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) + +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CR register byte 3 (Bits[23:16]) base address */ +#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions + * @brief Internal and external clocks, PLL, CSS and MCO configuration functions + * +@verbatim + =============================================================================== + Internal/external clocks, PLL, CSS and MCO configuration functions + =============================================================================== + + This section provide functions allowing to configure the internal/external clocks, + PLLs, CSS and MCO pins. + + 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + 5. PLL (clocked by HSI or HSE), featuring two different output clocks: + - The first output is used to generate the high speed system clock (up to 120 MHz) + - The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + + 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve + high-quality audio performance on the I2S interface. + + 7. CSS (Clock security system), once enable and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) + exception vector. + + 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL and PLLI2S OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the Clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint8_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; + + /* Set the new HSE configuration -------------------------------------------*/ + *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; +} + +/** + * @brief Waits for HSE start-up. + * @note This functions waits on HSERDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * HSE_STARTUP_TIMEOUT in stm32f2xx.h file. You can tailor it depending + * on the HSE crystal used in your application. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t startupcounter = 0; + ErrorStatus status = ERROR; + FlagStatus hsestatus = RESET; + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + startupcounter++; + } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->CR; + + /* Clear HSITRIM[4:0] bits */ + tmpreg &= ~RCC_CR_HSITRIM; + + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @param NewState: new state of the HSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch (RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param RCC_PLLSource: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * + * @param PLLM: specifies the division factor for PLL VCO input clock + * This parameter must be a number between 0 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + * @param PLLN: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLP: specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on + * the System clock frequency. + * + * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between 4 and 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(PLLM)); + assert_param(IS_RCC_PLLN_VALUE(PLLN)); + assert_param(IS_RCC_PLLP_VALUE(PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); + + RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | + (PLLQ << 24); +} + +/** + * @brief Enables or disables the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLLI2S clock multiplication and division factors. + * + * @note PLLI2S is available only in Silicon RevisionB and RevisionY. + * @note This function must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * + * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between 192 and 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between 192 and 432 MHz. + * + * @param PLLI2SR: specifies the division factor for I2S clock + * This parameter must be a number between 2 and 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @retval None + */ +void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); + + RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); +} + +/** + * @brief Enables or disables the PLLI2S. + * @note PLLI2S is available only in RevisionB and RevisionY + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLI2SCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. + * @param NewState: new state of the Clock Security System. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8). + * @note PA8 should be configured in alternate function mode. + * @param RCC_MCO1Source: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source + * @param RCC_MCO1Div: specifies the MCO1 prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO1Div_1: no division applied to MCO1 clock + * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock + * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock + * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock + * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock + * @retval None + */ +void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); + assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); + + tmpreg = RCC->CFGR; + + /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ + tmpreg &= CFGR_MCO1_RESET_MASK; + + /* Select MCO1 clock source and prescaler */ + tmpreg |= RCC_MCO1Source | RCC_MCO1Div; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Selects the clock source to output on MCO2 pin(PC9). + * @note PC9 should be configured in alternate function mode. + * @param RCC_MCO2Source: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source + * @param RCC_MCO2Div: specifies the MCO2 prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCO2Div_1: no division applied to MCO2 clock + * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock + * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock + * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock + * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock + * @retval None + */ +void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); + assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); + + tmpreg = RCC->CFGR; + + /* Clear MCO2 and MCO2PRE[2:0] bits */ + tmpreg &= CFGR_MCO2_RESET_MASK; + + /* Select MCO2 clock source and prescaler */ + tmpreg |= RCC_MCO2Source | RCC_MCO2Div; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @} + */ + +/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions + * @brief System, AHB and APB busses clocks configuration functions + * +@verbatim + =============================================================================== + System, AHB and APB busses clocks configuration functions + =============================================================================== + + This section provide functions allowing to configure the System, AHB, APB1 and + APB2 busses clocks. + + 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable prescaler + and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). + APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through + configurable prescalers and used to clock the peripherals mapped on these busses. + You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. + +@note All the peripheral clocks are derived from the System clock (SYSCLK) except: + - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or + from an external clock mapped on the I2S_CKIN pin. + You have to use RCC_I2SCLKConfig() function to configure this clock. + - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() + functions to configure this clock. + - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly, while the SDIO require a frequency equal or lower than + to 48. This clock is derived of the main PLL through PLLQ divider. + - IWDG clock which is always the LSI clock. + + 2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz. + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + +-------------------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |---------------------------------------------------------------------| + | | voltage range | voltage range | voltage range | voltage range | + | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | + |---------------|----------------|----------------|-----------------|-----------------| + |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | + |---------------|----------------|----------------|-----------------|-----------------| + |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | + |---------------|----------------|----------------|-----------------|-----------------| + |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | + |---------------|----------------|----------------|-----------------|-----------------| + |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | + |---------------|----------------|----------------|-----------------|-----------------| + |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | + |---------------|----------------|----------------|-----------------|-----------------| + |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | + |---------------|----------------|----------------|-----------------|-----------------| + |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | + |---------------|----------------|----------------|-----------------|-----------------| + |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| + +-------------------------------------------------------------------------------------+ + + +@endverbatim + * @{ + */ + +/** + * @brief Configures the system clock (SYSCLK). + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use RCC_GetSYSCLKSource() function to know which clock is + * currently used as system clock source. + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= ~RCC_CFGR_SW; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @note Depending on the device voltage range, the software has to set correctly + * these bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above + * "CPU, AHB and APB busses clocks configuration functions") + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[3:0] bits */ + tmpreg &= ~RCC_CFGR_HPRE; + + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE1[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE1; + + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE2[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE2; + + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, + * PCLK1 and PCLK2. + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function + * must be called to update the structure's field. Otherwise, any + * configuration based on this function will be incorrect. + * + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; + break; + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ + + /* Get HCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_HPRE; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE1; + tmp = tmp >> 10; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE2; + tmp = tmp >> 13; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; +} + +/** + * @} + */ + +/** @defgroup RCC_Group3 Peripheral clocks configuration functions + * @brief Peripheral clocks configuration functions + * +@verbatim + =============================================================================== + Peripheral clocks configuration functions + =============================================================================== + + This section provide functions allowing to configure the Peripheral clocks. + + 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. + + 2. After restart from Reset or wakeup from STANDBY, all peripherals are off + except internal SRAM, Flash and JTAG. Before to start using a peripheral you + have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd() + , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. + + 3. To reset the peripherals configuration (to the default state after device reset) + you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and + RCC_APB1PeriphResetCmd() functions. + + 4. To further reduce power consumption in SLEEP mode the peripheral clocks can + be disabled prior to executing the WFI or WFE instructions. You can do this + using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and + RCC_APB1PeriphClockLPModeCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using PWR_BackupAccessCmd(ENABLE) function before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using RCC_BackupResetCmd() function, or by + * a Power On Reset (POR). + * + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) + { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ + tmpreg = RCC->CFGR; + + /* Clear RTCPRE[4:0] bits */ + tmpreg &= ~RCC_CFGR_RTCPRE; + + /* Configure HSE division factor for RTC clock */ + tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); + + /* Store the new value */ + RCC->CFGR = tmpreg; + } + + /* Select the RTC clock source */ + RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock source was selected + * using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Forces or releases the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the I2S clock source (I2SCLK). + * + * @note This function must be called before enabling the I2S APB clock. + * @note This function applies only to Silicon RevisionB and RevisionY. + * + * @param RCC_I2SCLKSource: specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source + * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin + * used as I2S clock source + * @retval None + */ +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); + + *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; +} + +/** + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock + * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock + * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB1ENR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1ENR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2ENR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2ENR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. + * This parameter must be: RCC_AHB3Periph_FSMC + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3ENR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3ENR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases AHB1 peripheral reset. + * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB1RSTR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1RSTR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Forces or releases AHB2 peripheral reset. + * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2RSTR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2RSTR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Forces or releases AHB3 peripheral reset. + * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. + * This parameter must be: RCC_AHB3Periph_FSMC + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3RSTR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3RSTR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOF: GPIOF clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOG: GPIOG clock + * @arg RCC_AHB1Periph_GPIOI: GPIOI clock + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock + * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock + * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock + * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock + * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock + * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB1LPENR |= RCC_AHB1Periph; + } + else + { + RCC->AHB1LPENR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_DCMI: DCMI clock + * @arg RCC_AHB2Periph_CRYP: CRYP clock + * @arg RCC_AHB2Periph_HASH: HASH clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB2LPENR |= RCC_AHB2Periph; + } + else + { + RCC->AHB2LPENR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. + * This parameter must be: RCC_AHB3Periph_FSMC + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB3LPENR |= RCC_AHB3Periph; + } + else + { + RCC->AHB3LPENR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_USART3: USART3 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1LPENR |= RCC_APB1Periph; + } + else + { + RCC->APB1LPENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_ADC2: ADC2 clock + * @arg RCC_APB2Periph_ADC3: ADC3 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2LPENR |= RCC_APB2Periph; + } + else + { + RCC->APB2LPENR &= ~RCC_APB2Periph; + } +} + +/** + * @} + */ + +/** @defgroup RCC_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: main PLL clock ready + * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= RCC_CSR_RMVF; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c new file mode 100644 index 000000000..99d88b22d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c @@ -0,0 +1,405 @@ +/** + ****************************************************************************** + * @file stm32f2xx_rng.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Random Number Generator (RNG) peripheral: + * - Initialization and Configuration + * - Get 32 bit Random number + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable The RNG controller clock using + * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. + * + * 2. Activate the RNG peripheral using RNG_Cmd() function. + * + * 3. Wait until the 32 bit Random number Generator contains a valid + * random data (using polling/interrupt mode). For more details, + * refer to "Interrupts and flags management functions" module + * description. + * + * 4. Get the 32 bit Random number using RNG_GetRandomNumber() function + * + * 5. To get another 32 bit Random number, go to step 3. + * + * + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RNG + * @brief RNG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RNG_Private_Functions + * @{ + */ + +/** @defgroup RNG_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + This section provides functions allowing to + - Initialize the RNG peripheral + - Enable or disable the RNG peripheral + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the RNG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void RNG_DeInit(void) +{ + /* Enable RNG reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); + + /* Release RNG from reset state */ + RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE); +} + +/** + * @brief Enables or disables the RNG peripheral. + * @param NewState: new state of the RNG peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RNG_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the RNG */ + RNG->CR |= RNG_CR_RNGEN; + } + else + { + /* Disable the RNG */ + RNG->CR &= ~RNG_CR_RNGEN; + } +} +/** + * @} + */ + +/** @defgroup RNG_Group2 Get 32 bit Random number function + * @brief Get 32 bit Random number function + * + +@verbatim + =============================================================================== + Get 32 bit Random number function + =============================================================================== + This section provides a function allowing to get the 32 bit Random number + + @note Before to call this function you have to wait till DRDY flag is set, + using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. + +@endverbatim + * @{ + */ + + +/** + * @brief Returns a 32-bit random number. + * + * @note Before to call this function you have to wait till DRDY (data ready) + * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. + * @note Each time the the Random number data is read (using RNG_GetRandomNumber() + * function), the RNG_FLAG_DRDY flag is automatically cleared. + * @note In the case of a seed error, the generation of random numbers is + * interrupted for as long as the SECS bit is '1'. If a number is + * available in the RNG_DR register, it must not be used because it may + * not have enough entropy. In this case, it is recommended to clear the + * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable + * and enable the RNG peripheral (using RNG_Cmd() function) to + * reinitialize and restart the RNG. + * @note In the case of a clock error, the RNG is no more able to generate + * random numbers because the PLL48CLK clock is not correct. User have + * to check that the clock controller is correctly configured to provide + * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) + * function) . The clock error has no impact on the previously generated + * random numbers, and the RNG_DR register contents can be used. + * + * @param None + * @retval 32-bit random number. + */ +uint32_t RNG_GetRandomNumber(void) +{ + /* Return the 32 bit random number from the DR register */ + return RNG->DR; +} + + +/** + * @} + */ + +/** @defgroup RNG_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides functions allowing to configure the RNG Interrupts and + to get the status and clear flags and Interrupts pending bits. + + The RNG provides 3 Interrupts sources and 3 Flags: + + Flags : + ---------- + 1. RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid + random data. it is cleared by reading the valid data + (using RNG_GetRandomNumber() function). + + 2. RNG_FLAG_CECS : In the case of a seed error detection. + + 3. RNG_FLAG_SECS : In the case of a clock error detection. + + + Interrupts : + ------------ + if enabled, an RNG interrupt is pending : + + 1. In the case of the RNG_DR register contains valid random data. + This interrupt source is cleared once the RNG_DR register has been read + (using RNG_GetRandomNumber() function) until a new valid value is + computed. + + or + 2. In the case of a seed error : One of the following faulty sequences has + been detected: + - More than 64 consecutive bits at the same value (0 or 1) + - More than 32 consecutive alternance of 0 and 1 (0101010101...01) + This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) + function. + + or + 3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source) + was not correctly detected (fPLL48CLK< fHCLK/16). + This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI) + function. + @note In this case, User have to check that the clock controller is + correctly configured to provide the RNG clock. + + Managing the RNG controller events : + ------------------------------------ + The user should identify which mode will be used in his application to manage + the RNG controller events: Polling mode or Interrupt mode. + + 1. In the Polling Mode it is advised to use the following functions: + - RNG_GetFlagStatus() : to check if flags events occur. + - RNG_ClearFlag() : to clear the flags events. + + @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only + by reading the Random number data. + + 2. In the Interrupt Mode it is advised to use the following functions: + - RNG_ITConfig() : to enable or disable the interrupt source. + - RNG_GetITStatus() : to check if Interrupt occurs. + - RNG_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). + + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the RNG interrupt. + * @note The RNG provides 3 interrupt sources, + * - Computed data is ready event (DRDY), and + * - Seed error Interrupt (SEI) and + * - Clock error Interrupt (CEI), + * all these interrupts sources are enabled by setting the IE bit in + * CR register. However, each interrupt have its specific status bit + * (see RNG_GetITStatus() function) and clear bit except the DRDY event + * (see RNG_ClearITPendingBit() function). + * @param NewState: new state of the RNG interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RNG_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the RNG interrupt */ + RNG->CR |= RNG_CR_IE; + } + else + { + /* Disable the RNG interrupt */ + RNG->CR &= ~RNG_CR_IE; + } +} + +/** + * @brief Checks whether the specified RNG flag is set or not. + * @param RNG_FLAG: specifies the RNG flag to check. + * This parameter can be one of the following values: + * @arg RNG_FLAG_DRDY: Data Ready flag. + * @arg RNG_FLAG_CECS: Clock Error Current flag. + * @arg RNG_FLAG_SECS: Seed Error Current flag. + * @retval The new state of RNG_FLAG (SET or RESET). + */ +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RNG_GET_FLAG(RNG_FLAG)); + + /* Check the status of the specified RNG flag */ + if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET) + { + /* RNG_FLAG is set */ + bitstatus = SET; + } + else + { + /* RNG_FLAG is reset */ + bitstatus = RESET; + } + /* Return the RNG_FLAG status */ + return bitstatus; +} + + +/** + * @brief Clears the RNG flags. + * @param RNG_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RNG_FLAG_CECS: Clock Error Current flag. + * @arg RNG_FLAG_SECS: Seed Error Current flag. + * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. + * This flag is cleared only by reading the Random number data (using + * RNG_GetRandomNumber() function). + * @retval None + */ +void RNG_ClearFlag(uint8_t RNG_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG)); + /* Clear the selected RNG flags */ + RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); +} + +/** + * @brief Checks whether the specified RNG interrupt has occurred or not. + * @param RNG_IT: specifies the RNG interrupt source to check. + * This parameter can be one of the following values: + * @arg RNG_IT_CEI: Clock Error Interrupt. + * @arg RNG_IT_SEI: Seed Error Interrupt. + * @retval The new state of RNG_IT (SET or RESET). + */ +ITStatus RNG_GetITStatus(uint8_t RNG_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RNG_GET_IT(RNG_IT)); + + /* Check the status of the specified RNG interrupt */ + if ((RNG->SR & RNG_IT) != (uint8_t)RESET) + { + /* RNG_IT is set */ + bitstatus = SET; + } + else + { + /* RNG_IT is reset */ + bitstatus = RESET; + } + /* Return the RNG_IT status */ + return bitstatus; +} + + +/** + * @brief Clears the RNG interrupt pending bit(s). + * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear. + * This parameter can be any combination of the following values: + * @arg RNG_IT_CEI: Clock Error Interrupt. + * @arg RNG_IT_SEI: Seed Error Interrupt. + * @retval None + */ +void RNG_ClearITPendingBit(uint8_t RNG_IT) +{ + /* Check the parameters */ + assert_param(IS_RNG_IT(RNG_IT)); + + /* Clear the selected RNG interrupt pending bit */ + RNG->SR = (uint8_t)~RNG_IT; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c new file mode 100644 index 000000000..7ec11f0e2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c @@ -0,0 +1,2244 @@ +/** + ****************************************************************************** + * @file stm32f2xx_rtc.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * - Initialization + * - Calendar (Time and Date) configuration + * - Alarms (Alarm A and Alarm B) configuration + * - WakeUp Timer configuration + * - Daylight Saving configuration + * - Output pin Configuration + * - Coarse Calibration configuration + * - TimeStamp configuration + * - Tampers configuration + * - Backup Data Registers configuration + * - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * Backup Domain Operating Condition + * =================================================================== + * The real-time clock (RTC), the RTC backup registers, and the backup + * SRAM (BKP SRAM) can be powered from the VBAT voltage when the main + * VDD supply is powered off. + * To retain the content of the RTC backup registers, backup SRAM, + * and supply the RTC when VDD is turned off, VBAT pin can be connected + * to an optional standby voltage supplied by a battery or by another + * source. + * + * To allow the RTC to operate even when the main digital supply (VDD) + * is turned off, the VBAT pin powers the following blocks: + * 1 - The RTC + * 2 - The LSE oscillator + * 3 - The backup SRAM when the low power backup regulator is enabled + * 4 - PC13 to PC15 I/Os, plus PI8 I/O (when available) + * + * When the backup domain is supplied by VDD (analog switch connected + * to VDD), the following functions are available: + * 1 - PC14 and PC15 can be used as either GPIO or LSE pins + * 2 - PC13 can be used as a GPIO or as the RTC_AF1 pin + * 3 - PI8 can be used as a GPIO or as the RTC_AF2 pin + * + * When the backup domain is supplied by VBAT (analog switch connected + * to VBAT because VDD is not present), the following functions are available: + * 1 - PC14 and PC15 can be used as LSE pins only + * 2 - PC13 can be used as the RTC_AF1 pin + * 3 - PI8 can be used as the RTC_AF2 pin + * + * =================================================================== + * Backup Domain Reset + * =================================================================== + * The backup domain reset sets all RTC registers and the RCC_BDCR + * register to their reset values. The BKPSRAM is not affected by this + * reset. The only way of resetting the BKPSRAM is through the Flash + * interface by requesting a protection level change from 1 to 0. + * A backup domain reset is generated when one of the following events + * occurs: + * 1 - Software reset, triggered by setting the BDRST bit in the + * RCC Backup domain control register (RCC_BDCR). You can use the + * RCC_BackupResetCmd(). + * 2 - VDD or VBAT power on, if both supplies have previously been + * powered off. + * + * =================================================================== + * Backup Domain Access + * =================================================================== + * After reset, the backup domain (RTC registers, RTC backup data + * registers and backup SRAM) is protected against possible unwanted + * write accesses. + * To enable access to the RTC Domain and RTC registers, proceed as follows: + * - Enable the Power Controller (PWR) APB1 interface clock using the + * RCC_APB1PeriphClockCmd() function. + * - Enable access to RTC domain using the PWR_BackupAccessCmd() function. + * - Select the RTC clock source using the RCC_RTCCLKConfig() function. + * - Enable RTC Clock using the RCC_RTCCLKCmd() function. + * + * =================================================================== + * RTC Driver: how to use it + * =================================================================== + * - Enable the RTC domain access (see description in the section above) + * - Configure the RTC Prescaler (Asynchronous and Synchronous) and + * RTC hour format using the RTC_Init() function. + * + * Time and Date configuration + * =========================== + * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime() + * and RTC_SetDate() functions. + * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() + * functions. + * - Use the RTC_DayLightSavingConfig() function to add or sub one + * hour to the RTC Calendar. + * + * Alarm configuration + * =================== + * - To configure the RTC Alarm use the RTC_SetAlarm() function. + * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function + * - To read the RTC Alarm, use the RTC_GetAlarm() function. + * + * RTC Wakeup configuration + * ======================== + * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() + * function. + * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() + * function + * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function + * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() + * function. + * + * Outputs configuration + * ===================== + * The RTC has 2 different outputs: + * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B + * and WaKeUp signals. + * To output the selected RTC signal on RTC_AF1 pin, use the + * RTC_OutputConfig() function. + * - AFO_CALIB: this output is used to manage the RTC Clock divided + * by 64 (512Hz) signal. + * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() + * function. + * + * Coarse Calibration configuration + * ================================= + * - Configure the RTC Coarse Calibration Value and the corresponding + * sign using the RTC_CoarseCalibConfig() function. + * - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() + * function + * + * TimeStamp configuration + * ======================= + * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp + * using the RTC_TimeStampCmd() function. + * - To read the RTC TimeStamp Time and Date register, use the + * RTC_GetTimeStamp() function. + * - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) + * or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in + * RTC_TAFCR register. You can use the RTC_TamperPinSelection() + * function to select the corresponding pin. + * + * Tamper configuration + * ==================== + * - Configure the RTC Tamper trigger using the RTC_TamperConfig() + * function. + * - Enable the RTC Tamper using the RTC_TamperCmd() function. + * - The TIMESTAMP alternate function can be mapped to either RTC_AF1 + * or RTC_AF2 depending on the value of the TSINSEL bit in the + * RTC_TAFCR register. You can use the RTC_TimeStampPinSelection() + * function to select the corresponding pin. + * + * Backup Data Registers configuration + * =================================== + * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() + * function. + * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() + * function. + * + * =================================================================== + * RTC and low power modes + * =================================================================== + * The MCU can be woken up from a low power mode by an RTC alternate + * function. + * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + * RTC wakeup, RTC tamper event detection and RTC time stamp event detection. + * These RTC alternate functions can wake up the system from the Stop + * and Standby lowpower modes. + * The system can also wake up from low power modes without depending + * on an external interrupt (Auto-wakeup mode), by using the RTC alarm + * or the RTC wakeup events. + * The RTC provides a programmable time base for waking up from the + * Stop or Standby mode at regular intervals. + * Wakeup from STOP and Standby modes is possible only when the RTC + * clock source is LSE or LSI. + * + * =================================================================== + * Selection of RTC_AF1 alternate functions + * =================================================================== + * The RTC_AF1 pin (PC13) can be used for the following purposes: + * - AFO_ALARM output + * - AFO_CALIB output + * - AFI_TAMPER + * - AFI_TIMESTAMP + * + * +-------------------------------------------------------------------------------------------------------------+ + * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | + * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | + * | and function | | | | | selection | selection |Configuration | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | Alarm out | | | | | Don't | Don't | | + * | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | Alarm out | | | | | Don't | Don't | | + * | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | Calibration out | | | | | Don't | Don't | | + * | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | TAMPER input | | | | | | Don't | | + * | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | TIMESTAMP and | | | | | | | | + * | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | + * | floating | | | | | | | | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | TIMESTAMP input | | | | | Don't | | | + * | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | + * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| + * | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | + * +-------------------------------------------------------------------------------------------------------------+ + * + * + * =================================================================== + * Selection of RTC_AF2 alternate functions + * =================================================================== + * The RTC_AF2 pin (PI8) can be used for the following purposes: + * - AFI_TAMPER + * - AFI_TIMESTAMP + * + * +---------------------------------------------------------------------------------------+ + * | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | + * | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | + * | and function | | | selection | selection |Configuration | + * |-----------------|-----------|--------------|------------|--------------|--------------| + * | TAMPER input | | | | Don't | | + * | floating | 1 | 0 | 1 | care | Don't care | + * |-----------------|-----------|--------------|------------|--------------|--------------| + * | TIMESTAMP and | | | | | | + * | TAMPER input | 1 | 1 | 1 | 1 | Don't care | + * | floating | | | | | | + * |-----------------|-----------|--------------|------------|--------------|--------------| + * | TIMESTAMP input | | | Don't | | | + * | floating | 0 | 1 | care | 1 | Don't care | + * |-----------------|-----------|--------------|------------|--------------|--------------| + * | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | + * +---------------------------------------------------------------------------------------+ + * + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) +#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ + RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ + RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ + RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F )) + +#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) +#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** @defgroup RTC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + + This section provide functions allowing to initialize and configure the RTC + Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers + Write protection, enter and exit the RTC initialization mode, RTC registers + synchronization check and reference clock detection enable. + + 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is + split into 2 programmable prescalers to minimize power consumption. + - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. + - When both prescalers are used, it is recommended to configure the asynchronous + prescaler to a high value to minimize consumption. + + 2. All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + + 3. To Configure the RTC Calendar, user application should enter initialization + mode. In this mode, the calendar counter is stopped and its value can be + updated. When the initialization sequence is complete, the calendar restarts + counting after 4 RTCCLK cycles. + + 4. To read the calendar through the shadow registers after Calendar initialization, + calendar update or after wakeup from low power modes the software must first + clear the RSF flag. The software must then wait until it is set again before + reading the calendar, which means that the calendar registers have been + correctly copied into the RTC_TR and RTC_DR shadow registers. + The RTC_WaitForSynchro() function implements the above software sequence + (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are deinitialized + * - ERROR: RTC registers are not deinitialized + */ +ErrorStatus RTC_DeInit(void) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Reset TR, DR and CR registers */ + RTC->TR = (uint32_t)0x00000000; + RTC->DR = (uint32_t)0x00002101; + /* Reset All CR bits except CR[2:0] */ + RTC->CR &= (uint32_t)0x00000007; + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; + wutcounter++; + } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) + { + status = ERROR; + } + else + { + /* Reset all RTC CR register bits */ + RTC->CR &= (uint32_t)0x00000000; + RTC->WUTR = (uint32_t)0x0000FFFF; + RTC->PRER = (uint32_t)0x007F00FF; + RTC->CALIBR = (uint32_t)0x00000000; + RTC->ALRMAR = (uint32_t)0x00000000; + RTC->ALRMBR = (uint32_t)0x00000000; + + /* Reset ISR register and exit initialization mode */ + RTC->ISR = (uint32_t)0x00000000; + + /* Reset Tamper and alternate functions configuration register */ + RTC->TAFCR = 0x00000000; + + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Clear RTC CR FMT Bit */ + RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); + /* Set RTC_CR register */ + RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); + + /* Configure the RTC PRER */ + RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); + RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_InitStruct member with its default value. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) +{ + /* Initialize the RTC_HourFormat member */ + RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; + + /* Initialize the RTC_AsynchPrediv member */ + RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; + + /* Initialize the RTC_SynchPrediv member */ + RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; +} + +/** + * @brief Enables or disables the RTC registers write protection. + * @note All the RTC registers are write protected except for RTC_ISR[13:8], + * RTC_TAFCR and RTC_BKPxR. + * @note Writing a wrong key reactivates the write protection. + * @note The protection mechanism is not affected by system reset. + * @param NewState: new state of the write protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_WriteProtectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + } +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus RTC_EnterInitMode(void) +{ + __IO uint32_t initcounter = 0x00; + ErrorStatus status = ERROR; + uint32_t initstatus = 0x00; + + /* Check if the Initialization mode is set */ + if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + RTC->ISR = (uint32_t)RTC_INIT_MASK; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do + { + initstatus = RTC->ISR & RTC_ISR_INITF; + initcounter++; + } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_INITF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + } + else + { + status = SUCCESS; + } + + return (status); +} + +/** + * @brief Exits the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @param None + * @retval None + */ +void RTC_ExitInitMode(void) +{ + /* Exit Initialization mode */ + RTC->ISR &= (uint32_t)~RTC_ISR_INIT; +} + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus RTC_WaitForSynchro(void) +{ + __IO uint32_t synchrocounter = 0; + ErrorStatus status = ERROR; + uint32_t synchrostatus = 0x00; + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear RSF flag */ + RTC->ISR &= (uint32_t)RTC_RSF_MASK; + + /* Wait the registers to be synchronised */ + do + { + synchrostatus = RTC->ISR & RTC_ISR_RSF; + synchrocounter++; + } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_RSF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return (status); +} + +/** + * @brief Enables or disables the RTC reference clock detection. + * @param NewState: new state of the RTC reference clock. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC reference clock detection is enabled + * - ERROR: RTC reference clock detection is disabled + */ +ErrorStatus RTC_RefClockCmd(FunctionalState NewState) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (NewState != DISABLE) + { + /* Enable the RTC reference clock detection */ + RTC->CR |= RTC_CR_REFCKON; + } + else + { + /* Disable the RTC reference clock detection */ + RTC->CR &= ~RTC_CR_REFCKON; + } + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @} + */ + +/** @defgroup RTC_Group2 Time and Date configuration functions + * @brief Time and Date configuration functions + * +@verbatim + =============================================================================== + Time and Date configuration functions + =============================================================================== + + This section provide functions allowing to program and read the RTC Calendar + (Time and Date). + +@endverbatim + * @{ + */ + +/** + * @brief Set the RTC current time. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == RTC_Format_BIN) + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + RTC_TimeStruct->RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); + } + else + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + RTC_TimeStruct->RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ + ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); + } + else + { + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ + (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_TR register */ + RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_TimeStruct member with its default value + * (Time = 00h:00min:00sec). + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->RTC_H12 = RTC_H12_AM; + RTC_TimeStruct->RTC_Hours = 0; + RTC_TimeStruct->RTC_Minutes = 0; + RTC_TimeStruct->RTC_Seconds = 0; +} + +/** + * @brief Get the RTC current Time. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contain the returned current time configuration. + * @retval None + */ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); + RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); + RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); + RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); + RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); + } +} + +/** + * @brief Set the RTC current date. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * the date configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Date register is configured + * - ERROR: RTC Date register is not configured + */ +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) + { + RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; + } + if (RTC_Format == RTC_Format_BIN) + { + assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); + assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); + assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); + tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); + assert_param(IS_RTC_MONTH(tmpreg)); + tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); + assert_param(IS_RTC_DATE(tmpreg)); + } + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ + (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_DateStruct->RTC_Date) | \ + (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); + } + else + { + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ + ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_DR register */ + RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_DateStruct member with its default value + * (Monday, January 01 xx00). + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; + RTC_DateStruct->RTC_Date = 1; + RTC_DateStruct->RTC_Month = RTC_Month_January; + RTC_DateStruct->RTC_Year = 0; +} + +/** + * @brief Get the RTC current date. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will + * contain the returned current date configuration. + * @retval None + */ +void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); + RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); + RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); + RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); + RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); + RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group3 Alarms configuration functions + * @brief Alarms (Alarm A and Alarm B) configuration functions + * +@verbatim + =============================================================================== + Alarms (Alarm A and Alarm B) configuration functions + =============================================================================== + + This section provide functions allowing to program and read the RTC Alarms. + +@endverbatim + * @{ + */ + +/** + * @brief Set the specified RTC Alarm. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the RTC_AlarmCmd(DISABLE)). + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval None + */ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); + + if (RTC_Format == RTC_Format_BIN) + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); + + if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + } + else + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); + + if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + } + else + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + } + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + else + { + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm register */ + if (RTC_Alarm == RTC_Alarm_A) + { + RTC->ALRMAR = (uint32_t)tmpreg; + } + else + { + RTC->ALRMBR = (uint32_t)tmpreg; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Fills each RTC_AlarmStruct member with its default value + * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = + * all fields are masked). + * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which + * will be initialized. + * @retval None + */ +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; + + /* Alarm Date Settings : Date = 1st day of the month */ + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; + RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will + * contains the output alarm configuration values. + * @retval None + */ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM(RTC_Alarm)); + + /* Get the RTC_ALRMxR register */ + if (RTC_Alarm == RTC_Alarm_A) + { + tmpreg = (uint32_t)(RTC->ALRMAR); + } + else + { + tmpreg = (uint32_t)(RTC->ALRMBR); + } + + /* Fill the structure with the read parameters */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ + RTC_ALRMAR_HU)) >> 16); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ + RTC_ALRMAR_MNU)) >> 8); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ + RTC_ALRMAR_SU)); + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); + + if (RTC_Format == RTC_Format_BIN) + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Hours); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Minutes); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Seconds); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + } +} + +/** + * @brief Enables or disables the specified RTC Alarm. + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be any combination of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param NewState: new state of the specified alarm. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Alarm is enabled/disabled + * - ERROR: RTC Alarm is not enabled/disabled + */ +ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) +{ + __IO uint32_t alarmcounter = 0x00; + uint32_t alarmstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm state */ + if (NewState != DISABLE) + { + RTC->CR |= (uint32_t)RTC_Alarm; + + status = SUCCESS; + } + else + { + /* Disable the Alarm in RTC_CR register */ + RTC->CR &= (uint32_t)~RTC_Alarm; + + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ + do + { + alarmstatus = RTC->ISR & (RTC_Alarm >> 8); + alarmcounter++; + } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); + + if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @} + */ + +/** @defgroup RTC_Group4 WakeUp Timer configuration functions + * @brief WakeUp Timer configuration functions + * +@verbatim + =============================================================================== + WakeUp Timer configuration functions + =============================================================================== + + This section provide functions allowing to program and read the RTC WakeUp. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Wakeup clock source. + * @note The WakeUp Clock source can only be changed when the RTC WakeUp + * is disabled (Use the RTC_WakeUpCmd(DISABLE)). + * @param RTC_WakeUpClock: Wakeup Clock source. + * This parameter can be one of the following values: + * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 + * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 + * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 + * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 + * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE + * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE + * @retval None + */ +void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) +{ + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the Wakeup Timer clock source bits in CR register */ + RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + RTC->CR |= (uint32_t)RTC_WakeUpClock; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Configures the RTC Wakeup counter. + * @note The RTC WakeUp counter can only be written when the RTC WakeUp + * is disabled (Use the RTC_WakeUpCmd(DISABLE)). + * @param RTC_WakeUpCounter: specifies the WakeUp counter. + * This parameter can be a value from 0x0000 to 0xFFFF. + * @retval None + */ +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) +{ + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Wakeup Timer counter */ + RTC->WUTR = (uint32_t)RTC_WakeUpCounter; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Returns the RTC WakeUp timer counter value. + * @param None + * @retval The RTC WakeUp Counter value. + */ +uint32_t RTC_GetWakeUpCounter(void) +{ + /* Get the counter value */ + return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); +} + +/** + * @brief Enables or Disables the RTC WakeUp timer. + * @param NewState: new state of the WakeUp timer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Enable the Wakeup Timer */ + RTC->CR |= (uint32_t)RTC_CR_WUTE; + status = SUCCESS; + } + else + { + /* Disable the Wakeup Timer */ + RTC->CR &= (uint32_t)~RTC_CR_WUTE; + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; + wutcounter++; + } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @} + */ + +/** @defgroup RTC_Group5 Daylight Saving configuration functions + * @brief Daylight Saving configuration functions + * +@verbatim + =============================================================================== + Daylight Saving configuration functions + =============================================================================== + + This section provide functions allowing to configure the RTC DayLight Saving. + +@endverbatim + * @{ + */ + +/** + * @brief Adds or substract one hour from the current time. + * @param RTC_DayLightSaveOperation: the value of hour adjustment. + * This parameter can be one of the following values: + * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) + * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) + * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit + * in CR register to store the operation. + * This parameter can be one of the following values: + * @arg RTC_StoreOperation_Reset: BCK Bit Reset + * @arg RTC_StoreOperation_Set: BCK Bit Set + * @retval None + */ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) +{ + /* Check the parameters */ + assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the bits to be configured */ + RTC->CR &= (uint32_t)~(RTC_CR_BCK); + + /* Configure the RTC_CR register */ + RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Returns the RTC Day Light Saving stored operation. + * @param None + * @retval RTC Day Light Saving stored operation. + * - RTC_StoreOperation_Reset + * - RTC_StoreOperation_Set + */ +uint32_t RTC_GetStoreOperation(void) +{ + return (RTC->CR & RTC_CR_BCK); +} + +/** + * @} + */ + +/** @defgroup RTC_Group6 Output pin Configuration function + * @brief Output pin Configuration function + * +@verbatim + =============================================================================== + Output pin Configuration function + =============================================================================== + + This section provide functions allowing to configure the RTC Output source. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC output source (AFO_ALARM). + * @param RTC_Output: Specifies which signal will be routed to the RTC output. + * This parameter can be one of the following values: + * @arg RTC_Output_Disable: No output selected + * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output + * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output + * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output + * @param RTC_OutputPolarity: Specifies the polarity of the output signal. + * This parameter can be one of the following: + * @arg RTC_OutputPolarity_High: The output pin is high when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL) + * @arg RTC_OutputPolarity_Low: The output pin is low when the + * ALRAF/ALRBF/WUTF is high (depending on OSEL) + * @retval None + */ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT(RTC_Output)); + assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the bits to be configured */ + RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); + + /* Configure the output selection and polarity */ + RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @} + */ + +/** @defgroup RTC_Group7 Coarse Calibration configuration functions + * @brief Coarse Calibration configuration functions + * +@verbatim + =============================================================================== + Coarse Calibration configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Coarse calibration parameters. + * @param RTC_CalibSign: specifies the sign of the coarse calibration value. + * This parameter can be one of the following values: + * @arg RTC_CalibSign_Positive: The value sign is positive + * @arg RTC_CalibSign_Negative: The value sign is negative + * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). + * + * @note This Calibration value should be between 0 and 63 when using negative + * sign with a 2-ppm step. + * + * @note This Calibration value should be between 0 and 126 when using positive + * sign with a 4-ppm step. + * + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Coarse calibration are initialized + * - ERROR: RTC Coarse calibration are not initialized + */ +ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); + assert_param(IS_RTC_CALIB_VALUE(Value)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the coarse calibration value */ + RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Enables or disables the Coarse calibration process. + * @param NewState: new state of the Coarse calibration. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Coarse calibration are enabled/disabled + * - ERROR: RTC Coarse calibration are not enabled/disabled + */ +ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (NewState != DISABLE) + { + /* Enable the Coarse Calibration */ + RTC->CR |= (uint32_t)RTC_CR_DCE; + } + else + { + /* Disable the Coarse Calibration */ + RTC->CR &= (uint32_t)~RTC_CR_DCE; + } + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Enables or disables the RTC clock to be output through the relative pin. + * @param NewState: new state of the digital calibration Output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_CalibOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Enable the RTC clock output */ + RTC->CR |= (uint32_t)RTC_CR_COE; + } + else + { + /* Disable the RTC clock output */ + RTC->CR &= (uint32_t)~RTC_CR_COE; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @} + */ + + +/** @defgroup RTC_Group8 TimeStamp configuration functions + * @brief TimeStamp configuration functions + * +@verbatim + =============================================================================== + TimeStamp configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or Disables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge. + * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following: + * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the + * falling edge of the related pin. + * @param NewState: new state of the TimeStamp. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Get the new configuration */ + if (NewState != DISABLE) + { + tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); + } + else + { + tmpreg |= (uint32_t)(RTC_TimeStampEdge); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CR = (uint32_t)tmpreg; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Get the RTC TimeStamp value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contains the TimeStamp time values. + * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will + * contains the TimeStamp date values. + * @retval None + */ +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, + RTC_DateTypeDef* RTC_StampDateStruct) +{ + uint32_t tmptime = 0, tmpdate = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); + RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); + + /* Fill the Date structure fields with the read parameters */ + RTC_StampDateStruct->RTC_Year = 0; + RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); + RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the Time structure parameters to Binary format */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); + + /* Convert the Date structure parameters to Binary format */ + RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); + RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group9 Tampers configuration functions + * @brief Tampers configuration functions + * +@verbatim + =============================================================================== + Tampers configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the select Tamper pin edge. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be RTC_Tamper_1. + * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that + * stimulates tamper event. + * This parameter can be one of the following values: + * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. + * @retval None + */ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + + if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) + { + /* Configure the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); + } + else + { + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); + } +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be RTC_Tamper_1. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TAFCR |= (uint32_t)RTC_Tamper; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TAFCR &= (uint32_t)~RTC_Tamper; + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group10 Backup Data Registers configuration functions + * @brief Backup Data Registers configuration functions + * +@verbatim + =============================================================================== + Backup Data Registers configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @param RTC_BKP_DR: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @param Data: Data to be written in the specified RTC Backup data register. + * @retval None + */ +void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + + tmp = RTC_BASE + 0x50; + tmp += (RTC_BKP_DR * 4); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param RTC_BKP_DR: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @retval None + */ +uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + + tmp = RTC_BASE + 0x50; + tmp += (RTC_BKP_DR * 4); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions + * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config + * configuration functions + * +@verbatim + =============================================================================== + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration + functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Selects the RTC Tamper Pin. + * @param RTC_TamperPin: specifies the RTC Tamper Pin. + * This parameter can be one of the following values: + * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin. + * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin. + * @retval None + */ +void RTC_TamperPinSelection(uint32_t RTC_TamperPin) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL); + RTC->TAFCR |= (uint32_t)(RTC_TamperPin); +} + +/** + * @brief Selects the RTC TimeStamp Pin. + * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin. + * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. + * @retval None + */ +void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin) +{ + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL); + RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); +} + +/** + * @brief Configures the RTC Output Pin mode. + * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in + * Open Drain mode. + * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in + * Push Pull mode. + * @retval None + */ +void RTC_OutputTypeConfig(uint32_t RTC_OutputType) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); + RTC->TAFCR |= (uint32_t)(RTC_OutputType); +} + +/** + * @} + */ + +/** @defgroup RTC_Group12 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + All RTC interrupts are connected to the EXTI controller. + + - To enable the RTC Alarm interrupt, the following sequence is required: + - Configure and enable the EXTI Line 17 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() + function. + - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using + the RTC_SetAlarm() and RTC_AlarmCmd() functions. + + - To enable the RTC Wakeup interrupt, the following sequence is required: + - Configure and enable the EXTI Line 22 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init() + function. + - Configure the RTC to generate the RTC wakeup timer event using the + RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. + + - To enable the RTC Tamper interrupt, the following sequence is required: + - Configure and enable the EXTI Line 21 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() + function. + - Configure the RTC to detect the RTC tamper event using the + RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. + + - To enable the RTC TimeStamp interrupt, the following sequence is required: + - Configure and enable the EXTI Line 21 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() + function. + - Configure the RTC to detect the RTC time-stamp event using the + RTC_TimeStampCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt mask + * @arg RTC_IT_WUT: WakeUp Timer interrupt mask + * @arg RTC_IT_ALRB: Alarm B interrupt mask + * @arg RTC_IT_ALRA: Alarm A interrupt mask + * @arg RTC_IT_TAMP: Tamper event interrupt mask + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_CONFIG_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); + } + else + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_WUTF: WakeUp Timer flag + * @arg RTC_FLAG_ALRBF: Alarm B flag + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_INITF: Initialization mode flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_INITS: Registers Configured flag + * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag + * @arg RTC_FLAG_ALRBWF: Alarm B Write flag + * @arg RTC_FLAG_ALRAWF: Alarm A write flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + /* Get all the flags */ + tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); + + /* Return the status of the flag */ + if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG: specifies the RTC flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_WUTF: WakeUp Timer flag + * @arg RTC_FLAG_ALRBF: Alarm B flag + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @retval None + */ +void RTC_ClearFlag(uint32_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the Flags in the RTC_ISR register */ + RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_IT: specifies the RTC interrupt source to check. + * This parameter can be one of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt + * @arg RTC_IT_WUT: WakeUp Timer interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_TAMP1: Tamper 1 event interrupt + * @retval The new state of RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint32_t RTC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + /* Get the TAMPER Interrupt enable bit and pending bit */ + tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); + + /* Get the Interrupt enable Status */ + enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15))); + + /* Get the Interrupt pending bit */ + tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); + + /* Get the status of the Interrupt */ + if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_IT: specifies the RTC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt + * @arg RTC_IT_WUT: WakeUp Timer interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_TAMP1: Tamper 1 event interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint32_t RTC_IT) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_IT(RTC_IT)); + + /* Get the RTC_ISR Interrupt pending bits mask */ + tmpreg = (uint32_t)(RTC_IT >> 4); + + /* Clear the interrupt pending bits in the RTC_ISR register */ + RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); +} + +/** + * @} + */ + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value: Byte to be converted. + * @retval Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + + while (Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value: BCD value to be converted. + * @retval Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint8_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c new file mode 100644 index 000000000..515b24652 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c @@ -0,0 +1,1010 @@ +/** + ****************************************************************************** + * @file stm32f2xx_sdio.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Secure digital input/output interface (SDIO) + * peripheral: + * - Initialization and Configuration + * - Command path state machine (CPSM) management + * - Data path state machine (DPSM) management + * - SDIO IO Cards mode management + * - CE-ATA mode management + * - DMA transfers management + * - Interrupts and flags management + * + * @verbatim + * + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output + * of PLL (PLL48CLK). Before to start working with SDIO peripheral + * make sure that the PLL is well configured. + * The SDIO peripheral uses two clock signals: + * - SDIO adapter clock (SDIOCLK = 48 MHz) + * - APB2 bus clock (PCLK2) + * PCLK2 and SDIO_CK clock frequencies must respect the following condition: + * Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) + * + * 2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). + * + * 3. According to the SDIO mode, enable the GPIO clocks using + * RCC_AHB1PeriphClockCmd() function. + * The I/O can be one of the following configurations: + * - 1-bit data length: SDIO_CMD, SDIO_CK and D0. + * - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. + * - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. + * + * 4. Peripheral's alternate function: + * - Connect the pin to the desired peripherals' Alternate + * Function (AF) using GPIO_PinAFConfig() function + * - Configure the desired pin in alternate function by: + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * + * 5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, + * hardware, flow control and the Clock Divider using the SDIO_Init() + * function. + * + * 6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) + * function. + * + * 7. Enable the clock using the SDIO_ClockCmd() function. + * + * 8. Enable the NVIC and the corresponding interrupt using the function + * SDIO_ITConfig() if you need to use interrupt mode. + * + * 9. When using the DMA mode + * - Configure the DMA using DMA_Init() function + * - Active the needed channel Request using SDIO_DMACmd() function + * + * 10. Enable the DMA using the DMA_Cmd() function, when using DMA mode. + * + * 11. To control the CPSM (Command Path State Machine) and send + * commands to the card use the SDIO_SendCommand(), + * SDIO_GetCommandResponse() and SDIO_GetResponse() functions. + * First, user has to fill the command structure (pointer to + * SDIO_CmdInitTypeDef) according to the selected command to be sent. + * The parameters that should be filled are: + * - Command Argument + * - Command Index + * - Command Response type + * - Command Wait + * - CPSM Status (Enable or Disable) + * + * To check if the command is well received, read the SDIO_CMDRESP + * register using the SDIO_GetCommandResponse(). + * The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the + * SDIO_GetResponse() function. + * + * 12. To control the DPSM (Data Path State Machine) and send/receive + * data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), + * SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. + * + * Read Operations + * --------------- + * a) First, user has to fill the data structure (pointer to + * SDIO_DataInitTypeDef) according to the selected data type to + * be received. + * The parameters that should be filled are: + * - Data TimeOut + * - Data Length + * - Data Block size + * - Data Transfer direction: should be from card (To SDIO) + * - Data Transfer mode + * - DPSM Status (Enable or Disable) + * + * b) Configure the SDIO resources to receive the data from the card + * according to selected transfer mode (Refer to Step 8, 9 and 10). + * + * c) Send the selected Read command (refer to step 11). + * + * d) Use the SDIO flags/interrupts to check the transfer status. + * + * Write Operations + * --------------- + * a) First, user has to fill the data structure (pointer to + * SDIO_DataInitTypeDef) according to the selected data type to + * be received. + * The parameters that should be filled are: + * - Data TimeOut + * - Data Length + * - Data Block size + * - Data Transfer direction: should be to card (To CARD) + * - Data Transfer mode + * - DPSM Status (Enable or Disable) + * + * b) Configure the SDIO resources to send the data to the card + * according to selected transfer mode (Refer to Step 8, 9 and 10). + * + * c) Send the selected Write command (refer to step 11). + * + * d) Use the SDIO flags/interrupts to check the transfer status. + * + * + * @endverbatim + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ +/* --- CLKCR Register ---*/ +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMD Register ---*/ +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SDIO_Private_Functions + * @{ + */ + +/** @defgroup SDIO_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default reset values. + * @param None + * @retval None + */ +void SDIO_DeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * @retval None + */ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param NewState: new state of the SDIO Clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState: new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_PowerState_OFF: SDIO Power OFF + * @arg SDIO_PowerState_ON: SDIO Power ON + * @retval None + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER = SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @param None + * @retval Power status of the controller. The returned value can be one of the + * following values: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/** + * @} + */ + +/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions + * @brief Command path state machine (CPSM) management functions + * +@verbatim + =============================================================================== + Command path state machine (CPSM) management functions + =============================================================================== + + This section provide functions allowing to program and read the Command path + state machine (CPSM). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for the SDIO + * command. + * @retval None + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * @retval None + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/** + * @brief Returns command index of last command for which response received. + * @param None + * @retval Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @} + */ + +/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions + * @brief Data path state machine (DPSM) management functions + * +@verbatim + =============================================================================== + Data path state machine (DPSM) management functions + =============================================================================== + + This section provide functions allowing to program and read the Data path + state machine (DPSM). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure + * that contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure + * which will be initialized. + * @retval None + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param None + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/** + * @brief Read one data word from Rx FIFO. + * @param None + * @retval Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/** + * @brief Write one data word to Tx FIFO. + * @param Data: 32-bit data word to write. + * @retval None + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read from FIFO. + * @param None + * @retval Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions + * @brief SDIO IO Cards mode management functions + * +@verbatim + =============================================================================== + SDIO IO Cards mode management functions + =============================================================================== + + This section provide functions allowing to program and read the SDIO IO Cards. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param NewState: new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param NewState: new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parameter can be: + * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 + * @retval None + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param NewState: new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param NewState: new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group5 CE-ATA mode management functions + * @brief CE-ATA mode management functions + * +@verbatim + =============================================================================== + CE-ATA mode management functions + =============================================================================== + + This section provide functions allowing to program and read the CE-ATA card. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the command completion signal. + * @param NewState: new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param NewState: new state of CE-ATA interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param NewState: new state of CE-ATA command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group6 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + DMA transfers management functions + =============================================================================== + + This section provide functions allowing to program SDIO DMA transfer. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SDIO DMA request. + * @param NewState: new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; +} + +/** + * @} + */ + +/** @defgroup SDIO_Group7 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @param NewState: new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's interrupt pending bits. + * @param SDIO_IT: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c new file mode 100644 index 000000000..033475e68 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c @@ -0,0 +1,1183 @@ +/** + ****************************************************************************** + * @file stm32f2xx_spi.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Serial peripheral interface (SPI): + * - Initialization and Configuration + * - Data transfers functions + * - Hardware CRC Calculation + * - DMA transfers management + * - Interrupts and flags management + * + * @verbatim + * + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable peripheral clock using the following functions + * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 + * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 + * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3. + * + * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() + * function. + * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO + * clock should also be enabled. + * + * 3. Peripherals alternate function: + * - Connect the pin to the desired peripherals' Alternate + * Function (AF) using GPIO_PinAFConfig() function + * - Configure the desired pin in alternate function by: + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * In I2S mode, if an external clock source is used then the I2S CKIN pin + * should be also configured in Alternate function Push-pull pull-up mode. + * + * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave + * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + * function. + * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio + * frequency and Polarity using I2S_Init() function. + * For I2S mode, make sure that either: + * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), + * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY). + * or + * - External clock source is configured using the function + * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant + * I2S_EXTERNAL_CLOCK_VAL in the stm32f2xx_conf.h file. + * + * 5. Enable the NVIC and the corresponding interrupt using the function + * SPI_ITConfig() if you need to use interrupt mode. + * + * 6. When using the DMA mode + * - Configure the DMA using DMA_Init() function + * - Active the needed channel Request using SPI_I2S_DMACmd() function + * + * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using + * I2S_Cmd(). + * + * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. + * + * 9. Optionally, you can enable/configure the following parameters without + * re-initialization (i.e there is no need to call again SPI_Init() function): + * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) + * is programmed as Data direction parameter using the SPI_Init() function + * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx + * using the SPI_BiDirectionalLineConfig() function. + * - When SPI_NSS_Soft is selected as Slave Select Management parameter + * using the SPI_Init() function it can be possible to manage the + * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. + * - Reconfigure the data size using the SPI_DataSizeConfig() function + * - Enable or disable the SS output using the SPI_SSOutputCmd() function + * + * 10. To use the CRC Hardware calculation feature refer to the Peripheral + * CRC hardware Calculation subsection. + * + * + * @note This driver supports only the I2S clock scheme available in Silicon + * RevisionB and RevisionY. + * + * @note In I2S mode: if an external clock is used as source clock for the I2S, + * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should + * be enabled and set to the value of the source clock frequency (in Hz). + * + * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() + * just after calling the function SPI_Init(). + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_spi.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* SPI registers Masks */ +#define CR1_CLEAR_MASK ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) + +/* RCC PLLs masks */ +#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) +#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) + +#define SPI_CR2_FRF ((uint16_t)0x0010) +#define SPI_SR_TIFRFE ((uint16_t)0x0100) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** @defgroup SPI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + + This section provides a set of functions allowing to initialize the SPI Direction, + SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud + Rate Prescaler, SPI First Bit and SPI CRC Polynomial. + + The SPI_Init() function follows the SPI configuration procedures for Master mode + and Slave mode (details for these procedures are available in reference manual + (RM0033)). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the SPIx peripheral registers to their default reset values. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * + * @note The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. + * + * @note if an external clock is used as source clock for the I2S, then the define + * I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should be enabled and set + * to the value of the the source clock frequency (in Hz). + * + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0, i2sclk = 0; +#ifndef I2S_EXTERNAL_CLOCK_VAL + uint32_t pllm = 0, plln = 0, pllr = 0; +#endif /* I2S_EXTERNAL_CLOCK_VAL */ + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) *******************/ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */ + + /* If an external I2S clock has to be used, this define should be set + in the project configuration or in the stm32f2xx_conf.h file */ + #ifdef I2S_EXTERNAL_CLOCK_VAL + /* Set external clock as I2S clock source */ + if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) + { + RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; + } + + /* Set the I2S clock to the external clock value */ + i2sclk = I2S_EXTERNAL_CLOCK_VAL; + + #else /* There is no define for External I2S clock source */ + /* Set PLLI2S as I2S clock source */ + if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) + { + RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; + } + + /* Get the PLLI2SN value */ + plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ + (RCC_PLLI2SCFGR_PLLI2SN >> 6)); + + /* Get the PLLI2SR value */ + pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ + (RCC_PLLI2SCFGR_PLLI2SR >> 28)); + + /* Get the PLLM value */ + pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + + /* Get the I2S source clock value */ + i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); + #endif /* I2S_EXTERNAL_CLOCK_VAL */ + + /* Compute the Real divider depending on the MCLK output state, with a floating point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the flatting point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= SPI_CR1_SPE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; + } + else + { + /* Disable the selected SPI peripheral in I2S mode */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * + * @note This function can be called only after the SPI_Init() function has + * been called. + * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA + * are not taken into consideration and are configured by hardware + * respectively to the TI mode requirements. + * + * @param SPIx: where x can be 1, 2 or 3 + * @param NewState: new state of the selected SPI TI communication mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TI mode for the selected SPI peripheral */ + SPIx->CR2 |= SPI_CR2_FRF; + } + else + { + /* Disable the TI mode for the selected SPI peripheral */ + SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; + } +} + +/** + * @} + */ + +/** @defgroup SPI_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + Data transfers functions + =============================================================================== + + This section provides a set of functions allowing to manage the SPI data transfers + + In reception, data are received and then stored into an internal Rx buffer while + In transmission, data are first stored into an internal Tx buffer before being + transmitted. + + The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() + function and returns the Rx buffered value. Whereas a write access to the SPI_DR + can be done using SPI_I2S_SendData() function and stores the written data into + Tx buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param Data: Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @} + */ + +/** @defgroup SPI_Group3 Hardware CRC Calculation functions + * @brief Hardware CRC Calculation functions + * +@verbatim + =============================================================================== + Hardware CRC Calculation functions + =============================================================================== + + This section provides a set of functions allowing to manage the SPI CRC hardware + calculation + + SPI communication using CRC is possible through the following procedure: + 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, + Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + function. + 2. Enable the CRC calculation using the SPI_CalculateCRC() function. + 3. Enable the SPI using the SPI_Cmd() function + 4. Before writing the last data to the TX buffer, set the CRCNext bit using the + SPI_TransmitCRC() function to indicate that after transmission of the last + data, the CRC should be transmitted. + 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT + bit is reset. The CRC is also received and compared against the SPI_RXCRCR + value. + If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt + can be generated when the SPI_I2S_IT_ERR interrupt is enabled. + +@note It is advised not to read the calculated CRC values during the communication. + +@note When the SPI is in slave mode, be careful to enable CRC calculation only + when the clock is stable, that is, when the clock is in the steady state. + If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive + to the SCK slave input clock as soon as CRCEN is set, and this, whatever + the value of the SPE bit. + +@note With high bitrate frequencies, be careful when transmitting the CRC. + As the number of used CPU cycles has to be as low as possible in the CRC + transfer phase, it is forbidden to call software functions in the CRC + transmission sequence to avoid errors in the last data and CRC reception. + In fact, CRCNEXT bit has to be written before the end of the transmission/reception + of the last data. + +@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the + degradation of the SPI speed performance due to CPU accesses impacting the + SPI bandwidth. + +@note When the STM32F2xx is configured as slave and the NSS hardware mode is + used, the NSS pin needs to be kept low between the data phase and the CRC + phase. + +@note When the SPI is configured in slave mode with the CRC feature enabled, CRC + calculation takes place even if a high level is applied on the NSS pin. + This may happen for example in case of a multi-slave environment where the + communication master addresses slaves alternately. + +@note Between a slave de-selection (high level on NSS) and a new slave selection + (low level on NSS), the CRC value should be cleared on both master and slave + sides in order to resynchronize the master and slave for their respective + CRC calculation. + +@note To clear the CRC, follow the procedure below: + 1. Disable SPI using the SPI_Cmd() function + 2. Disable the CRC calculation using the SPI_CalculateCRC() function. + 3. Enable the CRC calculation using the SPI_CalculateCRC() function. + 4. Enable SPI using the SPI_Cmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= SPI_CR1_CRCEN; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); + } +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= SPI_CR1_CRCNEXT; +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @} + */ + +/** @defgroup SPI_Group4 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + DMA transfers management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @} + */ + +/** @defgroup SPI_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This section provides a set of functions allowing to configure the SPI Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + Polling Mode + ============= + In Polling Mode, the SPI/I2S communication can be managed by 9 flags: + 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register + 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register + 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. + 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur + 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur + 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur + 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. + 8. I2S_FLAG_UDR: to indicate an Underrun error occurs. + 9. I2S_FLAG_CHSIDE: to indicate Channel Side. + +@note Do not use the BSY flag to handle each data transmission or reception. It is + better to use the TXE and RXNE flags instead. + + In this Mode it is advised to use the following functions: + - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + + Interrupt Mode + =============== + In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources + and 7 pending bits: + Pending Bits: + ------------- + 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register + 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register + 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) + 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) + 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur + 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). + 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). + + Interrupt Source: + ----------------- + 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty + interrupt. + 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. + + In this Mode it is advised to use the following functions: + - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); + - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + + DMA Mode + ======== + In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: + 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request + 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request + + In this Mode it is advised to use the following function: + - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Checks whether the specified SPIx/I2Sx flag is set or not. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_FLAG: specifies the SPI flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg SPI_I2S_FLAG_TIFRFE: Format Error. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + + /* Check the status of the specified SPI flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * + * @note OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * @note UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_IT: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun interrupt. + * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI_I2S_IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI_I2S_IT IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 + * in SPI mode or 2 or 3 in I2S mode. + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR interrupt pending bit. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * + * @note OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI_I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c new file mode 100644 index 000000000..83c9da675 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c @@ -0,0 +1,210 @@ +/** + ****************************************************************************** + * @file stm32f2xx_syscfg.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the SYSCFG peripheral. + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * + * This driver provides functions for: + * + * 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() + * + * 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() + * + * 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() + * + * @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers, + * using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SYSCFG + * @brief SYSCFG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) +/* --- PMC Register ---*/ +/* Alias word address of MII_RMII_SEL bit */ +#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) +#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) +#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) + +/* --- CMPCR Register ---*/ +/* Alias word address of CMP_PD bit */ +#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) +#define CMP_PD_BitNumber ((uint8_t)0x00) +#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SYSCFG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) + * registers to their default reset values. + * @param None + * @retval None + */ +void SYSCFG_DeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); +} + +/** + * @brief Changes the mapping of the specified pin. + * @param SYSCFG_Memory: selects the memory remapping. + * This parameter can be one of the following values: + * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 + * + * @note In remap mode, the FSMC addressing is fixed to the remap address area only + * (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) and FSMC control registers are not + * accessible. The FSMC remap function must be disabled to allows addressing + * other memory devices through the FSMC and/or to access FSMC control + * registers. + * + * @retval None + */ +void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); + + SYSCFG->MEMRMP = SYSCFG_MemoryRemap; +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for + * EXTI lines where x can be (A..I). + * @param EXTI_PinSourcex: specifies the EXTI line to be configured. + * This parameter can be EXTI_PinSourcex where x can be (0..15, except + * for EXTI_PortSourceGPIOI x can be (0..11). + * @retval None + */ +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) +{ + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); + assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); + + tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); +} + +/** + * @brief Selects the ETHERNET media interface + * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. + * This parameter can be one of the following values: + * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected + * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected + * @retval None + */ +void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) +{ + assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); + /* Configure MII_RMII selection bit */ + *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; +} + +/** + * @brief Enables or disables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @param NewState: new state of the I/O Compensation Cell. + * This parameter can be one of the following values: + * @arg ENABLE: I/O compensation cell enabled + * @arg DISABLE: I/O compensation cell power-down mode + * @retval None + */ +void SYSCFG_CompensationCellCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; +} + +/** + * @brief Checks whether the I/O Compensation Cell ready flag is set or not. + * @param None + * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) + */ +FlagStatus SYSCFG_GetCompensationCellStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c new file mode 100644 index 000000000..a9f6e6b16 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c @@ -0,0 +1,3358 @@ +/** + ****************************************************************************** + * @file stm32f2xx_tim.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the TIM peripheral: + * - TimeBase management + * - Output Compare management + * - Input Capture management + * - Advanced-control timers (TIM1 and TIM8) specific features + * - Interrupts, DMA and flags management + * - Clocks management + * - Synchronization management + * - Specific interface management + * - Specific remapping management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * This driver provides functions to configure and program the TIM + * of all STM32F2xx devices. + * These functions are split in 9 groups: + * + * 1. TIM TimeBase management: this group includes all needed functions + * to configure the TM Timebase unit: + * - Set/Get Prescaler + * - Set/Get Autoreload + * - Counter modes configuration + * - Set Clock division + * - Select the One Pulse mode + * - Update Request Configuration + * - Update Disable Configuration + * - Auto-Preload Configuration + * - Enable/Disable the counter + * + * 2. TIM Output Compare management: this group includes all needed + * functions to configure the Capture/Compare unit used in Output + * compare mode: + * - Configure each channel, independently, in Output Compare mode + * - Select the output compare modes + * - Select the Polarities of each channel + * - Set/Get the Capture/Compare register values + * - Select the Output Compare Fast mode + * - Select the Output Compare Forced mode + * - Output Compare-Preload Configuration + * - Clear Output Compare Reference + * - Select the OCREF Clear signal + * - Enable/Disable the Capture/Compare Channels + * + * 3. TIM Input Capture management: this group includes all needed + * functions to configure the Capture/Compare unit used in + * Input Capture mode: + * - Configure each channel in input capture mode + * - Configure Channel1/2 in PWM Input mode + * - Set the Input Capture Prescaler + * - Get the Capture/Compare values + * + * 4. Advanced-control timers (TIM1 and TIM8) specific features + * - Configures the Break input, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable) + * - Enable/Disable the TIM peripheral Main Outputs + * - Select the Commutation event + * - Set/Reset the Capture Compare Preload Control bit + * + * 5. TIM interrupts, DMA and flags management + * - Enable/Disable interrupt sources + * - Get flags status + * - Clear flags/ Pending bits + * - Enable/Disable DMA requests + * - Configure DMA burst mode + * - Select CaptureCompare DMA request + * + * 6. TIM clocks management: this group includes all needed functions + * to configure the clock controller unit: + * - Select internal/External clock + * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx + * + * 7. TIM synchronization management: this group includes all needed + * functions to configure the Synchronization unit: + * - Select Input Trigger + * - Select Output Trigger + * - Select Master Slave Mode + * - ETR Configuration when used as external trigger + * + * 8. TIM specific interface management, this group includes all + * needed functions to use the specific TIM interface: + * - Encoder Interface Configuration + * - Select Hall Sensor + * + * 9. TIM specific remapping management includes the Remapping + * configuration of specific timers + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_tim.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_MASK ((uint16_t)0x00FF) +#define CCMR_OFFSET ((uint16_t)0x0018) +#define CCER_CCE_SET ((uint16_t)0x0001) +#define CCER_CCNE_SET ((uint16_t)0x0004) +#define CCMR_OC13M_MASK ((uint16_t)0xFF8F) +#define CCMR_OC24M_MASK ((uint16_t)0x8FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** @defgroup TIM_Group1 TimeBase management functions + * @brief TimeBase management functions + * +@verbatim + =============================================================================== + TimeBase management functions + =============================================================================== + + =================================================================== + TIM Driver: how to use it in Timing(Time base) Mode + =================================================================== + To use the Timer in Timing(Time base) mode, the following steps are mandatory: + + 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function + + 2. Fill the TIM_TimeBaseInitStruct with the desired parameters. + + 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit + with the corresponding configuration + + 4. Enable the NVIC if you need to generate the update interrupt. + + 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) + + 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + Note1: All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval None + + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if (TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if (TIMx == TIM11) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); + } + else if (TIMx == TIM12) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); + } + else if (TIMx == TIM13) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); + } + else + { + if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM8)|| + (TIMx == TIM2) || (TIMx == TIM3)|| + (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter(only for TIM1 and TIM8) value immediatly */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + + tmpcr1 = TIMx->CR1; + + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); + + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval Counter Register value + */ +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Global: Source of update is the counter + * overflow/underflow or the setting of UG bit, or an update + * generation through the slave mode controller. + * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; + } +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); + + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group2 Output Compare management functions + * @brief Output Compare management functions + * +@verbatim + =============================================================================== + Output Compare management functions + =============================================================================== + + =================================================================== + TIM Driver: how to use it in Output Compare Mode + =================================================================== + To use the Timer in Output Compare mode, the following steps are mandatory: + + 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function + + 2. Configure the TIM pins by configuring the corresponding GPIO pins + + 2. Configure the Time base unit as described in the first part of this driver, + if needed, else the Timer will run with the default configuration: + - Autoreload value = 0xFFFF + - Prescaler value = 0x0000 + - Counter mode = Up counting + - Clock Division = TIM_CKD_DIV1 + + 3. Fill the TIM_OCInitStruct with the desired parameters including: + - The TIM Output Compare mode: TIM_OCMode + - TIM Output State: TIM_OutputState + - TIM Pulse value: TIM_Pulse + - TIM Output Compare Polarity : TIM_OCPolarity + + 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the + corresponding configuration + + 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + Note1: All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + + Note2: In case of PWM mode, this function is mandatory: + TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); + + Note3: If the corresponding interrupt or DMA request are needed, the user should: + 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). + 2. Enable the corresponding interrupt (or DMA request) using the function + TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIMx Channel1 according to the specified parameters in + * the TIM_OCInitStruct. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; + tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NE; + + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; + tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NE; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; + tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NE; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; + tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified parameters + * in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; + tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x00000000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. If needed, user has to enable this channel using + * TIM_CCxCmd() and TIM_CCxNCmd() functions. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_OFFSET; + + tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; + + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; + + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; + + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; + + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)(~TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC1NP; + tmpccer |= TIM_OCNPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)(~TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC2NP; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC3P; + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC3NP; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~TIM_CCER_CC4P; + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_SET << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_SET << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} +/** + * @} + */ + +/** @defgroup TIM_Group3 Input Capture management functions + * @brief Input Capture management functions + * +@verbatim + =============================================================================== + Input Capture management functions + =============================================================================== + + =================================================================== + TIM Driver: how to use it in Input Capture Mode + =================================================================== + To use the Timer in Input Capture mode, the following steps are mandatory: + + 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function + + 2. Configure the TIM pins by configuring the corresponding GPIO pins + + 2. Configure the Time base unit as described in the first part of this driver, + if needed, else the Timer will run with the default configuration: + - Autoreload value = 0xFFFF + - Prescaler value = 0x0000 + - Counter mode = Up counting + - Clock Division = TIM_CKD_DIV1 + + 3. Fill the TIM_ICInitStruct with the desired parameters including: + - TIM Channel: TIM_Channel + - TIM Input Capture polarity: TIM_ICPolarity + - TIM Input Capture selection: TIM_ICSelection + - TIM Input Capture Prescaler: TIM_ICPrescaler + - TIM Input CApture filter value: TIM_ICFilter + + 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the + corresponding configuration and to measure only frequency or duty cycle of the input signal, + or, + Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the + corresponding configuration and to measure the frequency and the duty cycle of the input signal + + 5. Enable the NVIC or the DMA to read the measured frequency. + + 6. Enable the corresponding interrupt (or DMA request) to read the Captured value, + using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) + + 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + + 8. Use TIM_GetCapturex(TIMx); to read the captured value. + + Note1: All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM peripheral according to the specified parameters + * in the TIM_ICInitStruct. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Configures the TIM peripheral according to the specified parameters + * in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains + * the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @retval Capture Compare 2 Register value. + */ +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} +/** + * @} + */ + +/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features + * @brief Advanced-control timers (TIM1 and TIM8) specific features + * +@verbatim + =============================================================================== + Advanced-control timers (TIM1 and TIM8) specific features + =============================================================================== + + =================================================================== + TIM Driver: how to use the Break feature + =================================================================== + After configuring the Timer channel(s) in the appropriate Output Compare mode: + + 1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer + Break Polarity, dead time, Lock level, the OSSI/OSSR State and the + AOE(automatic output enable). + + 2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer + + 3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) + + 4. Once the break even occurs, the Timer's output signals are put in reset + state or in a known state (according to the configuration made in + TIM_BDTRConfig() function). + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group5 Interrupts DMA and flags management functions + * @brief Interrupts, DMA and flags management functions + * +@verbatim + =============================================================================== + Interrupts, DMA and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used + * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, + * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. + * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can + * be used: TIM_IT_Update or TIM_IT_CC1 + * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 + * + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * + * @note TIM6 and TIM7 can only generate an update event. + * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag + * + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. + * + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag + * + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note TIM6 and TIM7 can generate only an update interrupt. + * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. + * + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * + * @note TIM6 and TIM7 can generate only an update interrupt. + * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR1 + * @arg TIM_DMABase_CR2 + * @arg TIM_DMABase_SMCR + * @arg TIM_DMABase_DIER + * @arg TIM1_DMABase_SR + * @arg TIM_DMABase_EGR + * @arg TIM_DMABase_CCMR1 + * @arg TIM_DMABase_CCMR2 + * @arg TIM_DMABase_CCER + * @arg TIM_DMABase_CNT + * @arg TIM_DMABase_PSC + * @arg TIM_DMABase_ARR + * @arg TIM_DMABase_RCR + * @arg TIM_DMABase_CCR1 + * @arg TIM_DMABase_CCR2 + * @arg TIM_DMABase_CCR3 + * @arg TIM_DMABase_CCR4 + * @arg TIM_DMABase_BDTR + * @arg TIM_DMABase_DCR + * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value + * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group6 Clocks management functions + * @brief Clocks management functions + * +@verbatim + =============================================================================== + Clocks management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_InputTriggerSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter: specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; + + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)~TIM_SMCR_TS; + tmpsmcr |= TIM_TS_ETRF; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} +/** + * @} + */ + +/** @defgroup TIM_Group7 Synchronization management functions + * @brief Synchronization management functions + * +@verbatim + =============================================================================== + Synchronization management functions + =============================================================================== + + =================================================================== + TIM Driver: how to use it in synchronization Mode + =================================================================== + Case of two/several Timers + ************************** + 1. Configure the Master Timers using the following functions: + - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); + - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); + 2. Configure the Slave Timers using the following functions: + - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); + - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + + Case of Timers and external trigger(ETR pin) + ******************************************** + 1. Configure the External trigger using this function: + - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); + 2. Configure the Slave Timers using the following functions: + - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); + - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + +@endverbatim + * @{ + */ + +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)~TIM_SMCR_TS; + + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. + * + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This parameter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs(TRGO) + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize + * the counter and triggers an update of the registers + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; + + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO) + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_MASK; + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @} + */ + +/** @defgroup TIM_Group8 Specific interface management functions + * @brief Specific interface management functions + * +@verbatim + =============================================================================== + Specific interface management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; + } +} +/** + * @} + */ + +/** @defgroup TIM_Group9 Specific remapping management function + * @brief Specific remapping management function + * +@verbatim + =============================================================================== + Specific remapping management function + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. + * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. + * @param TIM_Remap: specifies the TIM input remapping source. + * This parameter can be one of the following values: + * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) + * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output. + * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. + * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. + * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. + * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. + * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. + * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock + * (HSE divided by a programmable prescaler) + * @retval None + */ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_REMAP(TIM_Remap)); + + /* Set the Timer remapping configuration */ + TIMx->OR = TIM_Remap; +} +/** + * @} + */ + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input and set the filter */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM + * peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + + /* Select the Input and set the filter */ + tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + + /* Select the Input and set the filter */ + tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @arg TIM_ICPolarity_BothEdge + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + + /* Select the Input and set the filter */ + tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c new file mode 100644 index 000000000..015fdd929 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c @@ -0,0 +1,1469 @@ +/** + ****************************************************************************** + * @file stm32f2xx_usart.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Universal synchronous asynchronous receiver + * transmitter (USART): + * - Initialization and Configuration + * - Data transfers + * - Multi-Processor Communication + * - LIN mode + * - Half-duplex mode + * - Smartcard mode + * - IrDA mode + * - DMA transfers management + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable peripheral clock using the follwoing functions + * RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 + * RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5. + * + * 2. According to the USART mode, enable the GPIO clocks using + * RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, + * or/and SCLK). + * + * 3. Peripheral's alternate function: + * - Connect the pin to the desired peripherals' Alternate + * Function (AF) using GPIO_PinAFConfig() function + * - Configure the desired pin in alternate function by: + * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * - Select the type, pull-up/pull-down and output speed via + * GPIO_PuPd, GPIO_OType and GPIO_Speed members + * - Call GPIO_Init() function + * + * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + * flow control and Mode(Receiver/Transmitter) using the USART_Init() + * function. + * + * 5. For synchronous mode, enable the clock and program the polarity, + * phase and last bit using the USART_ClockInit() function. + * + * 5. Enable the NVIC and the corresponding interrupt using the function + * USART_ITConfig() if you need to use interrupt mode. + * + * 6. When using the DMA mode + * - Configure the DMA using DMA_Init() function + * - Active the needed channel Request using USART_DMACmd() function + * + * 7. Enable the USART using the USART_Cmd() function. + * + * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. + * + * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections + * for more details + * + * In order to reach higher communication baudrates, it is possible to + * enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). + * This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) + * and before calling the function USART_Init(). + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_usart.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ +#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ + USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE)) + +/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ +#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) + +/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ +#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) + +/*!< USART Interrupts mask */ +#define IT_MASK ((uint16_t)0x001F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** @defgroup USART_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + Initialization and Configuration functions + =============================================================================== + + This subsection provides a set of functions allowing to initialize the USART + in asynchronous and in synchronous modes. + - For the asynchronous mode only these parameters can be configured: + - Baud Rate + - Word Length + - Stop Bit + - Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + - Hardware flow control + - Receiver/transmitter modes + + The USART_Init() function follows the USART asynchronous configuration procedure + (details for the procedure are available in reference manual (RM0033)). + + - For the synchronous mode in addition to the asynchronous mode parameters these + parameters should be also configured: + - USART Clock Enabled + - USART polarity + - USART phase + - USART LastBit + + These parameters can be configured using the USART_ClockInit() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else if (USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + else + { + if (USARTx == USART6) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains + * the configuration information for the specified USART peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + + /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ + if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + + /* Clear STOP[13:12] bits */ + tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); + + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : + Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); + + /* Configure the USART Word Length, Parity and mode: + Set the M bits according to USART_WordLength value + Set PCE and PS bits according to USART_Parity value + Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + + /* Write to USART CR1 */ + USARTx->CR1 = (uint16_t)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + + /* Clear CTSE and RTSE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); + + /* Configure the USART HFC : + Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + + /* Write to USART CR3 */ + USARTx->CR3 = (uint16_t)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate */ + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if ((USARTx == USART1) || (USARTx == USART6)) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + /* Write to USART BRR register */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that + * contains the configuration information for the specified USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_UE; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); + } +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_Prescaler: specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= USART_GTPR_GT; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @note This function has to be called before calling USART_Init() function + * in order to have correct baudrate Divider value. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART 8x oversampling mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_OVER8; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); + } +} + +/** + * @brief Enables or disables the USART's one bit sampling method. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_ONEBIT; + } + else + { + /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + Data transfers functions + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART data + transfers. + + During an USART reception, data shifts in least significant bit first through + the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) + between the internal bus and the received shift register. + + When a transmission is taking place, a write instruction to the USART_DR register + stores the data in the TDR register and which is copied in the shift register + at the end of the current transmission. + + The read access of the USART_DR register can be done using the USART_ReceiveData() + function and returns the RDR buffered value. Whereas a write access to the USART_DR + can be done using USART_SendData() function and stores the written data into + TDR buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +} + +/** + * @} + */ + +/** @defgroup USART_Group3 MultiProcessor Communication functions + * @brief Multi-Processor Communication functions + * +@verbatim + =============================================================================== + Multi-Processor Communication functions + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART + multiprocessor communication. + + For instance one of the USARTs can be the master, its TX output is connected to + the RX input of the other USART. The others are slaves, their respective TX outputs + are logically ANDed together and connected to the RX input of the master. + + USART multiprocessor communication is possible through the following procedure: + 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter + or Mode receiver and hardware flow control values using the USART_Init() + function. + 2. Configures the USART address using the USART_SetAddress() function. + 3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) + using USART_WakeUpConfig() function only for the slaves. + 4. Enable the USART using the USART_Cmd() function. + 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. + + The USART Slave exit from mute mode when receive the wake up condition. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the address of the USART node. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_RWU; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); + } +} +/** + * @brief Selects the USART WakeUp method. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @} + */ + +/** @defgroup USART_Group4 LIN mode functions + * @brief LIN mode functions + * +@verbatim + =============================================================================== + LIN mode functions + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART LIN + Mode communication. + + In LIN mode, 8-bit data format with 1 stop bit is required in accordance with + the LIN standard. + + Only this LIN Feature is supported by the USART IP: + - LIN Master Synchronous Break send capability and LIN slave break detection + capability : 13-bit break generation and 10/11 bit break detection + + + USART LIN Master transmitter communication is possible through the following procedure: + 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + 2. Enable the USART using the USART_Cmd() function. + 3. Enable the LIN mode using the USART_LINCmd() function. + 4. Send the break character using USART_SendBreak() function. + + USART LIN Master receiver communication is possible through the following procedure: + 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values using + the USART_Init() function. + 2. Enable the USART using the USART_Cmd() function. + 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig() + function. + 4. Enable the LIN mode using the USART_LINCmd() function. + + +@note In LIN mode, the following bits must be kept cleared: + - CLKEN in the USART_CR2 register, + - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART's LIN mode. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= USART_CR2_LINEN; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); + } +} + +/** + * @brief Transmits break characters. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @retval None + */ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= USART_CR1_SBK; +} + +/** + * @} + */ + +/** @defgroup USART_Group5 Halfduplex mode function + * @brief Half-duplex mode function + * +@verbatim + =============================================================================== + Half-duplex mode function + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART + Half-duplex communication. + + The USART can be configured to follow a single-wire half-duplex protocol where + the TX and RX lines are internally connected. + + USART Half duplex communication is possible through the following procedure: + 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter + or Mode receiver and hardware flow control values using the USART_Init() + function. + 2. Configures the USART address using the USART_SetAddress() function. + 3. Enable the USART using the USART_Cmd() function. + 4. Enable the half duplex mode using USART_HalfDuplexCmd() function. + + +@note The RX pin is no longer used +@note In Half-duplex mode the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register. + - SCEN and IREN bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's Half Duplex communication. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_HDSEL; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); + } +} + +/** + * @} + */ + + +/** @defgroup USART_Group6 Smartcard mode functions + * @brief Smartcard mode functions + * +@verbatim + =============================================================================== + Smartcard mode functions + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART + Smartcard communication. + + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. + + The USART can provide a clock to the smartcard through the SCLK output. + In smartcard mode, SCLK is not associated to the communication but is simply derived + from the internal peripheral input clock through a 5-bit prescaler. + + Smartcard communication is possible through the following procedure: + 1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function. + 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function. + 3. Program the USART clock using the USART_ClockInit() function as following: + - USART Clock enabled + - USART CPOL Low + - USART CPHA on first edge + - USART Last Bit Clock Enabled + 4. Program the Smartcard interface using the USART_Init() function as following: + - Word Length = 9 Bits + - 1.5 Stop Bit + - Even parity + - BaudRate = 12096 baud + - Hardware flow control disabled (RTS and CTS signals) + - Tx and Rx enabled + 5. Optionally you can enable the parity error interrupt using the USART_ITConfig() + function + 6. Enable the USART using the USART_Cmd() function. + 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. + 8. Enable the Smartcard interface using the USART_SmartCardCmd() function. + + Please refer to the ISO 7816-3 specification for more details. + + +@note It is also possible to choose 0.5 stop bit for receiving but it is recommended + to use 1.5 stop bits for both transmitting and receiving to avoid switching + between the two configurations. +@note In smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register. + - HDSEL and IREN bits in the USART_CR3 register. +@note Smartcard mode is available on USART peripherals only (not available on UART4 + and UART5 peripherals). + +@endverbatim + * @{ + */ + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= USART_GTPR_PSC; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Enables or disables the USART's Smart Card mode. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_SCEN; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1236_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_NACK; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group7 IrDA mode functions + * @brief IrDA mode functions + * +@verbatim + =============================================================================== + IrDA mode functions + =============================================================================== + + This subsection provides a set of functions allowing to manage the USART + IrDA communication. + + IrDA is a half duplex communication protocol. If the Transmitter is busy, any data + on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver + is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. + While receiving data, transmission should be avoided as the data to be transmitted + could be corrupted. + + IrDA communication is possible through the following procedure: + 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver + modes and hardware flow control values using the USART_Init() function. + 2. Enable the USART using the USART_Cmd() function. + 3. Configures the IrDA pulse width by configuring the prescaler using + the USART_SetPrescaler() function. + 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode + using the USART_IrDAConfig() function. + 5. Enable the IrDA using the USART_IrDACmd() function. + +@note A pulse of width less than two and greater than one PSC period(s) may or may + not be rejected. +@note The receiver set up time should be managed by software. The IrDA physical layer + specification specifies a minimum of 10 ms delay between transmission and + reception (IrDA is a half duplex protocol). +@note In IrDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register. + - SCEN and HDSEL bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_IREN; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group8 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + DMA transfers management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's DMA interface. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @} + */ + +/** @defgroup USART_Group9 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + + This subsection provides a set of functions allowing to configure the USART + Interrupts sources, DMA channels requests and check or clear the flags or + pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + Polling Mode + ============= + In Polling Mode, the SPI communication can be managed by 10 flags: + 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register + 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register + 3. USART_FLAG_TC : to indicate the status of the transmit operation + 4. USART_FLAG_IDLE : to indicate the status of the Idle Line + 5. USART_FLAG_CTS : to indicate the status of the nCTS input + 6. USART_FLAG_LBD : to indicate the status of the LIN break detection + 7. USART_FLAG_NE : to indicate if a noise error occur + 8. USART_FLAG_FE : to indicate if a frame error occur + 9. USART_FLAG_PE : to indicate if a parity error occur + 10. USART_FLAG_ORE : to indicate if an Overrun error occur + + In this Mode it is advised to use the following functions: + - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); + - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); + + Interrupt Mode + =============== + In Interrupt Mode, the USART communication can be managed by 8 interrupt sources + and 10 pending bits: + + Pending Bits: + ------------- + 1. USART_IT_TXE : to indicate the status of the transmit buffer register + 2. USART_IT_RXNE : to indicate the status of the receive buffer register + 3. USART_IT_TC : to indicate the status of the transmit operation + 4. USART_IT_IDLE : to indicate the status of the Idle Line + 5. USART_IT_CTS : to indicate the status of the nCTS input + 6. USART_IT_LBD : to indicate the status of the LIN break detection + 7. USART_IT_NE : to indicate if a noise error occur + 8. USART_IT_FE : to indicate if a frame error occur + 9. USART_IT_PE : to indicate if a parity error occur + 10. USART_IT_ORE : to indicate if an Overrun error occur + + Interrupt Source: + ----------------- + 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty + interrupt. + 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + 3. USART_IT_TC : specifies the interrupt source for the Transmit complete + interrupt. + 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. + 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. + 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection + interrupt. + 7. USART_IT_PE : specifies the interrupt source for the parity error interrupt. + 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt. + +@note Some parameters are coded in order to use them as interrupt source or as pending bits. + + In this Mode it is advised to use the following functions: + - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); + - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); + - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + + DMA Mode + ======== + In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: + 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request + 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request + + In this Mode it is advised to use the following function: + - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_MASK; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + + /* The CTS flag is not available for UART4 and UART5 */ + if (USART_FLAG == USART_FLAG_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * @note RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * @note TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + * + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + + /* The CTS flag is not available for UART4 and UART5 */ + if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + USARTx->SR = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS : CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD : LIN Break detection interrupt + * @arg USART_IT_TXE : Transmit Data Register empty interrupt + * @arg USART_IT_TC : Transmission complete interrupt + * @arg USART_IT_RXNE : Receive Data register not empty interrupt + * @arg USART_IT_IDLE : Idle line detection interrupt + * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set + * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set + * @arg USART_IT_NE : Noise Error interrupt + * @arg USART_IT_FE : Framing Error interrupt + * @arg USART_IT_PE : Parity Error interrupt + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_IT & IT_MASK; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->SR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or + * UART peripheral. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetITStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * @note RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * @note TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * @note TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + * + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_1236_PERIPH(USARTx)); + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->SR = (uint16_t)~itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c new file mode 100644 index 000000000..c893fb383 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c @@ -0,0 +1,309 @@ +/** + ****************************************************************************** + * @file stm32f2xx_wwdg.c + * @author MCD Application Team + * @version V1.1.2 + * @date 05-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Window watchdog (WWDG) peripheral: + * - Prescaler, Refresh window and Counter configuration + * - WWDG activation + * - Interrupts and flags management + * + * @verbatim + * + * =================================================================== + * WWDG features + * =================================================================== + * + * Once enabled the WWDG generates a system reset on expiry of a programmed + * time period, unless the program refreshes the counter (downcounter) + * before to reach 0x3F value (i.e. a reset is generated when the counter + * value rolls over from 0x40 to 0x3F). + * An MCU reset is also generated if the counter value is refreshed + * before the counter has reached the refresh window value. This + * implies that the counter must be refreshed in a limited window. + * + * Once enabled the WWDG cannot be disabled except by a system reset. + * + * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG + * reset occurs. + * + * The WWDG counter input clock is derived from the APB clock divided + * by a programmable prescaler. + * + * WWDG counter clock = PCLK1 / Prescaler + * WWDG timeout = (WWDG counter clock) * (counter value) + * + * Min-max timeout value @30 MHz(PCLK1): ~136.5 us / ~69.9 ms + * + * =================================================================== + * How to use this driver + * =================================================================== + * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function + * + * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function + * + * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function + * + * 4. Set the WWDG counter value and start it using WWDG_Enable() function. + * When the WWDG is enabled the counter value should be configured to + * a value greater than 0x40 to prevent generating an immediate reset. + * + * 5. Optionally you can enable the Early wakeup interrupt which is + * generated when the counter reach 0x40. + * Once enabled this interrupt cannot be disabled except by a system reset. + * + * 6. Then the application program must refresh the WWDG counter at regular + * intervals during normal operation to prevent an MCU reset, using + * WWDG_SetCounter() function. This operation must occur only when + * the counter value is lower than the refresh window value, + * programmed using WWDG_SetWindowValue(). + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_wwdg.h" +#include "stm32f2xx_rcc.h" + +/** @addtogroup STM32F2xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ +/* CFR register bit mask */ +#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) +#define CFR_W_MASK ((uint32_t)0xFFFFFF80) +#define BIT_MASK ((uint8_t)0x7F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions + * @brief Prescaler, Refresh window and Counter configuration functions + * +@verbatim + =============================================================================== + Prescaler, Refresh window and Counter configuration functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_MASK; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_MASK; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_MASK; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @note Once enabled this interrupt cannot be disabled except by a system reset. + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent generating + * an immediate reset) + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_MASK; +} +/** + * @} + */ + +/** @defgroup WWDG_Group2 WWDG activation functions + * @brief WWDG activation functions + * +@verbatim + =============================================================================== + WWDG activation function + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent generating + * an immediate reset) + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = WWDG_CR_WDGA | Counter; +} +/** + * @} + */ + +/** @defgroup WWDG_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + Interrupts and flags management functions + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((WWDG->SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/MCD-ST Liberty SW License Agreement V2.pdf b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/MCD-ST Liberty SW License Agreement V2.pdf new file mode 100644 index 000000000..d61f43008 Binary files /dev/null and b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/MCD-ST Liberty SW License Agreement V2.pdf differ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/main.c new file mode 100644 index 000000000..e28877a95 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/main.c @@ -0,0 +1,261 @@ +/** + ****************************************************************************** + * @file ADC/ADC3_DMA/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stm322xg_eval_lcd.h" +#include + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup ADC_ADC3_DMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* used to display the ADC converted value on LCD */ +#define PRINT_ON_LCD + /* if you are not using the LCD, you can monitor the converted value by adding + the variable "ADC3ConvertedValue" to the debugger watch window */ + +#define ADC3_DR_ADDRESS ((uint32_t)0x4001224C) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint16_t ADC3ConvertedValue = 0; +__IO uint32_t ADC3ConvertedVoltage = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +void ADC3_CH7_DMA_Config(void); + +#ifdef PRINT_ON_LCD +void Display_Init(void); +void Display(void); +#endif /* PRINT_ON_LCD */ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ +#ifdef PRINT_ON_LCD + /* LCD Display init */ + Display_Init(); +#endif + + /* ADC3 configuration *******************************************************/ + /* - Enable peripheral clocks */ + /* - DMA2_Stream0 channel2 configuration */ + /* - Configure ADC Channel7 pin as analog input */ + /* - Configure ADC3 Channel7 */ + ADC3_CH7_DMA_Config(); + + /* Start ADC3 Software Conversion */ + ADC_SoftwareStartConv(ADC3); + + while (1) + { + ADC3ConvertedVoltage = ADC3ConvertedValue *3300/0xFFF; +#ifdef PRINT_ON_LCD + /* Display ADC3 converted value on LCD */ + Display(); +#endif + } +} + + +/** + * @brief ADC3 channel07 with DMA configuration + * @param None + * @retval None + */ +void ADC3_CH7_DMA_Config(void) +{ + ADC_InitTypeDef ADC_InitStructure; + ADC_CommonInitTypeDef ADC_CommonInitStructure; + DMA_InitTypeDef DMA_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable ADC3, DMA2 and GPIO clocks ****************************************/ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2 | RCC_AHB1Periph_GPIOF, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE); + + /* DMA2 Stream0 channel2 configuration **************************************/ + DMA_InitStructure.DMA_Channel = DMA_Channel_2; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADC3_DR_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&ADC3ConvertedValue; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = 1; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(DMA2_Stream0, &DMA_InitStructure); + DMA_Cmd(DMA2_Stream0, ENABLE); + + /* Configure ADC3 Channel7 pin as analog input ******************************/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; + GPIO_Init(GPIOF, &GPIO_InitStructure); + + /* ADC Common Init **********************************************************/ + ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div2; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; + ADC_CommonInit(&ADC_CommonInitStructure); + + /* ADC3 Init ****************************************************************/ + ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b; + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1; + ADC_Init(ADC3, &ADC_InitStructure); + + /* ADC3 regular channel7 configuration *************************************/ + ADC_RegularChannelConfig(ADC3, ADC_Channel_7, 1, ADC_SampleTime_3Cycles); + + /* Enable DMA request after last transfer (Single-ADC mode) */ + ADC_DMARequestAfterLastTransferCmd(ADC3, ENABLE); + + /* Enable ADC3 DMA */ + ADC_DMACmd(ADC3, ENABLE); + + /* Enable ADC3 */ + ADC_Cmd(ADC3, ENABLE); +} + +#ifdef PRINT_ON_LCD +/** + * @brief Display ADC converted value on LCD + * @param None + * @retval None + */ +void Display(void) +{ + uint32_t v=0,mv=0; + uint8_t text[50]; + + v=(ADC3ConvertedVoltage)/1000; + mv = (ADC3ConvertedVoltage%1000)/100; + sprintf((char*)text," ADC = %d,%d V ",v,mv); + LCD_DisplayStringLine(LINE(6),text); +} + +/** + * @brief Display Init (LCD) + * @param None + * @retval None + */ +void Display_Init(void) +{ + /* Initialize the LCD */ + STM322xG_LCD_Init(); + + /* Clear the LCD */ + LCD_Clear(White); + + /* Set the LCD Text size */ + LCD_SetFont(&Font8x12); + + /* Set the LCD Back Color and Text Color*/ + LCD_SetBackColor(Blue); + LCD_SetTextColor(White); + + /* Display */ + LCD_DisplayStringLine(LINE(0x13), " ADC conversion w/ DMA transfer example "); + + /* Set the LCD Text size */ + LCD_SetFont(&Font16x24); + + /* Display */ + LCD_DisplayStringLine(LINE(0), "ADC Conversion @2Msps"); + + + /* Set the LCD Back Color and Text Color*/ + LCD_SetBackColor(White); + LCD_SetTextColor(Blue); + + /* Display */ + LCD_DisplayStringLine(LINE(2)," Turn RV1(PF.09) "); + LCD_DisplayStringLine(LINE(4)," Potentiometer "); +} +#endif /* PRINT_ON_LCD */ + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/readme.txt new file mode 100644 index 000000000..f9658d964 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/readme.txt @@ -0,0 +1,81 @@ +/** + @page ADC_ADC3_DMA ADC3 conversion using DMA for Data transfer + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file ADC/ADC3_DMA/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the ADC3 DMA example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example describes how to use the ADC3 and DMA to transfer continuously +converted data from ADC3 to memory. +The ADC3 is configured to convert continuously channel7. +Each time an end of conversion occurs the DMA transfers, in circular mode, the +converted data from ADC3 DR register to the ADC3ConvertedValue variable. + +In this example, the system clock is 120MHz, APB2 =60MHz and ADC clock = APB2 /2. +Since ADC3 clock is 30 MHz and sampling time is set to 3 cycles, the total +conversion time is 0.5 us (2Msps). + +User can vary the ADC3 channel7 voltage using the Eval Board potentiometer +The converted voltage is displayed on the Eval Board LCD (when the define PRINT_ON_LCD +is enabled in main.c) + + +@par Directory contents + + - ADC/ADC3_DMA/system_stm32f2xx.c STM32F2xx system clock configuration file + - ADC/ADC3_DMA/stm32f2xx_conf.h Library Configuration file + - ADC/ADC3_DMA/stm32f2xx_it.c Interrupt handlers + - ADC/ADC3_DMA/stm32f2xx_it.h Interrupt handlers header file + - ADC/ADC3_DMA/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use the Potentiometer (RV1) of the Eval board (connected to PF.09). + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/stm32f2xx_conf.h new file mode 100644 index 000000000..e628d3a42 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file ADC/ADC3_DMA/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/stm32f2xx_it.c new file mode 100644 index 000000000..007e9f34b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/stm32f2xx_it.c @@ -0,0 +1,170 @@ +/** + ****************************************************************************** + * @file ADC/ADC3_DMA/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup ADC_ADC3_DMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/stm32f2xx_it.h new file mode 100644 index 000000000..e7ed20488 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file ADC/ADC3_DMA/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/ADC3_DMA/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/main.c new file mode 100644 index 000000000..85ffed586 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/main.c @@ -0,0 +1,274 @@ +/** + ****************************************************************************** + * @file ADC/DualADC_Interleaved_DMAmode3/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stm322xg_eval_lcd.h" +#include + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup ADC_DualADC_Interleaved_DMAmode3 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* used to display the ADC converted value on LCD */ +#define PRINT_ON_LCD + /* if you are not using the LCD, you can monitor the converted values by adding + the variable "ADCDualConvertedValue" to the debugger watch window */ + +#define ADC_CDR_ADDRESS ((uint32_t)0x40012308) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint16_t ADCDualConvertedValue; + +ADC_InitTypeDef ADC_InitStructure; +ADC_CommonInitTypeDef ADC_CommonInitStructure; +DMA_InitTypeDef DMA_InitStructure; +GPIO_InitTypeDef GPIO_InitStructure; + +/* Private function prototypes -----------------------------------------------*/ +#ifdef PRINT_ON_LCD +void Display_Init(void); +void Display(void); +#endif /* PRINT_ON_LCD */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ +#ifdef PRINT_ON_LCD + /* LCD Display init */ + Display_Init(); +#endif /* PRINT_ON_LCD */ + +/******************************************************************************/ +/* ADCs interface clock, pin and DMA configuration */ +/******************************************************************************/ + + /* Enable peripheral clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2 | RCC_AHB1Periph_GPIOC, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2, ENABLE); + + /* Configure ADC Channel 12 pin as analog input */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* DMA2 Stream0 channel0 configuration */ + DMA_InitStructure.DMA_Channel = DMA_Channel_0; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADC_CDR_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&ADCDualConvertedValue; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = 1; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(DMA2_Stream0, &DMA_InitStructure); + + /* DMA2_Stream0 enable */ + DMA_Cmd(DMA2_Stream0, ENABLE); + +/******************************************************************************/ +/* ADCs configuration: double interleaved with 6cycles delay to reach 5Msps */ +/******************************************************************************/ + + /* ADC Common configuration *************************************************/ + ADC_CommonInitStructure.ADC_Mode = ADC_DualMode_Interl; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_6Cycles; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_3; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div2; + ADC_CommonInit(&ADC_CommonInitStructure); + + /* DMA mode 3 is used in interleaved mode in 6-bit or 8-bit resolutions */ + ADC_InitStructure.ADC_Resolution = ADC_Resolution_8b; + + /* ADC1 regular channel 12 configuration ************************************/ + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1; + ADC_Init(ADC1, &ADC_InitStructure); + /* ADC1 regular channel12 configuration */ + ADC_RegularChannelConfig(ADC1, ADC_Channel_12, 1, ADC_SampleTime_3Cycles); + + /* ADC2 regular channel 12 configuration ************************************/ + ADC_Init(ADC2, &ADC_InitStructure); + /* ADC2 regular channel12 configuration */ + ADC_RegularChannelConfig(ADC2, ADC_Channel_12, 1, ADC_SampleTime_3Cycles); + + /* Enable DMA request after last transfer (multi-ADC mode) ******************/ + ADC_MultiModeDMARequestAfterLastTransferCmd(ENABLE); + + /* Enable ADC1 **************************************************************/ + ADC_Cmd(ADC1, ENABLE); + + /* Enable ADC2 **************************************************************/ + ADC_Cmd(ADC2, ENABLE); + + /* Start ADC1 Software Conversion */ + ADC_SoftwareStartConv(ADC1); + + while (1) + { +#ifdef PRINT_ON_LCD + /* Display ADCs converted values on LCD */ + Display(); +#endif /* PRINT_ON_LCD */ + } +} + +#ifdef PRINT_ON_LCD +/** + * @brief Display ADCs converted values on LCD + * @param None + * @retval None + */ +void Display(void) +{ + uint32_t Voltage =0, mVoltage=0; + uint8_t text[50]; + __IO uint32_t ADC1ConvertedVoltage; + __IO uint32_t ADC2ConvertedVoltage; + __IO uint8_t ADC1ConvertedValue; + __IO uint8_t ADC2ConvertedValue; + + ADC1ConvertedValue = (ADCDualConvertedValue & 0x00FF); + ADC1ConvertedVoltage = ADC1ConvertedValue *3300/0xFF; + + Voltage = (ADC1ConvertedVoltage)/1000; + mVoltage = (ADC1ConvertedVoltage%1000)/100; + sprintf((char*)text," ADC1 = %d,%d V ",Voltage,mVoltage); + LCD_DisplayStringLine(LINE(6),text); + + + ADC2ConvertedValue = (ADCDualConvertedValue >>8); + ADC2ConvertedVoltage = ADC2ConvertedValue *3300/0xFF; + + Voltage=ADC2ConvertedVoltage/1000; + mVoltage = (ADC2ConvertedVoltage%1000)/100; + sprintf((char*)text," ADC2 = %d,%d V ",Voltage,mVoltage); + LCD_DisplayStringLine(LINE(7),text); +} + +/** + * @brief Display Init (LCD) + * @param None + * @retval None + */ +void Display_Init(void) +{ + +/* Initialize the LCD */ + STM322xG_LCD_Init(); + + /* Clear the LCD */ + LCD_Clear(White); + + /* Set the LCD Text size */ + LCD_SetFont(&Font8x12); + + /* Set the LCD Back Color and Text Color*/ + LCD_SetBackColor(Blue); + LCD_SetTextColor(White); + + LCD_DisplayStringLine(LINE(0x13), " Dual ADC Interleaved DMA mode3 example "); + + + /* Set the LCD Text size */ + LCD_SetFont(&Font16x24); + + LCD_DisplayStringLine(LINE(0), "ADC Ch12 Conv 5Msps "); + + + /* Set the LCD Back Color and Text Color*/ + LCD_SetBackColor(White); + LCD_SetTextColor(Blue); + + LCD_DisplayStringLine(LINE(2)," Connect voltage to "); + LCD_DisplayStringLine(LINE(3)," ADC Ch12 (PC.02) "); +} +#endif /* PRINT_ON_LCD */ + + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/readme.txt new file mode 100644 index 000000000..def2f4998 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/readme.txt @@ -0,0 +1,93 @@ +/** + @page DualADC_Interleaved_DMAmode3 Use ADC1 and ADC2 in Dual interleaved mode and DMA mode3 + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file ADC/DualADC_Interleaved_DMAmode3/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the Dual interleaved mode and DMA mode3 Example + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the ADC peripheral to +convert a regular channel in Dual interleaved mode using DMA in mode 3 with 5Msps. + +DMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions. + +The Dual interleaved delay is configured 6 ADC clk cycles. + +On each DMA request (two data items are available) two bytes representing two +ADC-converted data items are transferred as a half word. +The data transfer order is similar to that of the DMA mode 2. + +A DMA request is generated each time 2 data items are available +1st request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0] +2nd request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0] + +The ADC1 and ADC2 are configured to convert ADC Channel 12, with conversion +triggered by software. +By this way, ADC channel 12 is converted each 6 cycles. + +In this example, the system clock is 120MHz, APB2 =60MHz and ADC clock = APB2 /2. +Since ADCCLK= 30MHz and Conversion rate = 6 cycle +==> Conversion Time = 30M/6cyc = 5Msps. + +@note Refer to "simulation.xls" file to have the diagram simulation of the example. + + +@par Directory contents + + - ADC/DualADC_Interleaved_DMAmode3/system_stm32f2xx.c STM32F2xx system clock configuration file + - ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_conf.h Library Configuration file + - ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.h Interrupt handlers header file + - ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.c Interrupt handlers + - ADC/DualADC_Interleaved_DMAmode3/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + - STM322xG-EVAL Set-up + - Connect PC.2 to a power supply (do not forget to connect the power supply + GND to the EVAL board GND) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/simulation.xls b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/simulation.xls new file mode 100644 index 000000000..14cac4a57 Binary files /dev/null and b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/simulation.xls differ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_conf.h new file mode 100644 index 000000000..acbcd1d6c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.c new file mode 100644 index 000000000..1626c7062 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.c @@ -0,0 +1,174 @@ +/** + ****************************************************************************** + * @file ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup ADC_DualADC_Interleaved_DMAmode3 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.h new file mode 100644 index 000000000..d8a4d2970 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_Interleaved_DMAmode3/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/main.c new file mode 100644 index 000000000..bc161d6b8 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/main.c @@ -0,0 +1,234 @@ +/** + ****************************************************************************** + * @file ADC/DualADC_RegulSimu_DMAmode1/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup ADC_DualADC_RegulSimu_DMAmode1 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define ADC_CCR_ADDRESS ((uint32_t)0x40012308) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint16_t ADCDualConvertedValue[4]; + +/* Private function prototypes -----------------------------------------------*/ +void DMA_Config(void); +void GPIO_Config(void); +void ADC1_CH10_CH11_Config(void); +void ADC2_CH11_CH12_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + ADC_CommonInitTypeDef ADC_CommonInitStructure; + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Enable peripheral clocks *************************************************/ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2 | RCC_AHB1Periph_GPIOC, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1|RCC_APB2Periph_ADC2, ENABLE); + + /* DMA2 Stream0 channel0 configuration **************************************/ + DMA_Config(); + + /* ADCs configuration ------------------------------------------------------*/ + /* Configure ADC Channel10, 11, 12 pin as analog input */ + GPIO_Config(); + + /* ADC Common Init */ + ADC_CommonInitStructure.ADC_Mode = ADC_DualMode_RegSimult; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div2; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_1; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; + ADC_CommonInit(&ADC_CommonInitStructure); + + /* ADC1 regular channels 10, 11 configuration */ + ADC1_CH10_CH11_Config(); + + /* ADC2 regular channels 11, 12 configuration */ + ADC2_CH11_CH12_Config(); + + /* Enable DMA request after last transfer (Multi-ADC mode) */ + ADC_MultiModeDMARequestAfterLastTransferCmd(ENABLE); + + /* Enable ADC1 */ + ADC_Cmd(ADC1, ENABLE); + + /* Enable ADC2 */ + ADC_Cmd(ADC2, ENABLE); + + /* Start ADC1 Software Conversion */ + ADC_SoftwareStartConv(ADC1); + + while (1) + { + } +} + +/** + * @brief ADC1 regular channels 10 and 11 configuration + * @param None + * @retval None + */ +void ADC1_CH10_CH11_Config(void) +{ + ADC_InitTypeDef ADC_InitStructure; + + ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b; + ADC_InitStructure.ADC_ScanConvMode = ENABLE; + ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 2; + ADC_Init(ADC1, &ADC_InitStructure); + + /* ADC1 regular channels 10, 11 configuration */ + ADC_RegularChannelConfig(ADC1, ADC_Channel_10, 1, ADC_SampleTime_3Cycles); + ADC_RegularChannelConfig(ADC1, ADC_Channel_11, 2, ADC_SampleTime_3Cycles); +} + +/** + * @brief ADC2 regular channels 11, 12 configuration + * @param None + * @retval None + */ +void ADC2_CH11_CH12_Config(void) +{ + ADC_InitTypeDef ADC_InitStructure; + + ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b; + ADC_InitStructure.ADC_ScanConvMode = ENABLE; + ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 2; + ADC_Init(ADC2, &ADC_InitStructure); + + /* ADC2 regular channels 11, 12 configuration */ + ADC_RegularChannelConfig(ADC2, ADC_Channel_11, 1, ADC_SampleTime_3Cycles); + ADC_RegularChannelConfig(ADC2, ADC_Channel_12, 2, ADC_SampleTime_3Cycles); +} + +/** + * @brief DMA Configuration + * @param None + * @retval None + */ +void DMA_Config(void) +{ + DMA_InitTypeDef DMA_InitStructure; + + DMA_InitStructure.DMA_Channel = DMA_Channel_0; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&ADCDualConvertedValue; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADC_CCR_ADDRESS; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = 4; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(DMA2_Stream0, &DMA_InitStructure); + + /* DMA2_Stream0 enable */ + DMA_Cmd(DMA2_Stream0, ENABLE); +} + +/** + * @brief Configure ADC Channels 10, 11, 12 pins as analog inputs + * @param None + * @retval None + */ +void GPIO_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + /* ADC Channel 10 -> PC0 + ADC Channel 11 -> PC1 + ADC Channel 12 -> PC2 + */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; + GPIO_Init(GPIOC, &GPIO_InitStructure); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/readme.txt new file mode 100644 index 000000000..dddf6a163 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/readme.txt @@ -0,0 +1,94 @@ +/** + @page DualADC_RegulSimu_DMAmode1 Use ADC1 and ADC2 in Dual regular simultaneous mode and DMA mode1 + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file ADC/DualADC_RegulSimu_DMAmode1/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the Dual regular simultaneous mode and DMA mode1 + * Example + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the ADC peripheral to +convert regular channels simultaneously in dual mode using DMA in mode 1. + +Regular simultaneous mode is performed on a regular group of channels. +In Dual ADC mode, ADC1 data are transferred on the first request, ADC2 data are +transferred on the second request and so on. +On each DMA request (one data item is available), a half-word representing an +ADC-converted data item is transferred. +The conversion is triggered by software. + +The ADC1 is configured to convert ADC Channel 10 and 11. +The ADC2 is configured to convert ADC Channel 11 and 12. + +Note: the sequence length must be the same for both ADCs + +In this example, the system clock is 120MHz, APB2 =60MHz and ADC clock = APB2 /2. +So ADCCLK= 30MHz + +Conversion rate of channel 10 and 12 = 30 cycles => Conversion Time = 30M/30cyc = 1Msps. +Conversion rate of channel 11 = 15 cycles => Conversion Time = 30M/15cyc = 2Msps. + +@note Refer to "simulation.xls" file to have the diagram simulation of the example. + + +@par Directory contents + + - ADC/DualADC_RegulSimu_DMAmode1/system_stm32f2xx.c STM32F2xx system clock configuration file + - ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_conf.h Library Configuration file + - ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.h Interrupt handlers header file + - ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.c Interrupt handlers + - ADC/DualADC_RegulSimu_DMAmode1/main.c Main program + + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect PC.0, PC.1 and PC.2 to a power supply (do not forget to connect the + power supply GND to the EVAL board GND) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/simulation.xls b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/simulation.xls new file mode 100644 index 000000000..c14afef64 Binary files /dev/null and b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/simulation.xls differ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_conf.h new file mode 100644 index 000000000..a022d13b4 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.c new file mode 100644 index 000000000..555d0b3fb --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup ADC_DualADC_RegulSimu_DMAmode1 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.h new file mode 100644 index 000000000..33d0f7625 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/DualADC_RegulSimu_DMAmode1/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/main.c new file mode 100644 index 000000000..bcc74a36f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/main.c @@ -0,0 +1,187 @@ +/** + ****************************************************************************** + * @file ADC/TripleADC_Interleaved_DMAmode2/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup ADC_TripleADC_Interleaved_DMAmode2 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define ADC_CDR_ADDRESS ((uint32_t)0x40012308) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t ADCTripleConvertedValue[3]; + +ADC_InitTypeDef ADC_InitStructure; +ADC_CommonInitTypeDef ADC_CommonInitStructure; +DMA_InitTypeDef DMA_InitStructure; +GPIO_InitTypeDef GPIO_InitStructure; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + +/******************************************************************************/ +/* ADCs interface clock, pin and DMA configuration */ +/******************************************************************************/ + + /* Enable peripheral clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2 | RCC_AHB1Periph_GPIOC, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_ADC2 | + RCC_APB2Periph_ADC3, ENABLE); + + /* Configure ADC Channel 12 pin as analog input */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* DMA2 Stream0 channel0 configuration */ + DMA_InitStructure.DMA_Channel = DMA_Channel_0; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADC_CDR_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&ADCTripleConvertedValue; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = 3; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(DMA2_Stream0, &DMA_InitStructure); + + /* DMA2_Stream0 enable */ + DMA_Cmd(DMA2_Stream0, ENABLE); + + +/******************************************************************************/ +/* ADCs configuration: triple interleaved with 5cycles delay to reach 6Msps */ +/******************************************************************************/ + + /* ADC Common configuration *************************************************/ + ADC_CommonInitStructure.ADC_Mode = ADC_TripleMode_Interl; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_2; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div2; + ADC_CommonInit(&ADC_CommonInitStructure); + + /* ADC1 regular channel 12 configuration ************************************/ + ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b; + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1; + ADC_Init(ADC1, &ADC_InitStructure); + + ADC_RegularChannelConfig(ADC1, ADC_Channel_12, 1, ADC_SampleTime_3Cycles); + + /* ADC2 regular channel 12 configuration ************************************/ + ADC_Init(ADC2, &ADC_InitStructure); + /* ADC2 regular channel12 configuration */ + ADC_RegularChannelConfig(ADC2, ADC_Channel_12, 1, ADC_SampleTime_3Cycles); + + /* ADC3 regular channel 12 configuration ************************************/ + ADC_Init(ADC3, &ADC_InitStructure); + /* ADC3 regular channel12 configuration */ + ADC_RegularChannelConfig(ADC3, ADC_Channel_12, 1, ADC_SampleTime_3Cycles); + + /* Enable DMA request after last transfer (multi-ADC mode) ******************/ + ADC_MultiModeDMARequestAfterLastTransferCmd(ENABLE); + + /* Enable ADC1 **************************************************************/ + ADC_Cmd(ADC1, ENABLE); + + /* Enable ADC2 **************************************************************/ + ADC_Cmd(ADC2, ENABLE); + + /* Enable ADC3 **************************************************************/ + ADC_Cmd(ADC3, ENABLE); + + /* Start ADC1 Software Conversion */ + ADC_SoftwareStartConv(ADC1); + + while (1) + { + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/readme.txt new file mode 100644 index 000000000..944147319 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/readme.txt @@ -0,0 +1,105 @@ +/** + @page TripleADC_Interleaved_DMAmode2 Use ADC1, ADC2 and ADC3 in Triple interleaved mode and DMA mode2 with 6Msps + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file ADC/TripleADC_Interleaved_DMAmode2/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the Triple interleaved mode and DMA mode2 Example + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the ADC peripheral to +convert a regular channel in Triple interleaved mode using DMA in mode 2 with +6Msps . + +The Triple interleaved delay is configured 5 ADC clk cycles. + +In Triple ADC mode, three DMA requests are generated: +- On the first request, both ADC2 and ADC1 data are transferred (ADC2 data take + the upper half-word and ADC1 data take the lower half-word). +- On the second request, both ADC1 and ADC3 data are transferred (ADC1 data take + the upper half-word and ADC3 data take the lower half-word). +- On the third request, both ADC3 and ADC2 data are transferred (ADC3 data take + the upper half-word and ADC2 data take the lower half-word) and so on. + +On each DMA request (two data items are available) two half-words representing +two ADC-converted data items are transferred as a word. + +A DMA request is generated each time 2 data items are available : +1st request: ADC_CDR[31:0] = (ADC2_DR[15:0] << 16) | ADC1_DR[15:0] (step1) +2nd request: ADC_CDR[31:0] = (ADC1_DR[15:0] << 16) | ADC3_DR[15:0] (step2) +3rd request: ADC_CDR[31:0] = (ADC3_DR[15:0] << 16) | ADC2_DR[15:0] (step3) +4th request: ADC_CDR[31:0] = (ADC2_DR[15:0] << 16) | ADC1_DR[15:0] (step1) and so on. + +The conversion is triggered by software. + +The ADC1, ADC2 and ADC3 are configured to convert ADC Channel 12. +By this way, the ADC can reach 6Msps, in fact the same channel is converted +each 5 cycles + +In this example, the system clock is 120MHz, APB2 = 60MHz and ADC clock = APB2 /2. +Since ADCCLK= 30MHz and Conversion rate = 5 cycles +==> Conversion Time = 30M/5cyc = 6Msps + +@note Refer to "simulation.xls" file to have the diagram simulation of the example. + + +@par Directory contents + + - ADC/TripleADC_Interleaved_DMAmode2/system_stm32f2xx.c STM32F2xx system clock configuration file + - ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_conf.h Library Configuration file + - ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.h Interrupt handlers header file + - ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.c Interrupt handlers + - ADC/TripleADC_Interleaved_DMAmode2/main.c Main program + + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect PC.2 to a power supply (do not forget to connect the power supply GND + to the EVAL board GND) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/simulation.xls b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/simulation.xls new file mode 100644 index 000000000..89ff21d21 Binary files /dev/null and b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/simulation.xls differ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_conf.h new file mode 100644 index 000000000..874d423b7 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.c new file mode 100644 index 000000000..15cc61d5b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup ADC_TripleADC_Interleaved_DMAmode2 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.h new file mode 100644 index 000000000..0f48f141e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/TripleADC_Interleaved_DMAmode2/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/main.c new file mode 100644 index 000000000..f06197845 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/main.c @@ -0,0 +1,270 @@ +/** + ****************************************************************************** + * @file ADC/VBAT_Measurement/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stm322xg_eval_lcd.h" +#include + + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup ADC_VBAT_Measurement + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* used to display the ADC converted value on LCD */ +#define PRINT_ON_LCD + /* if you are not using the LCD, you can monitor the converted value by adding + the variable "ADCConvertedValue" to the debugger watch window */ + +#define ADC1_DR_ADDRESS ((uint32_t)0x4001204C) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint16_t ADCConvertedValue = 0; +__IO uint32_t VBATVoltage = 0; + +/* Private function prototypes -----------------------------------------------*/ +void ADC1_ChVbat_DMA_Config(void); + +#ifdef PRINT_ON_LCD +void Display_Init(void); +void Display(void); +static void delay(__IO uint32_t nCount); +#endif /* PRINT_ON_LCD */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ +#ifdef PRINT_ON_LCD + /* LCD Display init */ + Display_Init(); +#endif /* PRINT_ON_LCD */ + + /* ADC1 Channel Vbat configuration */ + ADC1_ChVbat_DMA_Config(); + + /* Start ADC1 Software Conversion */ + ADC_SoftwareStartConv(ADC1); + + while (1) + { +#ifdef PRINT_ON_LCD + /* Display ADC converted value on LCD */ + Display(); +#endif /* PRINT_ON_LCD */ + } +} + +/** + * @brief ADC1 Channel Vbat configuration (DMA, ADC, CLK) + * @param None + * @retval None + */ +void ADC1_ChVbat_DMA_Config(void) +{ + ADC_InitTypeDef ADC_InitStructure; + ADC_CommonInitTypeDef ADC_CommonInitStructure; + DMA_InitTypeDef DMA_InitStructure; + + /* Enable peripheral clocks *************************************************/ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); + + /* DMA2_Stream0 channel0 configuration **************************************/ + DMA_DeInit(DMA2_Stream0); + DMA_InitStructure.DMA_Channel = DMA_Channel_0; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)ADC1_DR_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&ADCConvertedValue; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = 1; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(DMA2_Stream0, &DMA_InitStructure); + /* DMA2_Stream0 enable */ + DMA_Cmd(DMA2_Stream0, ENABLE); + + /* ADC Common Init **********************************************************/ + ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div2; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; + ADC_CommonInit(&ADC_CommonInitStructure); + + /* ADC1 Init ****************************************************************/ + ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b; + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1; + ADC_Init(ADC1, &ADC_InitStructure); + + /* Enable ADC1 DMA */ + ADC_DMACmd(ADC1, ENABLE); + + /* ADC1 regular channel18 (VBAT) configuration ******************************/ + ADC_RegularChannelConfig(ADC1, ADC_Channel_Vbat, 1, ADC_SampleTime_15Cycles); + + /* Enable VBAT channel */ + ADC_VBATCmd(ENABLE); + + /* Enable DMA request after last transfer (Single-ADC mode) */ + ADC_DMARequestAfterLastTransferCmd(ADC1, ENABLE); + + /* Enable ADC1 **************************************************************/ + ADC_Cmd(ADC1, ENABLE); +} + +#ifdef PRINT_ON_LCD +/** + * @brief Display ADC converted value on LCD + * @param None + * @retval None + */ +void Display(void) +{ + uint32_t vbatV=0,vbatmV=0; + uint8_t text[50]; + + /*The VBAT pin is internally connected to a bridge divider by 2 */ + VBATVoltage = (ADCConvertedValue*2)*3300/0xFFF; + vbatV=VBATVoltage/1000; + vbatmV = (VBATVoltage%1000)/100; + sprintf((char*)text," %d,%d V ",vbatV,vbatmV); + LCD_DisplayStringLine(LINE(6),text); + + delay(100); +} + +/** + * @brief Display Init (LCD) + * @param None + * @retval None + */ +void Display_Init(void) +{ + + /* Initialize the LCD */ + STM322xG_LCD_Init(); + + /* Clear the LCD */ + LCD_Clear(White); + + /* Set the LCD Text size */ + LCD_SetFont(&Font8x12); + + /* Set the LCD Back Color and Text Color*/ + LCD_SetBackColor(Blue); + LCD_SetTextColor(White); + + LCD_DisplayStringLine(LINE(0x13), " STM32F2xx ADC1 VBAT Measurement example"); + + /* Set the LCD Text size */ + LCD_SetFont(&Font16x24); + + LCD_DisplayStringLine(LINE(0), "**VBAT Measurement**"); + + /* Set the LCD Back Color and Text Color*/ + LCD_SetBackColor(White); + LCD_SetTextColor(Blue); + + LCD_DisplayStringLine(LINE(2)," Eval Board Instant "); + LCD_DisplayStringLine(LINE(4)," Battery Voltage "); +} + +/** + * @brief Inserts a delay time + * @param nCount: specifies the delay time length + * @retval None + */ +static void delay(__IO uint32_t nCount) +{ + __IO uint32_t index = 0; + for(index = (100000 * nCount); index != 0; index--) + { + } +} +#endif /* PRINT_ON_LCD */ + + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/readme.txt new file mode 100644 index 000000000..d2c303f24 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/readme.txt @@ -0,0 +1,86 @@ +/** + @page ADC_VBAT_Measurement ADC_VBAT_Measurement + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file ADC/VBAT_Measurement/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the ADC1 VBAT Measurement example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example describes how to measure VBAT voltage using ADC1 regular channel 18. +In fact, the measured value correspond to VBAT/2; as the VBAT voltage could be higher +than VDDA, to ensure the correct operation of the ADC, the VBAT pin is internally +connected to a bridge divider by 2. + +In this example the VBAT/2 voltage is continuously converted, each time an end +of conversion occurs the DMA transfers, in circular mode, the converted data from +ADC1 DR register to the ADCConvertedValue variable. +However, in real application to prevent any unwanted consumption on the battery, +it is recommended to enable the bridge divider only when needed for ADC +conversion then disable it. + +User can display the VBAT voltage on the Eval Board LCD (when the define PRINT_ON_LCD +is enabled in main.c) + +In this example, the system clock is 120MHz, APB2 =60MHz and ADC clock = APB2 /2. +So ADCCLK= 30MHz + +Conversion rate of Vbat channel = Sampling Time + Conversion Time = 15 + 12 cycles + = 27 cycles ==> Conversion Time = 30MHz/27cyc = 1.11Msps. + + +@par Directory contents + + - ADC/VBAT_Measurement/system_stm32f2xx.c STM32F2xx system clock configuration file + - ADC/VBAT_Measurement/stm32f2xx_conf.h Library Configuration file + - ADC/VBAT_Measurement/stm32f2xx_it.c Interrupt handlers + - ADC/VBAT_Measurement/stm32f2xx_it.h Interrupt handlers header file + - ADC/VBAT_Measurement/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/stm32f2xx_conf.h new file mode 100644 index 000000000..4e892df09 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file ADC/VBAT_Measurement/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/stm32f2xx_it.c new file mode 100644 index 000000000..3f090a8b7 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/stm32f2xx_it.c @@ -0,0 +1,170 @@ +/** + ****************************************************************************** + * @file ADC/VBAT_Measurement/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup ADC_VBAT_Measurement + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/stm32f2xx_it.h new file mode 100644 index 000000000..633ec0a8b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file ADC/VBAT_Measurement/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/ADC/VBAT_Measurement/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/main.c new file mode 100644 index 000000000..8fe878266 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/main.c @@ -0,0 +1,359 @@ +/** + ****************************************************************************** + * @file CAN/LoopBack/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CAN_LoopBack + * @{ + */ + +/* Private define ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t ret = 0; /* for return of the interrupt handling */ +volatile TestStatus TestRx; + +/* Private function prototypes -----------------------------------------------*/ +void NVIC_Config(void); +TestStatus CAN_Polling(void); +TestStatus CAN_Interrupt(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + +#ifdef USE_CAN1 + /* CANx Periph clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); +#else /* USE_CAN2 */ + /* CAN1 & 2 Periph clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1 | RCC_APB1Periph_CAN2, ENABLE); +#endif /* USE_CAN1 */ + + /* NVIC Configuration */ + NVIC_Config(); + + /* Configures LED 1..4 */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* CAN transmit at 125Kb/s and receive by polling in loopback mode */ + TestRx = CAN_Polling(); + + if (TestRx != FAILED) + { /* OK */ + + /* Turn on LED1 */ + STM_EVAL_LEDOn(LED1); + } + else + { /* KO */ + + /* Turn on LED3 */ + STM_EVAL_LEDOn(LED3); + } + + /* CAN transmit at 500Kb/s and receive by interrupt in loopback mode */ + TestRx = CAN_Interrupt(); + + if (TestRx != FAILED) + { /* OK */ + + /* Turn on LED4 */ + STM_EVAL_LEDOn(LED4); + } + else + { /* KO */ + + /* Turn on LED2 */ + STM_EVAL_LEDOn(LED2); + } + + /* Infinite loop */ + while (1) + { + } +} + +/** + * @brief Configures the CAN, transmit and receive by polling + * @param None + * @retval PASSED if the reception is well done, FAILED in other case + */ +TestStatus CAN_Polling(void) +{ + CAN_InitTypeDef CAN_InitStructure; + CAN_FilterInitTypeDef CAN_FilterInitStructure; + CanTxMsg TxMessage; + CanRxMsg RxMessage; + uint32_t i = 0; + uint8_t TransmitMailbox = 0; + + /* CAN register init */ + CAN_DeInit(CANx); + + /* CAN cell init */ + CAN_InitStructure.CAN_TTCM = DISABLE; + CAN_InitStructure.CAN_ABOM = DISABLE; + CAN_InitStructure.CAN_AWUM = DISABLE; + CAN_InitStructure.CAN_NART = DISABLE; + CAN_InitStructure.CAN_RFLM = DISABLE; + CAN_InitStructure.CAN_TXFP = DISABLE; + CAN_InitStructure.CAN_Mode = CAN_Mode_LoopBack; + CAN_InitStructure.CAN_SJW = CAN_SJW_1tq; + + /* CAN Baudrate = 125kbps (CAN clocked at 30 MHz) */ + CAN_InitStructure.CAN_BS1 = CAN_BS1_6tq; + CAN_InitStructure.CAN_BS2 = CAN_BS2_8tq; + CAN_InitStructure.CAN_Prescaler = 16; + CAN_Init(CANx, &CAN_InitStructure); + + /* CAN filter init */ +#ifdef USE_CAN1 + CAN_FilterInitStructure.CAN_FilterNumber = 0; +#else /* USE_CAN2 */ + CAN_FilterInitStructure.CAN_FilterNumber = 14; +#endif /* USE_CAN1 */ + CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask; + CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit; + CAN_FilterInitStructure.CAN_FilterIdHigh = 0x0000; + CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000; + CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000; + CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000; + CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0; + + CAN_FilterInitStructure.CAN_FilterActivation = ENABLE; + CAN_FilterInit(&CAN_FilterInitStructure); + + /* transmit */ + TxMessage.StdId = 0x11; + TxMessage.RTR = CAN_RTR_DATA; + TxMessage.IDE = CAN_ID_STD; + TxMessage.DLC = 2; + TxMessage.Data[0] = 0xCA; + TxMessage.Data[1] = 0xFE; + + TransmitMailbox = CAN_Transmit(CANx, &TxMessage); + i = 0; + while((CAN_TransmitStatus(CANx, TransmitMailbox) != CANTXOK) && (i != 0xFFFF)) + { + i++; + } + + i = 0; + while((CAN_MessagePending(CANx, CAN_FIFO0) < 1) && (i != 0xFFFF)) + { + i++; + } + + /* receive */ + RxMessage.StdId = 0x00; + RxMessage.IDE = CAN_ID_STD; + RxMessage.DLC = 0; + RxMessage.Data[0] = 0x00; + RxMessage.Data[1] = 0x00; + CAN_Receive(CANx, CAN_FIFO0, &RxMessage); + + if (RxMessage.StdId != 0x11) + { + return FAILED; + } + + if (RxMessage.IDE != CAN_ID_STD) + { + return FAILED; + } + + if (RxMessage.DLC != 2) + { + return FAILED; + } + + if ((RxMessage.Data[0]<<8|RxMessage.Data[1]) != 0xCAFE) + { + return FAILED; + } + + return PASSED; /* Test Passed */ +} + +/** + * @brief Configures the CAN, transmit and receive using interrupt. + * @param None + * @retval PASSED if the reception is well done, FAILED in other case + */ +TestStatus CAN_Interrupt(void) +{ + CAN_InitTypeDef CAN_InitStructure; + CAN_FilterInitTypeDef CAN_FilterInitStructure; + CanTxMsg TxMessage; + uint32_t i = 0; + + /* CAN register init */ + CAN_DeInit(CANx); + + /* CAN cell init */ + CAN_InitStructure.CAN_TTCM = DISABLE; + CAN_InitStructure.CAN_ABOM = DISABLE; + CAN_InitStructure.CAN_AWUM = DISABLE; + CAN_InitStructure.CAN_NART = DISABLE; + CAN_InitStructure.CAN_RFLM = DISABLE; + CAN_InitStructure.CAN_TXFP = DISABLE; + CAN_InitStructure.CAN_Mode = CAN_Mode_LoopBack; + CAN_InitStructure.CAN_SJW = CAN_SJW_1tq; + + /* Baudrate = 500 Kbps */ + CAN_InitStructure.CAN_BS1 = CAN_BS1_6tq; + CAN_InitStructure.CAN_BS2 = CAN_BS2_8tq; + CAN_InitStructure.CAN_Prescaler = 4; + CAN_Init(CANx, &CAN_InitStructure); + + /* CAN filter init */ +#ifdef USE_CAN1 + CAN_FilterInitStructure.CAN_FilterNumber = 1; +#else /* USE_CAN2 */ + CAN_FilterInitStructure.CAN_FilterNumber = 15; +#endif /* USE_CAN1 */ + CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask; + CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit; + CAN_FilterInitStructure.CAN_FilterIdHigh = 0x0000; + CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000; + CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000; + CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000; + CAN_FilterInitStructure.CAN_FilterFIFOAssignment = CAN_FIFO0; + CAN_FilterInitStructure.CAN_FilterActivation = ENABLE; + CAN_FilterInit(&CAN_FilterInitStructure); + + /* CAN FIFO0 message pending interrupt enable */ + CAN_ITConfig(CANx, CAN_IT_FMP0, ENABLE); + + /* transmit 1 message */ + TxMessage.StdId = 0; + TxMessage.ExtId = 0x1234; + TxMessage.IDE = CAN_ID_EXT; + TxMessage.RTR = CAN_RTR_DATA; + TxMessage.DLC = 2; + TxMessage.Data[0] = 0xDE; + TxMessage.Data[1] = 0xCA; + CAN_Transmit(CANx, &TxMessage); + + /* initialize the value that will be returned */ + ret = 0xFF; + + /* receive message with interrupt handling */ + i = 0; + while((ret == 0xFF) && (i < 0xFFF)) + { + i++; + } + + if (i == 0xFFF) + { + ret = 0; + } + + /* disable interrupt handling */ + CAN_ITConfig(CANx, CAN_IT_FMP0, DISABLE); + + return (TestStatus)ret; +} + +/** + * @brief Configures the NVIC. + * @param None + * @retval None + */ +void NVIC_Config(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + /* Enable CANx RX0 interrupt IRQ channel */ +#ifdef USE_CAN1 + NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn; +#else /* USE_CAN2 */ + NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn; +#endif /* USE_CAN1 */ + + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/main.h new file mode 100644 index 000000000..b75df6e52 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/main.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file CAN/LoopBack/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define USE_CAN1 +/* #define USE_CAN2 */ + +#ifdef USE_CAN1 + #define CANx CAN1 +#else /* USE_CAN2 */ + #define CANx CAN2 +#endif /* USE_CAN1 */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/readme.txt new file mode 100644 index 000000000..a2be4e768 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/readme.txt @@ -0,0 +1,85 @@ +/** + @page CAN_LoopBack CAN LoopBack example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file CAN/LoopBack/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the CAN LoopBack example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a description of how to set a communication with the CAN +in loopback mode. + +The CAN cell first performs a transmission and a reception of a standard data +frame by polling at 125 Kbps. The received frame is checked and some LEDs light +up to indicate whether the communication was successful. Then, an extended data +frame is transmitted at 500 Kbps. Reception is done in the interrupt handler +when the message becomes pending in the FIFO. Finally, the LEDs indicate if both +transmission and reception have been successful. + +User can select CAN1 or CAN2 cell using the defines in main.h : +@code +#define USE_CAN1 +/* #define USE_CAN2*/ +@endcode + + +@par Directory contents + + - CAN/LoopBack/system_stm32f2xx.c STM32F2xx system clock configuration file + - CAN/LoopBack/stm32f2xx_conf.h Library Configuration file + - CAN/LoopBack/stm32f2xx_it.h Interrupt handlers header file + - CAN/LoopBack/stm32f2xx_it.c Interrupt handlers + - CAN/LoopBack/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/stm32f2xx_conf.h new file mode 100644 index 000000000..92615b9f5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file CAN/LoopBack/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/stm32f2xx_it.c new file mode 100644 index 000000000..a02658f26 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/stm32f2xx_it.c @@ -0,0 +1,240 @@ +/** + ****************************************************************************** + * @file CAN/LoopBack/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CAN_LoopBack + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern __IO uint32_t ret; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +#ifdef USE_CAN1 +/** + * @brief This function handles CAN1 RX0 request. + * @param None + * @retval None + */ +void CAN1_RX0_IRQHandler(void) +{ + CanRxMsg RxMessage; + + RxMessage.StdId = 0x00; + RxMessage.ExtId = 0x00; + RxMessage.IDE = 0; + RxMessage.DLC = 0; + RxMessage.FMI = 0; + RxMessage.Data[0] = 0x00; + RxMessage.Data[1] = 0x00; + + CAN_Receive(CAN1, CAN_FIFO0, &RxMessage); + + if((RxMessage.ExtId == 0x1234) && (RxMessage.IDE == CAN_ID_EXT) + && (RxMessage.DLC == 2) && ((RxMessage.Data[1]|RxMessage.Data[0]<<8) == 0xDECA)) + { + ret = 1; + } + else + { + ret = 0; + } +} +#endif /* USE_CAN1 */ + +#ifdef USE_CAN2 +/** + * @brief This function handles CAN2 RX0 request. + * @param None + * @retval None + */ +void CAN2_RX0_IRQHandler(void) +{ + CanRxMsg RxMessage; + + RxMessage.StdId = 0x00; + RxMessage.ExtId = 0x00; + RxMessage.IDE = 0; + RxMessage.DLC = 0; + RxMessage.FMI = 0; + RxMessage.Data[0] = 0x00; + RxMessage.Data[1] = 0x00; + + CAN_Receive(CAN2, CAN_FIFO0, &RxMessage); + + if((RxMessage.ExtId == 0x1234) && (RxMessage.IDE == CAN_ID_EXT) + && (RxMessage.DLC == 2) && ((RxMessage.Data[1]|RxMessage.Data[0]<<8) == 0xDECA)) + { + ret = 1; + } + else + { + ret = 0; + } +} +#endif /* USE_CAN2 */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/stm32f2xx_it.h new file mode 100644 index 000000000..f1bf968d5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/stm32f2xx_it.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file CAN/LoopBack/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void CAN1_RX0_IRQHandler(void); +void CAN2_RX0_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/LoopBack/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/main.c new file mode 100644 index 000000000..f08f32a90 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/main.c @@ -0,0 +1,308 @@ +/** + ****************************************************************************** + * @file CAN/Networking/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CAN_Networking + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define KEY_PRESSED 0x00 +#define KEY_NOT_PRESSED 0x01 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +CAN_InitTypeDef CAN_InitStructure; +CAN_FilterInitTypeDef CAN_FilterInitStructure; +CanTxMsg TxMessage; +uint8_t KeyNumber = 0x0; + +/* Private function prototypes -----------------------------------------------*/ +void NVIC_Config(void); +void CAN_Config(void); +void Init_RxMes(CanRxMsg *RxMessage); +void Delay(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* NVIC configuration */ + NVIC_Config(); + + /* Configures LED 1..4 */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Configure Push button key */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); + + /* CAN configuration */ + CAN_Config(); + + /* Infinite loop */ + while(1) + { + while(STM_EVAL_PBGetState(BUTTON_KEY) == KEY_PRESSED) + { + if(KeyNumber == 0x4) + { + KeyNumber = 0x00; + } + else + { + LED_Display(++KeyNumber); + TxMessage.Data[0] = KeyNumber; + CAN_Transmit(CANx, &TxMessage); + Delay(); + + while(STM_EVAL_PBGetState(BUTTON_KEY) != KEY_NOT_PRESSED) + { + } + } + } + } +} + +/** + * @brief Configures the CAN. + * @param None + * @retval None + */ +void CAN_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* CAN GPIOs configuration **************************************************/ + + /* Enable GPIO clock */ + RCC_AHB1PeriphClockCmd(CAN_GPIO_CLK, ENABLE); + + /* Connect CAN pins to AF9 */ + GPIO_PinAFConfig(CAN_GPIO_PORT, CAN_RX_SOURCE, CAN_AF_PORT); + GPIO_PinAFConfig(CAN_GPIO_PORT, CAN_TX_SOURCE, CAN_AF_PORT); + + /* Configure CAN RX and TX pins */ + GPIO_InitStructure.GPIO_Pin = CAN_RX_PIN | CAN_TX_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(CAN_GPIO_PORT, &GPIO_InitStructure); + + /* CAN configuration ********************************************************/ + /* Enable CAN clock */ + RCC_APB1PeriphClockCmd(CAN_CLK, ENABLE); + + /* CAN register init */ + CAN_DeInit(CANx); + + /* CAN cell init */ + CAN_InitStructure.CAN_TTCM = DISABLE; + CAN_InitStructure.CAN_ABOM = DISABLE; + CAN_InitStructure.CAN_AWUM = DISABLE; + CAN_InitStructure.CAN_NART = DISABLE; + CAN_InitStructure.CAN_RFLM = DISABLE; + CAN_InitStructure.CAN_TXFP = DISABLE; + CAN_InitStructure.CAN_Mode = CAN_Mode_Normal; + CAN_InitStructure.CAN_SJW = CAN_SJW_1tq; + + /* CAN Baudrate = 1MBps (CAN clocked at 30 MHz) */ + CAN_InitStructure.CAN_BS1 = CAN_BS1_6tq; + CAN_InitStructure.CAN_BS2 = CAN_BS2_8tq; + CAN_InitStructure.CAN_Prescaler = 2; + CAN_Init(CANx, &CAN_InitStructure); + + /* CAN filter init */ +#ifdef USE_CAN1 + CAN_FilterInitStructure.CAN_FilterNumber = 0; +#else /* USE_CAN2 */ + CAN_FilterInitStructure.CAN_FilterNumber = 14; +#endif /* USE_CAN1 */ + CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask; + CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit; + CAN_FilterInitStructure.CAN_FilterIdHigh = 0x0000; + CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000; + CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000; + CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000; + CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0; + CAN_FilterInitStructure.CAN_FilterActivation = ENABLE; + CAN_FilterInit(&CAN_FilterInitStructure); + + /* Transmit Structure preparation */ + TxMessage.StdId = 0x321; + TxMessage.ExtId = 0x01; + TxMessage.RTR = CAN_RTR_DATA; + TxMessage.IDE = CAN_ID_STD; + TxMessage.DLC = 1; + + /* Enable FIFO 0 message pending Interrupt */ + CAN_ITConfig(CANx, CAN_IT_FMP0, ENABLE); +} + +/** + * @brief Configures the NVIC for CAN. + * @param None + * @retval None + */ +void NVIC_Config(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + +#ifdef USE_CAN1 + NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn; +#else /* USE_CAN2 */ + NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn; +#endif /* USE_CAN1 */ + + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +/** + * @brief Initializes the Rx Message. + * @param RxMessage: pointer to the message to initialize + * @retval None + */ +void Init_RxMes(CanRxMsg *RxMessage) +{ + uint8_t i = 0; + + RxMessage->StdId = 0x00; + RxMessage->ExtId = 0x00; + RxMessage->IDE = CAN_ID_STD; + RxMessage->DLC = 0; + RxMessage->FMI = 0; + for (i = 0;i < 8;i++) + { + RxMessage->Data[i] = 0x00; + } +} + +/** + * @brief Turn ON/OFF the dedicated led + * @param Ledstatus: Led number from 0 to 3. + * @retval None + */ +void LED_Display(uint8_t Ledstatus) +{ + /* Turn off all leds */ + STM_EVAL_LEDOff(LED1); + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + + switch(Ledstatus) + { + case(1): + STM_EVAL_LEDOn(LED1); + break; + + case(2): + STM_EVAL_LEDOn(LED2); + break; + + case(3): + STM_EVAL_LEDOn(LED3); + break; + + case(4): + STM_EVAL_LEDOn(LED4); + break; + default: + break; + } +} + +/** + * @brief Delay + * @param None + * @retval None + */ +void Delay(void) +{ + uint16_t nTime = 0x0000; + + for(nTime = 0; nTime <0xFFF; nTime++) + { + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/main.h new file mode 100644 index 000000000..bf81ddb1f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/main.h @@ -0,0 +1,69 @@ +/** + ****************************************************************************** + * @file CAN/Networking/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define USE_CAN1 +/* #define USE_CAN2 */ + +#ifdef USE_CAN1 + #define CANx CAN1 + #define CAN_CLK RCC_APB1Periph_CAN1 + #define CAN_RX_PIN GPIO_Pin_0 + #define CAN_TX_PIN GPIO_Pin_1 + #define CAN_GPIO_PORT GPIOD + #define CAN_GPIO_CLK RCC_AHB1Periph_GPIOD + #define CAN_AF_PORT GPIO_AF_CAN1 + #define CAN_RX_SOURCE GPIO_PinSource0 + #define CAN_TX_SOURCE GPIO_PinSource1 +#else /*USE_CAN2*/ + #define CANx CAN2 + #define CAN_CLK (RCC_APB1Periph_CAN1 | RCC_APB1Periph_CAN2) + #define CAN_RX_PIN GPIO_Pin_5 + #define CAN_TX_PIN GPIO_Pin_13 + #define CAN_GPIO_PORT GPIOB + #define CAN_GPIO_CLK RCC_AHB1Periph_GPIOB + #define CAN_AF_PORT GPIO_AF_CAN2 + #define CAN_RX_SOURCE GPIO_PinSource5 + #define CAN_TX_SOURCE GPIO_PinSource13 +#endif /* USE_CAN1 */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void LED_Display(uint8_t Ledstatus); + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/readme.txt new file mode 100644 index 000000000..323565e09 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/readme.txt @@ -0,0 +1,118 @@ +/** + @page CAN_Networking CAN Networking example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file CAN/Networking/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the CAN Networking example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the CAN peripheral to send and receive +CAN frames in normal mode. The sent frames are used to control Leds by pressing +key push button. + +The CAN serial communication link is a bus to which a number of units may be +connected. This number has no theoretical limit. Practically the total number +of units will be limited by delay times and/or electrical loads on the bus line. + +This program behaves as follows: + - After reset LED1 is ON + - By Pressing on KEY Button : LED2 turns ON and all other Leds are OFF, on the N + eval boards connected to the bus. + - Press on KEY Button again to send CAN Frame to command LEDn+1 ON, all other Leds + are OFF on the N eval boards. + +@note This example is tested with a bus of 3 units. The same program example is + loaded in all units to send and receive frames. +@note Any unit in the CAN bus may play the role of sender (by pressing KEY button) + or receiver. + + The CAN is configured as follow: + - Bit Rate = 1 Mbit/s + - CAN Clock = external clock (HSE) + - ID Filter = All identifiers are allowed + - RTR = Data + - DLC = 1 byte + - Data: Led number that should be turned ON + +User can select CAN1 or CAN2 cell using the defines in main.h : +@code +#define USE_CAN1 +/* #define USE_CAN2*/ +@endcode + + +@par Directory contents + + - CAN/Networking/system_stm32f2xx.c STM32F2xx system clock configuration file + - CAN/Networking/stm32f2xx_conf.h Library Configuration file + - CAN/Networking/stm32f2xx_it.h Interrupt handlers header file + - CAN/Networking/stm32f2xx_it.c Interrupt handlers + - CAN/Networking/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + - Use KEY Push Button connected to PG15 + - Connect a female/female CAN cable between at least 2 EVAL CAN connectors (CN10) + - Depending on the CAN cell used, you have to configure the jumpers as follows: + + @verbatim + +-----------------------------------------------+ + | Jumper | CAN1 used | CAN2 used | + +-----------------------------------------------+ + | JP3 | 2-3 | 1-2 | + | JP10 | 2-3 | 1-2 | + | JP7 | 1-2 | 1-2 | + | JP9 | fitted | fitted | + +-----------------------------------------------+ + + @endverbatim + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/stm32f2xx_conf.h new file mode 100644 index 000000000..03f3d4789 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file CAN/Networking/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/stm32f2xx_it.c new file mode 100644 index 000000000..d36a343ea --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/stm32f2xx_it.c @@ -0,0 +1,213 @@ +/** + ****************************************************************************** + * @file CAN/Networking/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CAN_Networking + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +CanRxMsg RxMessage; +extern uint8_t KeyNumber; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +#ifdef USE_CAN1 +/** + * @brief This function handles CAN1 RX0 request. + * @param None + * @retval None + */ +void CAN1_RX0_IRQHandler(void) +{ + CAN_Receive(CAN1, CAN_FIFO0, &RxMessage); + + if ((RxMessage.StdId == 0x321)&&(RxMessage.IDE == CAN_ID_STD) && (RxMessage.DLC == 1)) + { + LED_Display(RxMessage.Data[0]); + KeyNumber = RxMessage.Data[0]; + } +} +#endif /* USE_CAN1 */ + +#ifdef USE_CAN2 +/** + * @brief This function handles CAN2 RX0 request. + * @param None + * @retval None + */ +void CAN2_RX0_IRQHandler(void) +{ + CAN_Receive(CAN2, CAN_FIFO0, &RxMessage); + + if ((RxMessage.StdId == 0x321)&&(RxMessage.IDE == CAN_ID_STD) && (RxMessage.DLC == 1)) + { + LED_Display(RxMessage.Data[0]); + KeyNumber = RxMessage.Data[0]; + } +} +#endif /* USE_CAN2 */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/stm32f2xx_it.h new file mode 100644 index 000000000..f49f842bc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/stm32f2xx_it.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file CAN/Networking/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void CAN1_RX0_IRQHandler(void); +void CAN2_RX0_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CAN/Networking/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/main.c new file mode 100644 index 000000000..4157b3214 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/main.c @@ -0,0 +1,127 @@ +/** + ****************************************************************************** + * @file CRC/CRC_Example/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CRC_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define BUFFER_SIZE 114 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static const uint32_t DataBuffer[BUFFER_SIZE] = + { + 0x00001021, 0x20423063, 0x408450a5, 0x60c670e7, 0x9129a14a, 0xb16bc18c, + 0xd1ade1ce, 0xf1ef1231, 0x32732252, 0x52b54294, 0x72f762d6, 0x93398318, + 0xa35ad3bd, 0xc39cf3ff, 0xe3de2462, 0x34430420, 0x64e674c7, 0x44a45485, + 0xa56ab54b, 0x85289509, 0xf5cfc5ac, 0xd58d3653, 0x26721611, 0x063076d7, + 0x569546b4, 0xb75ba77a, 0x97198738, 0xf7dfe7fe, 0xc7bc48c4, 0x58e56886, + 0x78a70840, 0x18612802, 0xc9ccd9ed, 0xe98ef9af, 0x89489969, 0xa90ab92b, + 0x4ad47ab7, 0x6a961a71, 0x0a503a33, 0x2a12dbfd, 0xfbbfeb9e, 0x9b798b58, + 0xbb3bab1a, 0x6ca67c87, 0x5cc52c22, 0x3c030c60, 0x1c41edae, 0xfd8fcdec, + 0xad2abd0b, 0x8d689d49, 0x7e976eb6, 0x5ed54ef4, 0x2e321e51, 0x0e70ff9f, + 0xefbedfdd, 0xcffcbf1b, 0x9f598f78, 0x918881a9, 0xb1caa1eb, 0xd10cc12d, + 0xe16f1080, 0x00a130c2, 0x20e35004, 0x40257046, 0x83b99398, 0xa3fbb3da, + 0xc33dd31c, 0xe37ff35e, 0x129022f3, 0x32d24235, 0x52146277, 0x7256b5ea, + 0x95a88589, 0xf56ee54f, 0xd52cc50d, 0x34e224c3, 0x04817466, 0x64475424, + 0x4405a7db, 0xb7fa8799, 0xe75ff77e, 0xc71dd73c, 0x26d336f2, 0x069116b0, + 0x76764615, 0x5634d94c, 0xc96df90e, 0xe92f99c8, 0xb98aa9ab, 0x58444865, + 0x78066827, 0x18c008e1, 0x28a3cb7d, 0xdb5ceb3f, 0xfb1e8bf9, 0x9bd8abbb, + 0x4a755a54, 0x6a377a16, 0x0af11ad0, 0x2ab33a92, 0xed0fdd6c, 0xcd4dbdaa, + 0xad8b9de8, 0x8dc97c26, 0x5c644c45, 0x3ca22c83, 0x1ce00cc1, 0xef1fff3e, + 0xdf7caf9b, 0xbfba8fd9, 0x9ff86e17, 0x7e364e55, 0x2e933eb2, 0x0ed11ef0 + }; + +__IO uint32_t CRCValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Enable CRC clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_CRC, ENABLE); + + /* Compute the CRC of "DataBuffer" */ + CRCValue = CRC_CalcBlockCRC((uint32_t *)DataBuffer, BUFFER_SIZE); + + while (1) + { + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/readme.txt new file mode 100644 index 000000000..0b440b1b7 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/readme.txt @@ -0,0 +1,71 @@ +/** + @page CRC_Example CRC Calculation Example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file CRC/CRC_Example/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the CRC example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to use CRC (cyclic redundancy check) calculation unit to +get a CRC code of a given buffer of data word(32-bit), based on a fixed generator +polynomial(0x4C11DB7). + + +@par Directory contents + + - CRC/CRC_Example/stm32f2xx_conf.h Library Configuration file + - CRC/CRC_Example/stm32f2xx_it.c Interrupt handlers + - CRC/CRC_Example/stm32f2xx_it.h Interrupt handlers header file + - CRC/CRC_Example/main.c Main program + - CRC/CRC_Example/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/stm32f2xx_conf.h new file mode 100644 index 000000000..65bdc335d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file CRC/CRC_Example/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/stm32f2xx_it.c new file mode 100644 index 000000000..363d0a45a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file CRC/CRC_Example/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CRC_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/stm32f2xx_it.h new file mode 100644 index 000000000..eebb605ae --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file CRC/CRC_Example/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRC/CRC_Example/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/Expected_Results.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/Expected_Results.txt new file mode 100644 index 000000000..999c836ae --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/Expected_Results.txt @@ -0,0 +1,25 @@ + ====================================== + === CRYP AES-128 Using DMA Example === + ====================================== + --------------------------------------- + Plain Data : + --------------------------------------- +[0x20212223][0x24252627][0x28292A2B][0x2C2D2E2F] Block 0 +[0xFFEEDDCC][0xBBAA9988][0x77665544][0x33221100] Block 1 + + --------------------------------------- + Key : + --------------------------------------- +[0x40414243][0x44454647][0x48494A4B][0x4C4D4E4F] + + --------------------------------------- + AES-128 Encrypted Data: + --------------------------------------- +[0x8CAA7F58][0x9AA0CEB6][0x350A45E7][0x A6E435B] Block 0 +[0xFE9BD6DE][0x4F5597F8][0x11FDF0A8][0x D55FAFE] Block 1 + + --------------------------------------- + AES-128 Decrypted Data: + --------------------------------------- +[0x20212223][0x24252627][0x28292A2B][0x2C2D2E2F] Block 0 +[0xFFEEDDCC][0xBBAA9988][0x77665544][0x33221100] Block 1 diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/main.c new file mode 100644 index 000000000..c85d69cc3 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/main.c @@ -0,0 +1,499 @@ +/** + ****************************************************************************** + * @file CRYP/AES_ECBmode_DMA/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stdio.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup AES_ECBmode_DMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define BLOCKS_NBR 2 /* User can change this value to enlarge or reduce + the number of blocks to encrypt */ +#define DATA_SIZE ((BLOCKS_NBR *128)/32) +#define CRYP_DIN_REG_ADDR ((uint32_t)0x50060008) /* Crypto DIN register address */ +#define CRYP_DOUT_REG_ADDR ((uint32_t)0x5006000C) /* Crypto DOUT register address */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +__IO uint32_t AES128key[4]={0x40414243,0x44454647,0x48494a4b,0x4c4d4e4f}; + +__IO uint32_t PlainData[DATA_SIZE]={ + 0x20212223,0x24252627,0x28292a2b,0x2c2d2e2f, /* Block 0 */ + 0xFFEEDDCC,0xBBAA9988,0x77665544,0x33221100}; /* Block 1 */ +__IO uint32_t EncryptedData[DATA_SIZE]; +__IO uint32_t DecryptedData[DATA_SIZE]; + +/* Private function prototypes -----------------------------------------------*/ +void AES128_Encrypt_DMA(void); +void AES128_Decrypt_DMA(void); + +void Display_PlainData(void); +void Display_EncryptedData(void); +void Display_DecryptedData(void); +void USART_Config(void); + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ +/*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + /* USART Configuration */ + USART_Config(); + + /* Display Plain Data*/ + Display_PlainData(); + +/*===================================================== + Encryption +======================================================*/ + /* Encryption */ + AES128_Encrypt_DMA(); + + /* Display encrypted Data */ + Display_EncryptedData(); + +/*===================================================== + Decryption +======================================================*/ + /* Decryption */ + AES128_Decrypt_DMA(); + + /* Display decrypted data */ + Display_DecryptedData(); + + while(1); +} + +/** + * @brief Encrypt Data using AES + * @note DATA transfer is done by the DMA + * @note DMA2 stream6 channel2 is used to transfer data from memory (the + * PlainData Table) to CRYP Peripheral (the INPUT data register). + * @note DMA2 stream5 channel2 is used to transfer data from CRYP Peripheral + * (the OUTPUT data register to memory (the EncryptedData Table). + * @param None + * @retval None + */ +void AES128_Encrypt_DMA(void) +{ + CRYP_InitTypeDef CRYP_InitStructure; + CRYP_KeyInitTypeDef CRYP_KeyInitStructure; + DMA_InitTypeDef DMA_InitStructure; + + /* Enable CRYP clock */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); + + /* Enable DMA2 clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + /* CRYP configuration********************************************************/ + /* Crypto key structure initialisation */ + CRYP_KeyStructInit(&CRYP_KeyInitStructure); + + /* Crypto Init for Encryption process */ + CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; + CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; + CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; + CRYP_Init(&CRYP_InitStructure); + + /* Key Initialisation */ + CRYP_KeyInitStructure.CRYP_Key2Left = AES128key[0]; + CRYP_KeyInitStructure.CRYP_Key2Right= AES128key[1]; + CRYP_KeyInitStructure.CRYP_Key3Left = AES128key[2]; + CRYP_KeyInitStructure.CRYP_Key3Right= AES128key[3]; + CRYP_KeyInit(&CRYP_KeyInitStructure); + + /* Enable DMA Requests ******************************************************/ + CRYP_DMACmd(CRYP_DMAReq_DataIN, ENABLE); + CRYP_DMACmd(CRYP_DMAReq_DataOUT, ENABLE); + + /* DMA Configuration*********************************************************/ + DMA_DeInit(DMA2_Stream5); + DMA_DeInit(DMA2_Stream6); + /* set common DMA parameters for Stream 5 and 6*/ + DMA_InitStructure.DMA_Channel = DMA_Channel_2; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_BufferSize = DATA_SIZE; + + /* Set the parameters to be configured for stream 6*/ + DMA_InitStructure.DMA_PeripheralBaseAddr = CRYP_DIN_REG_ADDR; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)PlainData; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + + /* Configure the DMA Stream 6 */ + DMA_Init(DMA2_Stream6, &DMA_InitStructure); + + /* Set the parameters to be configured for stream 5*/ + DMA_InitStructure.DMA_PeripheralBaseAddr = CRYP_DOUT_REG_ADDR; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)EncryptedData; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + + /* Configure the DMA Stream 5 */ + DMA_Init(DMA2_Stream5, &DMA_InitStructure); + + /* Enable DMA streams*******************************************************/ + DMA_Cmd(DMA2_Stream6, ENABLE); + DMA_Cmd(DMA2_Stream5, ENABLE); + + /* Enable Crypto processor *************************************************/ + CRYP_Cmd(ENABLE); + + /* wait until the last transfer from OUT FIFO : + all encrypted Data are transferred from crypt processor */ + while (DMA_GetFlagStatus(DMA2_Stream5, DMA_FLAG_TCIF5) == RESET); + + /* Disable Crypto and DMA **************************************************/ + CRYP_Cmd(DISABLE); + CRYP_DMACmd(CRYP_DMAReq_DataIN, DISABLE); + CRYP_DMACmd(CRYP_DMAReq_DataOUT, DISABLE); + DMA_Cmd(DMA2_Stream5, DISABLE); + DMA_Cmd(DMA2_Stream6, DISABLE); +} + +/** + * @brief Decrypt Data using AES + * @note DATA transfer is done by DMA + * @note DMA2 stream6 channel2 is used to transfer data from memory (the + * EncryptedData Table) to CRYP Peripheral (the INPUT data register). + * @note DMA2 stream5 channel2 is used to transfer data from CRYP Peripheral + * (the OUTPUT data register to memory (the DecryptedData Table). + * @param None + * @retval None + */ +void AES128_Decrypt_DMA(void) +{ + CRYP_InitTypeDef CRYP_InitStructure; + CRYP_KeyInitTypeDef CRYP_KeyInitStructure; + DMA_InitTypeDef DMA_InitStructure; + + /* Enable CRYP clock */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); + + /* Enable DMA2 clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + /* CRYP configuration*******************************************************/ + /* Crypto Init for Key preparation for Decryption process */ + CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key; + CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; + CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; + CRYP_Init(&CRYP_InitStructure); + + /* Key Initialisation */ + CRYP_KeyInitStructure.CRYP_Key2Left = AES128key[0]; + CRYP_KeyInitStructure.CRYP_Key2Right= AES128key[1]; + CRYP_KeyInitStructure.CRYP_Key3Left = AES128key[2]; + CRYP_KeyInitStructure.CRYP_Key3Right= AES128key[3]; + CRYP_KeyInit(&CRYP_KeyInitStructure); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + /* wait until the Busy flag is reset */ + while (CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET); + + /* Disable Crypto processor */ + CRYP_Cmd(DISABLE); + + /* Crypto Init for Decryption process */ + CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; + CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; + CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; + + CRYP_Init(&CRYP_InitStructure); + + + /* Enable DMA Requests ******************************************************/ + CRYP_DMACmd(CRYP_DMAReq_DataIN, ENABLE); + CRYP_DMACmd(CRYP_DMAReq_DataOUT, ENABLE); + + /* DMA Configuration*********************************************************/ + DMA_DeInit(DMA2_Stream5); + DMA_DeInit(DMA2_Stream6); + /* set common DMA parameters for Stream 5 and 6*/ + DMA_InitStructure.DMA_Channel = DMA_Channel_2; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_BufferSize = DATA_SIZE; + + /* Set the parameters to be configured for stream 6*/ + DMA_InitStructure.DMA_PeripheralBaseAddr = CRYP_DIN_REG_ADDR; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)EncryptedData; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + + /* Configure the DMA Stream 6 */ + DMA_Init(DMA2_Stream6, &DMA_InitStructure); + + /* Set the parameters to be configured for stream 5*/ + DMA_InitStructure.DMA_PeripheralBaseAddr = CRYP_DOUT_REG_ADDR; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)DecryptedData; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + + /* Configure the DMA Stream 5 */ + DMA_Init(DMA2_Stream5, &DMA_InitStructure); + + /* Enable DMA streams*******************************************************/ + DMA_Cmd(DMA2_Stream6, ENABLE); + DMA_Cmd(DMA2_Stream5, ENABLE); + + /* Enable Crypto processor *************************************************/ + CRYP_Cmd(ENABLE); + + /* wait until the last transfer from OUT FIFO : + all encrypted Data are transferred from crypt processor */ + while (DMA_GetFlagStatus(DMA2_Stream5, DMA_FLAG_TCIF5) == RESET); + + + /* Disable Crypto and DMA **************************************************/ + CRYP_Cmd(DISABLE); + CRYP_DMACmd(CRYP_DMAReq_DataIN, DISABLE); + CRYP_DMACmd(CRYP_DMAReq_DataOUT, DISABLE); + DMA_Cmd(DMA2_Stream5, DISABLE); + DMA_Cmd(DMA2_Stream6, DISABLE); + + DMA_ClearFlag(DMA2_Stream6, DMA_FLAG_TCIF5); +} + +/** + * @brief Display Plain Data + * @param None + * @retval None + */ +void Display_PlainData(void) +{ + uint32_t i=0; + uint8_t count=0; + + printf(" \n\r======================================\n\r"); + printf(" === CRYP AES-128 Using DMA Example ===\n\r"); + printf(" ======================================\n\r"); + printf(" ---------------------------------------\n\r"); + printf(" Plain Data :\n\r"); + printf(" ---------------------------------------\n\r"); + + for(i = 0; i < DATA_SIZE; i++) + { + printf("[0x%8X]", PlainData[i]); + count++; + + if(count == 4) + { + count = 0; + printf(" Block %d \n\r", i/4); + } + } + + printf(" ---------------------------------------\n\r"); + printf(" Key :\n\r"); + printf(" ---------------------------------------\n\r"); + + for(i = 0; i < 4; i++) + { + printf("[0x%8X]", AES128key[i]); + count++; + } + +} + +/** + * @brief Display Encrypted Data + * @param None + * @retval None + */ +void Display_EncryptedData(void) +{ + uint32_t i=0; + uint8_t count=0; + + printf("\n\r ---------------------------------------\n\r"); + printf(" AES-128 Encrypted Data:\n\r"); + printf(" ---------------------------------------\n\r"); + + for(i = 0; i < DATA_SIZE; i++) + { + printf("[0x%8X]", EncryptedData[i]); + count++; + + if(count == 4) + { + count = 0; + printf(" Block %d \n\r", i/4); + } + } +} + +/** + * @brief Display Decrypted Data + * @param None + * @retval None + */ +void Display_DecryptedData(void) +{ + uint32_t i=0; + uint8_t count=0; + + printf("\n\r ---------------------------------------\n\r"); + printf(" AES-128 Decrypted Data:\n\r"); + printf(" ---------------------------------------\n\r"); + + for(i = 0; i < DATA_SIZE; i++) + { + printf("[0x%8X]", DecryptedData[i]); + count++; + + if(count == 4) + { + count = 0; + printf(" Block %d \n\r", i/4); + } + } +} + +/** + * @brief USART configuration + * @param None + * @retval None + */ +void USART_Config(void) +{ + /* USARTx configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitTypeDef USART_InitStructure; + + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit(COM1, &USART_InitStructure); +} + + +/** + * @brief Retargets the C library printf function to the USART. + * @param None + * @retval None + */ +PUTCHAR_PROTOTYPE +{ + /* Place your implementation of fputc here */ + /* e.g. write a character to the USART */ + USART_SendData(EVAL_COM1, (uint8_t) ch); + + /* Loop until the end of transmission */ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) + {} + + return ch; +} + + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/readme.txt new file mode 100644 index 000000000..b3ed8abe0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/readme.txt @@ -0,0 +1,102 @@ +/** + @page AES_ECBmode_DMA Encrypt and Decrypt data using AES-128 Algo in ECB mode, with DMA + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file CRYP/AES_ECBmode_DMA/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the CRYP AES-128 Algo in ECB mode with DMA Example + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the CRYPTO peripheral to +encrypt and decrypt data using AES-128 Algorithm. + +For this example, DMA is used to transfer data from memory to the CRYPTO processor +IN FIFO and also to transfer data from CRYPTO processor OUT FIFO to memory. + +The data to be encrypted is a 640 bit data, which correspond to 5 AES Blocks. + +This example behaves as below: +- AES Encryption (PlainData --> EncryptedData) +- AES Key prepation for decryption (Encryption Key --> Decryption Key) +- AES Decryption (EncryptedData --> DecryptedData) + +The Plain data, encrypted data and decrypted data can be displayed on a PC +HyperTerminal using the USART (CN16). + +The USARTx is configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + + +@par Directory contents + + - CRYP/AES_ECBmode_DMA/system_stm32f2xx.c STM32F2xx system clock configuration file + - CRYP/AES_ECBmode_DMA/stm32f2xx_conf.h Library Configuration file + - CRYP/AES_ECBmode_DMA/stm32f2xx_it.h Interrupt handlers header file + - CRYP/AES_ECBmode_DMA/stm32f2xx_it.c Interrupt handlers + - CRYP/AES_ECBmode_DMA/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs only on STM32F21x Devices (Cryptographic acceleration not + embedded in STM32F20x Devices). + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/stm32f2xx_conf.h new file mode 100644 index 000000000..df86f8ef9 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file CRYP/AES_ECBmode_DMA/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/stm32f2xx_it.c new file mode 100644 index 000000000..245b0ca5a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file CRYP/AES_ECBmode_DMA/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup AES_ECBmode_DMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/stm32f2xx_it.h new file mode 100644 index 000000000..8d79d89dd --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file CRYP/AES_ECBmode_DMA/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_ECBmode_DMA/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/Expected_Results.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/Expected_Results.txt new file mode 100644 index 000000000..6951a4e66 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/Expected_Results.txt @@ -0,0 +1,170 @@ + ============================================================= + ================= Crypt Using HW Crypto ==================== + ============================================================ + --------------------------------------- + Plain Data : + --------------------------------------- +[0x6B][0xC1][0xBE][0xE2][0x2E][0x40][0x9F][0x96][0xE9][0x3D][0x7E][0x11][0x73][0x93][0x17][0x2A] Block 0 +[0xAE][0x2D][0x8A][0x57][0x1E][0x03][0xAC][0x9C][0x9E][0xB7][0x6F][0xAC][0x45][0xAF][0x8E][0x51] Block 1 +[0x30][0xC8][0x1C][0x46][0xA3][0x5C][0xE4][0x11][0xE5][0xFB][0xC1][0x19][0x1A][0x0A][0x52][0xEF] Block 2 +[0xF6][0x9F][0x24][0x45][0xDF][0x4F][0x9B][0x17][0xAD][0x2B][0x41][0x7B][0xE6][0x6C][0x37][0x10] Block 3 + + Press any key to continue... + + ======================================= + Encrypted Data with AES 128 Mode ECB + --------------------------------------- +[0x3A][0xD7][0x7B][0xB4][0x0D][0x7A][0x36][0x60][0xA8][0x9E][0xCA][0xF3][0x24][0x66][0xEF][0x97] Block 0 +[0xF5][0xD3][0xD5][0x85][0x03][0xB9][0x69][0x9D][0xE7][0x85][0x89][0x5A][0x96][0xFD][0xBA][0xAF] Block 1 +[0x43][0xB1][0xCD][0x7F][0x59][0x8E][0xCE][0x23][0x88][0x1B][0x00][0xE3][0xED][0x03][0x06][0x88] Block 2 +[0x7B][0x0C][0x78][0x5E][0x27][0xE8][0xAD][0x3F][0x82][0x23][0x20][0x71][0x04][0x72][0x5D][0xD4] Block 3 + + ======================================= + Encrypted Data with AES 192 Mode ECB + --------------------------------------- +[0xBD][0x33][0x4F][0x1D][0x6E][0x45][0xF2][0x5F][0xF7][0x12][0xA2][0x14][0x57][0x1F][0xA5][0xCC] Block 0 +[0x97][0x41][0x04][0x84][0x6D][0x0A][0xD3][0xAD][0x77][0x34][0xEC][0xB3][0xEC][0xEE][0x4E][0xEF] Block 1 +[0xEF][0x7A][0xFD][0x22][0x70][0xE2][0xE6][0x0A][0xDC][0xE0][0xBA][0x2F][0xAC][0xE6][0x44][0x4E] Block 2 +[0x9A][0x4B][0x41][0xBA][0x73][0x8D][0x6C][0x72][0xFB][0x16][0x69][0x16][0x03][0xC1][0x8E][0x0E] Block 3 + + ======================================= + Encrypted Data with AES 256 Mode ECB + --------------------------------------- +[0xF3][0xEE][0xD1][0xBD][0xB5][0xD2][0xA0][0x3C][0x06][0x4B][0x5A][0x7E][0x3D][0xB1][0x81][0xF8] Block 0 +[0x59][0x1C][0xCB][0x10][0xD4][0x10][0xED][0x26][0xDC][0x5B][0xA7][0x4A][0x31][0x36][0x28][0x70] Block 1 +[0xB6][0xED][0x21][0xB9][0x9C][0xA6][0xF4][0xF9][0xF1][0x53][0xE7][0xB1][0xBE][0xAF][0xED][0x1D] Block 2 +[0x23][0x30][0x4B][0x7A][0x39][0xF9][0xF3][0xFF][0x06][0x7D][0x8D][0x8F][0x9E][0x24][0xEC][0xC7] Block 3 + + Press any key to continue... + + ======================================= + Decrypted Data with AES 128 Mode ECB + --------------------------------------- +[0x6B][0xC0][0xBC][0xE1][0x2A][0x45][0x99][0x91][0xE1][0x34][0x74][0x1A][0x7F][0x9E][0x19][0x25] Block 0 +[0xD8][0x64][0x21][0xFB][0x9F][0x1A][0x1E][0xDA][0x50][0x5E][0xE1][0x37][0x57][0x46][0x97][0x2C] Block 1 +[0x60][0x4E][0xD7][0xDD][0xF3][0x2E][0xFD][0xFF][0x70][0x20][0xD0][0x23][0x8B][0x7C][0x2A][0x5D] Block 2 +[0x85][0x21][0xF2][0xFD][0x3C][0x8E][0xEF][0x2C][0xDC][0x3D][0xA7][0xE5][0xC4][0x4E][0xA2][0x06] Block 3 + + ======================================= + Decrypted Data with AES 192 Mode ECB + --------------------------------------- +[0x4F][0x29][0xDF][0x6B][0x08][0x18][0x89][0xD1][0xD5][0x32][0x39][0x5C][0xF9][0x68][0x6D][0x3C] Block 0 +[0xDA][0x32][0x3A][0x59][0x4B][0x66][0x84][0x2B][0x0C][0x2C][0x7D][0x54][0x26][0xBA][0xDB][0x43] Block 1 +[0x63][0xCC][0x39][0x59][0x12][0x82][0xF5][0x61][0xBB][0xC5][0xEC][0x77][0xD8][0x39][0x56][0xAE] Block 2 +[0xD5][0x70][0xFD][0x6D][0x5B][0x9E][0x8E][0x40][0xAE][0x2D][0xBB][0xF2][0x14][0xC3][0x80][0x7E] Block 3 + + ======================================= + Decrypted Data with AES 256 Mode ECB + --------------------------------------- +[0xBB][0xC4][0x2D][0x8F][0x95][0x09][0xDB][0x39][0x1F][0xD8][0xB6][0x44][0x81][0xE6][0x1E][0xED] Block 0 +[0x6D][0x7F][0xD8][0x8D][0x64][0x96][0x07][0x14][0xB8][0x12][0xDD][0xB8][0x16][0x75][0xF2][0x20] Block 1 +[0x6E][0xF9][0xB4][0x81][0x8E][0x70][0x61][0x4D][0x76][0x0C][0x03][0xE6][0xE1][0xB7][0xE1][0xED] Block 2 +[0x81][0x4B][0xC2][0x11][0xD7][0x9C][0x47][0xDF][0xE3][0xDC][0x76][0x15][0xBD][0x2D][0xEB][0x86] Block 3 + + Press any key to continue... + + ======================================= + Encrypted Data with AES 128 Mode CBC + --------------------------------------- +[0x76][0x49][0xAB][0xAC][0x81][0x19][0xB2][0x46][0xCE][0xE9][0x8E][0x9B][0x12][0xE9][0x19][0x7D] Block 0 +[0x50][0x86][0xCB][0x9B][0x50][0x72][0x19][0xEE][0x95][0xDB][0x11][0x3A][0x91][0x76][0x78][0xB2] Block 1 +[0x73][0xBE][0xD6][0xB8][0xE3][0xC1][0x74][0x3B][0x71][0x16][0xE6][0x9E][0x22][0x22][0x95][0x16] Block 2 +[0x3F][0xF1][0xCA][0xA1][0x68][0x1F][0xAC][0x09][0x12][0x0E][0xCA][0x30][0x75][0x86][0xE1][0xA7] Block 3 + + ======================================= + Encrypted Data with AES 192 Mode CBC + --------------------------------------- +[0x4F][0x02][0x1D][0xB2][0x43][0xBC][0x63][0x3D][0x71][0x78][0x18][0x3A][0x9F][0xA0][0x71][0xE8] Block 0 +[0xB4][0xD9][0xAD][0xA9][0xAD][0x7D][0xED][0xF4][0xE5][0xE7][0x38][0x76][0x3F][0x69][0x14][0x5A] Block 1 +[0x57][0x1B][0x24][0x20][0x12][0xFB][0x7A][0xE0][0x7F][0xA9][0xBA][0xAC][0x3D][0xF1][0x02][0xE0] Block 2 +[0x08][0xB0][0xE2][0x79][0x88][0x59][0x88][0x81][0xD9][0x20][0xA9][0xE6][0x4F][0x56][0x15][0xCD] Block 3 + + ======================================= + Encrypted Data with AES 256 Mode CBC + --------------------------------------- +[0xF5][0x8C][0x4C][0x04][0xD6][0xE5][0xF1][0xBA][0x77][0x9E][0xAB][0xFB][0x5F][0x7B][0xFB][0xD6] Block 0 +[0x9C][0xFC][0x4E][0x96][0x7E][0xDB][0x80][0x8D][0x67][0x9F][0x77][0x7B][0xC6][0x70][0x2C][0x7D] Block 1 +[0x39][0xF2][0x33][0x69][0xA9][0xD9][0xBA][0xCF][0xA5][0x30][0xE2][0x63][0x04][0x23][0x14][0x61] Block 2 +[0xB2][0xEB][0x05][0xE2][0xC3][0x9B][0xE9][0xFC][0xDA][0x6C][0x19][0x07][0x8C][0x6A][0x9D][0x1B] Block 3 + + Press any key to continue... + + ======================================= + Decrypted Data with AES 128 Mode CBC + --------------------------------------- +[0x6B][0xC1][0xBE][0xE2][0x2E][0x40][0x9F][0x96][0xE9][0x3D][0x7E][0x11][0x73][0x93][0x17][0x2A] Block 0 +[0xAE][0x2D][0x8A][0x57][0x1E][0x03][0xAC][0x9C][0x9E][0xB7][0x6F][0xAC][0x45][0xAF][0x8E][0x51] Block 1 +[0x30][0xC8][0x1C][0x46][0xA3][0x5C][0xE4][0x11][0xE5][0xFB][0xC1][0x19][0x1A][0x0A][0x52][0xEF] Block 2 +[0xF6][0x9F][0x24][0x45][0xDF][0x4F][0x9B][0x17][0xAD][0x2B][0x41][0x7B][0xE6][0x6C][0x37][0x10] Block 3 + + ======================================= + Decrypted Data with AES 192 Mode CBC + --------------------------------------- +[0x4F][0x28][0xDD][0x68][0x0C][0x1D][0x8F][0xD6][0xDD][0x3B][0x33][0x57][0xF5][0x65][0x63][0x33] Block 0 +[0xAC][0x7B][0x91][0xF5][0xCA][0x7F][0x36][0x6D][0xC2][0xC5][0xF3][0xCF][0x34][0x53][0xC2][0x3E] Block 1 +[0x33][0x4A][0xF2][0xC2][0x42][0xF0][0xEC][0x8F][0x2E][0x1E][0xFD][0x4D][0x49][0x4F][0x2E][0x1C] Block 2 +[0xA6][0xCE][0x2B][0xD5][0xB8][0x5F][0xFA][0x7B][0xDF][0x3B][0x5D][0x6C][0x36][0xE1][0x15][0x68] Block 3 + + ======================================= + Decrypted Data with AES 256 Mode CBC + --------------------------------------- +[0xBB][0xC5][0x2F][0x8C][0x91][0x0C][0xDD][0x3E][0x17][0xD1][0xBC][0x4F][0x8D][0xEB][0x10][0xE2] Block 0 +[0x1B][0x36][0x73][0x21][0xE5][0x8F][0xB5][0x52][0x76][0xFB][0x53][0x23][0x04][0x9C][0xEB][0x5D] Block 1 +[0x3E][0x7F][0x7F][0x1A][0xDE][0x02][0x78][0xA3][0xE3][0xD7][0x12][0xDC][0x70][0xC1][0x99][0x5F] Block 2 +[0xF2][0xF5][0x14][0xA9][0x34][0x5D][0x33][0xE4][0x92][0xCA][0x90][0x8B][0x9F][0x0F][0x7E][0x90] Block 3 + + Press any key to continue... + + ======================================= + Encrypted Data with AES 128 Mode CTR + --------------------------------------- +[0x3B][0x3F][0xD9][0x2E][0xB7][0x2D][0xAD][0x20][0x33][0x34][0x49][0xF8][0xE8][0x3C][0xFB][0x4A] Block 0 +[0x01][0x0C][0x04][0x19][0x99][0xE0][0x3F][0x36][0x44][0x86][0x24][0x48][0x3E][0x58][0x2D][0x0E] Block 1 +[0xA6][0x22][0x93][0xCF][0xA6][0xDF][0x74][0x53][0x5C][0x35][0x41][0x81][0x16][0x87][0x74][0xDF] Block 2 +[0x2D][0x55][0xA5][0x47][0x06][0x27][0x3C][0x50][0xD7][0xB4][0xF8][0xA8][0xCD][0xDC][0x6E][0xD7] Block 3 + + ======================================= + Encrypted Data with AES 192 Mode CTR + --------------------------------------- +[0xCD][0xC8][0x0D][0x6F][0xDD][0xF1][0x8C][0xAB][0x34][0xC2][0x59][0x09][0xC9][0x9A][0x41][0x74] Block 0 +[0x37][0xD8][0xA6][0x39][0x17][0x1F][0xDC][0xCA][0x63][0xEB][0xD1][0x7C][0xE2][0xD7][0x32][0x1A] Block 1 +[0x79][0xA0][0xC9][0x6B][0x53][0xC7][0xEE][0xEC][0xD9][0xED][0x71][0x57][0xC4][0x44][0xFC][0x7A] Block 2 +[0x84][0x5C][0x37][0xB2][0xF5][0x11][0x69][0x7B][0x0E][0x89][0xD5][0xED][0x60][0xC4][0xD4][0x9E] Block 3 + + ======================================= + Encrypted Data with AES 256 Mode CTR + --------------------------------------- +[0xDC][0x7E][0x84][0xBF][0xDA][0x79][0x16][0x4B][0x7E][0xCD][0x84][0x86][0x98][0x5D][0x38][0x60] Block 0 +[0xD5][0x77][0x78][0x8B][0x8D][0x8A][0x85][0x74][0x55][0x13][0xA5][0xD5][0x0F][0x82][0x1F][0x30] Block 1 +[0xFF][0xE9][0x6D][0x5C][0xF5][0x4B][0x23][0x8D][0xCC][0x8D][0x67][0x83][0xA8][0x7F][0x3B][0xEA] Block 2 +[0xE9][0xAF][0x54][0x63][0x44][0xCB][0x9C][0xA4][0xD1][0xE5][0x53][0xFF][0xC0][0x6B][0xC7][0x3E] Block 3 + + Press any key to continue... + + ======================================= + Decrypted Data with AES 128 Mode CTR + --------------------------------------- +[0x26][0xB7][0xCC][0x60][0x18][0x74][0x80][0xF0][0x14][0xE0][0xB9][0x72][0x89][0x46][0xF5][0x1D] Block 0 +[0xFF][0xA7][0x45][0xD5][0xD7][0x91][0x8A][0x44][0x4F][0xEA][0x5A][0xDE][0xEA][0x81][0xDB][0xED] Block 1 +[0xE5][0x54][0x59][0x31][0xE6][0x42][0xE4][0x79][0xC8][0xD8][0x66][0x06][0x2E][0xAF][0xB3][0x26] Block 2 +[0xE4][0x3B][0x4B][0xA3][0xB1][0x77][0x0B][0x4E][0x68][0x91][0x73][0xE3][0x5E][0x36][0xB8][0x60] Block 3 + + ======================================= + Decrypted Data with AES 192 Mode CTR + --------------------------------------- +[0xD0][0x40][0x18][0x21][0x72][0xA8][0xA1][0x7B][0x13][0x16][0xA9][0x83][0xA8][0xE0][0x4F][0x23] Block 0 +[0xC9][0x73][0xE7][0xF5][0x59][0x6E][0x69][0xB8][0x68][0x87][0xAF][0xEA][0x36][0x0E][0xC4][0xF9] Block 1 +[0x3A][0xD6][0x03][0x95][0x13][0x5A][0x7E][0xC6][0x4D][0x00][0x56][0xD0][0xFC][0x6C][0x3B][0x83] Block 2 +[0x4D][0x32][0xD9][0x56][0x42][0x41][0x5E][0x65][0xB1][0xAC][0x5E][0xA6][0xF3][0x2E][0x02][0x29] Block 3 + + ======================================= + Decrypted Data with AES 256 Mode CTR + --------------------------------------- +[0xC1][0xF6][0x91][0xF1][0x75][0x20][0x3B][0x9B][0x59][0x19][0x74][0x0C][0xF9][0x27][0x36][0x37] Block 0 +[0x2B][0xDC][0x39][0x47][0xC3][0xFB][0x30][0x06][0x5E][0x7F][0xDB][0x43][0xDB][0x5B][0xE9][0xD3] Block 1 +[0xBC][0x9F][0xA7][0xA2][0xB5][0xD6][0xB3][0xA7][0x58][0x60][0x40][0x04][0x90][0x57][0xFC][0x13] Block 2 +[0x20][0xC1][0xBA][0x87][0xF3][0x9B][0xAB][0xBA][0x6E][0xC0][0xD8][0xB4][0x53][0x81][0x11][0x89] Block 3 + + Press any key to continue... + + Example restarted... diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/main.c new file mode 100644 index 000000000..4604d49f8 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/main.c @@ -0,0 +1,543 @@ +/** + ****************************************************************************** + * @file CRYP/AES_modes/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stdio.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup AES_modes + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AES_TEXT_SIZE 64 + +#define ECB 1 +#define CBC 2 +#define CTR 3 + + uint8_t AES128key[16] = {0x2b,0x7e,0x15,0x16,0x28,0xae,0xd2,0xa6, + 0xab,0xf7,0x15,0x88,0x09,0xcf,0x4f,0x3c}; /* key size 128 bytes */ + + uint8_t AES192key[24] = {0x8e,0x73,0xb0,0xf7,0xda,0x0e,0x64,0x52, + 0xc8,0x10,0xf3,0x2b,0x80,0x90,0x79,0xe5, + 0x62,0xf8,0xea,0xd2,0x52,0x2c,0x6b,0x7b}; /* key size 192 bytes */ + + uint8_t AES256key[32] = {0x60,0x3d,0xeb,0x10,0x15,0xca,0x71,0xbe, + 0x2b,0x73,0xae,0xf0,0x85,0x7d,0x77,0x81, + 0x1f,0x35,0x2c,0x07,0x3b,0x61,0x08,0xd7, + 0x2d,0x98,0x10,0xa3,0x09,0x14,0xdf,0xf4}; /* key size 256 bytes */ + + uint8_t IV_1[16] = {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f}; /* initialization vector */ + + uint8_t Plaintext[AES_TEXT_SIZE] = + {0x6b,0xc1,0xbe,0xe2,0x2e,0x40,0x9f,0x96, + 0xe9,0x3d,0x7e,0x11,0x73,0x93,0x17,0x2a, + 0xae,0x2d,0x8a,0x57,0x1e,0x03,0xac,0x9c, + 0x9e,0xb7,0x6f,0xac,0x45,0xaf,0x8e,0x51, + 0x30,0xc8,0x1c,0x46,0xa3,0x5c,0xe4,0x11, + 0xe5,0xfb,0xc1,0x19,0x1a,0x0a,0x52,0xef, + 0xf6,0x9f,0x24,0x45,0xdf,0x4f,0x9b,0x17, + 0xad,0x2b,0x41,0x7b,0xe6,0x6c,0x37,0x10}; /* plaintext */ + +uint8_t Ciphertext[AES_TEXT_SIZE] = + {0x76,0x49,0xab,0xac,0x81,0x19,0xb2,0x46, + 0xce,0xe9,0x8e,0x9b,0x12,0xe9,0x19,0x7d, + 0x50,0x86,0xcb,0x9b,0x50,0x72,0x19,0xee, + 0x95,0xdb,0x11,0x3a,0x91,0x76,0x78,0xb2, + 0x73,0xbe,0xd6,0xb8,0xe3,0xc1,0x74,0x3b, + 0x71,0x16,0xe6,0x9e,0x22,0x22,0x95,0x16, + 0x3f,0xf1,0xca,0xa1,0x68,0x1f,0xac,0x09, + 0x12,0x0e,0xca,0x30,0x75,0x86,0xe1,0xa7}; /* ciphertext */ + +uint8_t Encryptedtext[AES_TEXT_SIZE]; /* Encrypted text */ +uint8_t Decryptedtext[AES_TEXT_SIZE]; /* Decrypted text */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +void USART_Config(void); + +void Display_PlainData(uint32_t datalength); +void Display_EncryptedData(uint8_t mode,uint16_t keysize,uint32_t datalength); +void Display_DecryptedData(uint8_t mode,uint16_t keysize,uint32_t datalength); +char PressToContinue(void); +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ +/*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* USARTx configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_Config(); + + /* Enable CRYP clock */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); + + while(1) + { + + /* Display Plain Data*/ + Display_PlainData(AES_TEXT_SIZE); + +/******************************************************************************/ +/* AES mode ECB */ +/******************************************************************************/ + +/*===================================================== + Encryption ECB mode +======================================================*/ + PressToContinue(); +/****************************************/ +/* AES 128 **/ +/****************************************/ + /* Encrypt the plaintext message*/ + CRYP_AES_ECB(MODE_ENCRYPT,AES128key,128,Plaintext,AES_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(ECB,128,AES_TEXT_SIZE); +/****************************************/ +/* AES 192 **/ +/****************************************/ + /* Encrypt the plaintext message*/ + CRYP_AES_ECB(MODE_ENCRYPT,AES192key,192,Plaintext,AES_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(ECB,192,AES_TEXT_SIZE); +/****************************************/ +/* AES 256 **/ +/****************************************/ + /* Encrypt the plaintext message*/ + CRYP_AES_ECB(MODE_ENCRYPT,AES256key,256,Plaintext,AES_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(ECB, 256,AES_TEXT_SIZE); + +/*===================================================== + Decryption in ECB mode +======================================================*/ + PressToContinue(); +/****************************************/ +/* AES 128 **/ +/****************************************/ + /* Decrypt the plaintext message */ + CRYP_AES_ECB(MODE_DECRYPT,AES128key,128,Ciphertext,AES_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(ECB,128,AES_TEXT_SIZE); +/****************************************/ +/* AES 192 **/ +/****************************************/ + /* Decrypt the plaintext message */ + CRYP_AES_ECB(MODE_DECRYPT,AES192key, 192,Ciphertext, AES_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(ECB, 192,AES_TEXT_SIZE); +/****************************************/ +/* AES 256 **/ +/****************************************/ + /* Decrypt the plaintext message */ + CRYP_AES_ECB(MODE_DECRYPT,AES256key, 256,Ciphertext, AES_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(ECB,256,AES_TEXT_SIZE); + + +/******************************************************************************/ +/* AES mode CBC */ +/******************************************************************************/ + PressToContinue(); +/*===================================================== + Encryption CBC mode +======================================================*/ + +/****************************************/ +/* AES 128 **/ +/****************************************/ + /* Encrypt the plaintext message*/ + CRYP_AES_CBC(MODE_ENCRYPT,IV_1,AES128key,128,Plaintext,AES_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(CBC,128,AES_TEXT_SIZE); +/****************************************/ +/* AES 192 **/ +/****************************************/ + /* Encrypt the plaintext message*/ + CRYP_AES_CBC(MODE_ENCRYPT,IV_1,AES192key,192,Plaintext,AES_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(CBC,192,AES_TEXT_SIZE); +/****************************************/ +/* AES 256 **/ +/****************************************/ + /* Encrypt the plaintext message*/ + CRYP_AES_CBC(MODE_ENCRYPT,IV_1,AES256key,256,Plaintext,AES_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(CBC, 256,AES_TEXT_SIZE); + +/*===================================================== + Decryption in CBC mode +======================================================*/ + PressToContinue(); + /* Deinitializes the CRYP peripheral */ + CRYP_DeInit(); +/****************************************/ +/* AES 128 **/ +/****************************************/ + /* Decrypt the plaintext message */ + CRYP_AES_CBC(MODE_DECRYPT,IV_1,AES128key,128,Ciphertext,AES_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(CBC,128,AES_TEXT_SIZE); +/****************************************/ +/* AES 192 **/ +/****************************************/ + /* Deinitializes the CRYP peripheral */ + CRYP_DeInit(); + + /* Decrypt the plaintext message */ + CRYP_AES_CBC(MODE_DECRYPT,IV_1,AES192key, 192,Ciphertext, AES_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(CBC, 192,AES_TEXT_SIZE); +/****************************************/ +/* AES 256 **/ +/****************************************/ + /* Deinitializes the CRYP peripheral */ + CRYP_DeInit(); + + /* Decrypt the plaintext message */ + CRYP_AES_CBC(MODE_DECRYPT,IV_1,AES256key, 256,Ciphertext, AES_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(CBC,256,AES_TEXT_SIZE); + + +/******************************************************************************/ +/* AES mode CTR */ +/******************************************************************************/ + +/*===================================================== + Encryption CTR mode +======================================================*/ + PressToContinue(); +/****************************************/ +/* AES 128 **/ +/****************************************/ + /* Encrypt the plaintext message*/ + CRYP_AES_CTR(MODE_ENCRYPT,IV_1,AES128key,128,Plaintext,AES_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(CTR,128, AES_TEXT_SIZE); +/****************************************/ +/* AES 192 **/ +/****************************************/ + /* Encrypt the plaintext message*/ + CRYP_AES_CTR(MODE_ENCRYPT,IV_1,AES192key,192,Plaintext,AES_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(CTR,192, AES_TEXT_SIZE); +/****************************************/ +/* AES 256 **/ +/****************************************/ + /* Encrypt the plaintext message*/ + CRYP_AES_CTR(MODE_ENCRYPT,IV_1,AES256key,256,Plaintext,AES_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(CTR, 256, AES_TEXT_SIZE); + +/*===================================================== + Decryption in CTR mode +======================================================*/ + PressToContinue(); +/****************************************/ +/* AES 128 **/ +/****************************************/ + /* Decrypt the plaintext message */ + CRYP_AES_CTR(MODE_DECRYPT,IV_1,AES128key,128,Ciphertext,AES_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(CTR, 128, AES_TEXT_SIZE); +/****************************************/ +/* AES 192 **/ +/****************************************/ + /* Decrypt the plaintext message */ + CRYP_AES_CTR(MODE_DECRYPT,IV_1,AES192key,192,Ciphertext,AES_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(CTR, 192, AES_TEXT_SIZE); +/****************************************/ +/* AES 256 **/ +/****************************************/ + /* Decrypt the plaintext message */ + CRYP_AES_CTR(MODE_DECRYPT,IV_1,AES256key, 256,Ciphertext, AES_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(CTR, 256, AES_TEXT_SIZE); + +/******************************************************************************/ + PressToContinue(); + printf("\n\r Example restarted...\n "); + } +} + +/** + * @brief Display Plain Data + * @param datalength: length of the data to display + * @retval None + */ +void Display_PlainData(uint32_t datalength) +{ + uint32_t BufferCounter =0; + uint32_t count = 0; + + printf("\n\r =============================================================\n\r"); + printf(" ================= Crypt Using HW Crypto ====================\n\r"); + printf(" ============================================================\n\r"); + printf(" ---------------------------------------\n\r"); + printf(" Plain Data :\n\r"); + printf(" ---------------------------------------\n\r"); + + for(BufferCounter = 0; BufferCounter < datalength; BufferCounter++) + { + printf("[0x%02X]", Plaintext[BufferCounter]); + count++; + + if(count == 16) + { + count = 0; + printf(" Block %d \n\r", BufferCounter/16); + } + } +} + +/** + * @brief Display Encrypted Data + * @param mode: chaining mode + * @param keysize: AES key size used + * @param datalength: length of the data to display + * @retval None + */ +void Display_EncryptedData(uint8_t mode, uint16_t keysize, uint32_t datalength) +{ + uint32_t BufferCounter = 0; + uint32_t count = 0; + + printf("\n\r =======================================\n\r"); + printf(" Encrypted Data with AES %d Mode ",keysize ); + + if(mode == ECB) + { + printf("ECB\n\r"); + } + else if(mode == CBC) + { + printf("CBC\n\r"); + } + else /* if(mode == CTR)*/ + { + printf("CTR\n\r"); + } + + printf(" ---------------------------------------\n\r"); + + for(BufferCounter = 0; BufferCounter < datalength; BufferCounter++) + { + printf("[0x%02X]", Encryptedtext[BufferCounter]); + + count++; + if(count == 16) + { + count = 0; + printf(" Block %d \n\r", BufferCounter/16); + } + } +} + +/** + * @brief Display Decrypted Data + * @param mode: chaining mode + * @param keysize: AES key size used + * @param datalength: length of the data to display + * @retval None + */ +void Display_DecryptedData(uint8_t mode, uint16_t keysize, uint32_t datalength) +{ + uint32_t BufferCounter = 0; + uint32_t count = 0; + + printf("\n\r =======================================\n\r"); + printf(" Decrypted Data with AES %d Mode ",keysize ); + + if(mode == ECB) + { + printf("ECB\n\r"); + } + else if(mode == CBC) + { + printf("CBC\n\r"); + } + else /* if(mode == CTR)*/ + { + printf("CTR\n\r"); + } + + printf(" ---------------------------------------\n\r"); + + for(BufferCounter = 0; BufferCounter < datalength; BufferCounter++) + { + printf("[0x%02X]", Decryptedtext[BufferCounter]); + count++; + + if(count == 16) + { + count = 0; + printf(" Block %d \n\r", BufferCounter/16); + } + } +} + +/** + * @brief USART configuration + * @param None + * @retval None + */ +void USART_Config(void) +{ + USART_InitTypeDef USART_InitStructure; + + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit(COM1, &USART_InitStructure); +} + +/** + * @brief Wait till a character is received by the USART + * @param None + * @retval Keyboard pressed character + */ +char PressToContinue(void) +{ + char c; + printf("\n\r Press any key to continue...\n\r "); + + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_RXNE) == RESET) + { + } + + c = USART_ReceiveData(EVAL_COM1); + + return(c); +} + +/** + * @brief Retargets the C library printf function to the USART. + * @param None + * @retval None + */ +PUTCHAR_PROTOTYPE +{ + /* Place your implementation of fputc here */ + /* e.g. write a character to the USART */ + USART_SendData(EVAL_COM1, (uint8_t) ch); + + /* Loop until the end of transmission */ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) + {} + + return ch; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/readme.txt new file mode 100644 index 000000000..e32570ae0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/readme.txt @@ -0,0 +1,126 @@ +/** + @page AES_modes Encrypt and Decrypt data using AES Algo in All modes and all key sizes + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file CRYP/AES_modes/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the CRYP AES Algorithm in all modes and all key sizes + Example + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the CRYPTO peripheral to +encrypt and decrypt data using AES in all modes (ECB, CBC, CTR) and all key sizes +(128, 192, 256) Algorithm. + +For this example, a firmware is used to interface with the Crypto peripheral +in polling mode. + +This example behaves as follows: + +1. ECB mode : + - AES128 ECB Encryption + - AES192 ECB Encryption + - AES256 ECB Encryption + + - AES128 ECB Decryption + - AES192 ECB Decryption + - AES256 ECB Decryption + +2. CBC mode : + - AES128 CBC Encryption + - AES192 CBC Encryption + - AES256 CBC Encryption + + - AES128 CBC Decryption + - AES192 CBC Decryption + - AES256 CBC Decryption + +3. CTR mode : + - AES128 CTR Encryption + - AES192 CTR Encryption + - AES256 CTR Encryption + + - AES128 CTR Decryption + - AES192 CTR Decryption + - AES256 CTR Decryption + +The Plain data, encrypted data and decrypted data can be displayed on a PC +HyperTerminal using the USART (CN16). + +The USARTx is configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + + +@par Directory contents + + - CRYP/AES_modes/system_stm32f2xx.c STM32F2xx system clock configuration file + - CRYP/AES_modes/stm32f2xx_conf.h Library Configuration file + - CRYP/AES_modes/stm32f2xx_it.h Interrupt handlers header file + - CRYP/AES_modes/stm32f2xx_it.c Interrupt handlers + - CRYP/AES_modes/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs only on STM32F21x Devices (Cryptographic acceleration not + embedded in STM32F20x Devices). + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/stm32f2xx_conf.h new file mode 100644 index 000000000..9bacc8dee --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file CRYP/AES_modes/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/stm32f2xx_it.c new file mode 100644 index 000000000..3dc8ba781 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file CRYP/AES_modes/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup AES_modes + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/stm32f2xx_it.h new file mode 100644 index 000000000..f745a290d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file CRYP/AES_modes/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/AES_modes/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/Expected_Results.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/Expected_Results.txt new file mode 100644 index 000000000..7176d3d5d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/Expected_Results.txt @@ -0,0 +1,48 @@ + ============================================================= + ================= Crypt Using HW Crypto ==================== + ============================================================= + + --------------------------------------- + Plain Data : + --------------------------------------- +[0x31][0x32][0x33][0x34][0x35][0x36][0x37][0x38] Block 0 + + ======================================= + Encrypted Data DES Mode ECB + --------------------------------------- +[0xAF][0xE6][0x49][0x61][0xCC][0x4F][0x7C][0x13] Block 0 + + ======================================= + Decrypted Data DES Mode ECB + --------------------------------------- +[0x31][0x32][0x33][0x34][0x35][0x36][0x37][0x38] Block 0 + + ======================================= + Encrypted Data DES Mode CBC + --------------------------------------- +[0xD4][0xE3][0x6B][0x07][0x60][0xBD][0x60][0x15] Block 0 + + ======================================= + Decrypted Data DES Mode CBC + --------------------------------------- +[0x31][0x32][0x33][0x34][0x35][0x36][0x37][0x38] Block 0 + + ======================================= + Encrypted Data TDES Mode ECB + --------------------------------------- +[0x50][0x08][0x77][0xCB][0x7B][0x95][0xBC][0x0C] Block 0 + + ======================================= + Decrypted Data TDES Mode ECB + --------------------------------------- +[0x31][0x32][0x33][0x34][0x35][0x36][0x37][0x38] Block 0 + + ======================================= + Encrypted Data TDES Mode CBC + --------------------------------------- +[0x06][0x63][0x86][0xC3][0x3E][0xCB][0x14][0xDF] Block 0 + + ======================================= + Decrypted Data TDES Mode CBC + --------------------------------------- +[0x31][0x32][0x33][0x34][0x35][0x36][0x37][0x38] Block 0 diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/main.c new file mode 100644 index 000000000..4e2e29283 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/main.c @@ -0,0 +1,392 @@ +/** + ****************************************************************************** + * @file CRYP/DES_TDES_modes/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stdio.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DES_TDES_modes + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define PLAIN_TEXT_SIZE 8 +#define ECB 1 +#define CBC 2 + +#define DES ' ' +#define TDES 'T' + +/* key size 64 bytes */ + uint8_t DESkey[8] = {0x2b,0x7e,0x15,0x16,0x28,0xae,0xd2,0xa6}; + +/* key : 192 bits */ +uint8_t TDESkey[24] = {0x01,0x23,0x45,0x67,0x89,0xAB,0xCD,0xEF, /* key 1 */ + 0xFE,0xDC,0xBA,0x98,0x76,0x54,0x32,0x10, /* key 2 */ + 0x89,0xAB,0xCD,0xEF,0x01,0x23,0x45,0x67}; /* key 3 */ + +uint8_t Plaintext[PLAIN_TEXT_SIZE] = {0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38}; /* Plaintext */ + +/* initialization vector */ +uint8_t IV_1[8] = {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07}; + +uint8_t Encryptedtext[PLAIN_TEXT_SIZE]; /* Encrypted text */ +uint8_t Decryptedtext[PLAIN_TEXT_SIZE]; /* Decrypted text */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +void USART_Config(void); + +void Display_PlainData(uint32_t datalength); +void Display_EncryptedData(uint8_t Algo, uint8_t mode,uint32_t datalength); +void Display_DecryptedData(uint8_t Algo, uint8_t mode,uint32_t datalength); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ +/*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* USARTx configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_Config(); + + /* Display Plain Data*/ + Display_PlainData(PLAIN_TEXT_SIZE); + + /* Enable CRYP clock */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); + +/******************************************************************************/ +/* DES mode ECB */ +/******************************************************************************/ + +/*===================================================== + Encryption ECB mode +======================================================*/ + + /* Encrypt the plaintext message */ + CRYP_DES_ECB(MODE_ENCRYPT,DESkey,Plaintext,PLAIN_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(DES,ECB,PLAIN_TEXT_SIZE); + +/*===================================================== + Decryption in ECB mode +======================================================*/ + + /* Decrypt the plaintext message */ + CRYP_DES_ECB(MODE_DECRYPT,DESkey,Encryptedtext,PLAIN_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(DES,ECB,PLAIN_TEXT_SIZE); + + +/******************************************************************************/ +/* DES mode CBC */ +/******************************************************************************/ + +/*===================================================== + Encryption CBC mode +======================================================*/ + + /* Encrypt the plaintext message*/ + CRYP_DES_CBC(MODE_ENCRYPT,DESkey,IV_1,Plaintext,PLAIN_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(DES,CBC,PLAIN_TEXT_SIZE); + +/*===================================================== + Decryption in CBC mode +======================================================*/ + + /* Decrypt the plaintext message */ + CRYP_DES_CBC(MODE_DECRYPT,DESkey,IV_1,Encryptedtext,PLAIN_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(DES,CBC,PLAIN_TEXT_SIZE); + + +/******************************************************************************/ +/* TDES mode ECB */ +/******************************************************************************/ + +/*===================================================== + Encryption ECB mode +======================================================*/ + + /* Encrypt the plaintext message*/ + CRYP_TDES_ECB(MODE_ENCRYPT,TDESkey,Plaintext,PLAIN_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(TDES,ECB,PLAIN_TEXT_SIZE); + +/*===================================================== + Decryption in ECB mode +======================================================*/ + + /* Decrypt the plaintext message */ + CRYP_TDES_ECB(MODE_DECRYPT,TDESkey,Encryptedtext,PLAIN_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(TDES,ECB,PLAIN_TEXT_SIZE); + + +/******************************************************************************/ +/* TDES mode CBC */ +/******************************************************************************/ + +/*===================================================== + Encryption CBC mode +======================================================*/ + + /* Encrypt the plaintext message*/ + CRYP_TDES_CBC(MODE_ENCRYPT,TDESkey,IV_1,Plaintext,PLAIN_TEXT_SIZE,Encryptedtext); + + /* Display encrypted Data*/ + Display_EncryptedData(TDES,CBC,PLAIN_TEXT_SIZE); + +/*===================================================== + Decryption in CBC mode +======================================================*/ + + /* Decrypt the plaintext message */ + CRYP_TDES_CBC(MODE_DECRYPT,TDESkey,IV_1,Encryptedtext,PLAIN_TEXT_SIZE,Decryptedtext); + + /* Display decrypted data*/ + Display_DecryptedData(TDES,CBC,PLAIN_TEXT_SIZE); +/******************************************************************************/ + + while(1); +} + +/** + * @brief Display Plain Data + * @param datalength: length of the data to display + * @retval None + */ +void Display_PlainData(uint32_t datalength) +{ + uint32_t BufferCounter = 0; + uint32_t count = 0; + + printf("\n\r =============================================================\n\r"); + printf(" ================= Crypt Using HW Crypto ====================\n\r"); + printf(" =============================================================\n\r"); + printf(" ---------------------------------------\n\r"); + printf(" Plain Data :\n\r"); + printf(" ---------------------------------------\n\r"); + + for(BufferCounter = 0; BufferCounter < datalength; BufferCounter++) + { + printf("[0x%02X]", Plaintext[BufferCounter]); + + count++; + if(count == 8) + { + count = 0; + printf(" Block %d \n\r", BufferCounter/8); + } + } +} +/** + * @brief Display Encrypted Data + * @param Algo: Algorithm used (DES or TDES) + * @param mode: chaining mode + * @param datalength: length of the data to display + * @retval None + */ +void Display_EncryptedData(uint8_t Algo, uint8_t mode, uint32_t datalength) +{ + uint32_t BufferCounter = 0; + uint32_t count = 0; + + printf("\n\r =======================================\n\r"); + printf(" Encrypted Data %cDES Mode ",Algo); + + if(mode == ECB) + { + printf("ECB\n\r"); + } + else/* if(mode == CBC)*/ + { + printf("CBC\n\r"); + } + + printf(" ---------------------------------------\n\r"); + + for(BufferCounter = 0; BufferCounter < datalength; BufferCounter++) + { + printf("[0x%02X]", Encryptedtext[BufferCounter]); + count++; + + if(count == 8) + { + count = 0; + printf(" Block %d \n\r", BufferCounter/8); + } + } +} + +/** + * @brief Display Decrypted Data + * @param Algo: Algorithm used (DES or TDES) + * @param mode: chaining mode + * @param datalength: length of the data to display + * @retval None + */ +void Display_DecryptedData(uint8_t Algo, uint8_t mode, uint32_t datalength) +{ + uint32_t BufferCounter = 0; + uint32_t count = 0; + + printf("\n\r =======================================\n\r"); + printf(" Decrypted Data %cDES Mode ",Algo); + + if(mode == ECB) + { + printf("ECB\n\r"); + } + else/* if(mode == CBC)*/ + { + printf("CBC\n\r"); + } + + printf(" ---------------------------------------\n\r"); + + for(BufferCounter = 0; BufferCounter < datalength; BufferCounter++) + { + printf("[0x%02X]", Decryptedtext[BufferCounter]); + count++; + + if(count == 8) + { + count = 0; + printf(" Block %d \n\r", BufferCounter/8); + } + } +} + +/** + * @brief USART configuration + * @param None + * @retval None + */ +void USART_Config(void) +{ + USART_InitTypeDef USART_InitStructure; + + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit(COM1, &USART_InitStructure); +} + +/** + * @brief Retargets the C library printf function to the USART. + * @param None + * @retval None + */ +PUTCHAR_PROTOTYPE +{ + /* Place your implementation of fputc here */ + /* e.g. write a character to the USART */ + USART_SendData(EVAL_COM1, (uint8_t) ch); + + /* Loop until the end of transmission */ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) + {} + + return ch; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/readme.txt new file mode 100644 index 000000000..2bf4a13f2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/readme.txt @@ -0,0 +1,107 @@ +/** + @page DES_TDES_modes Encrypt and Decrypt data using DES and TDES Algorithms in All modes + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file CRYP/DES_TDES_modes/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the CRYP DES and TDES Algorithm in all modes Example + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the CRYPTO peripheral to +encrypt and decrypt data using DES and TDES in all modes (ECB, CBC) Algorithm. + +For this example, a firmware is used to interface with the Crypto peripheral +in polling mode. + +This example is behaves as follow: +1. DES + - DES ECB Encryption + - DES ECB Decryption + - DES CBC Encryption + - DES CBC Decryption +2. TDES + - TDES ECB Encryption + - TDES ECB Decryption + - TDES CBC Encryption + - TDES CBC Decryption + +The Plain data, encrypted data and decrypted data can be displayed on a PC +HyperTerminal using the USART (CN16). + +The USARTx is configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + + +@par Directory contents + + - CRYP/DES_TDES_modes/system_stm32f2xx.c STM32F2xx system clock configuration file + - CRYP/DES_TDES_modes/stm32f2xx_conf.h Library Configuration file + - CRYP/DES_TDES_modes/stm32f2xx_it.h Interrupt handlers header file + - CRYP/DES_TDES_modes/stm32f2xx_it.c Interrupt handlers + - CRYP/DES_TDES_modes/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs only on STM32F21x Devices (Cryptographic acceleration not + embedded in STM32F20x Devices). + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/stm32f2xx_conf.h new file mode 100644 index 000000000..3041f2820 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file CRYP/DES_TDES_modes/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/stm32f2xx_it.c new file mode 100644 index 000000000..88b566016 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file CRYP/DES_TDES_modes/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DES_TDES_modes + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/stm32f2xx_it.h new file mode 100644 index 000000000..7b56b3e21 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file CRYP/DES_TDES_modes/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/DES_TDES_modes/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/Expected_Results.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/Expected_Results.txt new file mode 100644 index 000000000..434747e17 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/Expected_Results.txt @@ -0,0 +1,30 @@ + ====================================== + ==== CRYP TDES Using DMA Example ==== + ====================================== + + --------------------------------------- + Plain Data: + --------------------------------------- +[0x20212223][0x24252627] Block 0 +[0x28292a2b][0x2c2d2e2f] Block 1 +[0xffeeddcc][0xbbaa9988] Block 2 +[0x77665544][0x33221100] Block 3 +[0x10000000][0x20000000] Block 4 + + --------------------------------------- + TDES Encrypted Data: + --------------------------------------- +[0xc9406174][0xf076c814] Block 0 +[0x81a2bcb1][0x4ed3e70d] Block 1 +[0x54351409][0x6c4e674b] Block 2 +[0x4fde2aec][0xdbe00ac3] Block 3 +[0xee46220c][0xcab2cefb] Block 4 + + --------------------------------------- + TDES Decrypted Data: + --------------------------------------- +[0x20212223][0x24252627] Block 0 +[0x28292a2b][0x2c2d2e2f] Block 1 +[0xffeeddcc][0xbbaa9988] Block 2 +[0x77665544][0x33221100] Block 3 +[0x10000000][0x20000000] Block 4 diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/main.c new file mode 100644 index 000000000..e51d77c2a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/main.c @@ -0,0 +1,477 @@ +/** + ****************************************************************************** + * @file CRYP/TDES_ECBmode_DMA/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TDES_ECBmode_DMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define BLOCKS_NBR 5 /* User can change this value to enlarge or reduce the + nbre of blocks to encrypt */ + +#define DATA_SIZE ((BLOCKS_NBR*64)/32) +#define CRYP_DIN_REG_ADDR ((uint32_t)0x50060008) /* Crypto DIN register address */ +#define CRYP_DOUT_REG_ADDR ((uint32_t)0x5006000C) /* Crypto DOUT register address */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* 192 bit key */ +__IO uint32_t TDESkey[6]={0x40414243,0x44454647, /* K1 */ + 0x48494A4B,0x4C4D4E4F, /* K2 */ + 0x50515253,0x54555657}; /* K3 */ + +__IO uint32_t PlainData[DATA_SIZE]={0x20212223,0x24252627, /* Block 0 */ + 0x28292a2b,0x2c2d2e2f, /* Block 1 */ + 0xFFEEDDCC,0xBBAA9988, /* Block 2 */ + 0x77665544,0x33221100, /* Block 3 */ + 0x10000000,0x20000000 };/* Block 4 */ + +__IO uint32_t EncryptedData[DATA_SIZE]; +__IO uint32_t DecryptedData[DATA_SIZE]; + +/* Private function prototypes -----------------------------------------------*/ +void TDES_Encrypt_DMA(void); +void TDES_Decrypt_DMA(void); + +void Display_PlainData(void); +void Display_EncryptedData(void); +void Display_DecryptedData(void); + +void USART_Config(void); +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ +/*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* USARTx configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + /* USART Configuration */ + USART_Config(); + + /* Display Plain Data*/ + Display_PlainData(); + +/*===================================================== + Encryption +======================================================*/ + + /* Encrypt */ + TDES_Encrypt_DMA(); + + /* Display encrypted Data*/ + Display_EncryptedData(); + +/*===================================================== + Decryption +======================================================*/ + + /* Decrypt */ + TDES_Decrypt_DMA(); + + /* Display decrypted data*/ + Display_DecryptedData(); + + while(1); +} + +/** + * @brief Encrypt Data using TDES + * @note DATA transfer is done by DMA + * @note DMA2 stream6 channel2 is used to transfer data from memory (the + * PlainData Tab) to CRYP Peripheral (the INPUT data register). + * @note DMA2 stream5 channel2 is used to transfer data from CRYP Peripheral + * (the OUTPUT data register to memory (the EncryptedData Tab). + * @param None + * @retval None + */ +void TDES_Encrypt_DMA(void) +{ + CRYP_InitTypeDef CRYP_InitStructure; + CRYP_KeyInitTypeDef CRYP_KeyInitStructure; + DMA_InitTypeDef DMA_InitStructure; + + /* Enable CRYP clock */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); + + /* Enable DMA2 clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + /* Configure crypto as encoder TDES *****************************************/ + /* Crypto Init for Encryption process */ + CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; + CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; + CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; + + CRYP_FIFOFlush(); + CRYP_Init(&CRYP_InitStructure); + + /* Key Initialisation */ + CRYP_KeyInitStructure.CRYP_Key1Left = TDESkey[0]; + CRYP_KeyInitStructure.CRYP_Key1Right= TDESkey[1]; + CRYP_KeyInitStructure.CRYP_Key2Left = TDESkey[2]; + CRYP_KeyInitStructure.CRYP_Key2Right= TDESkey[3]; + CRYP_KeyInitStructure.CRYP_Key3Left = TDESkey[4]; + CRYP_KeyInitStructure.CRYP_Key3Right= TDESkey[5]; + CRYP_KeyInit(&CRYP_KeyInitStructure); + + CRYP_DMACmd(CRYP_DMAReq_DataOUT, ENABLE); + CRYP_DMACmd(CRYP_DMAReq_DataIN, ENABLE); + + /* DMA Configuration*********************************************************/ + /* set commun DMA parameters for Stream 5 and 6*/ + DMA_DeInit(DMA2_Stream5); + DMA_DeInit(DMA2_Stream6); + DMA_InitStructure.DMA_Channel = DMA_Channel_2; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_BufferSize = DATA_SIZE; + + /* Set the parameters to be configured specific to stream 6*/ + DMA_InitStructure.DMA_PeripheralBaseAddr = CRYP_DIN_REG_ADDR; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)PlainData; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + + /* Configure the DMA Stream 6 */ + DMA_Init(DMA2_Stream6, &DMA_InitStructure); + + /* Set the parameters to be configured specific to stream 5*/ + DMA_InitStructure.DMA_PeripheralBaseAddr = CRYP_DOUT_REG_ADDR; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)EncryptedData; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + + /* Configure the DMA Stream 5 */ + DMA_Init(DMA2_Stream5, &DMA_InitStructure); + + /* Enable DMA streams*/ + DMA_Cmd(DMA2_Stream6, ENABLE); + DMA_Cmd(DMA2_Stream5, ENABLE); + + /* Enable Crypto processor */ + CRYP_Cmd(ENABLE); + + /* wait until the last transfer from OUT FIFO : + all encrypted Data are transfered from crypt processor */ + while (DMA_GetFlagStatus(DMA2_Stream5, DMA_FLAG_TCIF5) == RESET); + + /* Disable Crypto and DMA ***************************************************/ + CRYP_Cmd(DISABLE); + CRYP_DMACmd(CRYP_DMAReq_DataOUT, DISABLE); + CRYP_DMACmd(CRYP_DMAReq_DataIN, DISABLE); + DMA_Cmd(DMA2_Stream5, DISABLE); + DMA_Cmd(DMA2_Stream6, DISABLE); +} + +/** + * @brief Decrypt Data using TDES + * @note DATA transfer is done by DMA + * @note DMA2 stream6 channel2 is used to transfer data from memory (the + * EncryptedData Tab) to CRYP Peripheral (the INPUT data register). + * @note DMA2 stream5 channel2 is used to transfer data from CRYP Peripheral + * (the OUTPUT data register to memory (the DecryptedData Tab). + * @param None + * @retval None + */ +void TDES_Decrypt_DMA(void) +{ + CRYP_InitTypeDef CRYP_InitStructure; + CRYP_KeyInitTypeDef CRYP_KeyInitStructure; + DMA_InitTypeDef DMA_InitStructure; + + /* Enable CRYP clock */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); + + /* Enable DMA2 clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + /* configure crypto as Decoder TDES *****************************************/ + CRYP_FIFOFlush(); + /* Crypto Init for Decryption process */ + CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; + CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; + CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; + CRYP_Init(&CRYP_InitStructure); + + /* Key Initialisation */ + CRYP_KeyInitStructure.CRYP_Key1Left = TDESkey[0]; + CRYP_KeyInitStructure.CRYP_Key1Right= TDESkey[1]; + CRYP_KeyInitStructure.CRYP_Key2Left = TDESkey[2]; + CRYP_KeyInitStructure.CRYP_Key2Right= TDESkey[3]; + CRYP_KeyInitStructure.CRYP_Key3Left = TDESkey[4]; + CRYP_KeyInitStructure.CRYP_Key3Right= TDESkey[5]; + CRYP_KeyInit(&CRYP_KeyInitStructure); + + CRYP_DMACmd(CRYP_DMAReq_DataOUT, ENABLE); + CRYP_DMACmd(CRYP_DMAReq_DataIN, ENABLE); + + /* DMA Configuration ********************************************************/ + /* set commun DMA parameters for Stream 5 and 6*/ + DMA_DeInit(DMA2_Stream5); + DMA_DeInit(DMA2_Stream6); + DMA_InitStructure.DMA_Channel = DMA_Channel_2; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_BufferSize = DATA_SIZE; + + /* Set the parameters to be configured specific to stream 6*/ + DMA_InitStructure.DMA_PeripheralBaseAddr = CRYP_DIN_REG_ADDR; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)EncryptedData; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + + /* Configure the DMA Stream 6 */ + DMA_Init(DMA2_Stream6, &DMA_InitStructure); + + /* Set the parameters to be configured specific to stream 5*/ + DMA_InitStructure.DMA_PeripheralBaseAddr = CRYP_DOUT_REG_ADDR; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)DecryptedData; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + + /* Configure the DMA Stream 5 */ + DMA_Init(DMA2_Stream5, &DMA_InitStructure); + + /* Enable DMA streams*/ + DMA_Cmd(DMA2_Stream6, ENABLE); + DMA_Cmd(DMA2_Stream5, ENABLE); + + /* Enable Crypo Processor */ + CRYP_Cmd(ENABLE); + + /* wait until the last transfer from OUT FIFO : + all encrypted Data are transfered from crypt processor */ + while (DMA_GetFlagStatus(DMA2_Stream5, DMA_FLAG_TCIF5) == RESET); + + /* Disable Crypto and DMA ***************************************************/ + CRYP_Cmd(DISABLE); + CRYP_DMACmd(CRYP_DMAReq_DataOUT, DISABLE); + CRYP_DMACmd(CRYP_DMAReq_DataIN, DISABLE); + DMA_Cmd(DMA2_Stream5, DISABLE); + DMA_Cmd(DMA2_Stream6, DISABLE); +} + +/** + * @brief Display Plain Data + * @param None + * @retval None + */ +void Display_PlainData(void) +{ + uint32_t BufferCounter = 0; + uint8_t count = 0; + printf("\n\r ======================================\n\r"); + printf(" ==== CRYP TDES Using DMA Example ====\n\r"); + printf(" ======================================\n\r"); + + printf(" ---------------------------------------\n\r"); + printf(" Plain Data:\n\r"); + printf(" ---------------------------------------\n\r"); + + for(BufferCounter=0; BufferCounter EncryptedData) +- TDES Decryption (EncryptedData --> DecryptedData) + +The Plain data, encrypted data and decrypted data can be displayed on a PC +HyperTerminal using the USART (CN16). + +The USARTx is configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + + +@par Directory contents + + - CRYP/TDES_ECBmode_DMA/system_stm32f2xx.c STM32F2xx system clock configuration file + - CRYP/TDES_ECBmode_DMA/stm32f2xx_conf.h Library Configuration file + - CRYP/TDES_ECBmode_DMA/stm32f2xx_it.h Interrupt handlers header file + - CRYP/TDES_ECBmode_DMA/stm32f2xx_it.c Interrupt handlers + - CRYP/TDES_ECBmode_DMA/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs only on STM32F21x Devices (Cryptographic acceleration not + embedded in STM32F20x Devices). + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/stm32f2xx_conf.h new file mode 100644 index 000000000..abc265092 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file CRYP/TDES_ECBmode_DMA/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/stm32f2xx_it.c new file mode 100644 index 000000000..28fbbf428 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file CRYP/TDES_ECBmode_DMA/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TDES_ECBmode_DMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/stm32f2xx_it.h new file mode 100644 index 000000000..24f06fee6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file CRYP/TDES_ECBmode_DMA/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CRYP/TDES_ECBmode_DMA/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/main.c new file mode 100644 index 000000000..1987dfe43 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/main.c @@ -0,0 +1,145 @@ +/** + ****************************************************************************** + * @file CortexM3/BitBand/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CortexM3_BitBand + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +#define Var_ResetBit_BB(VarAddr, BitNumber) \ + (*(__IO uint32_t *) (SRAM_BB_BASE | ((VarAddr - SRAM_BASE) << 5) | ((BitNumber) << 2)) = 0) + +#define Var_SetBit_BB(VarAddr, BitNumber) \ + (*(__IO uint32_t *) (SRAM_BB_BASE | ((VarAddr - SRAM_BASE) << 5) | ((BitNumber) << 2)) = 1) + +#define Var_GetBit_BB(VarAddr, BitNumber) \ + (*(__IO uint32_t *) (SRAM_BB_BASE | ((VarAddr - SRAM_BASE) << 5) | ((BitNumber) << 2))) + +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t Var, VarAddr = 0, VarBitValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + Var = 0x00005AA5; + +/* A mapping formula shows how to reference each word in the alias region to a + corresponding bit in the bit-band region. The mapping formula is: + bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number + 4) + +where: + - bit_word_addr: is the address of the word in the alias memory region that + maps to the targeted bit. + - bit_band_base is the starting address of the alias region + - byte_offset is the number of the byte in the bit-band region that contains + the targeted bit + - bit_number is the bit position (0-7) of the targeted bit */ + +/* Get the variable address --------------------------------------------------*/ + VarAddr = (uint32_t)&Var; + +/* Modify variable bit using bit-band access ---------------------------------*/ + /* Modify Var variable bit 0 -----------------------------------------------*/ + Var_ResetBit_BB(VarAddr, 0); /* Var = 0x00005AA4 */ + Var_SetBit_BB(VarAddr, 0); /* Var = 0x00005AA5 */ + + /* Modify Var variable bit 11 ----------------------------------------------*/ + Var_ResetBit_BB(VarAddr, 11); /* Var = 0x000052A5 */ + /* Get Var variable bit 11 value */ + VarBitValue = Var_GetBit_BB(VarAddr, 11); /* VarBitValue = 0x00000000 */ + + Var_SetBit_BB(VarAddr, 11); /* Var = 0x00005AA5 */ + /* Get Var variable bit 11 value */ + VarBitValue = Var_GetBit_BB(VarAddr, 11); /* VarBitValue = 0x00000001 */ + + /* Modify Var variable bit 31 ----------------------------------------------*/ + Var_SetBit_BB(VarAddr, 31); /* Var = 0x80005AA5 */ + /* Get Var variable bit 31 value */ + VarBitValue = Var_GetBit_BB(VarAddr, 31); /* VarBitValue = 0x00000001 */ + + Var_ResetBit_BB(VarAddr, 31); /* Var = 0x00005AA5 */ + /* Get Var variable bit 31 value */ + VarBitValue = Var_GetBit_BB(VarAddr, 31); /* VarBitValue = 0x00000000 */ + + while (1) + { + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/readme.txt new file mode 100644 index 000000000..f5fb53c5a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/readme.txt @@ -0,0 +1,71 @@ +/** + @page CortexM3_BitBand CortexM3 BitBand example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file CortexM3/BitBand/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the CortexM3 BitBand example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to use CortexM3 Bit-Band access to perform atomic +read-modify-write and read operations on a variable in SRAM. + + +@par Directory contents + + - CortexM3/BitBand/stm32f2xx_conf.h Library Configuration file + - CortexM3/BitBand/stm32f2xx_it.c Interrupt handlers + - CortexM3/BitBand/stm32f2xx_it.h Interrupt handlers header file + - CortexM3/BitBand/main.c Main program + - CortexM3/BitBand/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/stm32f2xx_conf.h new file mode 100644 index 000000000..5e21be46e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file CortexM3/BitBand/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/stm32f2xx_it.c new file mode 100644 index 000000000..c081ebd53 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file CortexM3/BitBand/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CortexM3_BitBand + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/stm32f2xx_it.h new file mode 100644 index 000000000..a853ca5aa --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file CortexM3/BitBand/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/BitBand/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/Linker/RIDE/stm32F_flash_ROAarray.ld b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/Linker/RIDE/stm32F_flash_ROAarray.ld new file mode 100644 index 000000000..0f212aecf --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/Linker/RIDE/stm32F_flash_ROAarray.ld @@ -0,0 +1,249 @@ +/* +Default linker script for STM32F2xx_1024K_128K +*/ + +/* include the common STM32F2xx sub-script */ + +/* Common part of the linker scripts for STM32F devices*/ + + +/* default stack sizes. + +These are used by the startup in order to allocate stacks for the different modes. +*/ + +__Stack_Size = 1024 ; + +PROVIDE ( _Stack_Size = __Stack_Size ) ; + +__Stack_Init = _estack - __Stack_Size ; + +/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/ +PROVIDE ( _Stack_Init = __Stack_Init ) ; + +/* +There will be a link error if there is not this amount of RAM free at the end. +*/ +_Minimum_Stack_Size = 0x100 ; + + +/* include the memory spaces definitions sub-script */ +/* +Linker subscript for STM32F2xx definitions with 1024 Flash and 128 Onchip SRAM */ + +/* Memory Spaces Definitions */ + +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 112K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K + FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + MEMORY_ARRAY (xrw) : ORIGIN = 0x20002000, LENGTH = 32 +} + +/* higher address of the user mode stack */ +_estack = 0x2001C000; + + + +/* include the sections management sub-script for FLASH mode */ + +/* Sections Definitions */ + +SECTIONS +{ + /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */ + .flashtext : + { + . = ALIGN(4); + *(.flashtext) /* Startup code */ + . = ALIGN(4); + } >FLASH + + + /* the program code is stored in the .text section, which goes to Flash */ + .text : + { + . = ALIGN(4); + + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + + . = ALIGN(4); + _etext = .; + /* This is used by the startup in order to initialize the .data secion */ + _sidata = _etext; + } >FLASH + + /* MEMORY_ARRAY */ + .ROarraySection : + { + *(.ROarraySection) + } >MEMORY_ARRAY + + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + + + /* This is the uninitialized data section */ + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* This is the user stack section + This is just to check that there is enough RAM left for the User mode stack + It should generate an error if it's full. + */ + ._usrstack : + { + . = ALIGN(4); + _susrstack = . ; + + . = . + _Minimum_Stack_Size ; + + . = ALIGN(4); + _eusrstack = . ; + } >RAM + + + + /* this is the FLASH Bank1 */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + .b1text : + { + *(.b1text) /* remaining code */ + *(.b1rodata) /* read-only data (constants) */ + *(.b1rodata*) + } >FLASHB1 + + /* this is the EXTMEM */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + + /* EXTMEM Bank0 */ + .eb0text : + { + *(.eb0text) /* remaining code */ + *(.eb0rodata) /* read-only data (constants) */ + *(.eb0rodata*) + } >EXTMEMB0 + + /* EXTMEM Bank1 */ + .eb1text : + { + *(.eb1text) /* remaining code */ + *(.eb1rodata) /* read-only data (constants) */ + *(.eb1rodata*) + } >EXTMEMB1 + + /* EXTMEM Bank2 */ + .eb2text : + { + *(.eb2text) /* remaining code */ + *(.eb2rodata) /* read-only data (constants) */ + *(.eb2rodata*) + } >EXTMEMB2 + + /* EXTMEM Bank0 */ + .eb3text : + { + *(.eb3text) /* remaining code */ + *(.eb3rodata) /* read-only data (constants) */ + *(.eb3rodata*) + } >EXTMEMB3 + + + + /* after that it's only debugging information. */ + + /* remove the debugging information from the standard libraries */ + DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + +} diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/Linker/TrueSTUDIO/stm32F_flash_ROAarray.ld b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/Linker/TrueSTUDIO/stm32F_flash_ROAarray.ld new file mode 100644 index 000000000..9556bd6f8 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/Linker/TrueSTUDIO/stm32F_flash_ROAarray.ld @@ -0,0 +1,174 @@ +/* +***************************************************************************** +** +** File : stm32_flash.ld +** +** Abstract : Linker script for STM32F207IG Device with +** 1MByte FLASH, 128KByte SRAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the Atollic TrueSTUDIO(R) toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x2001C000; /* end of 112K SRAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x200; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 112K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K + MEMORY_ARRAY (rw) : ORIGIN = 0x20002000, LENGTH = 32 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .ARM.attributes : { *(.ARM.attributes) } > FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ROarraySection : {*(.ROarraySection)} >MEMORY_ARRAY + +} diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/main.c new file mode 100644 index 000000000..111225248 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/main.c @@ -0,0 +1,130 @@ +/** + ****************************************************************************** + * @file CortexM3/MPU/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_mpu.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CortexM3_MPU + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define ACCESS_PERMISSION + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +void Delay (uint32_t nCount); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Configure LED1 and LED2 */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + + /* Set MPU regions */ + MPU_Config(); + + #ifdef ACCESS_PERMISSION + MPU_AccessPermConfig(); + #endif + + /* Infinite loop */ + while (1) + { + /* Toggle LED1 */ + STM_EVAL_LEDToggle(LED1); + + /* Insert a delay */ + Delay(0x7FFFF); + } +} + +/** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + */ +void Delay(__IO uint32_t nCount) +{ + /* Decrement nCount value */ + while (nCount != 0) + { + nCount--; + } +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/readme.txt new file mode 100644 index 000000000..e72fc2559 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/readme.txt @@ -0,0 +1,99 @@ +/** + @page CortexM3_MPU CortexM3 MPU example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file CortexM3/MPU/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the CortexM3 MPU example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example presents the MPU features on STM32F2xx devices and it can be easily +ported to any other STM32 device supporting MPU. + +The example purpose is to configure a memory region as privileged read only region +and tries to perform read and write operation in different mode. + +If the access is permitted LED1 is toggling. If the access is not permitted, +a memory management fault is generated and LED2 is ON. +To generate an MPU memory fault exception due to an access right error, uncomment +the following line "PrivilegedReadOnlyArray[0] = 'e';" in the "stm32_mpu.c" file. + + +@par Directory contents + + - CortexM3/MPU/stm32f2xx_conf.h Library Configuration file + - CortexM3/MPU/stm32f2xx_it.c Interrupt handlers + - CortexM3/MPU/stm32f2xx_it.h Header for stm32f2xx_it.c + - CortexM3/MPU/main.c Main program + - CortexM3/MPU/system_stm32f2xx.c STM32F2xx system source file + - CortexM3/MPU/stm32_mpu.c Cortex-M3 MPU regions Access rights file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain and setup your project configuration as follows + - Add the required example files + - stm32_mpu.c +
    +- For RIDE and TrueSTUDIO toolchains you have to follow these instructions + +
  • RIDE + - In the Application options -> script menu, set "Use Default Script File" + to "No" and use "stm32F_flash_ROAarray.ld" as Script File. + This linker is configured for STM32F2xx. It should be updated to use it + with other STM32 devices. + + +
  • TrueSTUDIO + - In the project properties window, select C/C++ Build->settings node then + the C Linker->General node and use "stm32F_flash_ROAarray.ld" as Script File. + This linker is configured for STM32F2xx. It should be updated to use it + with other STM32 devices. +
+ + - Rebuild all files and load your image into target memory + - Run the example + + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32_mpu.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32_mpu.c new file mode 100644 index 000000000..c1ca0fac2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32_mpu.c @@ -0,0 +1,126 @@ +/** + ****************************************************************************** + * @file CortexM3/MPU/stm32_mpu.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Access rights configuration using Cortex-M3 MPU regions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_mpu.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CortexM3_MPU + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define ARRAY_ADDRESS_START (0x20002000UL) +#define ARRAY_SIZE (0x09UL << 0UL) +#define ARRAY_REGION_NUMBER (0x03UL << MPU_RNR_REGION_Pos) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +#if defined ( __CC_ARM ) + uint8_t PrivilegedReadOnlyArray[32] __attribute__((at(0x20002000))); + +#elif defined ( __ICCARM__ ) + #pragma location=0x20002000 + __no_init uint8_t PrivilegedReadOnlyArray[32]; + +#elif defined ( __GNUC__ ) + uint8_t PrivilegedReadOnlyArray[32] __attribute__((section(".ROarraySection"))); + +#elif defined ( __TASKING__ ) + uint8_t PrivilegedReadOnlyArray[32] __at(0x20002000); +#endif + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Configures the main MPU regions. + * @param None + * @retval None + */ +void MPU_Config(void) +{ + /* Disable MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Configure RAM region as Region N°0, 8kB of size and R/W region */ + MPU->RNR = RAM_REGION_NUMBER; + MPU->RBAR = RAM_ADDRESS_START; + MPU->RASR = RAM_SIZE | portMPU_REGION_READ_WRITE; + + /* Configure FLASH region as REGION N°1, 1MB of size and R/W region */ + MPU->RNR = FLASH_REGION_NUMBER; + MPU->RBAR = FLASH_ADDRESS_START; + MPU->RASR = FLASH_SIZE | portMPU_REGION_READ_WRITE; + + /* Configure Peripheral region as REGION N°2, 0.5GB of size, R/W and Execute + Never region */ + MPU->RNR = PERIPH_REGION_NUMBER; + MPU->RBAR = PERIPH_ADDRESS_START; + MPU->RASR = PERIPH_SIZE |portMPU_REGION_READ_WRITE | MPU_RASR_XN_Msk; + + /* Enable the memory fault exception */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Enable MPU */ + MPU->CTRL |= MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk; +} + +/** + * @brief This function configure the access right using Cortex-M3 MPU regions. + * @param None + * @retval None + */ +void MPU_AccessPermConfig(void) +{ + /* Configure region for PrivilegedReadOnlyArray as REGION N°3, 32byte and R + only in privileged mode */ + MPU->RNR = ARRAY_REGION_NUMBER; + MPU->RBAR |= ARRAY_ADDRESS_START; + MPU->RASR |= ARRAY_SIZE | portMPU_REGION_PRIVILEGED_READ_ONLY; + + /* Read from PrivilegedReadOnlyArray. This will not generate error */ + (void)PrivilegedReadOnlyArray[0]; + + /* Uncomment the following line to write to PrivilegedReadOnlyArray. This will + generate error */ + //PrivilegedReadOnlyArray[0] = 'e'; +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32_mpu.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32_mpu.h new file mode 100644 index 000000000..84fe584c2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32_mpu.h @@ -0,0 +1,63 @@ +/** + ****************************************************************************** + * @file CortexM3/MPU/stm32_mpu.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for stm32_mpu.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_MPU_H +#define __STM32_MPU_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define MPU_RASR_XN_Pos 28 +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) +#define MPU_RASR_AP_Pos 24 +#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) +#define RAM_ADDRESS_START (0x20000000UL) +#define RAM_SIZE (0x19UL << 0UL) +#define PERIPH_ADDRESS_START (0x40000000) +#define PERIPH_SIZE (0x39UL << 0UL) +#define FLASH_ADDRESS_START (0x08000000) +#define FLASH_SIZE (0x27UL << 0UL) +#define portMPU_REGION_READ_WRITE (0x03UL << MPU_RASR_AP_Pos) +#define portMPU_REGION_PRIVILEGED_READ_ONLY (0x05UL << MPU_RASR_AP_Pos) +#define portMPU_REGION_READ_ONLY (0x06UL << MPU_RASR_AP_Pos) +#define portMPU_REGION_PRIVILEGED_READ_WRITE (0x01UL << MPU_RASR_AP_Pos) +#define RAM_REGION_NUMBER (0x00UL << MPU_RNR_REGION_Pos) +#define FLASH_REGION_NUMBER (0x01UL << MPU_RNR_REGION_Pos) +#define PERIPH_REGION_NUMBER (0x02UL << MPU_RNR_REGION_Pos) + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void MPU_Config(void); +void MPU_AccessPermConfig(void); + +#endif /* __STM32_MPU_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32f2xx_conf.h new file mode 100644 index 000000000..3eab2418c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file CortexM3/MPU/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32f2xx_it.c new file mode 100644 index 000000000..5b3136bbc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32f2xx_it.c @@ -0,0 +1,177 @@ +/** + ****************************************************************************** + * @file CortexM3/MPU/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CortexM3_MPU + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Turn on LED2 */ + STM_EVAL_LEDOn(LED2); + + /* Go to infinite loop */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32f2xx_it.h new file mode 100644 index 000000000..04cbc10a2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file CortexM3/MPU/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/MPU/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c new file mode 100644 index 000000000..9558c3523 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/main.c @@ -0,0 +1,186 @@ +/** + ****************************************************************************** + * @file CortexM3/Mode_Privilege/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CortexM3_Mode_Privilege + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SP_PROCESS_SIZE 0x200 /* Process stack size */ +#define SP_PROCESS 0x02 /* Process stack */ +#define SP_MAIN 0x00 /* Main stack */ +#define THREAD_MODE_PRIVILEGED 0x00 /* Thread mode has privileged access */ +#define THREAD_MODE_UNPRIVILEGED 0x01 /* Thread mode has unprivileged access */ + +/* Private macro -------------------------------------------------------------*/ +#if defined ( __CC_ARM ) + __ASM void __SVC(void) + { + SVC 0x01 + BX R14 + } +#elif defined ( __ICCARM__ ) + static __INLINE void __SVC() { __ASM ("svc 0x01");} +#elif defined ( __GNUC__ ) + static __INLINE void __SVC() { __ASM volatile ("svc 0x01");} + #elif defined ( __TASKING__ ) + static __INLINE void __SVC() { __ASM ("svc 0x01");} +#endif + +/* Private variables ---------------------------------------------------------*/ +__IO uint8_t PSPMemAlloc[SP_PROCESS_SIZE]; +__IO uint32_t Index = 0, PSPValue = 0, CurrentStack = 0, ThreadMode = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + +/* Switch Thread mode Stack from Main to Process -----------------------------*/ + /* Initialize memory reserved for Process Stack */ + for(Index = 0; Index < SP_PROCESS_SIZE; Index++) + { + PSPMemAlloc[Index] = 0x00; + } + + /* Set Process stack value */ + __set_PSP((uint32_t)PSPMemAlloc + SP_PROCESS_SIZE); + + /* Select Process Stack as Thread mode Stack */ + __set_CONTROL(SP_PROCESS); + + /* Get the Thread mode stack used */ + if((__get_CONTROL() & 0x02) == SP_MAIN) + { + /* Main stack is used as the current stack */ + CurrentStack = SP_MAIN; + } + else + { + /* Process stack is used as the current stack */ + CurrentStack = SP_PROCESS; + + /* Get process stack pointer value */ + PSPValue = __get_PSP(); + } + +/* Switch Thread mode from privileged to unprivileged ------------------------*/ + /* Thread mode has unprivileged access */ + __set_CONTROL(THREAD_MODE_UNPRIVILEGED | SP_PROCESS); + + /* Unprivileged access mainly affect ability to: + - Use or not use certain instructions such as MSR fields + - Access System Control Space (SCS) registers such as NVIC and SysTick */ + + /* Check Thread mode privilege status */ + if((__get_CONTROL() & 0x01) == THREAD_MODE_PRIVILEGED) + { + /* Thread mode has privileged access */ + ThreadMode = THREAD_MODE_PRIVILEGED; + } + else + { + /* Thread mode has unprivileged access*/ + ThreadMode = THREAD_MODE_UNPRIVILEGED; + } + +/* Switch back Thread mode from unprivileged to privileged -------------------*/ + /* Try to switch back Thread mode to privileged (Not possible, this can be + done only in Handler mode) */ + __set_CONTROL(THREAD_MODE_PRIVILEGED | SP_PROCESS); + + /* Generate a system call exception, and in the ISR switch back Thread mode + to privileged */ + __SVC(); + + /* Check Thread mode privilege status */ + if((__get_CONTROL() & 0x01) == THREAD_MODE_PRIVILEGED) + { + /* Thread mode has privileged access */ + ThreadMode = THREAD_MODE_PRIVILEGED; + } + else + { + /* Thread mode has unprivileged access*/ + ThreadMode = THREAD_MODE_UNPRIVILEGED; + } + + while (1) + { + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/readme.txt new file mode 100644 index 000000000..1a26d85e4 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/readme.txt @@ -0,0 +1,83 @@ +/** + @page CortexM3_Mode_Privilege CortexM3 Mode Privilege example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file CortexM3/Mode_Privilege/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the CortexM3 Mode Privilege example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to modify CortexM3 Thread mode privilege access and stack. +CortexM3 Thread mode is entered on Reset, and can be entered as a result of an +exception return. + +The associated program is used to: + +1. Switch the Thread mode stack from Main stack to Process stack + +2. Switch the Thread mode from Privileged to Unprivileged + +3. Switch the Thread mode from Unprivileged back to Privileged + +To monitor the stack used and the privileged or unprivileged access level of code +in Thread mode, a set of variables is available within the program. It is also +possible to use the 'Cortex register' window of the debugger. + + +@par Directory contents + + - CortexM3/Mode_Privilege/stm32f2xx_conf.h Library Configuration file + - CortexM3/Mode_Privilege/stm32f2xx_it.c Interrupt handlers + - CortexM3/Mode_Privilege/stm32f2xx_it.h Interrupt handlers header file + - CortexM3/Mode_Privilege/main.c Main program + - CortexM3/Mode_Privilege/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f2xx_conf.h new file mode 100644 index 000000000..8ded0ca86 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file CortexM3/Mode_Privilege/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f2xx_it.c new file mode 100644 index 000000000..45384362d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f2xx_it.c @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file CortexM3/Mode_Privilege/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup CortexM3_Mode_Privilege + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ + /* Switch back Thread mode to privileged */ + __set_CONTROL(2); +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f2xx_it.h new file mode 100644 index 000000000..df13c530a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file CortexM3/Mode_Privilege/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/main.c new file mode 100644 index 000000000..ba60beef1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/main.c @@ -0,0 +1,341 @@ +/** + ****************************************************************************** + * @file DAC/DAC_SignalsGeneration/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DAC_SignalsGeneration + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define DAC_DHR12R2_ADDRESS 0x40007414 +#define DAC_DHR8R1_ADDRESS 0x40007410 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +DAC_InitTypeDef DAC_InitStructure; + +const uint16_t Sine12bit[32] = { + 2047, 2447, 2831, 3185, 3498, 3750, 3939, 4056, 4095, 4056, + 3939, 3750, 3495, 3185, 2831, 2447, 2047, 1647, 1263, 909, + 599, 344, 155, 38, 0, 38, 155, 344, 599, 909, 1263, 1647}; +const uint8_t Escalator8bit[6] = {0x0, 0x33, 0x66, 0x99, 0xCC, 0xFF}; + +__IO uint8_t SelectedWavesForm = 1; +__IO uint8_t KeyPressed = SET; + +/* Private function prototypes -----------------------------------------------*/ +void TIM6_Config(void); + +void DAC_Ch1_EscalatorConfig(void); +void DAC_Ch2_SineWaveConfig(void); + +void DAC_Ch1_NoiseConfig(void); +void DAC_Ch2_TriangleConfig(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Preconfiguration before using DAC----------------------------------------*/ + GPIO_InitTypeDef GPIO_InitStructure; + + /* DMA1 clock and GPIOA clock enable (to be used with DAC) */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1 | RCC_AHB1Periph_GPIOA, ENABLE); + + /* DAC Periph clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE); + + /* DAC channel 1 & 2 (DAC_OUT1 = PA.4)(DAC_OUT2 = PA.5) configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* TIM6 Configuration ------------------------------------------------------*/ + TIM6_Config(); + + /* Configures Key Button */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI); + + while (1) + { + /* If the Key is pressed */ + if (KeyPressed != RESET) + { + DAC_DeInit(); + + /* select waves forms according to the Key Button status */ + if (SelectedWavesForm == 1) + { + /* The sine wave and the escalator wave has been selected */ + + /* Escalator Wave generator ------------------------------------------*/ + DAC_Ch1_EscalatorConfig(); + + /* Sine Wave generator -----------------------------------------------*/ + DAC_Ch2_SineWaveConfig(); + + } + else + { + /* The triangle wave and the noise wave has been selected */ + + /* Noise Wave generator ----------------------------------------------*/ + DAC_Ch1_NoiseConfig(); + + /* Triangle Wave generator -------------------------------------------*/ + DAC_Ch2_TriangleConfig(); + } + + KeyPressed = RESET; + } + } +} + +/** + * @brief TIM6 Configuration + * @note TIM6 configuration is based on APB1 frequency + * @note TIM6 Update event occurs each TIM6CLK/256 + * @param None + * @retval None + */ +void TIM6_Config(void) +{ + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + /* TIM6 Periph clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE); + + /* -------------------------------------------------------- + TIM3 input clock (TIM6CLK) is set to 2 * APB1 clock (PCLK1), + since APB1 prescaler is different from 1. + TIM6CLK = 2 * PCLK1 + TIM6CLK = HCLK / 2 = SystemCoreClock /2 + + TIM6 Update event occurs each TIM6CLK/256 + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + + ----------------------------------------------------------- */ + /* Time base configuration */ + TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); + TIM_TimeBaseStructure.TIM_Period = 0xFF; + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit(TIM6, &TIM_TimeBaseStructure); + + /* TIM6 TRGO selection */ + TIM_SelectOutputTrigger(TIM6, TIM_TRGOSource_Update); + + /* TIM6 enable counter */ + TIM_Cmd(TIM6, ENABLE); +} + +/** + * @brief DAC Channel2 SineWave Configuration + * @param None + * @retval None + */ +void DAC_Ch2_SineWaveConfig(void) +{ + DMA_InitTypeDef DMA_InitStructure; + + /* DAC channel2 Configuration */ + DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO; + DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None; + DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + DAC_Init(DAC_Channel_2, &DAC_InitStructure); + + /* DMA1_Stream6 channel7 configuration **************************************/ + DMA_DeInit(DMA1_Stream6); + DMA_InitStructure.DMA_Channel = DMA_Channel_7; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)DAC_DHR12R2_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&Sine12bit; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_BufferSize = 32; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(DMA1_Stream6, &DMA_InitStructure); + + /* Enable DMA1_Stream6 */ + DMA_Cmd(DMA1_Stream6, ENABLE); + + /* Enable DAC Channel2 */ + DAC_Cmd(DAC_Channel_2, ENABLE); + + /* Enable DMA for DAC Channel2 */ + DAC_DMACmd(DAC_Channel_2, ENABLE); +} + +/** + * @brief DAC Channel1 Escalator Configuration + * @param None + * @retval None + */ +void DAC_Ch1_EscalatorConfig(void) +{ + DMA_InitTypeDef DMA_InitStructure; + + /* DAC channel1 Configuration */ + DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO; + DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None; + DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + DAC_Init(DAC_Channel_1, &DAC_InitStructure); + + /* DMA1_Stream5 channel7 configuration **************************************/ + DMA_DeInit(DMA1_Stream5); + DMA_InitStructure.DMA_Channel = DMA_Channel_7; + DMA_InitStructure.DMA_PeripheralBaseAddr = DAC_DHR8R1_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&Escalator8bit; + DMA_InitStructure.DMA_BufferSize = 6; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(DMA1_Stream5, &DMA_InitStructure); + + /* Enable DMA1_Stream5 */ + DMA_Cmd(DMA1_Stream5, ENABLE); + + /* Enable DAC Channel1 */ + DAC_Cmd(DAC_Channel_1, ENABLE); + + /* Enable DMA for DAC Channel1 */ + DAC_DMACmd(DAC_Channel_1, ENABLE); +} + +/** + * @brief DAC Channel2 Triangle Configuration + * @param None + * @retval None + */ +void DAC_Ch2_TriangleConfig(void) +{ + /* DAC channel2 Configuration */ + DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO; + DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_Triangle; + DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1023; + DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + DAC_Init(DAC_Channel_2, &DAC_InitStructure); + + /* Enable DAC Channel2 */ + DAC_Cmd(DAC_Channel_2, ENABLE); + + /* Set DAC channel2 DHR12RD register */ + DAC_SetChannel2Data(DAC_Align_12b_R, 0x100); +} + +/** + * @brief DAC Channel1 Noise Configuration + * @param None + * @retval None + */ +void DAC_Ch1_NoiseConfig(void) +{ + /* DAC channel1 Configuration */ + DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO; + DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_Noise; + DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bits10_0; + DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + DAC_Init(DAC_Channel_1, &DAC_InitStructure); + + /* Enable DAC Channel1 */ + DAC_Cmd(DAC_Channel_1, ENABLE); + + /* Set DAC Channel1 DHR12L register */ + DAC_SetChannel1Data(DAC_Align_12b_L, 0x7FF0); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/readme.txt new file mode 100644 index 000000000..e722722aa --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/readme.txt @@ -0,0 +1,80 @@ +/** + @page DAC_SignalsGen DAC Signals generation example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file DAC/DAC_SignalsGeneration/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the DAC Signals generation example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the DAC peripheral to +generate several signals using DMA controller. +When the user presses the KEY push-button, DMA transfers the two selected +waveforms to the DAC. +For each press on KEY button, 2 signals has been selected and can be monitored on +the two DAC channels: + - Escalator waveform (Channel 1) and Sine waveForm (Channel 2). + - Noise waveform (Channel 1) and Triangle waveform (Channel 2). + + +@par Directory contents + + - DAC/DAC_SignalsGeneration/stm32f2xx_conf.h Library Configuration file + - DAC/DAC_SignalsGeneration/stm32f2xx_it.c Interrupt handlers + - DAC/DAC_SignalsGeneration/stm32f2xx_it.h Interrupt handlers header file + - DAC/DAC_SignalsGeneration/main.c Main program + - DAC/DAC_SignalsGeneration/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use KEY push-button connected to PG15. + - Connect PA4 (DAC Channel1) and PA5 (DAC Channel2) pins to an oscilloscope. + - Make sure that JP31 is removed. + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/stm32f2xx_conf.h new file mode 100644 index 000000000..742c07736 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file DAC/OneChannelDMA_SineWave/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/stm32f2xx_it.c new file mode 100644 index 000000000..76ca5bd62 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/stm32f2xx_it.c @@ -0,0 +1,191 @@ +/** + ****************************************************************************** + * @file DAC/DAC_SignalsGeneration/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ +/** @addtogroup DAC_SignalsGeneration + * @{ + */ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern __IO uint8_t SelectedWavesForm, KeyPressed; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ +/** + * @brief This function handles External line 15 interrupt request. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET) + { + /* Change the wave */ + KeyPressed = 1; + + /* Change the selected waves forms */ + SelectedWavesForm = !SelectedWavesForm; + + /* Clear the Right Button EXTI line pending bit */ + EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); + } +} +/** + * @} + */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/stm32f2xx_it.h new file mode 100644 index 000000000..03cc8bff5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/stm32f2xx_it.h @@ -0,0 +1,61 @@ +/** + ****************************************************************************** + * @file DAC/DAC_SignalsGeneration/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void EXTI15_10_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DAC/DAC_SignalsGeneration/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/camera_api.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/camera_api.c new file mode 100644 index 000000000..36e9f5691 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/camera_api.c @@ -0,0 +1,355 @@ +/** + ****************************************************************************** + * @file DCMI/Camera/camera_api.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the routinue needed to configure OV9655/OV2640 + * Camera modules. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "camera_api.h" +#include "dcmi_ov9655.h" +#include "dcmi_ov2640.h" + +/** @addtogroup stm32f2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DCMI_Camera + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Image Formats */ +const uint8_t *ImageForematArray[] = +{ + "BMP QQVGA Format ", + "BMP QVGA Format ", +}; +static __IO uint32_t TimingDelay; +__IO uint32_t PressedKey = 0; +uint8_t ValueMin = 0, ValueMax = 0; +Camera_TypeDef Camera; +ImageFormat_TypeDef ImageFormat; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Initialize resources used for this demo. + * @param None + * @retval Digit value + */ +uint8_t Demo_Init(void) +{ + __IO uint32_t tmpValue = 0; + PressedKey = NOKEY; + + /* Configure the IO Expander */ + if(IOE_Config() == IOE_OK) + { + LCD_DisplayStringLine(LINE(6), (uint8_t*)"IO Expander OK "); + Delay(0xFF); + } + else + { + LCD_SetTextColor(LCD_COLOR_RED); + LCD_DisplayStringLine(LINE(6), (uint8_t*)"IO Expander FAILED Please Reset the board"); + while (1); + } + + /* Enable the Joystick interrupt */ + IOE_ITConfig(IOE_ITSRC_JOYSTICK); + + Demo_LCD_Clear(); + LCD_DisplayStringLine(LINE(6), (uint8_t*)"Main Menu: "); + LCD_DisplayStringLine(LINE(7), (uint8_t*)"=========="); + LCD_DisplayStringLine(LINE(8), (uint8_t*)"Use UP and DOWN Buttons to Navigate"); + LCD_DisplayStringLine(LINE(9), (uint8_t*)"Use SEL Button to Select Image Format"); + + LCD_DisplayStringLine(LINE(11), (uint8_t*)"Select the Image Format:"); + Display_Menu(ValueMin, ValueMax); + + while (1) + { + /* If "UP" pushbutton is pressed */ + if (PressedKey == UP) + { + PressedKey = NOKEY; + + /* Increase the value of the digit */ + if (tmpValue == ValueMin) + { + tmpValue = ValueMax - 1; + } + else + { + tmpValue--; + } + /* Display new Menu */ + Display_Menu(tmpValue, ValueMax); + } + /* If "DOWN" pushbutton is pressed */ + if (PressedKey == DOWN) + { + PressedKey = NOKEY; + + /* Decrease the value of the digit */ + if (tmpValue == (ValueMax - 1)) + { + tmpValue = ValueMin; + } + else + { + tmpValue++; + } + /* Display new Menu */ + Display_Menu(tmpValue, ValueMax); + } + /* If "SEL" pushbutton is pressed */ + if (PressedKey == SEL) + { + PressedKey = NOKEY; + + /* Return the digit value and exit */ + return (ImageFormat_TypeDef)tmpValue; + } + } +} + +/** + * @brief Display the navigation menu. + * @param None + * @retval None + */ +void Display_Menu(uint8_t ForematIndex, uint8_t MaxForematIndex) +{ + uint32_t index; + + for(index=0; index
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CAMERA_API_H +#define __CAMERA_API_H + +/* Includes ------------------------------------------------------------------*/ +#include "lcd_log.h" +#include "main.h" + +/* Exported constants --------------------------------------------------------*/ +#define DCMI_DR_ADDRESS 0x50050028 +#define FSMC_LCD_ADDRESS 0x68000002 +#define NOKEY 0 +#define SEL 1 +#define UP 2 +#define DOWN 3 + +/* Exported types ------------------------------------------------------------*/ +/* Camera devices enumeration */ +typedef enum +{ + OV9655_CAMERA = 0x00, /* Use OV9655 Camera */ + OV2640_CAMERA = 0x01 /* Use OV2640 Camera */ +}Camera_TypeDef; + +/* Image Sizes enumeration */ +typedef enum +{ + BMP_QQVGA = 0x00, /* BMP Image QQVGA 160x120 Size */ + BMP_QVGA = 0x01, /* BMP Image QVGA 320x240 Size */ + JPEG_160x120 = 0x02, /* JPEG Image 160x120 Size */ + JPEG_176x144 = 0x03, /* JPEG Image 176x144 Size */ + JPEG_320x240 = 0x04, /* JPEG Image 320x240 Size */ + JPEG_352x288 = 0x05 /* JPEG Image 352x288 Size */ +}ImageFormat_TypeDef; + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +uint8_t Demo_Init(void); +void Display_Menu(uint8_t ForematIndex, uint8_t MaxForematIndex); +void Camera_Config(void); +void OV2640_SpecialEffects(uint8_t index); +void Delay(uint32_t nTime); +void TimingDelay_Decrement(void); +void Demo_LCD_Clear(void); + +#endif /* __CAMERA_API_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov2640.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov2640.c new file mode 100644 index 000000000..fbe3195a5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov2640.c @@ -0,0 +1,1563 @@ +/** + ****************************************************************************** + * @file DCMI/Camera/dcmi_ov2640.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file includes the driver for OV2640 Camera module mounted on + * STM322xG-EVAL board RevB. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "camera_api.h" +#include "dcmi_ov2640.h" + +/** @addtogroup stm32f2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DCMI_Camera + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TIMEOUT 2 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* QQVGA 160x120 */ +const char OV2640_QQVGA[][2]= +{ + 0xff, 0x00, + 0x2c, 0xff, + 0x2e, 0xdf, + 0xff, 0x01, + 0x3c, 0x32, + 0x11, 0x00, + 0x09, 0x02, + 0x03, 0xcf, + 0x04, 0x08, + 0x13, 0xe5, + 0x14, 0x48, + 0x2c, 0x0c, + 0x33, 0x78, + 0x3a, 0x33, + 0x3b, 0xfb, + 0x3e, 0x00, + 0x43, 0x11, + 0x16, 0x10, + 0x39, 0x02, + 0x35, 0x88, + 0x22, 0x0a, + 0x37, 0x40, + 0x23, 0x00, + 0x34, 0xa0, + 0x36, 0x1a, + 0x06, 0x02, + 0x07, 0xc0, + 0x0d, 0xb7, + 0x0e, 0x01, + 0x4c, 0x00, + 0x4a, 0x81, + 0x21, 0x99, + 0x24, 0x3a, + 0x25, 0x32, + 0x26, 0x82, + 0x5c, 0x00, + 0x63, 0x00, + 0x5d, 0x55, + 0x5e, 0x7d, + 0x5f, 0x7d, + 0x60, 0x55, + 0x61, 0x70, + 0x62, 0x80, + 0x7c, 0x05, + 0x20, 0x80, + 0x28, 0x30, + 0x6c, 0x00, + 0x6d, 0x80, + 0x6e, 0x00, + 0x70, 0x02, + 0x71, 0x96, + 0x73, 0xe1, + 0x3d, 0x34, + 0x5a, 0x57, + 0x4f, 0xbb, + 0x50, 0x9c, + 0x0f, 0x43, + 0xff, 0x00, + 0xe5, 0x7f, + 0xf9, 0xc0, + 0x41, 0x24, + 0xe0, 0x14, + 0x76, 0xff, + 0x33, 0xa0, + 0x42, 0x20, + 0x43, 0x18, + 0x4c, 0x00, + 0x87, 0xd0, + 0x88, 0x3f, + 0xd7, 0x03, + 0xd9, 0x10, + 0xd3, 0x82, + 0xc8, 0x08, + 0xc9, 0x80, + 0x7c, 0x00, + 0x7d, 0x02, + 0x7c, 0x03, + 0x7d, 0x48, + 0x7d, 0x48, + 0x7c, 0x08, + 0x7d, 0x20, + 0x7d, 0x10, + 0x7d, 0x0e, + 0x90, 0x00, + 0x91, 0x0e, + 0x91, 0x1a, + 0x91, 0x31, + 0x91, 0x5a, + 0x91, 0x69, + 0x91, 0x75, + 0x91, 0x7e, + 0x91, 0x88, + 0x91, 0x8f, + 0x91, 0x96, + 0x91, 0xa3, + 0x91, 0xaf, + 0x91, 0xc4, + 0x91, 0xd7, + 0x91, 0xe8, + 0x91, 0x20, + 0x92, 0x00, + 0x93, 0x06, + 0x93, 0xe3, + 0x93, 0x05, + 0x93, 0x05, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x96, 0x00, + 0x97, 0x08, + 0x97, 0x19, + 0x97, 0x02, + 0x97, 0x0c, + 0x97, 0x24, + 0x97, 0x30, + 0x97, 0x28, + 0x97, 0x26, + 0x97, 0x02, + 0x97, 0x98, + 0x97, 0x80, + 0x97, 0x00, + 0x97, 0x00, + 0xc3, 0xed, + 0xa4, 0x00, + 0xa8, 0x00, + 0xbf, 0x00, + 0xba, 0xf0, + 0xbc, 0x64, + 0xbb, 0x02, + 0xb6, 0x3d, + 0xb8, 0x57, + 0xb7, 0x38, + 0xb9, 0x4e, + 0xb3, 0xe8, + 0xb4, 0xe1, + 0xb5, 0x66, + 0xb0, 0x67, + 0xb1, 0x5e, + 0xb2, 0x04, + 0xc7, 0x00, + 0xc6, 0x51, + 0xc5, 0x11, + 0xc4, 0x9c, + 0xcf, 0x02, + 0xa6, 0x00, + 0xa7, 0xe0, + 0xa7, 0x10, + 0xa7, 0x1e, + 0xa7, 0x21, + 0xa7, 0x00, + 0xa7, 0x28, + 0xa7, 0xd0, + 0xa7, 0x10, + 0xa7, 0x16, + 0xa7, 0x21, + 0xa7, 0x00, + 0xa7, 0x28, + 0xa7, 0xd0, + 0xa7, 0x10, + 0xa7, 0x17, + 0xa7, 0x21, + 0xa7, 0x00, + 0xa7, 0x28, + 0xc0, 0xc8, + 0xc1, 0x96, + 0x86, 0x1d, + 0x50, 0x00, + 0x51, 0x90, + 0x52, 0x18, + 0x53, 0x00, + 0x54, 0x00, + 0x55, 0x88, + 0x57, 0x00, + 0x5a, 0x90, + 0x5b, 0x18, + 0x5c, 0x05, + 0xc3, 0xef, + 0x7f, 0x00, + 0xda, 0x00, + 0xe5, 0x1f, + 0xe1, 0x67, + 0xe0, 0x00, + 0xdd, 0xff, + 0x05, 0x00, + 0xff, 0x01, + 0xff, 0x01, + 0x12, 0x00, + 0x17, 0x11, + 0x18, 0x75, + 0x19, 0x01, + 0x1a, 0x97, + 0x32, 0x36, + 0x4f, 0xbb, + 0x6d, 0x80, + 0x3d, 0x34, + 0x39, 0x02, + 0x35, 0x88, + 0x22, 0x0a, + 0x37, 0x40, + 0x23, 0x00, + 0x34, 0xa0, + 0x36, 0x1a, + 0x06, 0x02, + 0x07, 0xc0, + 0x0d, 0xb7, + 0x0e, 0x01, + 0x4c, 0x00, + 0xff, 0x00, + 0xe0, 0x04, + 0x8c, 0x00, + 0x87, 0xd0, + 0xe0, 0x00, + 0xff, 0x00, + 0xe0, 0x14, + 0xe1, 0x77, + 0xe5, 0x1f, + 0xd7, 0x03, + 0xda, 0x10, + 0xe0, 0x00, + 0xff, 0x00, + 0xe0, 0x04, + 0xc0, 0xc8, + 0xc1, 0x96, + 0x86, 0x1d, + 0x50, 0x00, + 0x51, 0x90, + 0x52, 0x2c, + 0x53, 0x00, + 0x54, 0x00, + 0x55, 0x88, + 0x57, 0x00, + 0x5a, 0x90, + 0x5b, 0x2c, + 0x5c, 0x05, + 0xe0, 0x00, + 0xd3, 0x04, + 0xff, 0x00, + 0xc3, 0xef, + 0xa6, 0x00, + 0xa7, 0xdd, + 0xa7, 0x78, + 0xa7, 0x7e, + 0xa7, 0x24, + 0xa7, 0x00, + 0xa7, 0x25, + 0xa6, 0x06, + 0xa7, 0x20, + 0xa7, 0x58, + 0xa7, 0x73, + 0xa7, 0x34, + 0xa7, 0x00, + 0xa7, 0x25, + 0xa6, 0x0c, + 0xa7, 0x28, + 0xa7, 0x58, + 0xa7, 0x6d, + 0xa7, 0x34, + 0xa7, 0x00, + 0xa7, 0x25, + 0xff, 0x00, + 0xe0, 0x04, + 0xe1, 0x67, + 0xe5, 0x1f, + 0xd7, 0x01, + 0xda, 0x08, + 0xda, 0x09, + 0xe0, 0x00, + 0x98, 0x00, + 0x99, 0x00, + 0xff, 0x01, + 0x04, 0x28, + 0xff, 0x01, + 0x12, 0x40, + 0x17, 0x11, + 0x18, 0x43, + 0x19, 0x00, + 0x1a, 0x4b, + 0x32, 0x09, + 0x4f, 0xca, + 0x50, 0xa8, + 0x5a, 0x23, + 0x6d, 0x00, + 0x39, 0x12, + 0x35, 0xda, + 0x22, 0x1a, + 0x37, 0xc3, + 0x23, 0x00, + 0x34, 0xc0, + 0x36, 0x1a, + 0x06, 0x88, + 0x07, 0xc0, + 0x0d, 0x87, + 0x0e, 0x41, + 0x4c, 0x00, + 0xff, 0x00, + 0xe0, 0x04, + 0xc0, 0x64, + 0xc1, 0x4b, + 0x86, 0x35, + 0x50, 0x92, + 0x51, 0xc8, + 0x52, 0x96, + 0x53, 0x00, + 0x54, 0x00, + 0x55, 0x00, + 0x57, 0x00, + 0x5a, 0x28, + 0x5b, 0x1e, + 0x5c, 0x00, + 0xe0, 0x00, + 0xff, 0x01, + 0x11, 0x00, + 0x3d, 0x38, + 0x2d, 0x00, + 0x50, 0x65, + 0xff, 0x00, + 0xd3, 0x04, + 0x7c, 0x00, + 0x7d, 0x04, + 0x7c, 0x09, + 0x7d, 0x28, + 0x7d, 0x00, +}; + +/* QVGA 320x240 */ +const unsigned char OV2640_QVGA[][2]= +{ + 0xff, 0x00, + 0x2c, 0xff, + 0x2e, 0xdf, + 0xff, 0x01, + 0x3c, 0x32, + 0x11, 0x00, + 0x09, 0x02, + 0x04, 0x28, + 0x13, 0xe5, + 0x14, 0x48, + 0x2c, 0x0c, + 0x33, 0x78, + 0x3a, 0x33, + 0x3b, 0xfB, + 0x3e, 0x00, + 0x43, 0x11, + 0x16, 0x10, + 0x4a, 0x81, + 0x21, 0x99, + 0x24, 0x40, + 0x25, 0x38, + 0x26, 0x82, + 0x5c, 0x00, + 0x63, 0x00, + 0x46, 0x3f, + 0x0c, 0x3c, + 0x61, 0x70, + 0x62, 0x80, + 0x7c, 0x05, + 0x20, 0x80, + 0x28, 0x30, + 0x6c, 0x00, + 0x6d, 0x80, + 0x6e, 0x00, + 0x70, 0x02, + 0x71, 0x94, + 0x73, 0xc1, + 0x3d, 0x34, + 0x5a, 0x57, + 0x12, 0x00, + 0x11, 0x00, + 0x17, 0x11, + 0x18, 0x75, + 0x19, 0x01, + 0x1a, 0x97, + 0x32, 0x36, + 0x03, 0x0f, + 0x37, 0x40, + 0x4f, 0xbb, + 0x50, 0x9c, + 0x5a, 0x57, + 0x6d, 0x80, + 0x6d, 0x38, + 0x39, 0x02, + 0x35, 0x88, + 0x22, 0x0a, + 0x37, 0x40, + 0x23, 0x00, + 0x34, 0xa0, + 0x36, 0x1a, + 0x06, 0x02, + 0x07, 0xc0, + 0x0d, 0xb7, + 0x0e, 0x01, + 0x4c, 0x00, + 0xff, 0x00, + 0xe5, 0x7f, + 0xf9, 0xc0, + 0x41, 0x24, + 0xe0, 0x14, + 0x76, 0xff, + 0x33, 0xa0, + 0x42, 0x20, + 0x43, 0x18, + 0x4c, 0x00, + 0x87, 0xd0, + 0x88, 0x3f, + 0xd7, 0x03, + 0xd9, 0x10, + 0xd3, 0x82, + 0xc8, 0x08, + 0xc9, 0x80, + 0x7d, 0x00, + 0x7c, 0x03, + 0x7d, 0x48, + 0x7c, 0x08, + 0x7d, 0x20, + 0x7d, 0x10, + 0x7d, 0x0e, + 0x90, 0x00, + 0x91, 0x0e, + 0x91, 0x1a, + 0x91, 0x31, + 0x91, 0x5a, + 0x91, 0x69, + 0x91, 0x75, + 0x91, 0x7e, + 0x91, 0x88, + 0x91, 0x8f, + 0x91, 0x96, + 0x91, 0xa3, + 0x91, 0xaf, + 0x91, 0xc4, + 0x91, 0xd7, + 0x91, 0xe8, + 0x91, 0x20, + 0x92, 0x00, + 0x93, 0x06, + 0x93, 0xe3, + 0x93, 0x02, + 0x93, 0x02, + 0x93, 0x00, + 0x93, 0x04, + 0x93, 0x00, + 0x93, 0x03, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x96, 0x00, + 0x97, 0x08, + 0x97, 0x19, + 0x97, 0x02, + 0x97, 0x0c, + 0x97, 0x24, + 0x97, 0x30, + 0x97, 0x28, + 0x97, 0x26, + 0x97, 0x02, + 0x97, 0x98, + 0x97, 0x80, + 0x97, 0x00, + 0x97, 0x00, + 0xc3, 0xef, + 0xff, 0x00, + 0xba, 0xdc, + 0xbb, 0x08, + 0xb6, 0x24, + 0xb8, 0x33, + 0xb7, 0x20, + 0xb9, 0x30, + 0xb3, 0xb4, + 0xb4, 0xca, + 0xb5, 0x43, + 0xb0, 0x5c, + 0xb1, 0x4f, + 0xb2, 0x06, + 0xc7, 0x00, + 0xc6, 0x51, + 0xc5, 0x11, + 0xc4, 0x9c, + 0xbf, 0x00, + 0xbc, 0x64, + 0xa6, 0x00, + 0xa7, 0x1e, + 0xa7, 0x6b, + 0xa7, 0x47, + 0xa7, 0x33, + 0xa7, 0x00, + 0xa7, 0x23, + 0xa7, 0x2e, + 0xa7, 0x85, + 0xa7, 0x42, + 0xa7, 0x33, + 0xa7, 0x00, + 0xa7, 0x23, + 0xa7, 0x1b, + 0xa7, 0x74, + 0xa7, 0x42, + 0xa7, 0x33, + 0xa7, 0x00, + 0xa7, 0x23, + 0xc0, 0xc8, + 0xc1, 0x96, + 0x8c, 0x00, + 0x86, 0x3d, + 0x50, 0x92, + 0x51, 0x90, + 0x52, 0x2c, + 0x53, 0x00, + 0x54, 0x00, + 0x55, 0x88, + 0x5a, 0x50, + 0x5b, 0x3c, + 0x5c, 0x00, + 0xd3, 0x04, + 0x7f, 0x00, + 0xda, 0x00, + 0xe5, 0x1f, + 0xe1, 0x67, + 0xe0, 0x00, + 0xdd, 0x7f, + 0x05, 0x00, + 0xff, 0x00, + 0xe0, 0x04, + 0xc0, 0xc8, + 0xc1, 0x96, + 0x86, 0x3d, + 0x50, 0x92, + 0x51, 0x90, + 0x52, 0x2c, + 0x53, 0x00, + 0x54, 0x00, + 0x55, 0x88, + 0x57, 0x00, + 0x5a, 0x50, + 0x5b, 0x3c, + 0x5c, 0x00, + 0xd3, 0x04, + 0xe0, 0x00, + 0xFF, 0x00, + 0x05, 0x00, + 0xDA, 0x08, + 0xda, 0x09, + 0x98, 0x00, + 0x99, 0x00, + 0x00, 0x00, +}; + +const unsigned char OV2640_JPEG_INIT[][2]= +{ + 0xff, 0x00, + 0x2c, 0xff, + 0x2e, 0xdf, + 0xff, 0x01, + 0x3c, 0x32, + 0x11, 0x30, + 0x09, 0x02, + 0x04, 0x28, + 0x13, 0xe5, + 0x14, 0x48, + 0x2c, 0x0c, + 0x33, 0x78, + 0x3a, 0x33, + 0x3b, 0xfB, + 0x3e, 0x00, + 0x43, 0x11, + 0x16, 0x10, + 0x39, 0x92, + 0x35, 0xda, + 0x22, 0x1a, + 0x37, 0xc3, + 0x23, 0x00, + 0x34, 0xc0, + 0x36, 0x1a, + 0x06, 0x88, + 0x07, 0xc0, + 0x0d, 0x87, + 0x0e, 0x41, + 0x4c, 0x00, + 0x48, 0x00, + 0x5B, 0x00, + 0x42, 0x03, + 0x4a, 0x81, + 0x21, 0x99, + 0x24, 0x40, + 0x25, 0x38, + 0x26, 0x82, + 0x5c, 0x00, + 0x63, 0x00, + 0x61, 0x70, + 0x62, 0x80, + 0x7c, 0x05, + 0x20, 0x80, + 0x28, 0x30, + 0x6c, 0x00, + 0x6d, 0x80, + 0x6e, 0x00, + 0x70, 0x02, + 0x71, 0x94, + 0x73, 0xc1, + 0x12, 0x40, + 0x17, 0x11, + 0x18, 0x43, + 0x19, 0x00, + 0x1a, 0x4b, + 0x32, 0x09, + 0x37, 0xc0, + 0x4f, 0x60, + 0x50, 0xa8, + 0x6d, 0x00, + 0x3d, 0x38, + 0x46, 0x3f, + 0x4f, 0x60, + 0x0c, 0x3c, + 0xff, 0x00, + 0xe5, 0x7f, + 0xf9, 0xc0, + 0x41, 0x24, + 0xe0, 0x14, + 0x76, 0xff, + 0x33, 0xa0, + 0x42, 0x20, + 0x43, 0x18, + 0x4c, 0x00, + 0x87, 0xd5, + 0x88, 0x3f, + 0xd7, 0x03, + 0xd9, 0x10, + 0xd3, 0x82, + 0xc8, 0x08, + 0xc9, 0x80, + 0x7c, 0x00, + 0x7d, 0x00, + 0x7c, 0x03, + 0x7d, 0x48, + 0x7d, 0x48, + 0x7c, 0x08, + 0x7d, 0x20, + 0x7d, 0x10, + 0x7d, 0x0e, + 0x90, 0x00, + 0x91, 0x0e, + 0x91, 0x1a, + 0x91, 0x31, + 0x91, 0x5a, + 0x91, 0x69, + 0x91, 0x75, + 0x91, 0x7e, + 0x91, 0x88, + 0x91, 0x8f, + 0x91, 0x96, + 0x91, 0xa3, + 0x91, 0xaf, + 0x91, 0xc4, + 0x91, 0xd7, + 0x91, 0xe8, + 0x91, 0x20, + 0x92, 0x00, + 0x93, 0x06, + 0x93, 0xe3, + 0x93, 0x05, + 0x93, 0x05, + 0x93, 0x00, + 0x93, 0x04, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x93, 0x00, + 0x96, 0x00, + 0x97, 0x08, + 0x97, 0x19, + 0x97, 0x02, + 0x97, 0x0c, + 0x97, 0x24, + 0x97, 0x30, + 0x97, 0x28, + 0x97, 0x26, + 0x97, 0x02, + 0x97, 0x98, + 0x97, 0x80, + 0x97, 0x00, + 0x97, 0x00, + 0xc3, 0xed, + 0xa4, 0x00, + 0xa8, 0x00, + 0xc5, 0x11, + 0xc6, 0x51, + 0xbf, 0x80, + 0xc7, 0x10, + 0xb6, 0x66, + 0xb8, 0xA5, + 0xb7, 0x64, + 0xb9, 0x7C, + 0xb3, 0xaf, + 0xb4, 0x97, + 0xb5, 0xFF, + 0xb0, 0xC5, + 0xb1, 0x94, + 0xb2, 0x0f, + 0xc4, 0x5c, + 0xc0, 0x64, + 0xc1, 0x4B, + 0x8c, 0x00, + 0x86, 0x3D, + 0x50, 0x00, + 0x51, 0xC8, + 0x52, 0x96, + 0x53, 0x00, + 0x54, 0x00, + 0x55, 0x00, + 0x5a, 0xC8, + 0x5b, 0x96, + 0x5c, 0x00, + 0xd3, 0x7f, + 0xc3, 0xed, + 0x7f, 0x00, + 0xda, 0x00, + 0xe5, 0x1f, + 0xe1, 0x67, + 0xe0, 0x00, + 0xdd, 0x7f, + 0x05, 0x00, + + 0x12, 0x40, + 0xd3, 0x7f, + 0xc0, 0x16, + 0xC1, 0x12, + 0x8c, 0x00, + 0x86, 0x3d, + 0x50, 0x00, + 0x51, 0x2C, + 0x52, 0x24, + 0x53, 0x00, + 0x54, 0x00, + 0x55, 0x00, + 0x5A, 0x2c, + 0x5b, 0x24, + 0x5c, 0x00, +}; + +const unsigned char OV2640_YUV422[][2]= +{ + 0xFF, 0x00, + 0x05, 0x00, + 0xDA, 0x10, + 0xD7, 0x03, + 0xDF, 0x00, + 0x33, 0x80, + 0x3C, 0x40, + 0xe1, 0x77, + 0x00, 0x00, +}; + +const unsigned char OV2640_JPEG[][2]= +{ + 0xe0, 0x14, + 0xe1, 0x77, + 0xe5, 0x1f, + 0xd7, 0x03, + 0xda, 0x10, + 0xe0, 0x00, + 0xFF, 0x01, + 0x04, 0x08, +}; + +/* JPG 160x120 */ +const unsigned char OV2640_160x120_JPEG[][2]= +{ + 0xff, 0x01, + 0x12, 0x40, + 0x17, 0x11, + 0x18, 0x43, + 0x19, 0x00, + 0x1a, 0x4b, + 0x32, 0x09, + 0x4f, 0xca, + 0x50, 0xa8, + 0x5a, 0x23, + 0x6d, 0x00, + 0x39, 0x12, + 0x35, 0xda, + 0x22, 0x1a, + 0x37, 0xc3, + 0x23, 0x00, + 0x34, 0xc0, + 0x36, 0x1a, + 0x06, 0x88, + 0x07, 0xc0, + 0x0d, 0x87, + 0x0e, 0x41, + 0x4c, 0x00, + 0xff, 0x00, + 0xe0, 0x04, + 0xc0, 0x64, + 0xc1, 0x4b, + 0x86, 0x35, + 0x50, 0x92, + 0x51, 0xc8, + 0x52, 0x96, + 0x53, 0x00, + 0x54, 0x00, + 0x55, 0x00, + 0x57, 0x00, + 0x5a, 0x28, + 0x5b, 0x1e, + 0x5c, 0x00, + 0xe0, 0x00, +}; + +/* JPG, 0x176x144 */ +const unsigned char OV2640_176x144_JPEG[][2]= +{ + 0xff, 0x01, + 0x12, 0x40, + 0x17, 0x11, + 0x18, 0x43, + 0x19, 0x00, + 0x1a, 0x4b, + 0x32, 0x09, + 0x4f, 0xca, + 0x50, 0xa8, + 0x5a, 0x23, + 0x6d, 0x00, + 0x39, 0x12, + 0x35, 0xda, + 0x22, 0x1a, + 0x37, 0xc3, + 0x23, 0x00, + 0x34, 0xc0, + 0x36, 0x1a, + 0x06, 0x88, + 0x07, 0xc0, + 0x0d, 0x87, + 0x0e, 0x41, + 0x4c, 0x00, + 0xff, 0x00, + 0xe0, 0x04, + 0xc0, 0x64, + 0xc1, 0x4b, + 0x86, 0x35, + 0x50, 0x92, + 0x51, 0xc8, + 0x52, 0x96, + 0x53, 0x00, + 0x54, 0x00, + 0x55, 0x00, + 0x57, 0x00, + 0x5a, 0x2c, + 0x5b, 0x24, + 0x5c, 0x00, + 0xe0, 0x00, +}; + +/* JPG 320x240 */ +const unsigned char OV2640_320x240_JPEG[][2]= +{ + 0xff, 0x01, + 0x12, 0x40, + 0x17, 0x11, + 0x18, 0x43, + 0x19, 0x00, + 0x1a, 0x4b, + 0x32, 0x09, + 0x4f, 0xca, + 0x50, 0xa8, + 0x5a, 0x23, + 0x6d, 0x00, + 0x39, 0x12, + 0x35, 0xda, + 0x22, 0x1a, + 0x37, 0xc3, + 0x23, 0x00, + 0x34, 0xc0, + 0x36, 0x1a, + 0x06, 0x88, + 0x07, 0xc0, + 0x0d, 0x87, + 0x0e, 0x41, + 0x4c, 0x00, + 0xff, 0x00, + 0xe0, 0x04, + 0xc0, 0x64, + 0xc1, 0x4b, + 0x86, 0x35, + 0x50, 0x89, + 0x51, 0xc8, + 0x52, 0x96, + 0x53, 0x00, + 0x54, 0x00, + 0x55, 0x00, + 0x57, 0x00, + 0x5a, 0x50, + 0x5b, 0x3c, + 0x5c, 0x00, + 0xe0, 0x00, +}; + +/* JPG 352x288 */ +const unsigned char OV2640_352x288_JPEG[][2]= +{ + 0xff, 0x01, + 0x12, 0x40, + 0x17, 0x11, + 0x18, 0x43, + 0x19, 0x00, + 0x1a, 0x4b, + 0x32, 0x09, + 0x4f, 0xca, + 0x50, 0xa8, + 0x5a, 0x23, + 0x6d, 0x00, + 0x39, 0x12, + 0x35, 0xda, + 0x22, 0x1a, + 0x37, 0xc3, + 0x23, 0x00, + 0x34, 0xc0, + 0x36, 0x1a, + 0x06, 0x88, + 0x07, 0xc0, + 0x0d, 0x87, + 0x0e, 0x41, + 0x4c, 0x00, + 0xff, 0x00, + 0xe0, 0x04, + 0xc0, 0x64, + 0xc1, 0x4b, + 0x86, 0x35, + 0x50, 0x89, + 0x51, 0xc8, + 0x52, 0x96, + 0x53, 0x00, + 0x54, 0x00, + 0x55, 0x00, + 0x57, 0x00, + 0x5a, 0x58, + 0x5b, 0x48, + 0x5c, 0x00, + 0xe0, 0x00, +}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Initializes the hardware resources (I2C and GPIO) used to configure + * the OV2640 camera. + * @param None + * @retval None + */ +void OV2640_HW_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + I2C_InitTypeDef I2C_InitStruct; + + /*** Configures the DCMI GPIOs to interface with the OV2640 camera module ***/ + /* Enable DCMI GPIOs clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOH | + RCC_AHB1Periph_GPIOI, ENABLE); + + /* Connect DCMI pins to AF13 */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource6, GPIO_AF_DCMI); + + GPIO_PinAFConfig(GPIOH, GPIO_PinSource8, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOH, GPIO_PinSource9, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOH, GPIO_PinSource10, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOH, GPIO_PinSource11, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOH, GPIO_PinSource12, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOH, GPIO_PinSource14, GPIO_AF_DCMI); + + GPIO_PinAFConfig(GPIOI, GPIO_PinSource5, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOI, GPIO_PinSource6, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOI, GPIO_PinSource7, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOI, GPIO_PinSource4, GPIO_AF_DCMI); + + /* DCMI GPIO configuration */ + /* D0..D4(PH9/10/11/12/14), HSYNC(PH8) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | + GPIO_Pin_12 | GPIO_Pin_14| GPIO_Pin_8; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOH, &GPIO_InitStructure); + + /* D5..D7(PI4/6/7), VSYNC(PI5) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_5; + GPIO_Init(GPIOI, &GPIO_InitStructure); + + /* PCLK(PA6) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /****** Configures the I2C1 used for OV2640 camera module configuration *****/ + /* I2C1 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE); + + /* GPIOB clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); + + /* Connect I2C1 pins to AF4 */ + GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_I2C1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_I2C1); + + /* Configure I2C1 GPIOs */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Configure I2C1 */ + /* I2C DeInit */ + I2C_DeInit(I2C1); + + /* Enable the I2C peripheral */ + I2C_Cmd(I2C1, ENABLE); + + /* Set the I2C structure parameters */ + I2C_InitStruct.I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct.I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct.I2C_OwnAddress1 = 0xFE; + I2C_InitStruct.I2C_Ack = I2C_Ack_Enable; + I2C_InitStruct.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + I2C_InitStruct.I2C_ClockSpeed = 30000; + + /* Initialize the I2C peripheral w/ selected parameters */ + I2C_Init(I2C1, &I2C_InitStruct); +} + +/** + * @brief Resets the OV2640 camera. + * @param None + * @retval None + */ +void OV2640_Reset(void) +{ + OV2640_WriteReg(OV2640_DSP_RA_DLMT, 0x01); + OV2640_WriteReg(OV2640_SENSOR_COM7, 0x80); +} + +/** + * @brief Reads the OV2640 Manufacturer identifier. + * @param OV2640ID: Pointer to the OV2640 Manufacturer identifier + * @retval None + */ +void OV2640_ReadID(OV2640_IDTypeDef *OV2640ID) +{ + OV2640_WriteReg(OV2640_DSP_RA_DLMT, 0x01); + OV2640ID->Manufacturer_ID1 = OV2640_ReadReg(OV2640_SENSOR_MIDH); + OV2640ID->Manufacturer_ID2 = OV2640_ReadReg(OV2640_SENSOR_MIDL); + OV2640ID->PIDH = OV2640_ReadReg(OV2640_SENSOR_PIDH); + OV2640ID->PIDL = OV2640_ReadReg(OV2640_SENSOR_PIDL); +} + +/** + * @brief Configures DCMI/DMA to capture image from the OV2640 camera. + * @param ImageFormat: Image format BMP or JPEG + * @param BMPImageSize: BMP Image size + * @retval None + */ +void OV2640_Init(ImageFormat_TypeDef ImageFormat) +{ + DCMI_InitTypeDef DCMI_InitStructure; + DMA_InitTypeDef DMA_InitStructure; + + /*** Configures the DCMI to interface with the OV2640 camera module ***/ + /* Enable DCMI clock */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); + + /* DCMI configuration */ + DCMI_InitStructure.DCMI_CaptureMode = DCMI_CaptureMode_Continuous; + DCMI_InitStructure.DCMI_SynchroMode = DCMI_SynchroMode_Hardware; + DCMI_InitStructure.DCMI_PCKPolarity = DCMI_PCKPolarity_Rising; + DCMI_InitStructure.DCMI_VSPolarity = DCMI_VSPolarity_Low; + DCMI_InitStructure.DCMI_HSPolarity = DCMI_HSPolarity_Low; + DCMI_InitStructure.DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; + DCMI_InitStructure.DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; + + /* Configures the DMA2 to transfer Data from DCMI */ + /* Enable DMA2 clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + /* DMA2 Stream1 Configuration */ + DMA_DeInit(DMA2_Stream1); + + DMA_InitStructure.DMA_Channel = DMA_Channel_1; + DMA_InitStructure.DMA_PeripheralBaseAddr = DCMI_DR_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = FSMC_LCD_ADDRESS; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = 1; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + + switch(ImageFormat) + { + case BMP_QQVGA: + { + /* DCMI configuration */ + DCMI_InitStructure.DCMI_VSPolarity = DCMI_VSPolarity_High; + DCMI_Init(&DCMI_InitStructure); + + /* DMA2 IRQ channel Configuration */ + DMA_Init(DMA2_Stream1, &DMA_InitStructure); + break; + } + case BMP_QVGA: + { + /* DCMI configuration */ + DCMI_Init(&DCMI_InitStructure); + + /* DMA2 IRQ channel Configuration */ + DMA_Init(DMA2_Stream1, &DMA_InitStructure); + break; + } + default: + { + /* DCMI configuration */ + DCMI_InitStructure.DCMI_VSPolarity = DCMI_VSPolarity_High; + DCMI_Init(&DCMI_InitStructure); + + /* DMA2 IRQ channel Configuration */ + DMA_Init(DMA2_Stream1, &DMA_InitStructure); + break; + } + } +} + +/** + * @brief Configures the OV2640 camera in QQVGA mode. + * @param None + * @retval None + */ +void OV2640_QQVGAConfig(void) +{ + uint32_t i; + + OV2640_Reset(); + Delay(200); + + /* Initialize OV2640 */ + for(i=0; i<(sizeof(OV2640_QQVGA)/2); i++) + { + OV2640_WriteReg(OV2640_QQVGA[i][0], OV2640_QQVGA[i][1]); + Delay(2); + } +} + +/** + * @brief Configures the OV2640 camera in QVGA mode. + * @param None + * @retval None + */ +void OV2640_QVGAConfig(void) +{ + uint32_t i; + + OV2640_Reset(); + Delay(200); + + /* Initialize OV2640 */ + for(i=0; i<(sizeof(OV2640_QVGA)/2); i++) + { + OV2640_WriteReg(OV2640_QVGA[i][0], OV2640_QVGA[i][1]); + Delay(2); + } +} + +/** + * @brief Configures the OV2640 camera in JPEG mode. + * @param JPEGImageSize: JPEG image size + * @retval None + */ +void OV2640_JPEGConfig(ImageFormat_TypeDef ImageFormat) +{ + uint32_t i; + + OV2640_Reset(); + Delay(200); + + /* Initialize OV2640 */ + for(i=0; i<(sizeof(OV2640_JPEG_INIT)/2); i++) + { + OV2640_WriteReg(OV2640_JPEG_INIT[i][0], OV2640_JPEG_INIT[i][1]); + } + + /* Set to output YUV422 */ + for(i=0; i<(sizeof(OV2640_YUV422)/2); i++) + { + OV2640_WriteReg(OV2640_YUV422[i][0], OV2640_YUV422[i][1]); + } + + OV2640_WriteReg(0xff, 0x01); + OV2640_WriteReg(0x15, 0x00); + + /* Set to output JPEG */ + for(i=0; i<(sizeof(OV2640_JPEG)/2); i++) + { + OV2640_WriteReg(OV2640_JPEG[i][0], OV2640_JPEG[i][1]); + } + + Delay(100); + + switch(ImageFormat) + { + case JPEG_160x120: + { + for(i=0; i<(sizeof(OV2640_160x120_JPEG)/2); i++) + { + OV2640_WriteReg(OV2640_160x120_JPEG[i][0], OV2640_160x120_JPEG[i][1]); + } + break; + } + case JPEG_176x144: + { + for(i=0; i<(sizeof(OV2640_176x144_JPEG)/2); i++) + { + OV2640_WriteReg(OV2640_176x144_JPEG[i][0], OV2640_176x144_JPEG[i][1]); + } + break; + } + case JPEG_320x240: + { + for(i=0; i<(sizeof(OV2640_320x240_JPEG)/2); i++) + { + OV2640_WriteReg(OV2640_320x240_JPEG[i][0], OV2640_320x240_JPEG[i][1]); + } + break; + } + case JPEG_352x288: + { + for(i=0; i<(sizeof(OV2640_352x288_JPEG)/2); i++) + { + OV2640_WriteReg(OV2640_352x288_JPEG[i][0], OV2640_352x288_JPEG[i][1]); + } + break; + } + default: + { + for(i=0; i<(sizeof(OV2640_160x120_JPEG)/2); i++) + { + OV2640_WriteReg(OV2640_160x120_JPEG[i][0], OV2640_160x120_JPEG[i][1]); + } + break; + } + } +} + +/** + * @brief Configures the OV2640 camera brightness. + * @param Brightness: Brightness value, where Brightness can be: + * 0x40 for Brightness +2, + * 0x30 for Brightness +1, + * 0x20 for Brightness 0, + * 0x10 for Brightness -1, + * 0x00 for Brightness -2, + * @retval None + */ +void OV2640_BrightnessConfig(uint8_t Brightness) +{ + OV2640_WriteReg(0xff, 0x00); + OV2640_WriteReg(0x7c, 0x00); + OV2640_WriteReg(0x7d, 0x04); + OV2640_WriteReg(0x7c, 0x09); + OV2640_WriteReg(0x7d, Brightness); + OV2640_WriteReg(0x7d, 0x00); +} + +/** + * @brief Configures the OV2640 camera Black and white mode. + * @param BlackWhite: BlackWhite value, where BlackWhite can be: + * 0x18 for B&W, + * 0x40 for Negative, + * 0x58 for B&W negative, + * 0x00 for Normal, + * @retval None + */ +void OV2640_BandWConfig(uint8_t BlackWhite) +{ + OV2640_WriteReg(0xff, 0x00); + OV2640_WriteReg(0x7c, 0x00); + OV2640_WriteReg(0x7d, BlackWhite); + OV2640_WriteReg(0x7c, 0x05); + OV2640_WriteReg(0x7d, 0x80); + OV2640_WriteReg(0x7d, 0x80); +} + +/** + * @brief Configures the OV2640 camera color effects. + * @param value1: Color effects value1 + * @param value2: Color effects value2 + * where value1 and value2 can be: + * value1 = 0x40, value2 = 0xa6 for Antique, + * value1 = 0xa0, value2 = 0x40 for Bluish, + * value1 = 0x40, value2 = 0x40 for Greenish, + * value1 = 0x40, value2 = 0xc0 for Reddish, + * @retval None + */ +void OV2640_ColorEffectsConfig(uint8_t value1, uint8_t value2) +{ + OV2640_WriteReg(0xff, 0x00); + OV2640_WriteReg(0x7c, 0x00); + OV2640_WriteReg(0x7d, 0x18); + OV2640_WriteReg(0x7c, 0x05); + OV2640_WriteReg(0x7d, value1); + OV2640_WriteReg(0x7d, value2); +} + +/** + * @brief Configures the OV2640 camera contrast. + * @param value1: Contrast value1 + * @param value2: Contrast value2 + * where value1 and value2 can be: + * value1 = 0x28, value2 = 0x0c for Contrast +2, + * value1 = 0x24, value2 = 0x16 for Contrast +1, + * value1 = 0x20, value2 = 0x20 for Contrast 0, + * value1 = 0x1c, value2 = 0x2a for Contrast -1, + * value1 = 0x18, value2 = 0x34 for Contrast -2, + * @retval None + */ +void OV2640_ContrastConfig(uint8_t value1, uint8_t value2) +{ + OV2640_WriteReg(0xff, 0x00); + OV2640_WriteReg(0x7c, 0x00); + OV2640_WriteReg(0x7d, 0x04); + OV2640_WriteReg(0x7c, 0x07); + OV2640_WriteReg(0x7d, 0x20); + OV2640_WriteReg(0x7d, value1); + OV2640_WriteReg(0x7d, value2); + OV2640_WriteReg(0x7d, 0x06); +} + +/** + * @brief Writes a byte at a specific Camera register + * @param Addr: OV2640 register address. + * @param Data: Data to be written to the specific register + * @retval 0x00 if write operation is OK. + * 0xFF if timeout condition occured (device not connected or bus error). + */ +uint8_t OV2640_WriteReg(uint16_t Addr, uint8_t Data) +{ + uint32_t timeout = DCMI_TIMEOUT_MAX; + + /* Generate the Start Condition */ + I2C_GenerateSTART(I2C1, ENABLE); + + /* Test on I2C1 EV5 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send DCMI selcted device slave Address for write */ + I2C_Send7bitAddress(I2C1, OV2640_DEVICE_WRITE_ADDRESS, I2C_Direction_Transmitter); + + /* Test on I2C1 EV6 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send I2C1 location address LSB */ + I2C_SendData(I2C1, (uint8_t)(Addr)); + + /* Test on I2C1 EV8 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send Data */ + I2C_SendData(I2C1, Data); + + /* Test on I2C1 EV8 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send I2C1 STOP Condition */ + I2C_GenerateSTOP(I2C1, ENABLE); + + /* If operation is OK, return 0 */ + return 0; +} + +/** + * @brief Reads a byte from a specific Camera register + * @param Addr: OV2640 register address. + * @retval data read from the specific register or 0xFF if timeout condition + * occured. + */ +uint8_t OV2640_ReadReg(uint16_t Addr) +{ + uint32_t timeout = DCMI_TIMEOUT_MAX; + uint8_t Data = 0; + + /* Generate the Start Condition */ + I2C_GenerateSTART(I2C1, ENABLE); + + /* Test on I2C1 EV5 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send DCMI selcted device slave Address for write */ + I2C_Send7bitAddress(I2C1, OV2640_DEVICE_READ_ADDRESS, I2C_Direction_Transmitter); + + /* Test on I2C1 EV6 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send I2C1 location address LSB */ + I2C_SendData(I2C1, (uint8_t)(Addr)); + + /* Test on I2C1 EV8 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Clear AF flag if arised */ + I2C1->SR1 |= (uint16_t)0x0400; + + /* Generate the Start Condition */ + I2C_GenerateSTART(I2C1, ENABLE); + + /* Test on I2C1 EV6 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send DCMI selcted device slave Address for write */ + I2C_Send7bitAddress(I2C1, OV2640_DEVICE_READ_ADDRESS, I2C_Direction_Receiver); + + /* Test on I2C1 EV6 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Prepare an NACK for the next data received */ + I2C_AcknowledgeConfig(I2C1, DISABLE); + + /* Test on I2C1 EV7 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_RECEIVED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Prepare Stop after receiving data */ + I2C_GenerateSTOP(I2C1, ENABLE); + + /* Receive the Data */ + Data = I2C_ReceiveData(I2C1); + + /* return the read data */ + return Data; +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov2640.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov2640.h new file mode 100644 index 000000000..9a14f6f7e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov2640.h @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file DCMI/Camera/dcmi_ov2640.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for dcmi_ov2640.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DCMI_OV2640_H +#define __DCMI_OV2640_H + +/* Includes ------------------------------------------------------------------*/ +#include "camera_api.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + uint8_t Manufacturer_ID1; + uint8_t Manufacturer_ID2; + uint8_t PIDH; + uint8_t PIDL; +}OV2640_IDTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/* Use this define to set the maximum delay timeout for the I2C DCMI_OV2640_SingleRandomWrite() + and DCMI_OV2640_SingleRandomRead() operations. Exeeding this timeout delay, + the read/write functions will be aborted and return error code (0xFF). + The period of the delay will depend on the system operating frequency. The following + value has been set for system running at 168 MHz. */ +#define DCMI_TIMEOUT_MAX 10000 + +#define OV2640_DEVICE_WRITE_ADDRESS 0x60 +#define OV2640_DEVICE_READ_ADDRESS 0x61 + +/* OV2640 Registers definition when DSP bank selected (0xFF = 0x00) */ +#define OV2640_DSP_R_BYPASS 0x05 +#define OV2640_DSP_Qs 0x44 +#define OV2640_DSP_CTRL 0x50 +#define OV2640_DSP_HSIZE1 0x51 +#define OV2640_DSP_VSIZE1 0x52 +#define OV2640_DSP_XOFFL 0x53 +#define OV2640_DSP_YOFFL 0x54 +#define OV2640_DSP_VHYX 0x55 +#define OV2640_DSP_DPRP 0x56 +#define OV2640_DSP_TEST 0x57 +#define OV2640_DSP_ZMOW 0x5A +#define OV2640_DSP_ZMOH 0x5B +#define OV2640_DSP_ZMHH 0x5C +#define OV2640_DSP_BPADDR 0x7C +#define OV2640_DSP_BPDATA 0x7D +#define OV2640_DSP_CTRL2 0x86 +#define OV2640_DSP_CTRL3 0x87 +#define OV2640_DSP_SIZEL 0x8C +#define OV2640_DSP_HSIZE2 0xC0 +#define OV2640_DSP_VSIZE2 0xC1 +#define OV2640_DSP_CTRL0 0xC2 +#define OV2640_DSP_CTRL1 0xC3 +#define OV2640_DSP_R_DVP_SP 0xD3 +#define OV2640_DSP_IMAGE_MODE 0xDA +#define OV2640_DSP_RESET 0xE0 +#define OV2640_DSP_MS_SP 0xF0 +#define OV2640_DSP_SS_ID 0x7F +#define OV2640_DSP_SS_CTRL 0xF8 +#define OV2640_DSP_MC_BIST 0xF9 +#define OV2640_DSP_MC_AL 0xFA +#define OV2640_DSP_MC_AH 0xFB +#define OV2640_DSP_MC_D 0xFC +#define OV2640_DSP_P_STATUS 0xFE +#define OV2640_DSP_RA_DLMT 0xFF + +/* OV2640 Registers definition when sensor bank selected (0xFF = 0x01) */ +#define OV2640_SENSOR_GAIN 0x00 +#define OV2640_SENSOR_COM1 0x03 +#define OV2640_SENSOR_REG04 0x04 +#define OV2640_SENSOR_REG08 0x08 +#define OV2640_SENSOR_COM2 0x09 +#define OV2640_SENSOR_PIDH 0x0A +#define OV2640_SENSOR_PIDL 0x0B +#define OV2640_SENSOR_COM3 0x0C +#define OV2640_SENSOR_COM4 0x0D +#define OV2640_SENSOR_AEC 0x10 +#define OV2640_SENSOR_CLKRC 0x11 +#define OV2640_SENSOR_COM7 0x12 +#define OV2640_SENSOR_COM8 0x13 +#define OV2640_SENSOR_COM9 0x14 +#define OV2640_SENSOR_COM10 0x15 +#define OV2640_SENSOR_HREFST 0x17 +#define OV2640_SENSOR_HREFEND 0x18 +#define OV2640_SENSOR_VSTART 0x19 +#define OV2640_SENSOR_VEND 0x1A +#define OV2640_SENSOR_MIDH 0x1C +#define OV2640_SENSOR_MIDL 0x1D +#define OV2640_SENSOR_AEW 0x24 +#define OV2640_SENSOR_AEB 0x25 +#define OV2640_SENSOR_W 0x26 +#define OV2640_SENSOR_REG2A 0x2A +#define OV2640_SENSOR_FRARL 0x2B +#define OV2640_SENSOR_ADDVSL 0x2D +#define OV2640_SENSOR_ADDVHS 0x2E +#define OV2640_SENSOR_YAVG 0x2F +#define OV2640_SENSOR_REG32 0x32 +#define OV2640_SENSOR_ARCOM2 0x34 +#define OV2640_SENSOR_REG45 0x45 +#define OV2640_SENSOR_FLL 0x46 +#define OV2640_SENSOR_FLH 0x47 +#define OV2640_SENSOR_COM19 0x48 +#define OV2640_SENSOR_ZOOMS 0x49 +#define OV2640_SENSOR_COM22 0x4B +#define OV2640_SENSOR_COM25 0x4E +#define OV2640_SENSOR_BD50 0x4F +#define OV2640_SENSOR_BD60 0x50 +#define OV2640_SENSOR_REG5D 0x5D +#define OV2640_SENSOR_REG5E 0x5E +#define OV2640_SENSOR_REG5F 0x5F +#define OV2640_SENSOR_REG60 0x60 +#define OV2640_SENSOR_HISTO_LOW 0x61 +#define OV2640_SENSOR_HISTO_HIGH 0x62 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void OV2640_HW_Init(void); +void OV2640_Reset(void); +void OV2640_ReadID(OV2640_IDTypeDef *OV2640ID); +void OV2640_Init(ImageFormat_TypeDef ImageFormat); +void OV2640_QQVGAConfig(void); +void OV2640_QVGAConfig(void); +void OV2640_JPEGConfig(ImageFormat_TypeDef ImageFormat); +void OV2640_BrightnessConfig(uint8_t Brightness); +void OV2640_ContrastConfig(uint8_t value1, uint8_t value2); +void OV2640_BandWConfig(uint8_t BlackWhite); +void OV2640_ColorEffectsConfig(uint8_t value1, uint8_t value2); +uint8_t OV2640_WriteReg(uint16_t Addr, uint8_t Data); +uint8_t OV2640_ReadReg(uint16_t Addr); + +#endif /* __DCMI_OV2640_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov9655.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov9655.c new file mode 100644 index 000000000..3339535f4 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov9655.c @@ -0,0 +1,766 @@ +/** + ****************************************************************************** + * @file DCMI/Camera/dcmi_ov9655.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file includes the driver for OV9655 Camera module mounted on + * STM322xG-EVAL board RevA and RevB. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "camera_api.h" +#include "dcmi_ov9655.h" + +/** @addtogroup stm32f2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DCMI_Camera + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TIMEOUT 2 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* QQVGA 160x120 */ +static unsigned char OV9655_QQVGA[][2]= +{ + 0x00, 0x00, + 0x01, 0x80, + 0x02, 0x80, + 0x03, 0x02, + 0x04, 0x03, + 0x09, 0x01, + 0x0b, 0x57, + 0x0e, 0x61, + 0x0f, 0x40, + 0x11, 0x01, + 0x12, 0x62, + 0x13, 0xc7, + 0x14, 0x3a, + 0x16, 0x24, + 0x17, 0x18, + 0x18, 0x04, + 0x19, 0x01, + 0x1a, 0x81, + 0x1e, 0x00,//0x20 + 0x24, 0x3c, + 0x25, 0x36, + 0x26, 0x72, + 0x27, 0x08, + 0x28, 0x08, + 0x29, 0x15, + 0x2a, 0x00, + 0x2b, 0x00, + 0x2c, 0x08, + 0x32, 0xa4, + 0x33, 0x00, + 0x34, 0x3f, + 0x35, 0x00, + 0x36, 0x3a, + 0x38, 0x72, + 0x39, 0x57, + 0x3a, 0xcc, + 0x3b, 0x04, + 0x3d, 0x99, + 0x3e, 0x0e, + 0x3f, 0xc1, + 0x40, 0xc0, + 0x41, 0x41, + 0x42, 0xc0, + 0x43, 0x0a, + 0x44, 0xf0, + 0x45, 0x46, + 0x46, 0x62, + 0x47, 0x2a, + 0x48, 0x3c, + 0x4a, 0xfc, + 0x4b, 0xfc, + 0x4c, 0x7f, + 0x4d, 0x7f, + 0x4e, 0x7f, + 0x4f, 0x98, + 0x50, 0x98, + 0x51, 0x00, + 0x52, 0x28, + 0x53, 0x70, + 0x54, 0x98, + 0x58, 0x1a, + 0x59, 0x85, + 0x5a, 0xa9, + 0x5b, 0x64, + 0x5c, 0x84, + 0x5d, 0x53, + 0x5e, 0x0e, + 0x5f, 0xf0, + 0x60, 0xf0, + 0x61, 0xf0, + 0x62, 0x00, + 0x63, 0x00, + 0x64, 0x02, + 0x65, 0x20, + 0x66, 0x00, + 0x69, 0x0a, + 0x6b, 0x5a, + 0x6c, 0x04, + 0x6d, 0x55, + 0x6e, 0x00, + 0x6f, 0x9d, + 0x70, 0x21, + 0x71, 0x78, + 0x72, 0x22, + 0x73, 0x02, + 0x74, 0x10, + 0x75, 0x10, + 0x76, 0x01, + 0x77, 0x02, + 0x7A, 0x12, + 0x7B, 0x08, + 0x7C, 0x16, + 0x7D, 0x30, + 0x7E, 0x5e, + 0x7F, 0x72, + 0x80, 0x82, + 0x81, 0x8e, + 0x82, 0x9a, + 0x83, 0xa4, + 0x84, 0xac, + 0x85, 0xb8, + 0x86, 0xc3, + 0x87, 0xd6, + 0x88, 0xe6, + 0x89, 0xf2, + 0x8a, 0x24, + 0x8c, 0x80, + 0x90, 0x7d, + 0x91, 0x7b, + 0x9d, 0x02, + 0x9e, 0x02, + 0x9f, 0x7a, + 0xa0, 0x79, + 0xa1, 0x40, + 0xa4, 0x50, + 0xa5, 0x68, + 0xa6, 0x4a, + 0xa8, 0xc1, + 0xa9, 0xef, + 0xaa, 0x92, + 0xab, 0x04, + 0xac, 0x80, + 0xad, 0x80, + 0xae, 0x80, + 0xaf, 0x80, + 0xb2, 0xf2, + 0xb3, 0x20, + 0xb4, 0x20, + 0xb5, 0x00, + 0xb6, 0xaf, + 0xb6, 0xaf, + 0xbb, 0xae, + 0xbc, 0x7f, + 0xbd, 0x7f, + 0xbe, 0x7f, + 0xbf, 0x7f, + 0xbf, 0x7f, + 0xc0, 0xaa, + 0xc1, 0xc0, + 0xc2, 0x01, + 0xc3, 0x4e, + 0xc6, 0x05, + 0xc7, 0x82, + 0xc9, 0xe0, + 0xca, 0xe8, + 0xcb, 0xf0, + 0xcc, 0xd8, + 0xcd, 0x93, + + 0x12, 0x63, + 0x40, 0x10, + 0x15, 0x08, +}; + +/* QVGA 360x240 */ +static unsigned char OV9655_QVGA[][2]= +{ + 0x00, 0x00, + 0x01, 0x80, + 0x02, 0x80, + 0x03, 0x02, + 0x04, 0x03, + 0x09, 0x01, + 0x0b, 0x57, + 0x0e, 0x61, + 0x0f, 0x40, + 0x11, 0x01, + 0x12, 0x62, + 0x13, 0xc7, + 0x14, 0x3a, + 0x16, 0x24, + 0x17, 0x18, + 0x18, 0x04, + 0x19, 0x01, + 0x1a, 0x81, + 0x1e, 0x00, + 0x24, 0x3c, + 0x25, 0x36, + 0x26, 0x72, + 0x27, 0x08, + 0x28, 0x08, + 0x29, 0x15, + 0x2a, 0x00, + 0x2b, 0x00, + 0x2c, 0x08, + 0x32, 0x12, + 0x33, 0x00, + 0x34, 0x3f, + 0x35, 0x00, + 0x36, 0x3a, + 0x38, 0x72, + 0x39, 0x57, + 0x3a, 0xcc, + 0x3b, 0x04, + 0x3d, 0x99, + 0x3e, 0x02, + 0x3f, 0xc1, + 0x40, 0xc0, + 0x41, 0x41, + 0x42, 0xc0, + 0x43, 0x0a, + 0x44, 0xf0, + 0x45, 0x46, + 0x46, 0x62, + 0x47, 0x2a, + 0x48, 0x3c, + 0x4a, 0xfc, + 0x4b, 0xfc, + 0x4c, 0x7f, + 0x4d, 0x7f, + 0x4e, 0x7f, + 0x4f, 0x98, + 0x50, 0x98, + 0x51, 0x00, + 0x52, 0x28, + 0x53, 0x70, + 0x54, 0x98, + 0x58, 0x1a, + 0x59, 0x85, + 0x5a, 0xa9, + 0x5b, 0x64, + 0x5c, 0x84, + 0x5d, 0x53, + 0x5e, 0x0e, + 0x5f, 0xf0, + 0x60, 0xf0, + 0x61, 0xf0, + 0x62, 0x00, + 0x63, 0x00, + 0x64, 0x02, + 0x65, 0x20, + 0x66, 0x00, + 0x69, 0x0a, + 0x6b, 0x5a, + 0x6c, 0x04, + 0x6d, 0x55, + 0x6e, 0x00, + 0x6f, 0x9d, + 0x70, 0x21, + 0x71, 0x78, + 0x72, 0x11, + 0x73, 0x01, + 0x74, 0x10, + 0x75, 0x10, + 0x76, 0x01, + 0x77, 0x02, + 0x7A, 0x12, + 0x7B, 0x08, + 0x7C, 0x16, + 0x7D, 0x30, + 0x7E, 0x5e, + 0x7F, 0x72, + 0x80, 0x82, + 0x81, 0x8e, + 0x82, 0x9a, + 0x83, 0xa4, + 0x84, 0xac, + 0x85, 0xb8, + 0x86, 0xc3, + 0x87, 0xd6, + 0x88, 0xe6, + 0x89, 0xf2, + 0x8a, 0x24, + 0x8c, 0x80, + 0x90, 0x7d, + 0x91, 0x7b, + 0x9d, 0x02, + 0x9e, 0x02, + 0x9f, 0x7a, + 0xa0, 0x79, + 0xa1, 0x40, + 0xa4, 0x50, + 0xa5, 0x68, + 0xa6, 0x4a, + 0xa8, 0xc1, + 0xa9, 0xef, + 0xaa, 0x92, + 0xab, 0x04, + 0xac, 0x80, + 0xad, 0x80, + 0xae, 0x80, + 0xaf, 0x80, + 0xb2, 0xf2, + 0xb3, 0x20, + 0xb4, 0x20, + 0xb5, 0x00, + 0xb6, 0xaf, + 0xb6, 0xaf, + 0xbb, 0xae, + 0xbc, 0x7f, + 0xbd, 0x7f, + 0xbe, 0x7f, + 0xbf, 0x7f, + 0xbf, 0x7f, + 0xc0, 0xaa, + 0xc1, 0xc0, + 0xc2, 0x01, + 0xc3, 0x4e, + 0xc6, 0x05, + 0xc7, 0x81, + 0xc9, 0xe0, + 0xca, 0xe8, + 0xcb, 0xf0, + 0xcc, 0xd8, + 0xcd, 0x93, + + 0x12, 0x63, + 0x40, 0x10, + 0x15, 0x08, +}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Initializes the hardware resources (I2C and GPIO) used to configure + * the OV9655 camera. + * @param None + * @retval None + */ +void OV9655_HW_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + I2C_InitTypeDef I2C_InitStruct; + + /*** Configures the DCMI GPIOs to interface with the OV9655 camera module ***/ + /* Enable DCMI GPIOs clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOH | + RCC_AHB1Periph_GPIOI, ENABLE); + + /* Connect DCMI pins to AF13 */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource6, GPIO_AF_DCMI); + + GPIO_PinAFConfig(GPIOH, GPIO_PinSource8, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOH, GPIO_PinSource9, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOH, GPIO_PinSource10, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOH, GPIO_PinSource11, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOH, GPIO_PinSource12, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOH, GPIO_PinSource14, GPIO_AF_DCMI); + + GPIO_PinAFConfig(GPIOI, GPIO_PinSource5, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOI, GPIO_PinSource6, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOI, GPIO_PinSource7, GPIO_AF_DCMI); + GPIO_PinAFConfig(GPIOI, GPIO_PinSource4, GPIO_AF_DCMI); + + /* DCMI GPIO configuration */ + /* D0..D4(PH9/10/11/12/14), HSYNC(PH8) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | + GPIO_Pin_12 | GPIO_Pin_14| GPIO_Pin_8; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOH, &GPIO_InitStructure); + + /* D5..D7(PI4/6/7), VSYNC(PI5) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_5; + GPIO_Init(GPIOI, &GPIO_InitStructure); + + /* PCLK(PA6) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /****** Configures the I2C1 used for OV9655 camera module configuration *****/ + /* I2C1 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE); + + /* GPIOB clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); + + /* Connect I2C1 pins to AF4 */ + GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_I2C1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_I2C1); + + /* Configure I2C1 GPIOs */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Configure I2C1 */ + /* I2C DeInit */ + I2C_DeInit(I2C1); + + /* Enable the I2C peripheral */ + I2C_Cmd(I2C1, ENABLE); + + /* Set the I2C structure parameters */ + I2C_InitStruct.I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct.I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct.I2C_OwnAddress1 = 0xFE; + I2C_InitStruct.I2C_Ack = I2C_Ack_Enable; + I2C_InitStruct.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + I2C_InitStruct.I2C_ClockSpeed = 30000; + + /* Initialize the I2C peripheral w/ selected parameters */ + I2C_Init(I2C1, &I2C_InitStruct); +} + +/** + * @brief Resets the OV9655 camera. + * @param None + * @retval None + */ +void OV9655_Reset(void) +{ + OV9655_WriteReg(OV9655_COM7, 0x80); +} + +/** + * @brief Reads the OV9655 Manufacturer identifier. + * @param OV9655ID: pointer to the OV9655 Manufacturer identifier. + * @retval None + */ +void OV9655_ReadID(OV9655_IDTypeDef* OV9655ID) +{ + OV9655ID->Manufacturer_ID1 = OV9655_ReadReg(OV9655_MIDH); + OV9655ID->Manufacturer_ID2 = OV9655_ReadReg(OV9655_MIDL); + OV9655ID->Version = OV9655_ReadReg(OV9655_VER); + OV9655ID->PID = OV9655_ReadReg(OV9655_PID); +} + +/** + * @brief Configures the DCMI/DMA to capture image from the OV9655 camera. + * @param ImageFormat: Image format BMP or JPEG + * @param BMPImageSize: BMP Image size + * @retval None + */ +void OV9655_Init(ImageFormat_TypeDef ImageFormat) +{ + DCMI_InitTypeDef DCMI_InitStructure; + DMA_InitTypeDef DMA_InitStructure; + + /*** Configures the DCMI to interface with the OV9655 camera module ***/ + /* Enable DCMI clock */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); + + /* DCMI configuration */ + DCMI_InitStructure.DCMI_CaptureMode = DCMI_CaptureMode_Continuous; + DCMI_InitStructure.DCMI_SynchroMode = DCMI_SynchroMode_Hardware; + DCMI_InitStructure.DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; + DCMI_InitStructure.DCMI_VSPolarity = DCMI_VSPolarity_High; + DCMI_InitStructure.DCMI_HSPolarity = DCMI_HSPolarity_High; + DCMI_InitStructure.DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; + DCMI_InitStructure.DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; + + /* Configures the DMA2 to transfer Data from DCMI */ + /* Enable DMA2 clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + /* DMA2 Stream1 Configuration */ + DMA_DeInit(DMA2_Stream1); + + DMA_InitStructure.DMA_Channel = DMA_Channel_1; + DMA_InitStructure.DMA_PeripheralBaseAddr = DCMI_DR_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = FSMC_LCD_ADDRESS; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = 1; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + + switch(ImageFormat) + { + case BMP_QQVGA: + { + /* DCMI configuration */ + DCMI_Init(&DCMI_InitStructure); + + /* DMA2 IRQ channel Configuration */ + DMA_Init(DMA2_Stream1, &DMA_InitStructure); + break; + } + case BMP_QVGA: + { + /* DCMI configuration */ + DCMI_Init(&DCMI_InitStructure); + + /* DMA2 IRQ channel Configuration */ + DMA_Init(DMA2_Stream1, &DMA_InitStructure); + break; + } + default: + { + /* DCMI configuration */ + DCMI_Init(&DCMI_InitStructure); + + /* DMA2 IRQ channel Configuration */ + DMA_Init(DMA2_Stream1, &DMA_InitStructure); + break; + } + } +} + +/** + * @brief Configures the OV9655 camera in QQVGA mode. + * @param None + * @retval None + */ +void OV9655_QQVGAConfig(void) +{ + uint32_t i; + + OV9655_Reset(); + Delay(200); + + /* Initialize OV9655 */ + for(i=0; i<(sizeof(OV9655_QQVGA)/2); i++) + { + OV9655_WriteReg(OV9655_QQVGA[i][0], OV9655_QQVGA[i][1]); + Delay(2); + } +} + +/** + * @brief SConfigures the OV9655 camera in QVGA mode. + * @param None + * @retval None + */ +void OV9655_QVGAConfig(void) +{ + uint32_t i; + + OV9655_Reset(); + Delay(200); + + /* Initialize OV9655 */ + for(i=0; i<(sizeof(OV9655_QVGA)/2); i++) + { + OV9655_WriteReg(OV9655_QVGA[i][0], OV9655_QVGA[i][1]); + Delay(2); + } +} + +/** + * @brief Configures the OV9655 camera brightness. + * @param Brightness: Brightness value, where Brightness can be: + * positively (0x01 ~ 0x7F) and negatively (0x80 ~ 0xFF) + * @retval None + */ +void OV9655_BrightnessConfig(uint8_t Brightness) +{ + OV9655_WriteReg(OV9655_BRTN, Brightness); +} + +/** + * @brief Writes a byte at a specific Camera register + * @param Addr: OV9655 register address + * @param Data: data to be written to the specific register + * @retval 0x00 if write operation is OK + * 0xFF if timeout condition occured (device not connected or bus error). + */ +uint8_t OV9655_WriteReg(uint16_t Addr, uint8_t Data) +{ + uint32_t timeout = DCMI_TIMEOUT_MAX; + + /* Generate the Start Condition */ + I2C_GenerateSTART(I2C1, ENABLE); + + /* Test on I2C1 EV5 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send DCMI selcted device slave Address for write */ + I2C_Send7bitAddress(I2C1, OV9655_DEVICE_WRITE_ADDRESS, I2C_Direction_Transmitter); + + /* Test on I2C1 EV6 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send I2C1 location address LSB */ + I2C_SendData(I2C1, (uint8_t)(Addr)); + + /* Test on I2C1 EV8 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send Data */ + I2C_SendData(I2C1, Data); + + /* Test on I2C1 EV8 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send I2C1 STOP Condition */ + I2C_GenerateSTOP(I2C1, ENABLE); + + /* If operation is OK, return 0 */ + return 0; +} + +/** + * @brief Reads a byte from a specific Camera register + * @param Addr: OV9655 register address. + * @retval data read from the specific register or 0xFF if timeout condition + * occured. + */ +uint8_t OV9655_ReadReg(uint16_t Addr) +{ + uint32_t timeout = DCMI_TIMEOUT_MAX; + uint8_t Data = 0; + + /* Generate the Start Condition */ + I2C_GenerateSTART(I2C1, ENABLE); + + /* Test on I2C1 EV5 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send DCMI selcted device slave Address for write */ + I2C_Send7bitAddress(I2C1, OV9655_DEVICE_READ_ADDRESS, I2C_Direction_Transmitter); + + /* Test on I2C1 EV6 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send I2C1 location address LSB */ + I2C_SendData(I2C1, (uint8_t)(Addr)); + + /* Test on I2C1 EV8 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Clear AF flag if arised */ + I2C1->SR1 |= (uint16_t)0x0400; + + /* Generate the Start Condition */ + I2C_GenerateSTART(I2C1, ENABLE); + + /* Test on I2C1 EV6 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Send DCMI selcted device slave Address for write */ + I2C_Send7bitAddress(I2C1, OV9655_DEVICE_READ_ADDRESS, I2C_Direction_Receiver); + + /* Test on I2C1 EV6 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Prepare an NACK for the next data received */ + I2C_AcknowledgeConfig(I2C1, DISABLE); + + /* Test on I2C1 EV7 and clear it */ + timeout = DCMI_TIMEOUT_MAX; /* Initialize timeout value */ + while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_RECEIVED)) + { + /* If the timeout delay is exeeded, exit with error code */ + if ((timeout--) == 0) return 0xFF; + } + + /* Prepare Stop after receiving data */ + I2C_GenerateSTOP(I2C1, ENABLE); + + /* Receive the Data */ + Data = I2C_ReceiveData(I2C1); + + /* return the read data */ + return Data; +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov9655.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov9655.h new file mode 100644 index 000000000..8e7bd298c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/dcmi_ov9655.h @@ -0,0 +1,222 @@ +/** + ****************************************************************************** + * @file DCMI/OV9655_Camera/dcmi_ov9655.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for dcmi_ov9655.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DCMI_OV9655_H +#define __DCMI_OV9655_H + +/* Includes ------------------------------------------------------------------*/ +#include "camera_api.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + uint8_t Manufacturer_ID1; + uint8_t Manufacturer_ID2; + uint8_t Version; + uint8_t PID; +}OV9655_IDTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/* Use this define to set the maximum delay timeout for the I2C DCMI_OV9655_SingleRandomWrite() + and DCMI_OV9655_SingleRandomRead() operations. Exeeding this timeout delay, + the read/write functions will be aborted and return error code (0xFF). + The period of the delay will depend on the system operating frequency. The following + value has been set for system running at 168 MHz. */ +#define DCMI_TIMEOUT_MAX 10000 + +#define OV9655_DEVICE_WRITE_ADDRESS 0x60 +#define OV9655_DEVICE_READ_ADDRESS 0x61 + +/* OV9655 Registers definition */ +#define OV9655_GAIN 0x00 +#define OV9655_BLUE 0x01 +#define OV9655_RED 0x02 +#define OV9655_VREF 0x03 +#define OV9655_COM1 0x04 +#define OV9655_BAVE 0x05 +#define OV9655_GbAVE 0x06 +#define OV9655_GrAVE 0x07 +#define OV9655_RAVE 0x08 +#define OV9655_COM2 0x09 +#define OV9655_PID 0x0A +#define OV9655_VER 0x0B +#define OV9655_COM3 0x0C +#define OV9655_COM4 0x0D +#define OV9655_COM5 0x0E +#define OV9655_COM6 0x0F +#define OV9655_AEC 0x10 +#define OV9655_CLKRC 0x11 +#define OV9655_COM7 0x12 +#define OV9655_COM8 0x13 +#define OV9655_COM9 0x14 +#define OV9655_COM10 0x15 +#define OV9655_REG16 0x16 +#define OV9655_HSTART 0x17 +#define OV9655_HSTOP 0x18 +#define OV9655_VSTART 0x19 +#define OV9655_VSTOP 0x1A +#define OV9655_PSHFT 0x1B +#define OV9655_MIDH 0x1C +#define OV9655_MIDL 0x1D +#define OV9655_MVFP 0x1E +#define OV9655_BOS 0x20 +#define OV9655_GBOS 0x21 +#define OV9655_GROS 0x22 +#define OV9655_ROS 0x23 +#define OV9655_AEW 0x24 +#define OV9655_AEB 0x25 +#define OV9655_VPT 0x26 +#define OV9655_BBIAS 0x27 +#define OV9655_GbBIAS 0x28 +#define OV9655_PREGAIN 0x29 +#define OV9655_EXHCH 0x2A +#define OV9655_EXHCL 0x2B +#define OV9655_RBIAS 0x2C +#define OV9655_ADVFL 0x2D +#define OV9655_ADVFH 0x2E +#define OV9655_YAVE 0x2F +#define OV9655_HSYST 0x30 +#define OV9655_HSYEN 0x31 +#define OV9655_HREF 0x32 +#define OV9655_CHLF 0x33 +#define OV9655_AREF1 0x34 +#define OV9655_AREF2 0x35 +#define OV9655_AREF3 0x36 +#define OV9655_ADC1 0x37 +#define OV9655_ADC2 0x38 +#define OV9655_AREF4 0x39 +#define OV9655_TSLB 0x3A +#define OV9655_COM11 0x3B +#define OV9655_COM12 0x3C +#define OV9655_COM13 0x3D +#define OV9655_COM14 0x3E +#define OV9655_EDGE 0x3F +#define OV9655_COM15 0x40 +#define OV9655_COM16 0x41 +#define OV9655_COM17 0x42 +#define OV9655_MTX1 0x4F +#define OV9655_MTX2 0x50 +#define OV9655_MTX3 0x51 +#define OV9655_MTX4 0x52 +#define OV9655_MTX5 0x53 +#define OV9655_MTX6 0x54 +#define OV9655_BRTN 0x55 +#define OV9655_CNST1 0x56 +#define OV9655_CNST2 0x57 +#define OV9655_MTXS 0x58 +#define OV9655_AWBOP1 0x59 +#define OV9655_AWBOP2 0x5A +#define OV9655_AWBOP3 0x5B +#define OV9655_AWBOP4 0x5C +#define OV9655_AWBOP5 0x5D +#define OV9655_AWBOP6 0x5E +#define OV9655_BLMT 0x5F +#define OV9655_RLMT 0x60 +#define OV9655_GLMT 0x61 +#define OV9655_LCC1 0x62 +#define OV9655_LCC2 0x63 +#define OV9655_LCC3 0x64 +#define OV9655_LCC4 0x65 +#define OV9655_MANU 0x66 +#define OV9655_MANV 0x67 +#define OV9655_MANY 0x68 +#define OV9655_VARO 0x69 +#define OV9655_BD50MAX 0x6A +#define OV9655_DBLV 0x6B +#define OV9655_DNSTH 0x70 +#define OV9655_POIDX 0x72 +#define OV9655_PCKDV 0x73 +#define OV9655_XINDX 0x74 +#define OV9655_YINDX 0x75 +#define OV9655_SLOP 0x7A +#define OV9655_GAM1 0x7B +#define OV9655_GAM2 0x7C +#define OV9655_GAM3 0x7D +#define OV9655_GAM4 0x7E +#define OV9655_GAM5 0x7F +#define OV9655_GAM6 0x80 +#define OV9655_GAM7 0x81 +#define OV9655_GAM8 0x82 +#define OV9655_GAM9 0x83 +#define OV9655_GAM10 0x84 +#define OV9655_GAM11 0x85 +#define OV9655_GAM12 0x86 +#define OV9655_GAM13 0x87 +#define OV9655_GAM14 0x88 +#define OV9655_GAM15 0x89 +#define OV9655_COM18 0x8B +#define OV9655_COM19 0x8C +#define OV9655_COM20 0x8D +#define OV9655_DMLNL 0x92 +#define OV9655_DMLNH 0x93 +#define OV9655_LCC6 0x9D +#define OV9655_LCC7 0x9E +#define OV9655_AECH 0xA1 +#define OV9655_BD50 0xA2 +#define OV9655_BD60 0xA3 +#define OV9655_COM21 0xA4 +#define OV9655_GREEN 0xA6 +#define OV9655_VZST 0xA7 +#define OV9655_REFA8 0xA8 +#define OV9655_REFA9 0xA9 +#define OV9655_BLC1 0xAC +#define OV9655_BLC2 0xAD +#define OV9655_BLC3 0xAE +#define OV9655_BLC4 0xAF +#define OV9655_BLC5 0xB0 +#define OV9655_BLC6 0xB1 +#define OV9655_BLC7 0xB2 +#define OV9655_BLC8 0xB3 +#define OV9655_CTRLB4 0xB4 +#define OV9655_FRSTL 0xB7 +#define OV9655_FRSTH 0xB8 +#define OV9655_ADBOFF 0xBC +#define OV9655_ADROFF 0xBD +#define OV9655_ADGbOFF 0xBE +#define OV9655_ADGrOFF 0xBF +#define OV9655_COM23 0xC4 +#define OV9655_BD60MAX 0xC5 +#define OV9655_COM24 0xC7 +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void OV9655_HW_Init(void); +void OV9655_Reset(void); +void OV9655_ReadID(OV9655_IDTypeDef* OV9655ID); +void OV9655_Init(ImageFormat_TypeDef ImageFormat); +void OV9655_QQVGAConfig(void); +void OV9655_QVGAConfig(void); +void OV9655_BrightnessConfig(uint8_t Brightness); +uint8_t OV9655_WriteReg(uint16_t Addr, uint8_t Data); +uint8_t OV9655_ReadReg(uint16_t Addr); + +#endif /* __DCMI_OV9655_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/lcd_log_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/lcd_log_conf.h new file mode 100644 index 000000000..a60b07be8 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/lcd_log_conf.h @@ -0,0 +1,113 @@ +/** + ****************************************************************************** + * @file DCMI/Camera/lcd_log_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief lcd_log configuration template file. + * This file should be copied to the application folder and modified + * as follows: + * - Rename it to 'lcd_log_conf.h'. + * - Update the name of the LCD header file depending on the EVAL board + * you are using (see line32 below). + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LCD_LOG_CONF_H__ +#define __LCD_LOG_CONF_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval_lcd.h" /* replace 'stm32xxx' with your EVAL board name, ex: stm3210c_eval_lcd.h */ +#include + +/** @addtogroup LCD_LOG + * @{ + */ + +/** @defgroup LCD_LOG + * @brief This file is the + * @{ + */ + + +/** @defgroup LCD_LOG_CONF_Exported_Defines + * @{ + */ +/* Comment the line below to disable the scroll back and forward features */ +#define LCD_SCROLL_ENABLED + +/* Define the LCD default text color */ +#define LCD_LOG_DEFAULT_COLOR LCD_COLOR_WHITE + +/* Define the display window settings */ +#define YWINDOW_MIN 3 +#define YWINDOW_SIZE 12 +#define XWINDOW_MAX 50 + +/* Define the cache depth */ +#define CACHE_SIZE 50 + +/** @defgroup LCD_LOG_CONF_Exported_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup LCD_LOG_Exported_Macros + * @{ + */ + + +/** + * @} + */ + +/** @defgroup LCD_LOG_CONF_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup LCD_LOG_CONF_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ + + +#endif /* __LCD_LOG_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/main.c new file mode 100644 index 000000000..7b4b3f581 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/main.c @@ -0,0 +1,273 @@ +/** + ****************************************************************************** + * @file DCMI/Camera/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "dcmi_ov9655.h" +#include "dcmi_ov2640.h" +#include "lcd_log.h" + +/** @addtogroup stm32f2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DCMI_Camera + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +RCC_ClocksTypeDef RCC_Clocks; +OV9655_IDTypeDef OV9655_Camera_ID; +OV2640_IDTypeDef OV2640_Camera_ID; +__IO uint16_t ADCVal = 0; +uint8_t buffer[40]; +extern Camera_TypeDef Camera; +extern ImageFormat_TypeDef ImageFormat; +extern __IO uint8_t ValueMax; +extern const uint8_t *ImageForematArray[]; + +/* Private function prototypes -----------------------------------------------*/ +void ADC_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* SysTick end of count event each 10ms */ + RCC_GetClocksFreq(&RCC_Clocks); + SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); + + /* Initialize LEDs and push-buttons mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + STM_EVAL_LEDOn(LED1); + + /* Initialize the LCD */ + STM322xG_LCD_Init(); + LCD_Clear(Black); + LCD_SetTextColor(White); + + LCD_LOG_SetHeader("STM32 Camera Demo"); + LCD_LOG_SetFooter (" Copyright (c) STMicroelectronics" ); + + /* ADC configuration */ + ADC_Config(); + + /* Initializes the DCMI interface (I2C and GPIO) used to configure the camera */ + OV2640_HW_Init(); + + /* Read the OV9655/OV2640 Manufacturer identifier */ + OV9655_ReadID(&OV9655_Camera_ID); + OV2640_ReadID(&OV2640_Camera_ID); + + if(OV9655_Camera_ID.PID == 0x96) + { + Camera = OV9655_CAMERA; + sprintf((char*)buffer, "OV9655 Camera ID 0x%x", OV9655_Camera_ID.PID); + ValueMax = 2; + } + else if(OV2640_Camera_ID.PIDH == 0x26) + { + Camera = OV2640_CAMERA; + sprintf((char*)buffer, "OV2640 Camera ID 0x%x", OV2640_Camera_ID.PIDH); + ValueMax = 2; + } + else + { + LCD_SetTextColor(LCD_COLOR_RED); + LCD_DisplayStringLine(LINE(4), "Check the Camera HW and try again"); + while(1); + } + + LCD_SetTextColor(LCD_COLOR_YELLOW); + LCD_DisplayStringLine(LINE(4), (uint8_t*)buffer); + LCD_SetTextColor(LCD_COLOR_WHITE); + Delay(200); + + /* Initialize demo */ + ImageFormat = (ImageFormat_TypeDef)Demo_Init(); + + /* Configure the Camera module mounted on STM322xG-EVAL board */ + Demo_LCD_Clear(); + LCD_DisplayStringLine(LINE(4), "Camera Init.. "); + Camera_Config(); + + sprintf((char*)buffer, " Image selected: %s", ImageForematArray[ImageFormat]); + LCD_DisplayStringLine(LINE(4),(uint8_t*)buffer); + + /* Enable DMA2 stream 1 and DCMI interface then start image capture */ + DMA_Cmd(DMA2_Stream1, ENABLE); + DCMI_Cmd(ENABLE); + + /* Insert 100ms delay: wait 100ms */ + Delay(200); + + DCMI_CaptureCmd(ENABLE); + + LCD_ClearLine(LINE(4)); + Demo_LCD_Clear(); + + if(ImageFormat == BMP_QQVGA) + { + /* LCD Display window */ + LCD_SetDisplayWindow(179, 239, 120, 160); + LCD_WriteReg(LCD_REG_3, 0x1038); + LCD_WriteRAM_Prepare(); + } + else if(ImageFormat == BMP_QVGA) + { + /* LCD Display window */ + LCD_SetDisplayWindow(239, 319, 240, 320); + LCD_WriteReg(LCD_REG_3, 0x1038); + LCD_WriteRAM_Prepare(); + } + + while(1) + { + /* Blink LD1, LED2 and LED4 */ + STM_EVAL_LEDToggle(LED1); + STM_EVAL_LEDToggle(LED2); + STM_EVAL_LEDToggle(LED3); + STM_EVAL_LEDToggle(LED4); + + /* Insert 100ms delay */ + Delay(10); + + /* Get the last ADC3 conversion result data */ + ADCVal = ADC_GetConversionValue(ADC3); + + /* Change the Brightness of camera using "Brightness Adjustment" register: + For OV9655 camera Brightness can be positively (0x01 ~ 0x7F) and negatively (0x80 ~ 0xFF) adjusted + For OV2640 camera Brightness can be positively (0x20 ~ 0x40) and negatively (0 ~ 0x20) adjusted */ + if(Camera == OV9655_CAMERA) + { + OV9655_BrightnessConfig(ADCVal); + } + if(Camera == OV2640_CAMERA) + { + OV2640_BrightnessConfig(ADCVal/2); + } + } +} + +/** + * @brief Configures the ADC. + * @param None + * @retval None + */ +void ADC_Config(void) +{ + ADC_InitTypeDef ADC_InitStructure; + ADC_CommonInitTypeDef ADC_CommonInitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable ADC3 clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE); + + /* GPIOF clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOF, ENABLE); + + /* Configure ADC Channel7 as analog */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; + GPIO_Init(GPIOF, &GPIO_InitStructure); + + /* ADC Common Init */ + ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div6; + ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; + ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; + ADC_CommonInit(&ADC_CommonInitStructure); + + /* ADC3 Configuration ------------------------------------------------------*/ + ADC_StructInit(&ADC_InitStructure); + ADC_InitStructure.ADC_Resolution = ADC_Resolution_8b; + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = ENABLE; + ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfConversion = 1; + ADC_Init(ADC3, &ADC_InitStructure); + + /* ADC3 Regular Channel Config */ + ADC_RegularChannelConfig(ADC3, ADC_Channel_7, 1, ADC_SampleTime_56Cycles); + + /* Enable ADC3 */ + ADC_Cmd(ADC3, ENABLE); + + /* ADC3 regular Software Start Conv */ + ADC_SoftwareStartConv(ADC3); +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/main.h new file mode 100644 index 000000000..801516d49 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/main.h @@ -0,0 +1,47 @@ +/** + ****************************************************************************** + * @file DCMI/Camera/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" +#include "stm322xg_eval_lcd.h" +#include "stm322xg_eval_ioe.h" +#include "camera_api.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/readme.txt new file mode 100644 index 000000000..194915a86 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/readme.txt @@ -0,0 +1,87 @@ +/** + @page DCMI_Camera Camera example Readme file + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file DCMI/Camera/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the stm32f2xx camera example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Description + +This example shows how to use the DCMI to control the OV9655 or OV2640 Camera module +mounted on STM322xG-EVAL board RevB. + +Both cameras have an image array capable of operating at up to 15 frames per second +in SXGA resolution with complete user control over image quality, formatting and +output data transfer. All required image processing functions are also programmable +through the SCCB interface (I2C like protocol). + +In this example the DCMI is configured to interface with this 8 bit data camera +in continuous mode. The I2C1 is used to configure the Camera in 8 bit RGB 5:6:5 mode. +The user can select between two resolutions QQVGA(160x120) or QVGA(320x240) in order +to display the captured image on the LCD(320x240), this selection is performed +at application run time using the Joystick UP, DOWN and SEL buttons. +All camera data received by the DCMI are transferred through the DMA and displayed +on the LCD (connected to FSMC). As a result the CPU is free to execute other tasks. + +You can use the potentiometer RV1 to fine tune on the fly the camera's brightness. + + +@par Project Directory contents + + - DCMI/Camera/main.h Main config file + - DCMI/Camera/camera_api.h Header for camera_api.c + - DCMI/Camera/dcmi_ov2640.h Header for dcmi_ov2640.c + - DCMI/Camera/dcmi_ov9655.h Header for dcmi_ov9655.c + - DCMI/Camera/lcd_lo_conf.h Lcd_log configuration file + - DCMI/Camera/stm32f2xx_it.h Header for stm32f2xx_it.c + - DCMI/Camera/stm32f2xx_conf.h library configuration file + - DCMI/Camera/main.c Main program + - DCMI/Camera/camera_api.c High level driver for OV9655/OV2640 Cameras + - DCMI/Camera/dcmi_ov2640.c Driver for OV2640 Camera module + - DCMI/Camera/dcmi_ov9655.c Driver for OV9655 Camera module + - DCMI/Camera/stm32f2xx_it.c Interrupt handlers + - DCMI/Camera/system_stm32f2xx.c stm32f2xx system clock configuration file + + +@par Hardware and Software environment + - This example runs on stm32f2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB. + + +@par How to use it ? +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\stm32f2xx_StdPeriph_Templates + - Open your preferred toolchain + - Add the following files the project source list + - camera_api.c + - dcmi_ov2640.c + - dcmi_ov9655.c + - Utilities\STM32_EVAL\Common\lcd_log.c + - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/stm32f2xx_conf.h new file mode 100644 index 000000000..6b6d34400 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file DCMI/Camera/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/stm32f2xx_it.c new file mode 100644 index 000000000..ff8ec45ed --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/stm32f2xx_it.c @@ -0,0 +1,241 @@ +/** + ****************************************************************************** + * @file DCMI/Camera/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DCMI_Camera + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern __IO uint32_t PressedKey; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + TimingDelay_Decrement(); +} + +/** + * @brief This function handles External line 10 interrupt request. + * @param None + * @retval None + */ +void EXTI2_IRQHandler(void) +{ + static JOY_State_TypeDef JoyState = JOY_NONE; + + if(EXTI_GetITStatus(IOE_IT_EXTI_LINE) != RESET) + { + if(IOE_GetGITStatus(IOE_2_ADDR, IOE_GIT_GPIO)) + { + /* Get the Joystick State */ + JoyState = IOE_JoyStickGetState(); + + switch (JoyState) + { + case JOY_NONE: + break; + + case JOY_UP: + { + PressedKey = UP; + break; + } + case JOY_DOWN: + { + PressedKey = DOWN; + break; + } + case JOY_RIGHT : + { + PressedKey = JOY_NONE; + break; + } + case JOY_LEFT: + { + PressedKey = JOY_NONE; + break; + } + case JOY_CENTER: + { + PressedKey = SEL; + break; + } + default: + { + PressedKey = JOY_NONE; + LCD_DisplayStringLine(LINE(17), (uint8_t*)" JOY ERROR "); + break; + } + } + } + /* Clear the interrupt pending bits */ + IOE_ClearGITPending(IOE_2_ADDR, IOE_GIT_GPIO); + IOE_ClearIOITPending(IOE_2_ADDR, IOE_JOY_IT); + } + /* Clear interrupt pending bit */ + EXTI_ClearITPendingBit(IOE_IT_EXTI_LINE); +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/stm32f2xx_it.h new file mode 100644 index 000000000..5c629635e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/stm32f2xx_it.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file DCMI/Camera/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void SDIO_IRQHandler(void); +void SD_SDIO_DMA_IRQHANDLER(void); +void DCMI_IRQHandler(void); +void DMA2_Stream1_IRQHandler(void); +void EXTI15_10_IRQHandler(void); +void EXTI2_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DCMI/Camera/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/Complete list of DMA examples.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/Complete list of DMA examples.txt new file mode 100644 index 000000000..2352bafdd --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/Complete list of DMA examples.txt @@ -0,0 +1,52 @@ +/** + @page DMA_EXAMPLES DMA examples List + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file DMA/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief STM32F2xx Standard Peripherals DMA examples List. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +In addition to this example (DMA\FLASH_RAM), other examples uses the DMA: + + *
    + *
  • Complet List of DMA Examples + * - @subpage ADC_ADC3_DMA + * - @subpage DualADC_Interleaved_DMAmode3 + * - @subpage DualADC_RegulSimu_DMAmode1 + * - @subpage TripleADC_Interleaved_DMAmode2 + * - @subpage ADC_VBAT_Measurement + * - @subpage AES_ECBmode_DMA + * - @subpage TDES_ECBmode_DMA + * - @subpage DAC_SignalsGen + * - @subpage DCMI_OV9655_Camera + * - @subpage SHA1_MD5_DMA + * - @subpage I2C_DataExchangeDMA + * - @subpage NVIC_DMA_WFIMode + * - @subpage TIM_DMA + * - @subpage TIM1_DMABURST + * - @subpage USART_DataExchangeDMA + *
+ + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/main.c new file mode 100644 index 000000000..e175c169c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/main.c @@ -0,0 +1,253 @@ +/** + ****************************************************************************** + * @file DMA/FLASH_RAM/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DMA_FLASH_RAM + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO TestStatus TransferStatus = FAILED; + +const uint32_t SRC_Const_Buffer[BUFFER_SIZE]= { + 0x01020304,0x05060708,0x090A0B0C,0x0D0E0F10, + 0x11121314,0x15161718,0x191A1B1C,0x1D1E1F20, + 0x21222324,0x25262728,0x292A2B2C,0x2D2E2F30, + 0x31323334,0x35363738,0x393A3B3C,0x3D3E3F40, + 0x41424344,0x45464748,0x494A4B4C,0x4D4E4F50, + 0x51525354,0x55565758,0x595A5B5C,0x5D5E5F60, + 0x61626364,0x65666768,0x696A6B6C,0x6D6E6F70, + 0x71727374,0x75767778,0x797A7B7C,0x7D7E7F80}; +uint32_t DST_Buffer[BUFFER_SIZE]; + +/* Private function prototypes -----------------------------------------------*/ +void DMA_Config(void); +TestStatus Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Configure LEDs to monitor program status */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + STM_EVAL_LEDOn(LED1); /* Turn LED1 on: start of configuration */ + + /* Configure and enable the DMA Stream for Memory to Memory transfer */ + DMA_Config(); + + STM_EVAL_LEDOn(LED2); /* Turn LED2 on: start of Transfer */ + + /* Wait the end of transmission (the DMA Stream is disabled by Hardware at the + end of the transfer) . + There is also another way to check on end of transfer by monitoring the + number of remaining data to be transferred. */ + /* while (DMA_GetCurrentMemoryTarget(DMA_STREAM) != 0) */ /* First method */ + while (DMA_GetCmdStatus(DMA_STREAM) != DISABLE) /* Second method */ + { + /* + Since this code present a simple example of how to use DMA, it is just + waiting on the end of transfer. + But, while DMA Stream is transferring data, the CPU is free to perform + other tasks in parallel to the DMA transfer. + */ + } + + /* Check if the transmitted and received data are equal */ + TransferStatus = Buffercmp(SRC_Const_Buffer, DST_Buffer, BUFFER_SIZE); + /* TransferStatus = PASSED, if the transmitted and received data + are the same */ + /* TransferStatus = FAILED, if the transmitted and received data + are different */ + + if (TransferStatus != FAILED) + { + /* Turn LED4 on: Transfer correct */ + STM_EVAL_LEDOn(LED4); + } + + while (1) + { + } +} + +/** + * @brief Configure the DMA controller according to the Stream parameters + * defined in main.h file + * @param None + * @retval None + */ +void DMA_Config(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + DMA_InitTypeDef DMA_InitStructure; + __IO uint32_t Timeout = TIMEOUT_MAX; + + /* Enable DMA clock */ + RCC_AHB1PeriphClockCmd(DMA_STREAM_CLOCK, ENABLE); + + /* Reset DMA Stream registers (for debug purpose) */ + DMA_DeInit(DMA_STREAM); + + /* Check if the DMA Stream is disabled before enabling it. + Note that this step is useful when the same Stream is used multiple times: + enabled, then disabled then re-enabled... In this case, the DMA Stream disable + will be effective only at the end of the ongoing data transfer and it will + not be possible to re-configure it before making sure that the Enable bit + has been cleared by hardware. If the Stream is used only once, this step might + be bypassed. */ + while (DMA_GetCmdStatus(DMA_STREAM) != DISABLE) + { + } + + /* Configure DMA Stream */ + DMA_InitStructure.DMA_Channel = DMA_CHANNEL; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SRC_Const_Buffer; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)DST_Buffer; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToMemory; + DMA_InitStructure.DMA_BufferSize = (uint32_t)BUFFER_SIZE; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(DMA_STREAM, &DMA_InitStructure); + + /* Enable DMA Stream Transfer Complete interrupt */ + DMA_ITConfig(DMA_STREAM, DMA_IT_TC, ENABLE); + + /* DMA Stream enable */ + DMA_Cmd(DMA_STREAM, ENABLE); + + /* Check if the DMA Stream has been effectively enabled. + The DMA Stream Enable bit is cleared immediately by hardware if there is an + error in the configuration parameters and the transfer is no started (ie. when + wrong FIFO threshold is configured ...) */ + Timeout = TIMEOUT_MAX; + while ((DMA_GetCmdStatus(DMA_STREAM) != ENABLE) && (Timeout-- > 0)) + { + } + + /* Check if a timeout condition occurred */ + if (Timeout == 0) + { + /* Manage the error: to simplify the code enter an infinite loop */ + while (1) + { + } + } + + /* Enable the DMA Stream IRQ Channel */ + NVIC_InitStructure.NVIC_IRQChannel = DMA_STREAM_IRQ; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +/** + * @brief Compares two buffers. + * @param pBuffer, pBuffer1: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer identical to pBuffer1 + * FAILED: pBuffer differs from pBuffer1 + */ +TestStatus Buffercmp(const uint32_t* pBuffer, uint32_t* pBuffer1, uint16_t BufferLength) +{ + while(BufferLength--) + { + if(*pBuffer != *pBuffer1) + { + return FAILED; + } + + pBuffer++; + pBuffer1++; + } + + return PASSED; +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/main.h new file mode 100644 index 000000000..b84d383c6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/main.h @@ -0,0 +1,56 @@ +/** + ****************************************************************************** + * @file DMA/FLASH_RAM/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* DMA Stream parameters definitions. You can modify these parameters to select + a different DMA Stream and/or channel. + But note that only DMA2 Streams are capable of Memory to Memory transfers. */ +#define DMA_STREAM DMA2_Stream0 +#define DMA_CHANNEL DMA_Channel_0 +#define DMA_STREAM_CLOCK RCC_AHB1Periph_DMA2 +#define DMA_STREAM_IRQ DMA2_Stream0_IRQn +#define DMA_IT_TCIF DMA_IT_TCIF0 +#define DMA_STREAM_IRQHANDLER DMA2_Stream0_IRQHandler + +#define BUFFER_SIZE 32 +#define TIMEOUT_MAX 10000 /* Maximum timeout value */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/readme.txt new file mode 100644 index 000000000..c5738646b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/readme.txt @@ -0,0 +1,107 @@ +/** + @page DMA_FLASH_RAM DMA_FLASH_RAM + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file DMA/FLASH_RAM/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the DMA FLASH to RAM example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a description of how to use a DMA channel to transfer +a word data buffer from FLASH memory to embedded SRAM memory. + +DMA2 Stream0 channel0 is configured to transfer the contents of a 32-word data +buffer stored in Flash memory to the reception buffer declared in RAM. + +The start of transfer is triggered by software. DMA2 Stream0 channel0 memory-to-memory +transfer is enabled. Source and destination addresses incrementing is also enabled. +The transfer is started by setting the Channel enable bit for DMA2 Stream0 channel0. +At the end of the transfer a Transfer Complete interrupt is generated since it +is enabled. The Transfer Complete Interrupt pending bit is then cleared. +When the DMA transfer is completed the DMA Stream is disabled by hardware. +The main application can check on the Stream Enable status to detect the end of +transfer or can also check on the number of remaining transfers which should be +equal to 0 at the end of the transfer. +A comparison between the source and destination buffers is done to check that all +data have been correctly transferred. + +STM32 Eval board's LEDs can be used to monitor the transfer status: + - LED1 is ON when the program starts. + - LED2 is ON when the configuration phase is done and the transfer is started. + - LED3 is ON when the transfer is complete (into the Transfer Complete interrupt + routine) + - LED4 is ON when the comparison result between source buffer and destination + buffer is passed. + +It is possible to select a different Stream and/or channel for the DMA transfer +example by modifying defines values in the file main.h. +Note that only DMA2 Streams are able to perform Memory-to-Memory transfers. + +There are different options to check on the DMA end of transfer: + 1. Use DMA Transfer Complete interrupt. + 2. Use DMA enable state (the DMA stream is disabled by hardware when transfer + is complete). + 3. Use DMA Stream transfer counter value (the counter value is decremented when + transfer is ongoing and is equal to 0 at the transfer end). + 4. Use DMA Transfer Complete flag (polling mode). + +In this example methods 1, 2 and 3 are provided (you can select between method 2 +and 3 by uncommenting relative code in waiting loop in the main.c file). + + +@par Directory contents + + - DMA/FLASH_RAM/system_stm32f2xx.c STM32F2xx system clock configuration file + - DMA/FLASH_RAM/stm32f2xx_conf.h Library Configuration file + - DMA/FLASH_RAM/stm32f2xx_it.c Interrupt handlers + - DMA/FLASH_RAM/stm32f2xx_it.h Interrupt handlers header file + - DMA/FLASH_RAM/main.c Main program + - DMA/FLASH_RAM/main.h Main program header file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/stm32f2xx_conf.h new file mode 100644 index 000000000..b7b188175 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file DMA/FLASH_RAM/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/stm32f2xx_it.c new file mode 100644 index 000000000..8ab771cab --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/stm32f2xx_it.c @@ -0,0 +1,188 @@ +/** + ****************************************************************************** + * @file DMA/FLASH_RAM/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DMA_FLASH_RAM + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles DMA Stream interrupt request. + * @param None + * @retval None + */ +void DMA_STREAM_IRQHANDLER(void) +{ + /* Test on DMA Stream Transfer Complete interrupt */ + if(DMA_GetITStatus(DMA_STREAM, DMA_IT_TCIF)) + { + /* Clear DMA Stream Transfer Complete interrupt pending bit */ + DMA_ClearITPendingBit(DMA_STREAM, DMA_IT_TCIF); + + /* Turn LED3 on: End of Transfer */ + STM_EVAL_LEDOn(LED3); + } +} + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/stm32f2xx_it.h new file mode 100644 index 000000000..d2284d0bd --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/stm32f2xx_it.h @@ -0,0 +1,61 @@ +/** + ****************************************************************************** + * @file DMA/FLASH_RAM/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void DMA_STREAM_IRQHANDLER(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/main.c new file mode 100644 index 000000000..153d2f961 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/main.c @@ -0,0 +1,192 @@ +/** + ****************************************************************************** + * @file EXTI/EXTI_Example/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup EXTI_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +void EXTILine0_Config(void); +void EXTILine15_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + + /* Configure EXTI Line0 (connected to PA0 pin) in interrupt mode */ + EXTILine0_Config(); + + /* Configure EXTI Line15 (connected to PG15 pin) in interrupt mode */ + EXTILine15_Config(); + + /* Generate software interrupt: simulate a falling edge applied on EXTI0 line */ + EXTI_GenerateSWInterrupt(EXTI_Line0); + + while (1) + { + } +} + +/** + * @brief Configures EXTI Line0 (connected to PA0 pin) in interrupt mode + * @param None + * @retval None + */ +void EXTILine0_Config(void) +{ + EXTI_InitTypeDef EXTI_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* Enable GPIOA clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + /* Enable SYSCFG clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + /* Configure PA0 pin as input floating */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Connect EXTI Line0 to PA0 pin */ + SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0); + + /* Configure EXTI Line0 */ + EXTI_InitStructure.EXTI_Line = EXTI_Line0; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Enable and set EXTI Line0 Interrupt to the lowest priority */ + NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +/** + * @brief Configures EXTI Line15 (connected to PG15 pin) in interrupt mode + * @param None + * @retval None + */ +void EXTILine15_Config(void) +{ + EXTI_InitTypeDef EXTI_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* Enable GPIOG clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE); + /* Enable SYSCFG clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + /* Configure PG15 pin as input floating */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* Connect EXTI Line15 to PG15 pin */ + SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOG, EXTI_PinSource15); + + /* Configure EXTI Line15 */ + EXTI_InitStructure.EXTI_Line = EXTI_Line15; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Enable and set EXTI15_10 Interrupt to the lowest priority */ + NVIC_InitStructure.NVIC_IRQChannel = EXTI15_10_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + + NVIC_Init(&NVIC_InitStructure); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/readme.txt new file mode 100644 index 000000000..e9cc76e3a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/readme.txt @@ -0,0 +1,93 @@ +/** + @page EXTI_Example EXTI Configuration Example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file EXTI/EXTI_Example/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the EXTI example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure external interrupt lines. +In this example, 2 EXTI lines (EXTI Line0 and Line15) are configured to generate +an interrupt on each rising and falling edge, respectively. +In the interrupt routine a led connected to a specific GPIO pin is toggled. + +In this example: + - EXTI Line0 is connected to PA0 pin + - EXTI Line15 is connected to PG15 pin + +After EXTI configuration, a software interrupt is generated on the EXTI0 toggles LED1. +After that, + when falling edge is detected on EXTI Line0, LED1 toggles + when falling edge is detected on EXTI Line15, LED2 toggles + +On STM322xG-EVA, + EXTI Line0 is connected to Wakeup push-button + EXTI Line15 is connected to Key push-button + +@note In this example, EXTILine15_Config() function can be substituted by + STM_EVAL_PBInit(Button_KEY, Mode_EXTI) provided in the STM322xG-EVAL driver. + + +@par Directory contents + + - EXTI/EXTI_Example/stm32f2xx_conf.h Library Configuration file + - EXTI/EXTI_Example/stm32f2xx_it.h Interrupt handlers header file + - EXTI/EXTI_Example/stm32f2xx_it.c Interrupt handlers + - EXTI/EXTI_Example/main.c Main program + - EXTI/EXTI_Example/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + - STM322xG-EVAL Set-up + - Use LED1 and LED2 connected respectively to PG.06 and PG.08 + - Use the Key push-button connected to pin PG15 (EXTI Line15) + - Use the Wakeup push-button connected to pin PA0 (EXTI Line0) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/stm32f2xx_conf.h new file mode 100644 index 000000000..502446672 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file EXTI/EXTI_Example/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/stm32f2xx_it.c new file mode 100644 index 000000000..d639eee3b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/stm32f2xx_it.c @@ -0,0 +1,208 @@ +/** + ****************************************************************************** + * @file EXTI/EXTI_Example/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup EXTI_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles External line 0 interrupt request. + * @param None + * @retval None + */ +void EXTI0_IRQHandler(void) +{ + if(EXTI_GetITStatus(EXTI_Line0) != RESET) + { + /* Toggle LED1 */ + STM_EVAL_LEDToggle(LED1); + + /* Clear the EXTI line 0 pending bit */ + EXTI_ClearITPendingBit(EXTI_Line0); + } +} + +/** + * @brief This function handles External lines 15 to 10 interrupt request. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + if(EXTI_GetITStatus(EXTI_Line15) != RESET) + { + /* Toggle LED2 */ + STM_EVAL_LEDToggle(LED2); + + /* Clear the EXTI line 15 pending bit */ + EXTI_ClearITPendingBit(EXTI_Line15); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/stm32f2xx_it.h new file mode 100644 index 000000000..410c0ea5d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file EXTI/EXTI_Example/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/EXTI/EXTI_Example/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/main.c new file mode 100644 index 000000000..6473441b4 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/main.c @@ -0,0 +1,254 @@ +/** + ****************************************************************************** + * @file FLASH/Program/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup FLASH_Program + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Private define ------------------------------------------------------------*/ + +#define FLASH_USER_START_ADDR ADDR_FLASH_SECTOR_2 /* Start @ of user Flash area */ +#define FLASH_USER_END_ADDR ADDR_FLASH_SECTOR_5 /* End @ of user Flash area */ + +/* Base address of the Flash sectors */ +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +#define DATA_32 ((uint32_t)0x12345678) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint32_t StartSector = 0, EndSector = 0, Address = 0, SectorCounter = 0; +__IO uint32_t data32 = 0 , MemoryProgramStatus = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +uint32_t GetSector(uint32_t Address); + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Unlock the Flash to enable the flash control register access *************/ + FLASH_Unlock(); + + /* Erase the user Flash area + (area defined by FLASH_USER_START_ADDR and FLASH_USER_END_ADDR) ***********/ + + /* Clear pending flags (if any) */ + FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR|FLASH_FLAG_PGSERR); + + /* Get the number of the start and end sectors */ + StartSector = GetSector(FLASH_USER_START_ADDR); + EndSector = GetSector(FLASH_USER_END_ADDR); + + for (SectorCounter = StartSector; SectorCounter < EndSector; SectorCounter += 8) + { + /* Device voltage range supposed to be [2.7V to 3.6V], the operation will + be done by word */ + if (FLASH_EraseSector(SectorCounter, VoltageRange_3) != FLASH_COMPLETE) + { + /* Error occurred while sector erase. + User can add here some code to deal with this error */ + while (1) + { + } + } + } + + /* Program the user Flash area word by word + (area defined by FLASH_USER_START_ADDR and FLASH_USER_END_ADDR) ***********/ + + Address = FLASH_USER_START_ADDR; + + while (Address < FLASH_USER_END_ADDR) + { + if (FLASH_ProgramWord(Address, DATA_32) == FLASH_COMPLETE) + { + Address = Address + 4; + } + else + { + /* Error occurred while writing data in Flash memory. + User can add here some code to deal with this error */ + while (1) + { + } + } + } + + /* Lock the Flash to disable the flash control register access (recommended + to protect the FLASH memory against possible unwanted operation) *********/ + FLASH_Lock(); + + + /* Check if the programmed data is OK + MemoryProgramStatus = 0: data programmed correctly + MemoryProgramStatus != 0: number of words not programmed correctly ******/ + Address = FLASH_USER_START_ADDR; + MemoryProgramStatus = 0x0; + + while (Address < FLASH_USER_END_ADDR) + { + data32 = *(__IO uint32_t*)Address; + + if (data32 != DATA_32) + { + MemoryProgramStatus++; + } + + Address = Address + 4; + } + + while (1) + { + } +} + +/** + * @brief Gets the sector of a given address + * @param None + * @retval The sector of a given address + */ +uint32_t GetSector(uint32_t Address) +{ + uint32_t sector = 0; + + if((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0)) + { + sector = FLASH_Sector_0; + } + else if((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1)) + { + sector = FLASH_Sector_1; + } + else if((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2)) + { + sector = FLASH_Sector_2; + } + else if((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3)) + { + sector = FLASH_Sector_3; + } + else if((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4)) + { + sector = FLASH_Sector_4; + } + else if((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5)) + { + sector = FLASH_Sector_5; + } + else if((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6)) + { + sector = FLASH_Sector_6; + } + else if((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7)) + { + sector = FLASH_Sector_7; + } + else if((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8)) + { + sector = FLASH_Sector_8; + } + else if((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9)) + { + sector = FLASH_Sector_9; + } + else if((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10)) + { + sector = FLASH_Sector_10; + } + else/*(Address < FLASH_END_ADDR) && (Address >= ADDR_FLASH_SECTOR_11))*/ + { + sector = FLASH_Sector_11; + } + + return sector; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/readme.txt new file mode 100644 index 000000000..347bcf780 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/readme.txt @@ -0,0 +1,79 @@ +/** + @page FLASH_Program FLASH_Program + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file FLASH/Program/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the FLASH Program example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a description of how to program the STM32F2xx FLASH. + +After Reset, the Flash memory Program/Erase Controller is locked. To unlock it, +the FLASH_Unlock function is used. +Before programming the desired addresses, an erase operation is performed using +the flash erase sector feature. The erase procedure starts with the calculation of +the number of sector to be used. Then all these sectors will be erased one by one by +calling FLASH_EraseSector function. + +Once this operation is finished, the programming operation will be performed by +using the FLASH_ProgramWord function. The written data is then checked and the +result of the programming operation is stored into the MemoryProgramStatus variable. + + +@par Directory contents + + - FLASH/Program/system_stm32f2xx.c STM32F2xx system clock configuration file + - FLASH/Program/stm32f2xx_conf.h Library Configuration file + - FLASH/Program/stm32f2xx_it.c Interrupt handlers + - FLASH/Program/stm32f2xx_it.h Header for stm32f2xx_it.c + - FLASH/Program/main.c Main program + + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + +@par How to use it ? + +In order to make the program work, you must do the following: + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/stm32f2xx_conf.h new file mode 100644 index 000000000..3e0c09d8b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file FLASH/Program/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/stm32f2xx_it.c new file mode 100644 index 000000000..278f64441 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file FLASH/Program/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup FLASH_Program + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx_md.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/stm32f2xx_it.h new file mode 100644 index 000000000..00d5abcaa --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file FLASH/Program/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Program/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/main.c new file mode 100644 index 000000000..d0d8cff09 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/main.c @@ -0,0 +1,194 @@ +/** + ****************************************************************************** + * @file FLASH/Write_Protection/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup FLASH_Write_Protection + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define FLASH_WRP_SECTORS (OB_WRP_Sector_2 | OB_WRP_Sector_3) /* sectors 2 and 3 */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t SectorsWRPStatus = 0xFFF; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Initialize Key Button mounted on STM322xG-EVAL board */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); + + /* Test if Key push-button on STM322xG-EVAL board is pressed */ + if (STM_EVAL_PBGetState(BUTTON_KEY) == 0x00) + { + /* Get FLASH_WRP_SECTORS write protection status */ + SectorsWRPStatus = FLASH_OB_GetWRP() & FLASH_WRP_SECTORS; + + if (SectorsWRPStatus == 0x00) + { + /* If FLASH_WRP_SECTORS are write protected, disable the write protection */ + + /* Enable the Flash option control register access */ + FLASH_OB_Unlock(); + + /* Disable FLASH_WRP_SECTORS write protection */ + FLASH_OB_WRPConfig(FLASH_WRP_SECTORS, DISABLE); + + /* Start the Option Bytes programming process */ + if (FLASH_OB_Launch() != FLASH_COMPLETE) + { + /* User can add here some code to deal with this error */ + while (1) + { + } + } + /* Disable the Flash option control register access (recommended to protect + the option Bytes against possible unwanted operations) */ + FLASH_OB_Lock(); + + /* Get FLASH_WRP_SECTORS write protection status */ + SectorsWRPStatus = FLASH_OB_GetWRP() & FLASH_WRP_SECTORS; + + /* Check if FLASH_WRP_SECTORS write protection is disabled */ + if (SectorsWRPStatus == FLASH_WRP_SECTORS) + { + /* OK, turn ON LED1 */ + STM_EVAL_LEDOn(LED1); + } + else + { + /* KO, turn ON LED3 */ + STM_EVAL_LEDOn(LED3); + } + } + else + { /* If FLASH_WRP_SECTORS are not write protected, enable the write protection */ + + /* Enable the Flash option control register access */ + FLASH_OB_Unlock(); + + /* Enable FLASH_WRP_SECTORS write protection */ + FLASH_OB_WRPConfig(FLASH_WRP_SECTORS, ENABLE); + + /* Start the Option Bytes programming process */ + if (FLASH_OB_Launch() != FLASH_COMPLETE) + { + /* User can add here some code to deal with this error */ + while (1) + { + } + } + + /* Disable the Flash option control register access (recommended to protect + the option Bytes against possible unwanted operations) */ + FLASH_OB_Lock(); + + /* Get FLASH_WRP_SECTORS write protection status */ + SectorsWRPStatus = FLASH_OB_GetWRP() & FLASH_WRP_SECTORS; + + /* Check if FLASH_WRP_SECTORS are write protected */ + if (SectorsWRPStatus == 0x00) + { + /* OK, turn ON LED4 */ + STM_EVAL_LEDOn(LED4); + } + else + { + /* KO, turn ON LED3 */ + STM_EVAL_LEDOn(LED3); + } + } + } + + /* Turn ON LED2 */ + STM_EVAL_LEDOn(LED2); + + while (1) + { + } +} + + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/readme.txt new file mode 100644 index 000000000..3497ba506 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/readme.txt @@ -0,0 +1,85 @@ +/** + @page FLASH_Write_Protection FLASH_Write_Protection + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file FLASH/Write_Protection/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the FLASH Write Protection example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a description of how to enable and disable the write protection +for the STM32F2xx FLASH. + +By maintaining the Key push-button pressed at Reset, the program will check the +write protection status of FLASH_WRP_SECTORS (defined in main.c) + - If FLASH_WRP_SECTORS are write protected, the write protection will be disabled. + Then LED1 will turn ON, if the protection disable operation is done correctly, + otherwise LED3 turns ON. + - If FLASH_WRP_SECTORS are not write protected, the write protection will be enabled. + Then LED4 will turn ON, if the protection enable operation is done correctly, + otherwise LED3 turns ON. + +If after reset the Key push-button is not pressed, the program will simply turn ON LED2. + + +@par Directory contents + + - FLASH/Write_Protection/system_stm32f2xx.c STM32F2xx system clock configuration file + - FLASH/Write_Protection/stm32f2xx_conf.h Library Configuration file + - FLASH/Write_Protection/stm32f2xx_it.c Interrupt handlers + - FLASH/Write_Protection/stm32f2xx_it.h Header for stm32f2xx_it.c + - FLASH/Write_Protection/main.c Main program + + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + - Use the Key push-button connected to pin PG15 (EXTI Line15) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/stm32f2xx_conf.h new file mode 100644 index 000000000..45e4c8f6a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file FLASH/Write_Protection/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/stm32f2xx_it.c new file mode 100644 index 000000000..7ed8bf9b1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file FLASH/Write_Protection/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup FLASH_Write_Protection + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx_md.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/stm32f2xx_it.h new file mode 100644 index 000000000..83b961efe --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file FLASH/Write_Protection/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/main.c new file mode 100644 index 000000000..49e6d8633 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/main.c @@ -0,0 +1,256 @@ +/** + ****************************************************************************** + * @file FSMC/OneNAND/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" +#include "stm322xg_eval_fsmc_onenand.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup FSMC_OneNAND + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define OneNAND_SAMSUNG_MANUFACTURER_ID 0x00EC +#define OneNAND_SAMSUNG_DEVICE_ID 0x0025 + +#define OneNAND_BUFFER_SIZE 0x0400 /* Page size: 1024 x 16 bits = 2048 Bytes */ +#define OneNAND_WRITE_BLOCK_NUMBER 0x0000 /* should be between 0 and 511, the block size is 128 KBytes */ +#define OneNAND_WRITE_PAGE_NUMBER 0x0000 /* The page size inside a Block is 2 KBytes */ +#define OneNAND_NUMBER_OF_PAGE_PER_BLOCK 0x0040 /* 64 pages per block */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +OneNAND_IDTypeDef OneNAND_ID; +OneNAND_ADDRESS Address; +uint16_t TxBuffer[OneNAND_BUFFER_SIZE], RxBuffer_A[OneNAND_BUFFER_SIZE], RxBuffer_S[OneNAND_BUFFER_SIZE]; +uint32_t Counter = 0, PageIndex = 0, Status = 0; + +/* Private function prototypes -----------------------------------------------*/ +void Fill_hBuffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset); + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* FSMC Initialization */ + OneNAND_Init(); + + /* Read OneNAND memory ID */ + OneNAND_ReadID(&OneNAND_ID); + + /* Verify the OneNAND ID */ + if((OneNAND_ID.Manufacturer_ID == OneNAND_SAMSUNG_MANUFACTURER_ID) && + (OneNAND_ID.Device_ID == OneNAND_SAMSUNG_DEVICE_ID)) + { + /* Fill the buffer to send */ + Fill_hBuffer(TxBuffer, OneNAND_BUFFER_SIZE , 0x320F); + Address.Block = OneNAND_WRITE_BLOCK_NUMBER; + Address.Page = OneNAND_WRITE_PAGE_NUMBER; + + /***** Erase then write to the OneNAND memory ******************************/ + /* Unlock the selected OneNAND block */ + Status = OneNAND_UnlockBlock(OneNAND_WRITE_BLOCK_NUMBER); + + if (Status == 0) + { + /* Erase the selected OneNAND block */ + Status = OneNAND_EraseBlock(Address.Block); + + if (Status == 0) + { + /* Write data to the OneNAND memory (128Kbytes by page 2KBytes each) */ + for(PageIndex = 0; (PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK) && (Status ==0); PageIndex++) + { + Status = OneNAND_WriteBuffer(TxBuffer, Address, OneNAND_BUFFER_SIZE); + Address.Page++; + } + + if (Status == 0) + { + /***** Verify of the written data using asynchronous read ***********/ + Fill_hBuffer(RxBuffer_A, OneNAND_BUFFER_SIZE , 0xFF); + Status = 0; + Address.Block = OneNAND_WRITE_BLOCK_NUMBER; + Address.Page = OneNAND_WRITE_PAGE_NUMBER; + + for(PageIndex = 0; PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK; PageIndex++) + { + /* Read back the written data (By page) */ + OneNAND_AsynchronousRead(RxBuffer_A, Address, OneNAND_BUFFER_SIZE); + + /* Verify the written data */ + for(Counter = 0; Counter < OneNAND_BUFFER_SIZE; Counter++) + { + if(TxBuffer[Counter] != RxBuffer_A[Counter]) + { + Status++; + } + } + Address.Page++; + } + + if (Status != 0) + { + /* Turn ON LED2 */ + STM_EVAL_LEDOn(LED2); + } + + /***** Verify of the written data using synchronous read ************/ + Fill_hBuffer(RxBuffer_S, OneNAND_BUFFER_SIZE , 0xFF); + Status = 0; + Address.Block = OneNAND_WRITE_BLOCK_NUMBER; + Address.Page = OneNAND_WRITE_PAGE_NUMBER; + + for(PageIndex = 0; PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK; PageIndex++) + { + /* Read back the written data (By page) */ + OneNAND_SynchronousRead(RxBuffer_S, Address, OneNAND_BUFFER_SIZE); + + /* Verify the written data */ + for(Counter = 0; Counter < OneNAND_BUFFER_SIZE; Counter++) + { + if(TxBuffer[Counter] != RxBuffer_S[Counter]) + { + Status++; + } + } + Address.Page++; + } + + if (Status != 0) + { + /* Turn ON LED3 */ + STM_EVAL_LEDOn(LED3); + } + } + else + { + /* Turn ON LED4 */ + STM_EVAL_LEDOn(LED4); + } + } + else + { + /* Turn ON LED2 and LED4*/ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED4); + } + } + else + { + /* Turn ON LED3 and LED4 */ + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + } + } + else + { + /* Turn ON LED2, LED3 and LED4 */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + } + + if (Status == 0) + { + /* Turn ON LED1 */ + STM_EVAL_LEDOn(LED1); + } + + /* Infinite loop */ + while (1) + { + } +} + +/** + * @brief Fills a global 16-bit buffer with user predefined data. + * @param pBuffer: pointer on the buffer to fill + * @param BufferSize: size of the buffer to fill + * @param Offset: first value to fill on the buffer + * @retval None + */ +void Fill_hBuffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset) +{ + uint16_t IndexTmp = 0; + + /* Put in global buffer different values */ + for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ ) + { + pBuffer[IndexTmp] = IndexTmp + Offset; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/readme.txt new file mode 100644 index 000000000..5748f315c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/readme.txt @@ -0,0 +1,78 @@ +/** + @page FSMC_OneNAND How to configure the FSMC to drive the OneNAND memory + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file FSMC/OneNAND/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the FSMC OneNAND example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the FSMC to drive the KFG1216U2A/B-DIB6 OneNAND +memory mounted on STM322xG-EVAL evaluation board(MB786) RevA. + +@note This memory is not available on STM322xG-EVAL board RevB. + +In this example a basic example of how to use the FSMC firmware library and +an associate driver to perform read/write operations on the KFG1216U2A OneNAND +memory. + + +@par Directory contents + + - FSMC/OneNAND/system_stm32f2xx.c STM32F2xx system clock configuration file + - FSMC/OneNAND/stm32f2xx_conf.h Library Configuration file + - FSMC/OneNAND/stm32f2xx_it.c Interrupt handlers + - FSMC/OneNAND/stm32f2xx_it.h Header for stm32f2xx_it.c + - FSMC/OneNAND/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + @note The STM322xG-EVAL board RevA was wrongly named STM3220F-EVAL + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Add the "stm322xg_eval_fsmc_onenand.c" file (under Utilities\STM32_EVAL\STM322xG_EVAL) + to the project source list + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/stm32f2xx_conf.h new file mode 100644 index 000000000..ba4a9be5c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file FSMC/OneNAND/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/stm32f2xx_it.c new file mode 100644 index 000000000..a85a5c699 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/stm32f2xx_it.c @@ -0,0 +1,174 @@ +/** + ****************************************************************************** + * @file FSMC/OneNAND/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup FSMC_OneNAND + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/stm32f2xx_it.h new file mode 100644 index 000000000..28fddd414 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file FSMC/OneNAND/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/OneNAND/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/main.c new file mode 100644 index 000000000..027b418ce --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/main.c @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file FSMC/SRAM/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" +#include "stm322xg_eval_fsmc_sram.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup FSMC_SRAM + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define BUFFER_SIZE 0x100 +#define WRITE_READ_ADDR 0x800 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint16_t TxBuffer[BUFFER_SIZE], RxBuffer[BUFFER_SIZE]; +__IO uint32_t WriteReadStatus = 0; +uint32_t Index = 0; + +/* Private function prototypes -----------------------------------------------*/ +void Fill_Buffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset); + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + + + /* Configure FSMC Bank 1 NOR/SRAM2 */ + SRAM_Init(); + + /* Write data to FSMC SRAM memory */ + /* Fill the buffer to send */ + Fill_Buffer(TxBuffer, BUFFER_SIZE, 0x320F); + SRAM_WriteBuffer(TxBuffer, WRITE_READ_ADDR, BUFFER_SIZE); + + /* Read data from FSMC SRAM memory */ + SRAM_ReadBuffer(RxBuffer, WRITE_READ_ADDR, BUFFER_SIZE); + + /* Read back SRAM memory and check content correctness */ + for (Index = 0x00; (Index < BUFFER_SIZE) && (WriteReadStatus == 0); Index++) + { + if (RxBuffer[Index] != TxBuffer[Index]) + { + WriteReadStatus++; + } + } + + if (WriteReadStatus == 0) + { + /* OK */ + /* Turn on LD1 */ + STM_EVAL_LEDOn(LED1); + } + else + { + /* KO */ + /* Turn on LD2 */ + STM_EVAL_LEDOn(LED2); + } + + while (1) + { + } +} + +/** + * @brief Fills buffer with user predefined data. + * @param pBuffer: pointer on the buffer to fill + * @param BufferLenght: size of the buffer to fill + * @param Offset: first value to fill on the buffer + * @retval None + */ +void Fill_Buffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset) +{ + uint16_t IndexTmp = 0; + + /* Put in global buffer different values */ + for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ ) + { + pBuffer[IndexTmp] = IndexTmp + Offset; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/readme.txt new file mode 100644 index 000000000..2820248d5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/readme.txt @@ -0,0 +1,76 @@ +/** + @page FSMC_SRAM How to configure the FSMC to drive the SRAM memory + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file FSMC/SRAM/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the FSMC SRAM example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the FSMC to drive the CY7C1071DV33-12BAXI SRAM +memory mounted on STM322xG-EVAL evaluation board(MB786) RevB. + +In this example a basic example of how to use the FSMC firmware library and +an associate driver to perform read/write operations on the CY7C1071DV33 SRAM memory. + +@note This SRAM memory is not available on STM322xG-EVAL board RevA. + + +@par Directory contents + + - FSMC/SRAM/system_stm32f2xx.c STM32F2xx system clock configuration file + - FSMC/SRAM/stm32f2xx_conf.h Library Configuration file + - FSMC/SRAM/stm32f2xx_it.c Interrupt handlers + - FSMC/SRAM/stm32f2xx_it.h Header for stm32f2xx_it.c + - FSMC/SRAM/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + @note The STM322xG-EVAL board RevA was wrongly named STM3220F-EVAL + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/stm32f2xx_conf.h new file mode 100644 index 000000000..3236a11ce --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file FSMC/SRAM/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/stm32f2xx_it.c new file mode 100644 index 000000000..a0b18f482 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/stm32f2xx_it.c @@ -0,0 +1,174 @@ +/** + ****************************************************************************** + * @file FSMC/SRAM/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup FSMC_SRAM + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/stm32f2xx_it.h new file mode 100644 index 000000000..4d2dc7933 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file FSMC/SRAM/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c new file mode 100644 index 000000000..67fcb5ecb --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file FSMC/SRAM_DataMemory/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup FSMC_SRAM_DataMemory + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint32_t Tab[1024], Index; +__IO uint32_t TabAddr, MSPValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + for (Index = 0; Index <1024 ; Index++) + { + Tab[Index] =Index; + } + + TabAddr = (uint32_t)Tab; /* should be 0x640xxxxx */ + + /* Get main stack pointer value */ + MSPValue = __get_MSP(); /* should be 0x640xxxxx */ + + while (1) + { + } +} + +/** + * @brief Fills buffer with user predefined data. + * @param pBuffer: pointer on the buffer to fill + * @param BufferLenght: size of the buffer to fill + * @param Offset: first value to fill on the buffer + * @retval None + */ +void Fill_Buffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset) +{ + uint16_t IndexTmp = 0; + + /* Put in global buffer different values */ + for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ ) + { + pBuffer[IndexTmp] = IndexTmp + Offset; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/readme.txt new file mode 100644 index 000000000..0c7a1c395 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/readme.txt @@ -0,0 +1,106 @@ +/** + @page FSMC_SRAM_DataMemory FSMC SRAM DataMemory example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file FSMC/SRAM_DataMemory/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the FSMC SRAM DataMemory example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to use the external SRAM mounted on STM322xG-EVAL RevB +as program data memory (including heap and stack). +The example scenario doesn't reflect a real application case; its purpose is to +provide only the procedure to follow to use the external SRAM as data memory. + +This example doesn't use the default library startup files, it uses startup files +provided within this folder. + +@note This SRAM memory is not available on STM322xG-EVAL board RevA. + + +@par Directory contents + + - FSMC/SRAM_DataMemory/system_stm32f2xx.c STM32F2xx system clock configuration file + - FSMC/SRAM_DataMemory/stm32f2xx_conf.h Library Configuration file + - FSMC/SRAM_DataMemory/stm32f2xx_it.c Interrupt handlers + - FSMC/SRAM_DataMemory/stm32f2xx_it.h Header for stm32f2xx_it.c + - FSMC/SRAM_DataMemory/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + @note The STM322xG-EVAL board RevA was wrongly named STM3220F-EVAL + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Update your project settings as follows: +
    +
  • MDK-ARM + - in Project->Options for Target window, select 'RAM1'and enter 0x64000000 + as start address with size of 0x100000 (IRAM1 must be un-checked) + - uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f2xx.c" file + +
  • EWARM + - use "stm32f2xx_flash_extsram.icf" as linker file (under Project\STM32F2xx_StdPeriph_Template\EWARM) + - uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f2xx.c" file + +
  • RIDE + - In the Application options -> script menu, set "Use Default Script File" + to "No" and use "stm32f2xx_flash_extsram.ld" as Script File. + - uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f2xx.c" file + +
  • TASKING + - In the project workspace window, open the stm32f2xx.lsl file. + - From the memory window, select rom and enter and enter 0x64000000 + as address with size of 1024k. + - uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f2xx.c" file + +
  • TrueSTUDIO + - In the project properties window, select 'C/C++ Build'->settings node then + the 'C Linker'->General node and use "stm32f2xx_flash_extsram.ld" as Script File. + - uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f2xx.c" file + +
+ - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/EWARM/startup_stm32f2xx.s b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/EWARM/startup_stm32f2xx.s new file mode 100644 index 000000000..20442e8be --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/EWARM/startup_stm32f2xx.s @@ -0,0 +1,630 @@ +;/******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f2xx.s +;* Author : MCD Application Team +;* Version : V1.1.0 +;* Date : 13-April-2012 +;* Description : STM32F2xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure he external SRAM mounted on STM322xG-EVAL board +;* to be used as data memory (optional, to be enabled by user) +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +;* You may not use this file except in compliance with the License. +;* You may obtain a copy of the License at: +;* +;* http://www.st.com/software_license_agreement_liberty_v2 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;* +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + +__initial_spTop EQU 0x20000400 ; stack used for SystemInit & SystemInit_ExtMemCtl + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD __initial_spTop ; Use internal RAM for stack for calling SystemInit + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =sfe(CSTACK) ; restore original stack pointer + MSR MSP, R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:REORDER(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/MDK-ARM/startup_stm32f2xx.s b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/MDK-ARM/startup_stm32f2xx.s new file mode 100644 index 000000000..41138de4c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/MDK-ARM/startup_stm32f2xx.s @@ -0,0 +1,429 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f2xx.s +;* Author : MCD Application Team +;* Version : V1.1.0 +;* Date : 13-April-2012 +;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +__initial_spTop EQU 0x20000400 ; stack used for SystemInit & SystemInit_ExtMemCtl + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_spTop ; use internal RAM for stack for calling SystemInit + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__initial_sp ; restore original stack pointer + MSR MSP, R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/RIDE/startup_stm32f2xx.s b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/RIDE/startup_stm32f2xx.s new file mode 100644 index 000000000..984902070 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/RIDE/startup_stm32f2xx.s @@ -0,0 +1,516 @@ +/** + ****************************************************************************** + * @file startup_stm32f2xx.s + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief STM32F2xx Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM322xG-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/* Stack used for SystemInit & SystemInit_ExtMemCtl*/ +.equ __initial_spTop, 0x20000400 + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Restore original stack pointer. */ + ldr r0, =_estack + msr MSP, r0 +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word __initial_spTop /* Use internal RAM for stack for calling SystemInit. */ + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/TASKING/cstart_thumb2.asm b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/TASKING/cstart_thumb2.asm new file mode 100644 index 000000000..0516dd661 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/TASKING/cstart_thumb2.asm @@ -0,0 +1,153 @@ + + +;; NOTE: To allow the use of this file for both ARMv6M and ARMv7M, +;; we will only use 16-bit Thumb intructions. + + .extern _lc_ub_stack ; usr/sys mode stack pointer + .extern _lc_ue_stack ; symbol required by debugger + .extern _lc_ub_table ; ROM to RAM copy table + .extern main + .extern _Exit + .extern exit + .weak exit + .global __get_argcv + .weak __get_argcv + .extern __argcvbuf + .weak __argcvbuf + ;;.extern __init_hardware + .extern __init_vector_table + .extern SystemInit + +__initial_spTop .equ 0x20000400 + + .if @defined('__PROF_ENABLE__') + .extern __prof_init + .endif + .if @defined('__POSIX__') + .extern posix_main + .extern _posix_boot_stack_top + .endif + + .global _START + + .section .text.cstart + + .thumb +_START: + ;; anticipate possible ROM/RAM remapping + ;; by loading the 'real' program address + ldr r1,=_Next + bx r1 +_Next: + + + + LDR R0, =__initial_spTop ; use internal RAM for stack for calling SystemInit + MSR MSP, R0 + + + + + bl SystemInit + + ;; initialize the stack pointer + ldr r1,=_lc_ub_stack ; TODO: make this part of the vector table + mov sp,r1 + + ;; copy initialized sections from ROM to RAM + ;; and clear uninitialized data sections in RAM + + ldr r3,=_lc_ub_table + movs r0,#0 +cploop: + ldr r4,[r3,#0] ; load type + ldr r5,[r3,#4] ; dst address + ldr r6,[r3,#8] ; src address + ldr r7,[r3,#12] ; size + + cmp r4,#1 + beq copy + cmp r4,#2 + beq clear + b done + +copy: + subs r7,r7,#1 + ldrb r1,[r6,r7] + strb r1,[r5,r7] + bne copy + + adds r3,r3,#16 + b cploop + +clear: + subs r7,r7,#1 + strb r0,[r5,r7] + bne clear + + adds r3,r3,#16 + b cploop + +done: + ;; initialize or copy the vector table + bl __init_vector_table + + .if @defined('__POSIX__') + + ;; posix stack buffer for system upbringing + ldr r0,=_posix_boot_stack_top + ldr r0, [r0] + mov sp,r0 + + .else + + ;; load r10 with end of USR/SYS stack, which is + ;; needed in case stack overflow checking is on + ;; NOTE: use 16-bit instructions only, for ARMv6M + ldr r0,=_lc_ue_stack + mov r10,r0 + + .endif + + .if @defined('__PROF_ENABLE__') + bl __prof_init + .endif + + .if @defined('__POSIX__') + ;; call posix_main with no arguments + bl posix_main + .else + ;; retrieve argc and argv (default argv[0]==NULL & argc==0) + bl __get_argcv + ldr r1,=__argcvbuf + ;; call main + bl main + .endif + + ;; call exit using the return value from main() + ;; Note. Calling exit will also run all functions + ;; that were supplied through atexit(). + bl exit + +__get_argcv: ; weak definition + movs r0,#0 + bx lr + + .ltorg + .endsec + + .calls '_START', ' ' + .calls '_START','__init_vector_table' + .if @defined('__PROF_ENABLE__') + .calls '_START','__prof_init' + .endif + .if @defined('__POSIX__') + .calls '_START','posix_main' + .else + .calls '_START','__get_argcv' + .calls '_START','main' + .endif + .calls '_START','exit' + .calls '_START','',0 + + .end diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/TrueSTUDIO/startup_stm32f2xx.s b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/TrueSTUDIO/startup_stm32f2xx.s new file mode 100644 index 000000000..74b82a9a0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/startup/TrueSTUDIO/startup_stm32f2xx.s @@ -0,0 +1,518 @@ +/** + ****************************************************************************** + * @file startup_stm32f2xx.s + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief STM32F2xx Devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system and the external SRAM mounted on + * STM322xG-EVAL board to be used as data memory (optional, + * to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/* stack used for SystemInit & SystemInit_ExtMemCtl*/ +.equ __initial_spTop, 0x20000400 + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call static constructors */ + bl __libc_init_array +/* Restore original stack pointer. */ + ldr r0, =_estack + msr MSP, r0 +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word __initial_spTop /* Use internal RAM for stack for calling SystemInit. */ + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f2xx_conf.h new file mode 100644 index 000000000..007d4b136 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file FSMC/SRAM_DataMemory/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f2xx_it.c new file mode 100644 index 000000000..e95fe2a2a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f2xx_it.c @@ -0,0 +1,174 @@ +/** + ****************************************************************************** + * @file FSMC/SRAM_DataMemory/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup FSMC_SRAM_DataMemory + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f2xx_it.h new file mode 100644 index 000000000..bde3933f9 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file FSMC/SRAM_DataMemory/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f2xx.c new file mode 100644 index 000000000..ee7aa6b0d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +#define DATA_IN_ExtSRAM + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/main.c new file mode 100644 index 000000000..7d1e96dce --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/main.c @@ -0,0 +1,174 @@ +/** + ****************************************************************************** + * @file GPIO/IOToggle/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup IOToggle + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +GPIO_InitTypeDef GPIO_InitStructure; + +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* GPIOG Periph clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE); + + /* Configure PG6 and PG8 in output pushpull mode */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_8; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* To achieve GPIO toggling maximum frequency, the following sequence is mandatory. + You can monitor PG6 or PG8 on the scope to measure the output signal. + If you need to fine tune this frequency, you can add more GPIO set/reset + cycles to minimize more the infinite loop timing. + This code needs to be compiled with high speed optimization option. */ + while (1) + { + /* Set PG6 and PG8 */ + GPIOG->BSRRL = GPIO_Pin_6 | GPIO_Pin_8; + /* Reset PG6 and PG8 */ + GPIOG->BSRRH = GPIO_Pin_6 | GPIO_Pin_8; + + /* Set PG6 and PG8 */ + GPIOG->BSRRL = GPIO_Pin_6 | GPIO_Pin_8; + /* Reset PG6 and PG8 */ + GPIOG->BSRRH = GPIO_Pin_6 | GPIO_Pin_8; + + /* Set PG6 and PG8 */ + GPIOG->BSRRL = GPIO_Pin_6 | GPIO_Pin_8; + /* Reset PG6 and PG8 */ + GPIOG->BSRRH = GPIO_Pin_6 | GPIO_Pin_8; + + /* Set PG6 and PG8 */ + GPIOG->BSRRL = GPIO_Pin_6 | GPIO_Pin_8; + /* Reset PG6 and PG8 */ + GPIOG->BSRRH = GPIO_Pin_6 | GPIO_Pin_8; + + /* Set PG6 and PG8 */ + GPIOG->BSRRL = GPIO_Pin_6 | GPIO_Pin_8; + /* Reset PG6 and PG8 */ + GPIOG->BSRRH = GPIO_Pin_6 | GPIO_Pin_8; + + /* Set PG6 and PG8 */ + GPIOG->BSRRL = GPIO_Pin_6 | GPIO_Pin_8; + /* Reset PG6 and PG8 */ + GPIOG->BSRRH = GPIO_Pin_6 | GPIO_Pin_8; + + /* Set PG6 and PG8 */ + GPIOG->BSRRL = GPIO_Pin_6 | GPIO_Pin_8; + /* Reset PG6 and PG8 */ + GPIOG->BSRRH = GPIO_Pin_6 | GPIO_Pin_8; + + /* Set PG6 and PG8 */ + GPIOG->BSRRL = GPIO_Pin_6 | GPIO_Pin_8; + /* Reset PG6 and PG8 */ + GPIOG->BSRRH = GPIO_Pin_6 | GPIO_Pin_8; + + /* Set PG6 and PG8 */ + GPIOG->BSRRL = GPIO_Pin_6 | GPIO_Pin_8; + /* Reset PG6 and PG8 */ + GPIOG->BSRRH = GPIO_Pin_6 | GPIO_Pin_8; + + /* Set PG6 and PG8 */ + GPIOG->BSRRL = GPIO_Pin_6 | GPIO_Pin_8; + /* Reset PG6 and PG8 */ + GPIOG->BSRRH = GPIO_Pin_6 | GPIO_Pin_8; + } +} + +/** + * @brief Delay Function. + * @param nCount:specifies the Delay time length. + * @retval None + */ +void Delay(__IO uint32_t nCount) +{ + while(nCount--) + { + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/readme.txt new file mode 100644 index 000000000..d7417a152 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/readme.txt @@ -0,0 +1,85 @@ +/** + @page GPIO_IOToggle GPIO IO Toggle example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file GPIO/IOToggle/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the GPIO IO Toggle example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +GPIO ports are connected on AHB bus, using BSRRH and BSRRL registers one cycle is +required to set a pin and another cycle to reset it. So GPIO pins can toggle at +AHB clock divided by 2. + +This example describes how to use BSRRH and BSRRL (Port Bit Set/Reset Register +High and Low) for maximum IO toggling. + +PG6 and PG8 (configured in output pushpull mode) toggles in a forever loop: + - Set PG6 and PG8 by setting corresponding bits in BSRRL register + - Reset PG6 and PG8 by setting corresponding bits in BSRRH register + +In this example, HCLK is configured at 120 MHz so PG6 and PG8 toggles at 60MHz. +To achieve the maximum IO toggling frequency, you have to configure your compiler +options for high speed optimization. + + +@par Directory contents + + - GPIO/IOToggle/stm32f2xx_conf.h Library Configuration file + - GPIO/IOToggle/stm32f2xx_it.c Interrupt handlers + - GPIO/IOToggle/stm32f2xx_it.h Interrupt handlers header file + - GPIO/IOToggle/main.c Main program + - GPIO/IOToggle/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + - STM322xG-EVAL Set-up + - Use LED1 and LED2 connected respectively to PG.06 and PG.08 + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/stm32f2xx_conf.h new file mode 100644 index 000000000..577f1dc1e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file GPIO/IOToggle/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/stm32f2xx_it.c new file mode 100644 index 000000000..c0d5babc0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file GPIO/IOToggle/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup IOToggle + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/stm32f2xx_it.h new file mode 100644 index 000000000..0be12270b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file GPIO/IOToggle/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/IOToggle/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/main.c new file mode 100644 index 000000000..665c83b57 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/main.c @@ -0,0 +1,172 @@ +/** + ****************************************************************************** + * @file GPIO/JTAG_Remap/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup GPIO_JTAG_Remap + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +GPIO_InitTypeDef GPIO_InitStructure; + +/* Private function prototypes -----------------------------------------------*/ +void Delay(__IO uint32_t nCount); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs and Key Button mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); + + /* Test if Key push-button on STM322xG-EVAL board is pressed */ + if (STM_EVAL_PBGetState(BUTTON_KEY) == 0x00) + { /* Key is pressed */ + + /* Enable GPIOA and GPIOB clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB , ENABLE); + + /* Turn on LED1 */ + STM_EVAL_LEDOn(LED1); + + /* Configure PA.13 (JTMS/SWDIO), PA.14 (JTCK/SWCLK) and PA.15 (JTDI) as + output push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Configure PB.03 (JTDO) and PB.04 (JTRST) as output push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + while (1) + { + /* Toggle JTMS/SWDAT pin */ + GPIO_WriteBit(GPIOA, GPIO_Pin_13, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOA, GPIO_Pin_13))); + /* Insert delay */ + Delay(0x5FFFF); + + /* Toggle JTCK/SWCLK pin */ + GPIO_WriteBit(GPIOA, GPIO_Pin_14, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOA, GPIO_Pin_14))); + /* Insert delay */ + Delay(0x5FFFF); + + /* Toggle JTDI pin */ + GPIO_WriteBit(GPIOA, GPIO_Pin_15, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOA, GPIO_Pin_15))); + /* Insert delay */ + Delay(0x5FFFF); + + /* Toggle JTDO pin */ + GPIO_WriteBit(GPIOB, GPIO_Pin_3, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOB, GPIO_Pin_3))); + /* Insert delay */ + Delay(0x5FFFF); + + /* Toggle JTRST pin */ + GPIO_WriteBit(GPIOB, GPIO_Pin_4, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOB, GPIO_Pin_4))); + /* Insert delay */ + Delay(0x5FFFF); + } + } + else + { + /* Turn on LED2 */ + STM_EVAL_LEDOn(LED2); + + while (1) + { + } + } +} + +/** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + */ +void Delay(__IO uint32_t nCount) +{ + for(; nCount != 0; nCount--); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/readme.txt new file mode 100644 index 000000000..66ebfaace --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/readme.txt @@ -0,0 +1,82 @@ +/** + @page GPIO_JTAG_Remap GPIO JTAG/SWD Remap example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file GPIO/JTAG_Remap/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the GPIO JTAG/SWD Remap example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the JTAG/SWD IOs as standard +GPIOs and gives a configuration sequence. + +Note that once the JTAG/SWD IOs are disabled, the connection with the host debugger is +lost and cannot be re-established as long as the JTAG/SWD IOs remain disabled. +To avoid this situation, the Key push-button is used to disable or not the JTAG/SWD IOs: + 1. Key push-button maintained pressed at reset: JTAG/SWD IOs disabled and LED1 turned ON + 2. Key push-button not pressed at reset: JTAG/SWD IOs unchanged and LED2 turned ON + +Before starting this example, you should disconnect your JTAG/SWD probe and run +the example in stand-alone mode. + + +@par Directory contents + + - GPIO/JTAG_Remap/system_stm32f2xx.c STM32F2xx system clock configuration file + - GPIO/JTAG_Remap/stm32f2xx_conf.h Library Configuration file + - GPIO/JTAG_Remap/stm32f2xx_it.c Interrupt handlers + - GPIO/JTAG_Remap/stm32f2xx_it.h Header for stm32f2xx_it.c + - GPIO/JTAG_Remap/main.c Main program + + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + - STM322xG-EVAL Set-up + - Use LED1 and LED2 connected respectively to PG.06 and PG.08 + - Use the Key push-button connected to pin PG15 (EXTI Line15) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f2xx_conf.h new file mode 100644 index 000000000..acc75663e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file GPIO/JTAG_Remap/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f2xx_it.c new file mode 100644 index 000000000..81389380e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file GPIO/JTAG_Remap/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup GPIO_JTAG_Remap + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f2xx_it.h new file mode 100644 index 000000000..10e0f77ca --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file GPIO/JTAG_Remap/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/Expected_Results.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/Expected_Results.txt new file mode 100644 index 000000000..bed5f5a77 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/Expected_Results.txt @@ -0,0 +1,57 @@ + ====================================== + ==== Context Swap Example ==== + ====================================== + + --------------------------------------- + MD5 Text to be Hashed : + --------------------------------------- + The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.*** STM32 ***The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.*** STM32 ***The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.*** STM32 *** + + --------------------------------------- + SHA1 Text to be Hashed : + --------------------------------------- +testing123 + +>> MD5 Digest Computation without context swap +>>> Start +>>> Done + --------------------------------------- + MD5 Message Digest (128 bits): + --------------------------------------- + A = [0x8aea9a70] + B = [0x04fc0592] + C = [0xc81dce1b] + D = [0xabe64da6] + +>> SHA1 Digest Computation without context swap +>>> Start +>>> Done + --------------------------------------- + SHA1 Message Digest (160 bits): + --------------------------------------- + H0 = [0x4c0d2b95] + H1 = [0x1ffabd6f] + H2 = [0x9a10489d] + H3 = [0xc40fc356] + H4 = [0xec1d26d5] + +>> MD5 Digest Computation with context swap +>>> Start + ====> During MD5 digest calculation, the context is saved and restored (15) times to calculate the SHA1 digest +>>> Done + --------------------------------------- + MD5 Message Digest (128 bits): + --------------------------------------- + A = [0x8aea9a70] + B = [0x04fc0592] + C = [0xc81dce1b] + D = [0xabe64da6] +>> SHA1 Digest computed during MD5 context swap + --------------------------------------- + SHA1 Message Digest (160 bits): + --------------------------------------- + H0 = [0x4c0d2b95] + H1 = [0x1ffabd6f] + H2 = [0x9a10489d] + H3 = [0xc40fc356] + H4 = [0xec1d26d5] diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/main.c new file mode 100644 index 000000000..a06418eec --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/main.c @@ -0,0 +1,464 @@ +/** + ****************************************************************************** + * @file HASH/Context_Swap/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup HASH_Context_Swap + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* "testing123" */ +const uint8_t Sha1Input[SHA1_INPUT_TAB_SIZE] = {0x74,0x65,0x73,0x74,0x69, + 0x6e,0x67,0x31,0x32,0x33}; + + +/* +3 x + "The hash processor is a fully compliant implementation of the secure + hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash + algorithm and the HMAC (keyed-hash message authentication code) + algorithm suitable for a variety of applications.*** STM32 ***" +*/ +const uint8_t Md5Input[MD5_INPUT_TAB_SIZE]= + {0x54,0x68,0x65,0x20,0x68,0x61,0x73,0x68, + 0x20,0x70,0x72,0x6f,0x63,0x65,0x73,0x73, + 0x6f,0x72,0x20,0x69,0x73,0x20,0x61,0x20, + 0x66,0x75,0x6c,0x6c,0x79,0x20,0x63,0x6f, + 0x6d,0x70,0x6c,0x69,0x61,0x6e,0x74,0x20, + 0x69,0x6d,0x70,0x6c,0x65,0x6d,0x65,0x6e, + 0x74,0x61,0x74,0x69,0x6f,0x6e,0x20,0x6f, + 0x66,0x20,0x74,0x68,0x65,0x20,0x73,0x65, + 0x63,0x75,0x72,0x65,0x20,0x68,0x61,0x73, + 0x68,0x20,0x61,0x6c,0x67,0x6f,0x72,0x69, + 0x74,0x68,0x6d,0x20,0x28,0x53,0x48,0x41, + 0x2d,0x31,0x29,0x2c,0x20,0x74,0x68,0x65, + 0x20,0x4d,0x44,0x35,0x20,0x28,0x6d,0x65, + 0x73,0x73,0x61,0x67,0x65,0x2d,0x64,0x69, + 0x67,0x65,0x73,0x74,0x20,0x61,0x6c,0x67, + 0x6f,0x72,0x69,0x74,0x68,0x6d,0x20,0x35, + 0x29,0x20,0x68,0x61,0x73,0x68,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x61,0x6e,0x64,0x20,0x74,0x68,0x65, + 0x20,0x48,0x4d,0x41,0x43,0x20,0x28,0x6b, + 0x65,0x79,0x65,0x64,0x2d,0x68,0x61,0x73, + 0x68,0x20,0x6d,0x65,0x73,0x73,0x61,0x67, + 0x65,0x20,0x61,0x75,0x74,0x68,0x65,0x6e, + 0x74,0x69,0x63,0x61,0x74,0x69,0x6f,0x6e, + 0x20,0x63,0x6f,0x64,0x65,0x29,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x73,0x75,0x69,0x74,0x61,0x62,0x6c, + 0x65,0x20,0x66,0x6f,0x72,0x20,0x61,0x20, + 0x76,0x61,0x72,0x69,0x65,0x74,0x79,0x20, + 0x6f,0x66,0x20,0x61,0x70,0x70,0x6c,0x69, + 0x63,0x61,0x74,0x69,0x6f,0x6e,0x73,0x2e, + 0x2a,0x2a,0x2a,0x20,0x53,0x54,0x4d,0x33, + 0x32,0x20,0x2a,0x2a,0x2a, + 0x54,0x68,0x65,0x20,0x68,0x61,0x73,0x68, + 0x20,0x70,0x72,0x6f,0x63,0x65,0x73,0x73, + 0x6f,0x72,0x20,0x69,0x73,0x20,0x61,0x20, + 0x66,0x75,0x6c,0x6c,0x79,0x20,0x63,0x6f, + 0x6d,0x70,0x6c,0x69,0x61,0x6e,0x74,0x20, + 0x69,0x6d,0x70,0x6c,0x65,0x6d,0x65,0x6e, + 0x74,0x61,0x74,0x69,0x6f,0x6e,0x20,0x6f, + 0x66,0x20,0x74,0x68,0x65,0x20,0x73,0x65, + 0x63,0x75,0x72,0x65,0x20,0x68,0x61,0x73, + 0x68,0x20,0x61,0x6c,0x67,0x6f,0x72,0x69, + 0x74,0x68,0x6d,0x20,0x28,0x53,0x48,0x41, + 0x2d,0x31,0x29,0x2c,0x20,0x74,0x68,0x65, + 0x20,0x4d,0x44,0x35,0x20,0x28,0x6d,0x65, + 0x73,0x73,0x61,0x67,0x65,0x2d,0x64,0x69, + 0x67,0x65,0x73,0x74,0x20,0x61,0x6c,0x67, + 0x6f,0x72,0x69,0x74,0x68,0x6d,0x20,0x35, + 0x29,0x20,0x68,0x61,0x73,0x68,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x61,0x6e,0x64,0x20,0x74,0x68,0x65, + 0x20,0x48,0x4d,0x41,0x43,0x20,0x28,0x6b, + 0x65,0x79,0x65,0x64,0x2d,0x68,0x61,0x73, + 0x68,0x20,0x6d,0x65,0x73,0x73,0x61,0x67, + 0x65,0x20,0x61,0x75,0x74,0x68,0x65,0x6e, + 0x74,0x69,0x63,0x61,0x74,0x69,0x6f,0x6e, + 0x20,0x63,0x6f,0x64,0x65,0x29,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x73,0x75,0x69,0x74,0x61,0x62,0x6c, + 0x65,0x20,0x66,0x6f,0x72,0x20,0x61,0x20, + 0x76,0x61,0x72,0x69,0x65,0x74,0x79,0x20, + 0x6f,0x66,0x20,0x61,0x70,0x70,0x6c,0x69, + 0x63,0x61,0x74,0x69,0x6f,0x6e,0x73,0x2e, + 0x2a,0x2a,0x2a,0x20,0x53,0x54,0x4d,0x33, + 0x32,0x20,0x2a,0x2a,0x2a, + 0x54,0x68,0x65,0x20,0x68,0x61,0x73,0x68, + 0x20,0x70,0x72,0x6f,0x63,0x65,0x73,0x73, + 0x6f,0x72,0x20,0x69,0x73,0x20,0x61,0x20, + 0x66,0x75,0x6c,0x6c,0x79,0x20,0x63,0x6f, + 0x6d,0x70,0x6c,0x69,0x61,0x6e,0x74,0x20, + 0x69,0x6d,0x70,0x6c,0x65,0x6d,0x65,0x6e, + 0x74,0x61,0x74,0x69,0x6f,0x6e,0x20,0x6f, + 0x66,0x20,0x74,0x68,0x65,0x20,0x73,0x65, + 0x63,0x75,0x72,0x65,0x20,0x68,0x61,0x73, + 0x68,0x20,0x61,0x6c,0x67,0x6f,0x72,0x69, + 0x74,0x68,0x6d,0x20,0x28,0x53,0x48,0x41, + 0x2d,0x31,0x29,0x2c,0x20,0x74,0x68,0x65, + 0x20,0x4d,0x44,0x35,0x20,0x28,0x6d,0x65, + 0x73,0x73,0x61,0x67,0x65,0x2d,0x64,0x69, + 0x67,0x65,0x73,0x74,0x20,0x61,0x6c,0x67, + 0x6f,0x72,0x69,0x74,0x68,0x6d,0x20,0x35, + 0x29,0x20,0x68,0x61,0x73,0x68,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x61,0x6e,0x64,0x20,0x74,0x68,0x65, + 0x20,0x48,0x4d,0x41,0x43,0x20,0x28,0x6b, + 0x65,0x79,0x65,0x64,0x2d,0x68,0x61,0x73, + 0x68,0x20,0x6d,0x65,0x73,0x73,0x61,0x67, + 0x65,0x20,0x61,0x75,0x74,0x68,0x65,0x6e, + 0x74,0x69,0x63,0x61,0x74,0x69,0x6f,0x6e, + 0x20,0x63,0x6f,0x64,0x65,0x29,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x73,0x75,0x69,0x74,0x61,0x62,0x6c, + 0x65,0x20,0x66,0x6f,0x72,0x20,0x61,0x20, + 0x76,0x61,0x72,0x69,0x65,0x74,0x79,0x20, + 0x6f,0x66,0x20,0x61,0x70,0x70,0x6c,0x69, + 0x63,0x61,0x74,0x69,0x6f,0x6e,0x73,0x2e, + 0x2a,0x2a,0x2a,0x20,0x53,0x54,0x4d,0x33, + 0x32,0x20,0x2a,0x2a,0x2a}; + +uint8_t Md5output[16]; +uint8_t Sha1output[20]; +uint32_t ContextSwapCounter=0; + +/* Private function prototypes -----------------------------------------------*/ +void USART_Config(void); +void TIM6_Config(void); +void Display_MainMessage(void); +void Display_MD5Digest(void); + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ +/*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + + /* TIM6 configuration to get a regular interrupt */ + TIM6_Config(); + + /* USART configuration */ + USART_Config(); + + /* Display the original message */ + Display_MainMessage(); + + /* Enable HASH clock */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); + +/*============================================================================= + SHA1/ MD5 Digest Computation without context swap +==============================================================================*/ + printf("\n\r>> MD5 Digest Computation without context swap \n\r"); + printf(">>> Start \n\r"); + + /* MD5 Digest Computation *******************************/ + HASH_MD5((uint8_t*)Md5Input, MD5_INPUT_TAB_SIZE,Md5output); + printf(">>> Done \n\r"); + + /* Display the MD5 digest */ + Display_MD5Digest(); + + printf("\n\r>> SHA1 Digest Computation without context swap \n\r"); + printf(">>> Start \n\r"); + + /* SHA1 Digest Computation */ + HASH_SHA1((uint8_t*)Sha1Input, SHA1_INPUT_TAB_SIZE, Sha1output); + printf(">>> Done \n\r"); + + /* Display the SHA1 digest */ + Display_SHA1Digest(); + +/*============================================================================= + SHA1 / MD5 Digest Computation with context swap +==============================================================================*/ + printf("\n\r>> MD5 Digest Computation with context swap \n\r"); + printf(">>> Start \n\r"); + + /* Enable TIM6 */ + TIM_Cmd(TIM6, ENABLE); + + /* MD5 Digest Computation */ + HASH_MD5((uint8_t*)Md5Input, MD5_INPUT_TAB_SIZE, Md5output); + + /* Disable TIM2 : no more interrupts */ + TIM_Cmd(TIM6, DISABLE); + + printf(" ====> During MD5 digest calculation, the context is saved and restored (%d) times to calculate the SHA1 digest \n\r", ContextSwapCounter); + printf(">>> Done \n\r"); + + /* Display the MD5 digest */ + Display_MD5Digest(); + + printf(">> SHA1 Digest computed during MD5 context swap \n\r"); + + /* Display the SHA1 digest */ + Display_SHA1Digest(); + + while(1); +} + +/** + * @brief Display the original messages to be hashed. + * @param None + * @retval None + */ +void Display_MainMessage(void) +{ + uint32_t BufferCounter = 0; + printf("\n\r ====================================== \n\r"); + printf(" ==== Context Swap Example ==== \n\r"); + printf(" ====================================== \n\r"); + printf("\r\n --------------------------------------- \n\r"); + printf(" MD5 Text to be Hashed : \n\r"); + printf(" ---------------------------------------\n\r "); + for(BufferCounter = 0; BufferCounter
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stdio.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define SHA1_INPUT_TAB_SIZE ((uint32_t)10) +#define MD5_INPUT_TAB_SIZE ((uint32_t)261*3) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void Display_SHA1Digest(void); + + +#endif /*__MAIN_H*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/readme.txt new file mode 100644 index 000000000..eee130010 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/readme.txt @@ -0,0 +1,96 @@ +/** + @page HASH_Context_Swap Context Swapping during Digest calculation example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file HASH/Context_Swap/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of Context Swapping during Digest calculation + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the HASH peripheral to +save and restore hash context to serve a high priority hash operation. + +For this example, no DMA is used for data transfer. +The SHA-1 and MD5 digests can be displayed on a PC HyperTerminal using the USART(CN16). + +- In the first step the MD5 and SHA1 digests are computed and displayed. +- In the second step, a TIM6 interruption is configured to occurs with frequency of + 200 KHz and a MD5 digest calculation is launched. + During the TIM6 interrupt routine, the current MD5 context is saved, then a SHA-1 + digest calculation is launched (a high priority hash operation) and a counter is + incremented (ContextSwapCounter). + When the SHA1 digest calculation is done, the saved MD5 context is restored and + the MD5 digest calculation is continued. + When the MD5 digest calculation is done, both MD5 and SHA1 digests are displayed + to show that there is no difference between the results of the first and the + second steps. + + +@par Directory contents + - HASH/Context_Swap/system_stm32f2xx.c STM32F2xx system clock configuration file + - HASH/Context_Swap/stm32f2xx_conf.h Library Configuration file + - HASH/Context_Swap/stm32f2xx_it.h Interrupt handlers header file + - HASH/Context_Swap/stm32f2xx_it.c Interrupt handlers + - HASH/Context_Swap/main.c Main program + - HASH/Context_Swap/main.h Main header file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs only on STM32F21x Devices (Cryptographic acceleration not + embedded in STM32F20x Devices). + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/stm32f2xx_conf.h new file mode 100644 index 000000000..1ff195445 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/stm32f2xx_conf.h @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file HASH/Context_Swap/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/stm32f2xx_it.c new file mode 100644 index 000000000..0b70322de --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/stm32f2xx_it.c @@ -0,0 +1,211 @@ +/** + ****************************************************************************** + * @file HASH/Context_Swap/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup HASH_Context_Swap + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +HASH_Context Md5Context; +extern const uint8_t Sha1Input[]; +extern unsigned char Sha1output[]; +extern uint32_t Sha1Len; +extern uint32_t ContextSwapCounter; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles TIM6 global interrupt request. + * @param None + * @retval None + */ +void TIM6_DAC_IRQHandler(void) +{ + if (TIM_GetITStatus(TIM6, TIM_IT_Update) != RESET) + { + +/*============================================================================= + Save MD5 Digest Computation context +==============================================================================*/ + HASH_SaveContext(&Md5Context); + ContextSwapCounter++; + +/*============================================================================= + SHA1 Digest Computation +==============================================================================*/ + HASH_SHA1((uint8_t*)Sha1Input, SHA1_INPUT_TAB_SIZE, Sha1output); + +/*============================================================================= + Restore MD5 Digest Computation context +==============================================================================*/ + HASH_RestoreContext(&Md5Context); + + TIM_ClearITPendingBit(TIM6, TIM_IT_Update); + } + +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/stm32f2xx_it.h new file mode 100644 index 000000000..2ecaba41e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/stm32f2xx_it.h @@ -0,0 +1,59 @@ +/** + ****************************************************************************** + * @file HASH/Context_Swap/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/Context_Swap/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/Expected_Results.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/Expected_Results.txt new file mode 100644 index 000000000..34df60a6a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/Expected_Results.txt @@ -0,0 +1,24 @@ + ====================================== + ==== HASH Example ==== + ====================================== + --------------------------------------- + Text to be Hashed ( 2088 bits): + --------------------------------------- +The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.*** STM32 *** + + --------------------------------------- + SHA1 Message Digest (160 bits): + --------------------------------------- + H0 = [0xf859c18d] + H1 = [0xec947242] + H2 = [0x7924fb61] + H3 = [0xef7c6a6b] + H4 = [0x670bf9c3] + + --------------------------------------- + MD5 Message Digest (128 bits): + --------------------------------------- + A = [0x6707862c] + B = [0x7cd0b522] + C = [0xb2dd22d8] + D = [0x477be318] diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/main.c new file mode 100644 index 000000000..f01ea2a22 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/main.c @@ -0,0 +1,311 @@ +/** + ****************************************************************************** + * @file HASH/HASH_SHA1_MD5/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stdio.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup HASH_SHA1_MD5 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define INPUT_TAB_SIZE ((uint32_t) 261) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* + "The hash processor is a fully compliant implementation of the secure + hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash + algorithm and the HMAC (keyed-hash message authentication code) + algorithm suitable for a variety of applications.*** STM32 ***" +*/ +const uint8_t Input[INPUT_TAB_SIZE] = + {0x54,0x68,0x65,0x20,0x68,0x61,0x73,0x68, + 0x20,0x70,0x72,0x6f,0x63,0x65,0x73,0x73, + 0x6f,0x72,0x20,0x69,0x73,0x20,0x61,0x20, + 0x66,0x75,0x6c,0x6c,0x79,0x20,0x63,0x6f, + 0x6d,0x70,0x6c,0x69,0x61,0x6e,0x74,0x20, + 0x69,0x6d,0x70,0x6c,0x65,0x6d,0x65,0x6e, + 0x74,0x61,0x74,0x69,0x6f,0x6e,0x20,0x6f, + 0x66,0x20,0x74,0x68,0x65,0x20,0x73,0x65, + 0x63,0x75,0x72,0x65,0x20,0x68,0x61,0x73, + 0x68,0x20,0x61,0x6c,0x67,0x6f,0x72,0x69, + 0x74,0x68,0x6d,0x20,0x28,0x53,0x48,0x41, + 0x2d,0x31,0x29,0x2c,0x20,0x74,0x68,0x65, + 0x20,0x4d,0x44,0x35,0x20,0x28,0x6d,0x65, + 0x73,0x73,0x61,0x67,0x65,0x2d,0x64,0x69, + 0x67,0x65,0x73,0x74,0x20,0x61,0x6c,0x67, + 0x6f,0x72,0x69,0x74,0x68,0x6d,0x20,0x35, + 0x29,0x20,0x68,0x61,0x73,0x68,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x61,0x6e,0x64,0x20,0x74,0x68,0x65, + 0x20,0x48,0x4d,0x41,0x43,0x20,0x28,0x6b, + 0x65,0x79,0x65,0x64,0x2d,0x68,0x61,0x73, + 0x68,0x20,0x6d,0x65,0x73,0x73,0x61,0x67, + 0x65,0x20,0x61,0x75,0x74,0x68,0x65,0x6e, + 0x74,0x69,0x63,0x61,0x74,0x69,0x6f,0x6e, + 0x20,0x63,0x6f,0x64,0x65,0x29,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x73,0x75,0x69,0x74,0x61,0x62,0x6c, + 0x65,0x20,0x66,0x6f,0x72,0x20,0x61,0x20, + 0x76,0x61,0x72,0x69,0x65,0x74,0x79,0x20, + 0x6f,0x66,0x20,0x61,0x70,0x70,0x6c,0x69, + 0x63,0x61,0x74,0x69,0x6f,0x6e,0x73,0x2e, + 0x2a,0x2a,0x2a,0x20,0x53,0x54,0x4d,0x33, + 0x32,0x20,0x2a,0x2a,0x2a}; + +uint8_t Md5output[16]; +uint8_t Sha1output[20]; + +/* Private function prototypes -----------------------------------------------*/ +void USART_Config(void); +void Display_MainMessage(uint32_t Len); +void Display_SHA1Digest(void); +void Display_MD5Digest(void); + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ +/*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* USART configuration */ + USART_Config(); + + /* Display the original message */ + Display_MainMessage(INPUT_TAB_SIZE); + + /* Enable HASH clock */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); + + +/*============================================================================= + SHA-1 Digest Computation +==============================================================================*/ + + /* SHA-1 Digest Computation */ + HASH_SHA1((uint8_t *)Input, INPUT_TAB_SIZE, Sha1output); + + /* Display the SHA1 digest */ + Display_SHA1Digest(); + +/*============================================================================= + MD5 Digest Computation +==============================================================================*/ + + /* MD5 Digest Computation */ + HASH_MD5((uint8_t *)Input, INPUT_TAB_SIZE, Md5output); + + /* Display the MD5 digest */ + Display_MD5Digest(); + + while(1); +} + +/** + * @brief USART configuration + * @param None + * @retval None + */ +void USART_Config(void) +{ + /* USARTx configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitTypeDef USART_InitStructure; + + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + STM_EVAL_COMInit(COM1, &USART_InitStructure); +} + +/** + * @brief Display the original message. + * @param None + * @retval None + */ +void Display_MainMessage(uint32_t Len) +{ + uint32_t BufferCounter = 0; + + printf("\n\r ======================================\n\r"); + printf(" ==== HASH Example ====\n\r"); + printf(" ======================================\n\r"); + printf(" ---------------------------------------\n\r"); + printf(" Text to be Hashed ( %d bits): \n\r", Len*8); + printf(" ---------------------------------------\n\r"); + + for(BufferCounter = 0; BufferCounter < Len ; BufferCounter++) + { + printf("%c", Input[BufferCounter]); + } +} + +/** + * @brief Display the SHA-1 digest. + * @param None + * @retval None + */ +void Display_SHA1Digest(void) +{ + printf("\n\r ---------------------------------------\n\r"); + printf(" SHA1 Message Digest (160 bits):\n\r"); + printf(" ---------------------------------------\n\r"); + printf(" H0 = [0x%02x%02x%02x%02x] \n\r",Sha1output[0], + Sha1output[1], + Sha1output[2], + Sha1output[3]); + printf(" H1 = [0x%02x%02x%02x%02x] \n\r",Sha1output[4], + Sha1output[5], + Sha1output[6], + Sha1output[7]); + printf(" H2 = [0x%02x%02x%02x%02x] \n\r",Sha1output[8], + Sha1output[9], + Sha1output[10], + Sha1output[11]); + printf(" H3 = [0x%02x%02x%02x%02x] \n\r",Sha1output[12], + Sha1output[13], + Sha1output[14], + Sha1output[15]); + printf(" H4 = [0x%02x%02x%02x%02x] \n\r",Sha1output[16], + Sha1output[17], + Sha1output[18], + Sha1output[19]); +} + +/** + * @brief Display the MD5 digest. + * @param None + * @retval None + */ +void Display_MD5Digest(void) +{ + printf("\n\r ---------------------------------------\n\r"); + printf(" MD5 Message Digest (128 bits):\n\r"); + printf(" ---------------------------------------\n\r"); + printf(" A = [0x%02x%02x%02x%02x] \n\r", Md5output[0], + Md5output[1], + Md5output[2], + Md5output[3]); + printf(" B = [0x%02x%02x%02x%02x] \n\r", Md5output[4], + Md5output[5], + Md5output[6], + Md5output[7]); + printf(" C = [0x%02x%02x%02x%02x] \n\r", Md5output[8], + Md5output[9], + Md5output[10], + Md5output[11]); + printf(" D = [0x%02x%02x%02x%02x] \n\r", Md5output[12], + Md5output[13], + Md5output[14], + Md5output[15]); +} + +/** + * @brief Retargets the C library printf function to the USART. + * @param None + * @retval None + */ +PUTCHAR_PROTOTYPE +{ + /* Place your implementation of fputc here */ + /* e.g. write a character to the USART */ + USART_SendData(EVAL_COM1, (uint8_t) ch); + + /* Loop until the end of transmission */ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) + {} + + return ch; +} + + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/readme.txt new file mode 100644 index 000000000..e8e3d61fc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/readme.txt @@ -0,0 +1,87 @@ +/** + @page HASH_SHA1_MD5 HASH digest calculation using SHA1 and MD5 example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file HASH/HASH_SHA1_MD5/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the digest calculation using SHA1 and MD5 Example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the HASH peripheral to +hash data using SHA-1 and MD5 Algorithms. + +For this example, no DMA is used for data transfer. + +The SHA-1 message digest result is a 160 bit data and the MD5 message digest result +is a 128 bit data. + +The SHA-1 and MD5 digests can be displayed on a PC HyperTerminal using the USART (CN16). + + +@par Directory contents + - HASH/HASH_SHA1_MD5/system_stm32f2xx.c STM32F2xx system clock configuration file + - HASH/HASH_SHA1_MD5/stm32f2xx_conf.h Library Configuration file + - HASH/HASH_SHA1_MD5/stm32f2xx_it.h Interrupt handlers header file + - HASH/HASH_SHA1_MD5/stm32f2xx_it.c Interrupt handlers + - HASH/HASH_SHA1_MD5/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs only on STM32F21x Devices (Cryptographic acceleration not + embedded in STM32F20x Devices). + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/stm32f2xx_conf.h new file mode 100644 index 000000000..26ef00a1b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/stm32f2xx_conf.h @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file HASH/HASH_SHA1_MD5/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/stm32f2xx_it.c new file mode 100644 index 000000000..245d833d1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/stm32f2xx_it.c @@ -0,0 +1,174 @@ +/** + ****************************************************************************** + * @file HASH/HMAC_SHA1_MD5/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup HASH_SHA1_MD5 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/stm32f2xx_it.h new file mode 100644 index 000000000..ddaa6d166 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file HASH/HASH_SHA1_MD5/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HASH_SHA1_MD5/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/Expected_Results.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/Expected_Results.txt new file mode 100644 index 000000000..4081db8e4 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/Expected_Results.txt @@ -0,0 +1,30 @@ + ====================================== + ==== HMAC Example ==== + ====================================== + + --------------------------------------- + Text to be Hashed ( 2088 bits): + --------------------------------------- +The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.*** STM32 *** + + --------------------------------------- + HMAC Key ( 2088 bits): + --------------------------------------- +The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.*** STM32 *** + + --------------------------------------- + SHA1 Message Digest (160 bits): + --------------------------------------- + H0 = [0x2b47ef34] + H1 = [0xf66658be] + H2 = [0x3b2ac6ec] + H3 = [0x5885f21e] + H4 = [0xd59fddad] + + --------------------------------------- + MD5 Message Digest (128 bits): + --------------------------------------- + A = [0x877ebbbf] + B = [0xc8a9c085] + C = [0x78a2c331] + D = [0xd67ec70e] diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/main.c new file mode 100644 index 000000000..027400cfc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/main.c @@ -0,0 +1,364 @@ +/** + ****************************************************************************** + * @file HASH/HMAC_SHA1_MD5/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stdio.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup HMAC_SHA1_MD5 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define INPUT_TAB_SIZE ((uint32_t) 261) +#define KEY_TAB_SIZE ((uint32_t) 261) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* "The hash processor is a fully compliant implementation of the secure + hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash + algorithm and the HMAC (keyed-hash message authentication code) + algorithm suitable for a variety of applications.*** STM32 ***" + */ +const uint8_t Input[INPUT_TAB_SIZE] = + {0x54,0x68,0x65,0x20,0x68,0x61,0x73,0x68, + 0x20,0x70,0x72,0x6f,0x63,0x65,0x73,0x73, + 0x6f,0x72,0x20,0x69,0x73,0x20,0x61,0x20, + 0x66,0x75,0x6c,0x6c,0x79,0x20,0x63,0x6f, + 0x6d,0x70,0x6c,0x69,0x61,0x6e,0x74,0x20, + 0x69,0x6d,0x70,0x6c,0x65,0x6d,0x65,0x6e, + 0x74,0x61,0x74,0x69,0x6f,0x6e,0x20,0x6f, + 0x66,0x20,0x74,0x68,0x65,0x20,0x73,0x65, + 0x63,0x75,0x72,0x65,0x20,0x68,0x61,0x73, + 0x68,0x20,0x61,0x6c,0x67,0x6f,0x72,0x69, + 0x74,0x68,0x6d,0x20,0x28,0x53,0x48,0x41, + 0x2d,0x31,0x29,0x2c,0x20,0x74,0x68,0x65, + 0x20,0x4d,0x44,0x35,0x20,0x28,0x6d,0x65, + 0x73,0x73,0x61,0x67,0x65,0x2d,0x64,0x69, + 0x67,0x65,0x73,0x74,0x20,0x61,0x6c,0x67, + 0x6f,0x72,0x69,0x74,0x68,0x6d,0x20,0x35, + 0x29,0x20,0x68,0x61,0x73,0x68,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x61,0x6e,0x64,0x20,0x74,0x68,0x65, + 0x20,0x48,0x4d,0x41,0x43,0x20,0x28,0x6b, + 0x65,0x79,0x65,0x64,0x2d,0x68,0x61,0x73, + 0x68,0x20,0x6d,0x65,0x73,0x73,0x61,0x67, + 0x65,0x20,0x61,0x75,0x74,0x68,0x65,0x6e, + 0x74,0x69,0x63,0x61,0x74,0x69,0x6f,0x6e, + 0x20,0x63,0x6f,0x64,0x65,0x29,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x73,0x75,0x69,0x74,0x61,0x62,0x6c, + 0x65,0x20,0x66,0x6f,0x72,0x20,0x61,0x20, + 0x76,0x61,0x72,0x69,0x65,0x74,0x79,0x20, + 0x6f,0x66,0x20,0x61,0x70,0x70,0x6c,0x69, + 0x63,0x61,0x74,0x69,0x6f,0x6e,0x73,0x2e, + 0x2a,0x2a,0x2a,0x20,0x53,0x54,0x4d,0x33, + 0x32,0x20,0x2a,0x2a,0x2a}; + +/* key = "The hash processor is a fully compliant implementation of the secure + hash algorithm (SHA-1), the MD5 (message-digest algorithm 5) hash algorithm + and the HMAC (keyed-hash message authentication code)algorithm suitable for + a variety of applications.*** STM32 ***" + */ +const uint8_t Key[KEY_TAB_SIZE] = + {0x54,0x68,0x65,0x20,0x68,0x61,0x73,0x68, + 0x20,0x70,0x72,0x6f,0x63,0x65,0x73,0x73, + 0x6f,0x72,0x20,0x69,0x73,0x20,0x61,0x20, + 0x66,0x75,0x6c,0x6c,0x79,0x20,0x63,0x6f, + 0x6d,0x70,0x6c,0x69,0x61,0x6e,0x74,0x20, + 0x69,0x6d,0x70,0x6c,0x65,0x6d,0x65,0x6e, + 0x74,0x61,0x74,0x69,0x6f,0x6e,0x20,0x6f, + 0x66,0x20,0x74,0x68,0x65,0x20,0x73,0x65, + 0x63,0x75,0x72,0x65,0x20,0x68,0x61,0x73, + 0x68,0x20,0x61,0x6c,0x67,0x6f,0x72,0x69, + 0x74,0x68,0x6d,0x20,0x28,0x53,0x48,0x41, + 0x2d,0x31,0x29,0x2c,0x20,0x74,0x68,0x65, + 0x20,0x4d,0x44,0x35,0x20,0x28,0x6d,0x65, + 0x73,0x73,0x61,0x67,0x65,0x2d,0x64,0x69, + 0x67,0x65,0x73,0x74,0x20,0x61,0x6c,0x67, + 0x6f,0x72,0x69,0x74,0x68,0x6d,0x20,0x35, + 0x29,0x20,0x68,0x61,0x73,0x68,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x61,0x6e,0x64,0x20,0x74,0x68,0x65, + 0x20,0x48,0x4d,0x41,0x43,0x20,0x28,0x6b, + 0x65,0x79,0x65,0x64,0x2d,0x68,0x61,0x73, + 0x68,0x20,0x6d,0x65,0x73,0x73,0x61,0x67, + 0x65,0x20,0x61,0x75,0x74,0x68,0x65,0x6e, + 0x74,0x69,0x63,0x61,0x74,0x69,0x6f,0x6e, + 0x20,0x63,0x6f,0x64,0x65,0x29,0x20,0x61, + 0x6c,0x67,0x6f,0x72,0x69,0x74,0x68,0x6d, + 0x20,0x73,0x75,0x69,0x74,0x61,0x62,0x6c, + 0x65,0x20,0x66,0x6f,0x72,0x20,0x61,0x20, + 0x76,0x61,0x72,0x69,0x65,0x74,0x79,0x20, + 0x6f,0x66,0x20,0x61,0x70,0x70,0x6c,0x69, + 0x63,0x61,0x74,0x69,0x6f,0x6e,0x73,0x2e, + 0x2a,0x2a,0x2a,0x20,0x53,0x54,0x4d,0x33, + 0x32,0x20,0x2a,0x2a,0x2a}; + +uint8_t Md5output[16]; +uint8_t Sha1output[20]; + +/* Private function prototypes -----------------------------------------------*/ +void USART_Config(void); +void Display_MainMessage(void); +void Display_SHA1Digest(void); +void Display_MD5Digest(void); + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ +/*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + /* USART configuration */ + USART_Config(); + /* Enable HASH clock */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); + + /* Display the original message */ + Display_MainMessage(); +/*============================================================================= + HMAC SHA-1 Digest Computation +==============================================================================*/ + + /* HMAC SHA-1 Digest Computation */ + HMAC_SHA1((uint8_t*)Key, KEY_TAB_SIZE, + (uint8_t*)Input, INPUT_TAB_SIZE, + Sha1output); + + + /* Display the HMAC SHA1 digest */ + Display_SHA1Digest(); + +/*============================================================================= + HMAC MD5 Digest Computation +==============================================================================*/ + + /* HMAC MD5 Digest Computation */ + HMAC_MD5((uint8_t*)Key, KEY_TAB_SIZE, + (uint8_t*)Input, INPUT_TAB_SIZE, + Md5output); + + /* Display the HMAC MD5 digest */ + Display_MD5Digest(); + + while(1); +} + +/** + * @brief Display the original message. + * @param None + * @retval None + */ +void Display_MainMessage(void) +{ + uint32_t i=0; + + printf("\n\r ======================================\n\r"); + printf(" ==== HMAC Example ====\n\r"); + printf(" ======================================\n\r"); + printf(" ---------------------------------------\n\r"); + printf(" Text to be Hashed ( %d bits): \n\r", INPUT_TAB_SIZE*8); + printf(" ---------------------------------------\n\r"); + + for(i = 0; i < INPUT_TAB_SIZE ; i++) + { + printf("%c", Input[i]); + } + printf("\n\r ---------------------------------------\n\r"); + printf(" HMAC Key ( %d bits): \n\r", KEY_TAB_SIZE*8); + printf(" ---------------------------------------\n\r"); + + for(i = 0; i < KEY_TAB_SIZE ; i++) + { + printf("%c", Key[i]); + } + +} + +/** + * @brief Display the SHA-1 digest. + * @param None + * @retval None + */ +void Display_SHA1Digest(void) +{ + __IO uint8_t i=0; + printf("\n\r ---------------------------------------\n\r"); + printf(" SHA1 Message Digest (160 bits):\n\r"); + printf(" ---------------------------------------\n\r"); + printf(" H0 = [0x%02x%02x%02x%02x] \n\r",Sha1output[0], + Sha1output[1], + Sha1output[2], + Sha1output[3]); + printf(" H1 = [0x%02x%02x%02x%02x] \n\r",Sha1output[4], + Sha1output[5], + Sha1output[6], + Sha1output[7]); + printf(" H2 = [0x%02x%02x%02x%02x] \n\r",Sha1output[8], + Sha1output[9], + Sha1output[10], + Sha1output[11]); + printf(" H3 = [0x%02x%02x%02x%02x] \n\r",Sha1output[12], + Sha1output[13], + Sha1output[14], + Sha1output[15]); + printf(" H4 = [0x%02x%02x%02x%02x] \n\r",Sha1output[16], + Sha1output[17], + Sha1output[18], + Sha1output[19]); +} + +/** + * @brief Display the MD5 digest. + * @param None + * @retval None + */ +void Display_MD5Digest(void) +{ + + printf("\n\r ---------------------------------------\n\r"); + printf(" MD5 Message Digest (128 bits): \n\r"); + printf(" ---------------------------------------\n\r"); + printf(" A = [0x%02x%02x%02x%02x] \n\r", Md5output[0], + Md5output[1], + Md5output[2], + Md5output[3]); + printf("\r B = [0x%02x%02x%02x%02x] \n", Md5output[4], + Md5output[5], + Md5output[6], + Md5output[7]); + printf("\r C = [0x%02x%02x%02x%02x] \n", Md5output[8], + Md5output[9], + Md5output[10], + Md5output[11]); + printf("\r D = [0x%02x%02x%02x%02x] \n", Md5output[12], + Md5output[13], + Md5output[14], + Md5output[15]); +} + +/** + * @brief USART configuration + * @param None + * @retval None + */ +void USART_Config(void) +{ + /* USARTx configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitTypeDef USART_InitStructure; + + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit(COM1, &USART_InitStructure); +} + +/** + * @brief Retargets the C library printf function to the USART. + * @param None + * @retval None + */ +PUTCHAR_PROTOTYPE +{ + /* Place your implementation of fputc here */ + /* e.g. write a character to the USART */ + USART_SendData(EVAL_COM1, (uint8_t) ch); + + /* Loop until the end of transmission */ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) + {} + + return ch; +} + + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/readme.txt new file mode 100644 index 000000000..85929ebf0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/readme.txt @@ -0,0 +1,89 @@ +/** + @page HMAC_SHA1_MD5 HMAC digest calculation using HMAC SHA1 and HMAC MD5 example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file HASH/HMAC_SHA1_MD5/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the HMAC digest calculation using HMAC SHA1 and + * HMAC MD5 Example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the HASH peripheral to +hash data using HMAC SHA-1 and HMAC MD5 Algorithms. + +For this example, no DMA is used for data transfer. +The key used is long type (2088 bit data). +The HMAC SHA-1 message digest result is a 160 bit data and the HMAC MD5 message +digest result is a 128 bit data. + +The HMAC SHA-1 and HMAC MD5 digests can be displayed on a PC HyperTerminal using +the USART (CN16). + + +@par Directory contents + - HASH/HMAC_SHA1_MD5/system_stm32f2xx.c STM32F2xx system clock configuration file + - HASH/HMAC_SHA1_MD5/stm32f2xx_conf.h Library Configuration file + - HASH/HMAC_SHA1_MD5/stm32f2xx_it.h Interrupt handlers header file + - HASH/HMAC_SHA1_MD5/stm32f2xx_it.c Interrupt handlers + - HASH/HMAC_SHA1_MD5/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs only on STM32F21x Devices (Cryptographic acceleration not + embedded in STM32F20x Devices). + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/stm32f2xx_conf.h new file mode 100644 index 000000000..167fbcbfc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/stm32f2xx_conf.h @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file HASH/HMAC_SHA1_MD5/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/stm32f2xx_it.c new file mode 100644 index 000000000..91083a94e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file HASH/HMAC_SHA1_MD5/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup HMAC_SHA1_MD5 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/stm32f2xx_it.h new file mode 100644 index 000000000..c3036fd29 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file HASH/HMAC_SHA1_MD5/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/HMAC_SHA1_MD5/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/Expected_Results.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/Expected_Results.txt new file mode 100644 index 000000000..7e72721ab --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/Expected_Results.txt @@ -0,0 +1,29 @@ + ====================================== + ==== HASH Using DMA Example ==== + ====================================== + --------------------------------------- + Text to be Hashed (1024 bits): + --------------------------------------- +Hash processor (HASH) computes a + message digest (128bit for MD5 + and 160bit for SHA-1) for mess +ages of up to (2exp64 – 1) bits +. + + --------------------------------------- + SHA1 Message Digest (160 bits): + --------------------------------------- + H0 = [0xd0640dbf] + H1 = [0x9f30019b] + H2 = [0x205527fb] + H3 = [0x71e35e48] + H4 = [0x9d9524fc] + + + --------------------------------------- + MD5 Message Digest (128 bits): + --------------------------------------- + A = [0x83a44877] + B = [0xb74f8bb4] + C = [0x4e741f1c] + D = [0xe835b673] diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/main.c new file mode 100644 index 000000000..d71ff63db --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/main.c @@ -0,0 +1,378 @@ +/** + ****************************************************************************** + * @file HASH/SHA1_MD5_DMA/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stdio.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SHA1_MD5_DMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SIZE_MSG_TO_HASH_IN_BITS (512 * 2) +#define SIZE_MSG_TO_HASH_IN_BYTES (SIZE_MSG_TO_HASH_IN_BITS / 8) +#define SIZE_MSG_TO_HASH_IN_WORDS (SIZE_MSG_TO_HASH_IN_BITS / 32) +#define HASH_DIN_REG_ADDR ((uint32_t)0x50060404) /* HASH DIN register address */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +HASH_MsgDigest MsgDigest; + +uint8_t MessageToHash[SIZE_MSG_TO_HASH_IN_BYTES]= +"Hash processor (HASH) computes a message digest (128bit for MD5 and 160bit for \ +SHA-1) for messages of up to (2exp64 – 1) bits."; + +/* Private function prototypes -----------------------------------------------*/ +void HASH_SHA1_DMA(void); +void HASH_MD5_DMA(void); + +void Display_MainMessage(void); +void Display_SHA1Digest(void); +void Display_MD5Digest(void); + +void USART_Config(void); +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ +/*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* USART configuration */ + USART_Config(); + + /* Enable HASH and DMA clocks */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + /* Display the original message */ + Display_MainMessage(); + +/*============================================================================= + SHA-1 Digest Computation +==============================================================================*/ + /* HASH SHA-1 Digest computation (using DMA for data transfer) */ + HASH_SHA1_DMA(); + + /* Display the SHA1 digest */ + Display_SHA1Digest(); + +/*============================================================================= + MD5 Digest Computation +==============================================================================*/ + /* HASH MD5 Digest computation (using DMA for data transfer) */ + HASH_MD5_DMA(); + + /* Display the MD5 digest */ + Display_MD5Digest(); + + while(1); +} + +/** + * @brief HASH SHA-1 Digest computation (using DMA for data transfer) + * @note DMA2 stream7 channel2 is used to transfer data from memory + * (MessageToHash[] array) to HASH Peripheral (the INPUT data register). + * @param None + * @retval None + */ +void HASH_SHA1_DMA(void) +{ + HASH_InitTypeDef HASH_InitStructure; + DMA_InitTypeDef DMA_InitStructure; + + /* HASH Configuration */ + HASH_StructInit(&HASH_InitStructure); + HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; + HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; + HASH_InitStructure.HASH_DataType = HASH_DataType_32b; + HASH_Init(&HASH_InitStructure); + + /*DMA Configuration*/ + DMA_DeInit(DMA2_Stream7); + DMA_InitStructure.DMA_Channel = DMA_Channel_2; + DMA_InitStructure.DMA_PeripheralBaseAddr = HASH_DIN_REG_ADDR; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)MessageToHash; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_BufferSize = SIZE_MSG_TO_HASH_IN_WORDS; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + + /* Configure the DMA Stream */ + DMA_Init(DMA2_Stream7, &DMA_InitStructure); + + /* Enable HASH DMA */ + HASH_DMACmd(ENABLE); + + /* Enable DMA2 Transfer */ + DMA_Cmd(DMA2_Stream7, ENABLE); + + /* Note : When the DMA is enabled, it provides the information to the hash + processor when it is transferring the last data word. Then the + padding and digest computation are performed automatically as if + DCAL had been written to 1.*/ + + /* Wait until DMA Transfer completed */ + while (DMA_GetFlagStatus(DMA2_Stream7, DMA_FLAG_TCIF7) == RESET); + + /* Wait until the Busy flag is RESET */ + while (HASH_GetFlagStatus(HASH_FLAG_BUSY) != RESET); + + /* Get the SHA-1 Digest */ + HASH_GetDigest(&MsgDigest); +} + + +/** + * @brief HASH MD5 Digest computation (using DMA for data transfer) + * @note DMA2 stream7 channel2 is used to transfer data from memory + * (MessageToHash[] array) to HASH Peripheral (the INPUT data register). + * @param None + * @retval None + */ +void HASH_MD5_DMA(void) +{ + HASH_InitTypeDef HASH_InitStructure; + DMA_InitTypeDef DMA_InitStructure; + + /* HASH Configuration */ + HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; + HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; + HASH_InitStructure.HASH_DataType = HASH_DataType_32b; + HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; + HASH_Init(&HASH_InitStructure); + + /*DMA Configuration*/ + DMA_DeInit(DMA2_Stream7); + DMA_InitStructure.DMA_Channel = DMA_Channel_2; + DMA_InitStructure.DMA_PeripheralBaseAddr = HASH_DIN_REG_ADDR; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)MessageToHash; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_BufferSize = SIZE_MSG_TO_HASH_IN_WORDS; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + + /* Configure the DMA Stream */ + DMA_Init(DMA2_Stream7, &DMA_InitStructure); + + /* Enable HASH DMA */ + HASH_DMACmd(ENABLE); + + /* Enable DMA2 Transfer */ + DMA_Cmd(DMA2_Stream7, ENABLE); + + /* Note : When the DMA is enabled, it provides the information to the hash + processor when it is transferring the last data word. Then the + padding and digest computation are performed automatically as if + DCAL had been written to 1.*/ + + /* wait until DMA Transfer completed */ + while (DMA_GetFlagStatus(DMA2_Stream7, DMA_FLAG_TCIF7) == RESET); + + /* wait until the Busy flag is RESET */ + while (HASH_GetFlagStatus(HASH_FLAG_BUSY) != RESET); + + /* Get the MD5 Digest */ + HASH_GetDigest(&MsgDigest); +} +/** + * @brief Display the original message. + * @param None + * @retval None + */ +void Display_MainMessage(void) +{ + uint32_t BufferCounter=0; + + printf("\n\r ======================================\n\r"); + printf(" ==== HASH Using DMA Example ====\n\r"); + printf(" ======================================\n\r"); + printf(" ---------------------------------------\n\r"); + printf(" Text to be Hashed (%d bits):\n\r", SIZE_MSG_TO_HASH_IN_BYTES*8); + printf(" ---------------------------------------\n\r"); + + for(BufferCounter = 0; BufferCounter ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs only on STM32F21x Devices (Cryptographic acceleration not + embedded in STM32F20x Devices). + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/stm32f2xx_conf.h new file mode 100644 index 000000000..193444669 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file HASH/SHA1_MD5_DMA/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/stm32f2xx_it.c new file mode 100644 index 000000000..6440f7d26 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file HASH/SHA1_MD5_DMA/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SHA1_MD5_DMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/stm32f2xx_it.h new file mode 100644 index 000000000..789f3f041 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file HASH/SHA1_MD5_DMA/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/HASH/SHA1_MD5_DMA/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/main.c new file mode 100644 index 000000000..14a5b245f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/main.c @@ -0,0 +1,324 @@ +/** + ****************************************************************************** + * @file I2C/EEPROM/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval_i2c_ee.h" +#include "stm322xg_eval_lcd.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2C_EEPROM + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Private define ------------------------------------------------------------*/ +/* Uncomment the following line to enable using LCD screen for messages display */ +#define ENABLE_LCD_MSG_DISPLAY + +#define sEE_WRITE_ADDRESS1 0x50 +#define sEE_READ_ADDRESS1 0x50 +#define BUFFER_SIZE1 (countof(Tx1_Buffer)-1) +#define BUFFER_SIZE2 (countof(Tx2_Buffer)-1) +#define sEE_WRITE_ADDRESS2 (sEE_WRITE_ADDRESS1 + BUFFER_SIZE1) +#define sEE_READ_ADDRESS2 (sEE_READ_ADDRESS1 + BUFFER_SIZE1) + +/* Private macro -------------------------------------------------------------*/ +#define countof(a) (sizeof(a) / sizeof(*(a))) + +/* Private variables ---------------------------------------------------------*/ +uint8_t Tx1_Buffer[] = "/* STM32F20xx I2C Firmware Library EEPROM driver example: \ + buffer 1 transfer into address sEE_WRITE_ADDRESS1 */ \ + Example Description \ + This firmware provides a basic example of how to use the I2C firmware library and\ + an associate I2C EEPROM driver to communicate with an I2C EEPROM device (here the\ + example is interfacing with M24C64 EEPROM)\ + \ + I2C peripheral is configured in Master transmitter during write operation and in\ + Master receiver during read operation from I2C EEPROM. \ + \ + The peripheral used is I2C1 but can be configured by modifying the defines values\ + in stm322xg_eval.h file. The speed is set to 100kHz and can be configured by \ + modifying the relative define in stm32_eval_i2c_ee.h file.\ + \ + For M24C64 devices all the memory is accessible through the two-bytes \ + addressing mode and need to define block addresses. In this case, only the physical \ + address has to be defined (according to the address pins (E0,E1 and E2) connection).\ + This address is defined in i2c_ee.h (default is 0xA0: E0, E1 and E2 tied to ground).\ + The EEPROM addresses where the program start the write and the read operations \ + is defined in the main.c file. \ + \ + First, the content of Tx1_Buffer is written to the EEPROM_WriteAddress1 and the\ + written data are read. The written and the read buffers data are then compared.\ + Following the read operation, the program waits that the EEPROM reverts to its \ + Standby state. A second write operation is, then, performed and this time, Tx2_Buffer\ + is written to EEPROM_WriteAddress2, which represents the address just after the last \ + written one in the first write. After completion of the second write operation, the \ + written data are read. The contents of the written and the read buffers are compared.\ + \ + All transfers are managed in DMA mode (except when 1-byte read/write operation is\ + required). Once sEE_ReadBuffer() or sEE_WriteBuffer() function is called, the \ + use application may perform other tasks in parallel while Read/Write operation is\ + managed by DMA.\ + \ + This example provides the possibility to use the STM322xG-EVAL LCD screen for\ + messages display (transfer status: Ongoing, PASSED, FAILED).\ + To enable this option uncomment the define ENABLE_LCD_MSG_DISPLAY in the main.c\ + file. "; +uint8_t Tx2_Buffer[] = "/* STM32F20xx I2C Firmware Library EEPROM driver example: \ + buffer 2 transfer into address sEE_WRITE_ADDRESS2 */"; +uint8_t Rx1_Buffer[BUFFER_SIZE1], Rx2_Buffer[BUFFER_SIZE2]; +volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED; +volatile uint16_t NumDataRead = 0; + +/* Private functions ---------------------------------------------------------*/ +TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength); + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + +#ifdef ENABLE_LCD_MSG_DISPLAY + /* Initialize the LCD screen for information display */ + STM322xG_LCD_Init(); + LCD_Clear(LCD_COLOR_BLUE); + LCD_SetBackColor(LCD_COLOR_BLUE); + LCD_SetTextColor(LCD_COLOR_WHITE); + LCD_DisplayStringLine(LCD_LINE_0, (uint8_t *)"SMT32F2xx FW Library"); + LCD_DisplayStringLine(LCD_LINE_1, (uint8_t *)" EEPROM Example "); +#endif /* ENABLE_LCD_MSG_DISPLAY */ + + /* Initialize the I2C EEPROM driver ----------------------------------------*/ + sEE_Init(); + + /* First write in the memory followed by a read of the written data --------*/ + /* Write on I2C EEPROM from sEE_WRITE_ADDRESS1 */ + sEE_WriteBuffer(Tx1_Buffer, sEE_WRITE_ADDRESS1, BUFFER_SIZE1); + + /* Wait for EEPROM standby state */ + sEE_WaitEepromStandbyState(); + + /* Set the Number of data to be read */ + NumDataRead = BUFFER_SIZE1; + + /* Read from I2C EEPROM from sEE_READ_ADDRESS1 */ + sEE_ReadBuffer(Rx1_Buffer, sEE_READ_ADDRESS1, (uint16_t *)(&NumDataRead)); + + + /* Starting from this point, if the requested number of data is higher than 1, + then only the DMA is managing the data transfer. Meanwhile, CPU is free to + perform other tasks: + + // Add your code here: + //... + //... + + For simplicity reasons, this example is just waiting till the end of the + transfer. */ + +#ifdef ENABLE_LCD_MSG_DISPLAY + LCD_DisplayStringLine(LCD_LINE_3, (uint8_t *)" Transfer 1 Ongoing "); +#endif /* ENABLE_LCD_MSG_DISPLAY */ + + /* Wait till DMA transfer is complete (Transfer complete interrupt handler + resets the variable holding the number of data to be read) */ + while (NumDataRead > 0) + {} + + /* Check if the data written to the memory is read correctly */ + TransferStatus1 = Buffercmp(Tx1_Buffer, Rx1_Buffer, BUFFER_SIZE1); + /* TransferStatus1 = PASSED, if the transmitted and received data + to/from the EEPROM are the same */ + /* TransferStatus1 = FAILED, if the transmitted and received data + to/from the EEPROM are different */ +#ifdef ENABLE_LCD_MSG_DISPLAY + if (TransferStatus1 == PASSED) + { + LCD_DisplayStringLine(LCD_LINE_3, (uint8_t *)" Transfer 1 PASSED "); + } + else + { + LCD_DisplayStringLine(LCD_LINE_3, (uint8_t *)" Transfer 1 FAILED "); + } +#endif /* ENABLE_LCD_MSG_DISPLAY */ + + /* Second write in the memory followed by a read of the written data -------*/ + /* Write on I2C EEPROM from sEE_WRITE_ADDRESS2 */ + sEE_WriteBuffer(Tx2_Buffer, sEE_WRITE_ADDRESS2, BUFFER_SIZE2); + + /* Wait for EEPROM standby state */ + sEE_WaitEepromStandbyState(); + + /* Set the Number of data to be read */ + NumDataRead = BUFFER_SIZE2; + + /* Read from I2C EEPROM from sEE_READ_ADDRESS2 */ + sEE_ReadBuffer(Rx2_Buffer, sEE_READ_ADDRESS2, (uint16_t *)(&NumDataRead)); + + + /* Starting from this point, if the requested number of data is higher than 1, + then only the DMA is managing the data transfer. Meanwhile, CPU is free to + perform other tasks: + + // Add your code here: + //... + //... + + For simplicity reasons, this example is just waiting till the end of the + transfer. */ + +#ifdef ENABLE_LCD_MSG_DISPLAY + LCD_DisplayStringLine(LCD_LINE_5, (uint8_t *)" Transfer 2 Ongoing "); +#endif /* ENABLE_LCD_MSG_DISPLAY */ + + /* Wait till DMA transfer is complete (Transfer complete interrupt handler + resets the variable holding the number of data to be read) */ + while (NumDataRead > 0) + {} + + /* Check if the data written to the memory is read correctly */ + TransferStatus2 = Buffercmp(Tx2_Buffer, Rx2_Buffer, BUFFER_SIZE2); + /* TransferStatus2 = PASSED, if the transmitted and received data + to/from the EEPROM are the same */ + /* TransferStatus2 = FAILED, if the transmitted and received data + to/from the EEPROM are different */ +#ifdef ENABLE_LCD_MSG_DISPLAY + if (TransferStatus1 == PASSED) + { + LCD_DisplayStringLine(LCD_LINE_5, (uint8_t *)" Transfer 2 PASSED "); + } + else + { + LCD_DisplayStringLine(LCD_LINE_5, (uint8_t *)" Transfer 2 FAILED "); + } +#endif /* ENABLE_LCD_MSG_DISPLAY */ + + /* Free all used resources */ + sEE_DeInit(); + + while (1) + { + } +} + +#ifndef USE_DEFAULT_TIMEOUT_CALLBACK +/** + * @brief Example of timeout situation management. + * @param None. + * @retval None. + */ +uint32_t sEE_TIMEOUT_UserCallback(void) +{ + /* Use application may try to recover the communication by resetting I2C + peripheral (calling the function I2C_SoftwareResetCmd()) then restart + the transmission/reception from a previously stored recover point. + For simplicity reasons, this example only shows a basic way for errors + managements which consists of stopping all the process and requiring system + reset. */ + +#ifdef ENABLE_LCD_MSG_DISPLAY + /* Display error message on screen */ + LCD_Clear(LCD_COLOR_RED); + LCD_DisplayStringLine(LCD_LINE_4, (uint8_t *)"Communication ERROR!"); + LCD_DisplayStringLine(LCD_LINE_5, (uint8_t *)"Try again after res-"); + LCD_DisplayStringLine(LCD_LINE_6, (uint8_t *)" etting the Board "); +#endif /* ENABLE_LCD_MSG_DISPLAY */ + + /* Block communication and all processes */ + while (1) + { + } +} +#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */ + +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer1 identical to pBuffer2 + * FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength) +{ + while(BufferLength--) + { + if(*pBuffer1 != *pBuffer2) + { + return FAILED; + } + + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/readme.txt new file mode 100644 index 000000000..8d769b489 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/readme.txt @@ -0,0 +1,107 @@ +/** + @page I2C_EEPROM How to use the I2C to drive an EEPROM memory + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file I2C/EEPROM/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the I2C and M24CXX EEPROM communication example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This firmware provides a basic example of how to use the I2C firmware library and +an associate I2C EEPROM driver to communicate with an I2C EEPROM device (here the +example is interfacing with M24C64 EEPROM) + +I2C peripheral is configured in Master transmitter during write operation and in +Master receiver during read operation from I2C EEPROM. + +The peripheral used is I2C1 but can be configured by modifying the defines values +in stm322xg_eval.h file. The speed is set to 100kHz and can be configured by +modifying the relative define in stm322xg_eval_i2c_ee.h file. + +For M24C64 devices all the memory is accessible through the two-bytes +addressing mode and need to define block addresses. In this case, only the physical +address has to be defined (according to the address pins (E0,E1 and E2) connection). +This address is defined in stm322xg_eval_i2c_ee.h (default is 0xA0: E0, E1 and E2 +tied to ground). +The EEPROM addresses where the program start the write and the read operations +is defined in the main.c file. + +First, the content of Tx1_Buffer is written to the EEPROM_WriteAddress1 and the +written data are read. The written and the read buffers data are then compared. +Following the read operation, the program waits that the EEPROM reverts to its +Standby state. A second write operation is, then, performed and this time, Tx2_Buffer +is written to EEPROM_WriteAddress2, which represents the address just after the last +written one in the first write. After completion of the second write operation, the +written data are read. The contents of the written and the read buffers are compared. + +All transfers are managed in DMA mode (except when 1-byte read/write operation is +required). Once sEE_ReadBuffer() or sEE_WriteBuffer() function is called, the +use application may perform other tasks in parallel while Read/Write operation is +managed by DMA. + +This example provides the possibility to use the STM322xG-EVAL LCD screen for +messages display (transfer status: Ongoing, PASSED, FAILED). +To enable this option uncomment the define ENABLE_LCD_MSG_DISPLAY in the main.c +file. + + +@par Directory contents + + - I2C/EEPROM/system_stm32f2xx.c STM32F2xx system clock configuration file + - I2C/EEPROM/stm32f2xx_conf.h Library Configuration file + - I2C/EEPROM/stm32f2xx_it.c Interrupt handlers + - I2C/EEPROM/stm32f2xx_it.h Interrupt handlers header file + - I2C/EEPROM/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB (with no additional + hardware), and can be easily tailored to any other development board. + + - STM322xG-EVAL Set-up + - Make sure the jumper JP24 "WP" is fitted on the board. + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Add the "stm322xg_eval_i2c_ee.c" file (under Utilities\STM32_EVAL\STM322xG_EVAL) + to the project source list + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/stm32f2xx_conf.h new file mode 100644 index 000000000..4808bf823 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file I2C/EEPROM/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/stm32f2xx_it.c new file mode 100644 index 000000000..724f84a1b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file I2C/EEPROM/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2C_EEPROM + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/stm32f2xx_it.h new file mode 100644 index 000000000..0f540ebb8 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file I2C/EEPROM/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/EEPROM/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/main.c new file mode 100644 index 000000000..6815ee75f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/main.c @@ -0,0 +1,726 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/DataExchangeDMA/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2C_DataExchangeDMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +uint8_t HEADER_ADDRESS_Write = (((SLAVE_ADDRESS & 0xFF00) >> 7) | 0xF0); +uint8_t HEADER_ADDRESS_Read = (((SLAVE_ADDRESS & 0xFF00) >> 7) | 0xF1); +#define countof(a) (sizeof(a) / sizeof(*(a))) + +/* Private variables ---------------------------------------------------------*/ +I2C_InitTypeDef I2C_InitStructure; +DMA_InitTypeDef DMA_InitStructure; +uint8_t TxBuffer[] = "I2C DMA Example: Communication between two I2C using DMA"; +uint8_t RxBuffer [256]; +__IO uint32_t TimeOut = 0x0; +RCC_ClocksTypeDef RCC_Clocks; + +/* Private function prototypes -----------------------------------------------*/ +static void I2C_Config(void); +static void SysTickConfig(void); +static void TimeOut_UserCallback(void); +static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength); +static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /* At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* I2C configuration ---------------------------------------------------------*/ + I2C_Config(); + + /* Initialize LEDs mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* SysTick configuration -----------------------------------------------------*/ + SysTickConfig(); + + /* Clear the RxBuffer */ + Fill_Buffer(RxBuffer, RXBUFFERSIZE); + + /*************************************Master Code******************************/ +#if defined (I2C_MASTER) + + /* I2C Struct Initialize */ + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DUTYCYCLE; + I2C_InitStructure.I2C_OwnAddress1 = 0xA0; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + +#ifndef I2C_10BITS_ADDRESS + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +#else + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_10bit; +#endif /* I2C_10BITS_ADDRESS */ + + /* I2C Initialize */ + I2C_Init(I2Cx, &I2C_InitStructure); + + /* Master Transmitter --------------------------------------------------------*/ + + /* Generate the Start condition */ + I2C_GenerateSTART(I2Cx, ENABLE); + +#ifdef I2C_10BITS_ADDRESS + /* Test on I2C1 EV5 and clear it */ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* Send Header to I2Cx for write or time out */ + I2C_SendData(I2Cx, HEADER_ADDRESS_Write); + /* Test on I2Cx EV9 and clear it */ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_ADDRESS10))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* Send I2Cx slave Address for write */ + I2C_Send7bitAddress(I2Cx, (uint8_t)SLAVE_ADDRESS, I2C_Direction_Transmitter); + + #else /* I2C_7BITS_ADDRESS */ + + /* Test on I2Cx EV5 and clear it or time out */ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* Send I2Cx slave Address for write */ + I2C_Send7bitAddress(I2Cx, SLAVE_ADDRESS, I2C_Direction_Transmitter); + +#endif /* I2C_10BITS_ADDRESS */ + + /* Test on I2Cx EV6 and clear it or time out */ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* I2Cx DMA Enable */ + I2C_DMACmd(I2Cx, ENABLE); + + /* Enable DMA TX Channel */ + DMA_Cmd(I2Cx_DMA_STREAM_TX, ENABLE); + + /* Wait until I2Cx_DMA_STREAM_TX enabled or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetCmdStatus(I2Cx_DMA_STREAM_TX)!= ENABLE)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Wait until DMA Transfer Complete or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetFlagStatus(I2Cx_DMA_STREAM_TX,I2Cx_TX_DMA_TCFLAG) == RESET)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* I2Cx DMA Disable */ + I2C_DMACmd(I2Cx, DISABLE); + + /* Wait until BTF Flag is set before generating STOP or time out */ + TimeOut = USER_TIMEOUT; + while ((!I2C_GetFlagStatus(I2Cx,I2C_FLAG_BTF))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Send I2Cx STOP Condition */ + I2C_GenerateSTOP(I2Cx, ENABLE); + + /* Disable DMA TX Channel */ + DMA_Cmd(I2Cx_DMA_STREAM_TX, DISABLE); + + /* Wait until I2Cx_DMA_STREAM_TX disabled or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetCmdStatus(I2Cx_DMA_STREAM_TX)!= DISABLE)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Clear any pending flag on Tx Stream */ + DMA_ClearFlag(I2Cx_DMA_STREAM_TX, I2Cx_TX_DMA_TCFLAG | I2Cx_TX_DMA_FEIFLAG | I2Cx_TX_DMA_DMEIFLAG | \ + I2Cx_TX_DMA_TEIFLAG | I2Cx_TX_DMA_HTIFLAG); + + /* Master Receiver -----------------------------------------------------------*/ + + /* Enable DMA NACK automatic generation */ + I2C_DMALastTransferCmd(I2Cx, ENABLE); + + /* Send I2Cx START condition */ + I2C_GenerateSTART(I2Cx, ENABLE); + +#ifdef I2C_10BITS_ADDRESS + /* Test on EV5 and clear it or time out */ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* Send Header to Slave for write */ + I2C_SendData(I2Cx, HEADER_ADDRESS_Write); + + /* Test on EV9 and clear it or time out */ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_ADDRESS10))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* Send slave Address */ + I2C_Send7bitAddress(I2Cx, (uint8_t)SLAVE_ADDRESS, I2C_Direction_Transmitter); + + /* Test on I2Cx EV6 and clear it or time out*/ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* Repeated Start */ + I2C_GenerateSTART(I2Cx, ENABLE); + + /* Test on EV5 and clear it or time out*/ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* Send Header to Slave for Read */ + I2C_SendData(I2Cx, HEADER_ADDRESS_Read); + +#else /* I2C_7BITS_ADDRESS */ + + /* Test on I2Cx EV5 and clear it or time out*/ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* Send I2Cx slave Address for write */ + I2C_Send7bitAddress(I2Cx, SLAVE_ADDRESS, I2C_Direction_Receiver); + +#endif /* I2C_10BITS_ADDRESS */ + + /* Test on I2Cx EV6 and clear it or time out */ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* I2Cx DMA Enable */ + I2C_DMACmd(I2Cx, ENABLE); + + /* Enable DMA RX Channel */ + DMA_Cmd(I2Cx_DMA_STREAM_RX, ENABLE); + + /* Wait until I2Cx_DMA_STREAM_RX enabled or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetCmdStatus(I2Cx_DMA_STREAM_RX)!= ENABLE)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Transfer complete or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetFlagStatus(I2Cx_DMA_STREAM_RX,I2Cx_RX_DMA_TCFLAG)==RESET)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* Send I2Cx STOP Condition */ + I2C_GenerateSTOP(I2Cx, ENABLE); + + /* Disable DMA RX Channel */ + DMA_Cmd(I2Cx_DMA_STREAM_RX, DISABLE); + + /* Wait until I2Cx_DMA_STREAM_RX disabled or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetCmdStatus(I2Cx_DMA_STREAM_RX)!= DISABLE)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Disable I2C DMA request */ + I2C_DMACmd(I2Cx,DISABLE); + + /* Clear any pending flag on Rx Stream */ + DMA_ClearFlag(I2Cx_DMA_STREAM_RX, I2Cx_RX_DMA_TCFLAG | I2Cx_RX_DMA_FEIFLAG | I2Cx_RX_DMA_DMEIFLAG | \ + I2Cx_RX_DMA_TEIFLAG | I2Cx_RX_DMA_HTIFLAG); + + if (Buffercmp(TxBuffer, RxBuffer, RXBUFFERSIZE) == PASSED) + { + /* LED2, LED3 and LED4 Toggle */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + } + else + { /* ED2, LED3 and LED4 On */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + } + +#endif /* I2C_MASTER */ + +/**********************************Slave Code**********************************/ +#if defined (I2C_SLAVE) + + /* Initialize I2C peripheral */ + /* I2C Init */ + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DUTYCYCLE; + I2C_InitStructure.I2C_OwnAddress1 = SLAVE_ADDRESS; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + +#ifndef I2C_10BITS_ADDRESS + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +#else + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_10bit; +#endif /* I2C_10BITS_ADDRESS */ + + I2C_Init(I2Cx, &I2C_InitStructure); + + /* Slave Receiver ------------------------------------------------------------*/ + + /* Test on I2C EV1 and clear it */ + while (!I2C_CheckEvent(I2Cx, I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED)) + {} + + /* I2Cx DMA Enable */ + I2C_DMACmd(I2Cx, ENABLE); + + /* Enable DMA RX Channel */ + DMA_Cmd(I2Cx_DMA_STREAM_RX, ENABLE); + + /* Wait until I2Cx_DMA_STREAM_RX enabled or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetCmdStatus(I2Cx_DMA_STREAM_RX)!= ENABLE)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Transfer complete or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetFlagStatus(I2Cx_DMA_STREAM_RX,I2Cx_RX_DMA_TCFLAG)==RESET)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* Test on I2Cx EV4 and clear it or time out */ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_SLAVE_STOP_DETECTED))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* Disable DMA RX Channel */ + DMA_Cmd(I2Cx_DMA_STREAM_RX, DISABLE); + + /* Wait until I2Cx_DMA_STREAM_RX disabled or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetCmdStatus(I2Cx_DMA_STREAM_RX)!= DISABLE)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Disable I2C DMA request */ + I2C_DMACmd(I2Cx,DISABLE); + + /* Clear any pending flag on Rx Stream */ + DMA_ClearFlag(I2Cx_DMA_STREAM_RX, I2Cx_RX_DMA_TCFLAG | I2Cx_RX_DMA_FEIFLAG | I2Cx_RX_DMA_DMEIFLAG | \ + I2Cx_RX_DMA_TEIFLAG | I2Cx_RX_DMA_HTIFLAG); + +/* Slave Transmitter ---------------------------------------------------------*/ + + /* Test on I2C EV1 and clear it or time out*/ + while (!I2C_CheckEvent(I2Cx, I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED)) + {} + /* I2Cx DMA Enable */ + I2C_DMACmd(I2Cx, ENABLE); + + /* Enable DMA RX Channel */ + DMA_Cmd(I2Cx_DMA_STREAM_TX, ENABLE); + + /* Wait until I2Cx_DMA_STREAM_TX enabled or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetCmdStatus(I2Cx_DMA_STREAM_TX)!= ENABLE)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Transfer complete or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetFlagStatus(I2Cx_DMA_STREAM_TX,I2Cx_TX_DMA_TCFLAG)==RESET)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Test on I2Cx EV3-2 and clear it or time out */ + TimeOut = USER_TIMEOUT; + while ((!I2C_CheckEvent(I2Cx, I2C_EVENT_SLAVE_ACK_FAILURE))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Disable DMA TX Channel */ + DMA_Cmd(I2Cx_DMA_STREAM_TX, DISABLE); + + /* Wait until I2Cx_DMA_STREAM_TX disabled or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetCmdStatus(I2Cx_DMA_STREAM_TX)!= DISABLE)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Disable I2C DMA request */ + I2C_DMACmd(I2Cx,DISABLE); + + /* Clear any pending flag on Tx Stream */ + DMA_ClearFlag(I2Cx_DMA_STREAM_TX, I2Cx_TX_DMA_TCFLAG | I2Cx_TX_DMA_FEIFLAG | I2Cx_TX_DMA_DMEIFLAG | \ + I2Cx_TX_DMA_TEIFLAG | I2Cx_TX_DMA_HTIFLAG); + + if (Buffercmp(TxBuffer, RxBuffer, RXBUFFERSIZE) == PASSED) + { + /* LED2, LED3 and LED4 are On */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + } + else + { /* LED2, LED3 and LED4 are Off */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + } + +#endif /* I2C_SLAVE */ + while(1) + {} +} + +/** + * @brief Enables the I2C Clock and configures the different GPIO ports. + * @param None + * @retval None + */ +static void I2C_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* RCC Configuration */ + /*I2C Peripheral clock enable */ + RCC_APB1PeriphClockCmd(I2Cx_CLK, ENABLE); + + /*SDA GPIO clock enable */ + RCC_AHB1PeriphClockCmd(I2Cx_SDA_GPIO_CLK, ENABLE); + + /*SCL GPIO clock enable */ + RCC_AHB1PeriphClockCmd(I2Cx_SCL_GPIO_CLK, ENABLE); + + /* Reset I2Cx IP */ + RCC_APB1PeriphResetCmd(I2Cx_CLK, ENABLE); + + /* Release reset signal of I2Cx IP */ + RCC_APB1PeriphResetCmd(I2Cx_CLK, DISABLE); + + /* Enable the DMA clock */ + RCC_AHB1PeriphClockCmd(DMAx_CLK, ENABLE); + + /* GPIO Configuration */ + /*Configure I2C SCL pin */ + GPIO_InitStructure.GPIO_Pin = I2Cx_SCL_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(I2Cx_SCL_GPIO_PORT, &GPIO_InitStructure); + + /*Configure I2C SDA pin */ + GPIO_InitStructure.GPIO_Pin = I2Cx_SDA_PIN; + GPIO_Init(I2Cx_SDA_GPIO_PORT, &GPIO_InitStructure); + + /* Connect PXx to I2C_SCL */ + GPIO_PinAFConfig(I2Cx_SCL_GPIO_PORT, I2Cx_SCL_SOURCE, I2Cx_SCL_AF); + + /* Connect PXx to I2C_SDA */ + GPIO_PinAFConfig(I2Cx_SDA_GPIO_PORT, I2Cx_SDA_SOURCE, I2Cx_SDA_AF); + + /* DMA Configuration */ + /* Clear any pending flag on Tx Stream */ + DMA_ClearFlag(I2Cx_DMA_STREAM_TX, I2Cx_TX_DMA_TCFLAG | I2Cx_TX_DMA_FEIFLAG | I2Cx_TX_DMA_DMEIFLAG | \ + I2Cx_TX_DMA_TEIFLAG | I2Cx_TX_DMA_HTIFLAG); + + /* Clear any pending flag on Rx Stream */ + DMA_ClearFlag(I2Cx_DMA_STREAM_RX, I2Cx_RX_DMA_TCFLAG | I2Cx_RX_DMA_FEIFLAG | I2Cx_RX_DMA_DMEIFLAG | \ + I2Cx_RX_DMA_TEIFLAG | I2Cx_RX_DMA_HTIFLAG); + + /* Disable the I2C Tx DMA stream */ + DMA_Cmd(I2Cx_DMA_STREAM_TX, DISABLE); + /* Configure the DMA stream for the I2C peripheral TX direction */ + DMA_DeInit(I2Cx_DMA_STREAM_TX); + + /* Disable the I2C Rx DMA stream */ + DMA_Cmd(I2Cx_DMA_STREAM_RX, DISABLE); + /* Configure the DMA stream for the I2C peripheral RX direction */ + DMA_DeInit(I2Cx_DMA_STREAM_RX); + + /* Initialize the DMA_Channel member */ + DMA_InitStructure.DMA_Channel = I2Cx_DMA_CHANNEL; + + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStructure.DMA_PeripheralBaseAddr = I2Cx_DR_ADDRESS; + + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + + /* Initialize the DMA_MemoryInc member */ + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + + /* Initialize the DMA_Mode member */ + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + + /* Initialize the DMA_Priority member */ + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + + /* Initialize the DMA_FIFOMode member */ + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + + /* Initialize the DMA_FIFOThreshold member */ + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + + /* Initialize the DMA_MemoryBurst member */ + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + + /* Initialize the DMA_PeripheralBurst member */ + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + + /* Init DMA for Reception */ + /* Initialize the DMA_DIR member */ + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + /* Initialize the DMA_Memory0BaseAddr member */ + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)RxBuffer; + /* Initialize the DMA_BufferSize member */ + DMA_InitStructure.DMA_BufferSize = RXBUFFERSIZE; + DMA_DeInit(I2Cx_DMA_STREAM_RX); + DMA_Init(I2Cx_DMA_STREAM_RX, &DMA_InitStructure); + + /* Init DMA for Transmission */ + /* Initialize the DMA_DIR member */ + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + /* Initialize the DMA_Memory0BaseAddr member */ + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)TxBuffer; + /* Initialize the DMA_BufferSize member */ + DMA_InitStructure.DMA_BufferSize = TXBUFFERSIZE; + DMA_DeInit(I2Cx_DMA_STREAM_TX); + DMA_Init(I2Cx_DMA_STREAM_TX, &DMA_InitStructure); + + /* I2C ENABLE */ + I2C_Cmd(I2Cx, ENABLE); +} + +/** + * @brief Configure a SysTick Base time to 10 ms. + * @param None + * @retval None + */ +static void SysTickConfig(void) +{ + /* SysTick end of count event each 10ms */ + RCC_GetClocksFreq(&RCC_Clocks); + SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); + + /* Configure the SysTick handler priority */ + NVIC_SetPriority(SysTick_IRQn, 0x0); +} + +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer1 identical to pBuffer2 + * FAILED: pBuffer1 differs from pBuffer2 + */ +static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} + +/** + * @brief Fills buffer. + * @param pBuffer: pointer on the Buffer to fill + * @param BufferLength: size of the buffer to fill + * @retval None + */ +static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength) +{ + uint16_t index = 0; + + /* Put in global buffer same values */ + for (index = 0; index < BufferLength; index++ ) + { + pBuffer[index] = 0x00; + } +} + +/** + * @brief Basic management of the timeout situation. + * @param None. + * @retval None. + */ +static void TimeOut_UserCallback(void) +{ + /* User can add his own implementation to manage TimeOut Communication failure */ + /* Block communication and all processes */ + while (1) + { + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/main.h new file mode 100644 index 000000000..1d5f353b1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/main.h @@ -0,0 +1,127 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/DataExchangeDMA/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program header + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/* Exported typedef -----------------------------------------------------------*/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Exported define ------------------------------------------------------------*/ +/* Uncomment the line below if you will use the I2C peripheral as a Master */ +#define I2C_MASTER +/* Uncomment the line below if you will use the I2C peripheral as a Slave */ +/* #define I2C_SLAVE */ + +/* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral + input clock) must be a multiple of 10 MHz */ +/* Uncomment the line below if you will use the I2C peripheral in Fast Mode */ +/* #define FAST_I2C_MODE */ + +/* Uncomment the line below if you will use the I2C peripheral in 10-bit addressing + mode */ +#define I2C_10BITS_ADDRESS + +/* Define I2C Speed --------------------------------------------------------*/ +#ifdef FAST_I2C_MODE + #define I2C_SPEED 340000 + #define I2C_DUTYCYCLE I2C_DutyCycle_16_9 +#else /* STANDARD_I2C_MODE*/ + #define I2C_SPEED 100000 + #define I2C_DUTYCYCLE I2C_DutyCycle_2 +#endif /* FAST_I2C_MODE*/ + +/* Define Slave Address ---------------------------------------------------*/ +#ifdef I2C_10BITS_ADDRESS + #define SLAVE_ADDRESS (uint16_t)0x0330 +#else /* I2C_7BITS_ADDRESS */ + #define SLAVE_ADDRESS 0x30 +#endif /* I2C_10BITS_ADDRESS */ + +/* USER_TIMEOUT value for waiting loops. This timeout is just a guarantee that the + application will not remain stuck if the I2C communication is corrupted. + You may modify this timeout value depending on CPU frequency and application + conditions (interrupts routines, number of data to transfer, speed, CPU + frequency...). */ +#define USER_TIMEOUT ((uint32_t)0x64) /* Waiting 1s */ + +/* I2Cx Communication boards Interface */ +#define I2Cx_DMA DMA1 +#define I2Cx_DMA_CHANNEL DMA_Channel_1 +#define I2Cx_DR_ADDRESS ((uint32_t)0x40005410) +#define I2Cx_DMA_STREAM_TX DMA1_Stream6 +#define I2Cx_DMA_STREAM_RX DMA1_Stream0 +#define I2Cx_TX_DMA_TCFLAG DMA_FLAG_TCIF6 +#define I2Cx_TX_DMA_FEIFLAG DMA_FLAG_FEIF6 +#define I2Cx_TX_DMA_DMEIFLAG DMA_FLAG_DMEIF6 +#define I2Cx_TX_DMA_TEIFLAG DMA_FLAG_TEIF6 +#define I2Cx_TX_DMA_HTIFLAG DMA_FLAG_HTIF6 +#define I2Cx_RX_DMA_TCFLAG DMA_FLAG_TCIF0 +#define I2Cx_RX_DMA_FEIFLAG DMA_FLAG_FEIF0 +#define I2Cx_RX_DMA_DMEIFLAG DMA_FLAG_DMEIF0 +#define I2Cx_RX_DMA_TEIFLAG DMA_FLAG_TEIF0 +#define I2Cx_RX_DMA_HTIFLAG DMA_FLAG_HTIF0 +#define DMAx_CLK RCC_AHB1Periph_DMA1 + +#define I2Cx I2C1 +#define I2Cx_CLK RCC_APB1Periph_I2C1 +#define I2Cx_SDA_GPIO_CLK RCC_AHB1Periph_GPIOB +#define I2Cx_SDA_PIN GPIO_Pin_9 +#define I2Cx_SDA_GPIO_PORT GPIOB +#define I2Cx_SDA_SOURCE GPIO_PinSource9 +#define I2Cx_SDA_AF GPIO_AF_I2C1 + +#define I2Cx_SCL_GPIO_CLK RCC_AHB1Periph_GPIOB +#define I2Cx_SCL_PIN GPIO_Pin_6 +#define I2Cx_SCL_GPIO_PORT GPIOB +#define I2Cx_SCL_SOURCE GPIO_PinSource6 +#define I2Cx_SCL_AF GPIO_AF_I2C1 + +#define TXBUFFERSIZE (countof(TxBuffer) - 1) +#define RXBUFFERSIZE TXBUFFERSIZE + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/readme.txt new file mode 100644 index 000000000..f401eda90 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/readme.txt @@ -0,0 +1,151 @@ +/** + @page I2C_DataExchangeDMA Two boards I2C Communication: Data Exchange using DMA example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file I2C/I2C_TwoBoards/DataExchangeDMA/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the I2C Data Exchange between two boards using DMA + * example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This is a typical example of how to use the I2C firmware library to ensure the +steps of an I2C communication between slave Receiver/Transmitter and master +Transmitter/Receiver using DMA. + +- Hardware Description + +To use this example, you need to load it on two STM32 boards (let's call them +Board A and Board B) then connect these two boards through I2C lines and GND. +In the firmware example uncomment the dedicated line in the main.h file to use +the I2C peripheral as STM32 Master device or as STM32 Slave. + +@verbatim +*------------------------------------------------------------------------------* +| BOARD A BOARD B | +| ____________________ ____________________ | +| | | | | | +| | | | | | +| | __________ | | __________ | | +| | |I2C Master|____|_______SDA_______|____|I2C Slave | | | +| | | Device |____|_______SCL_______|____| Device | | | +| | |__________| | | |__________| | | +| | O LD1 | | O LD1 | | +| | O LD2 RESET | | O LD2 RESET | | +| | O LD3 _ | | O LD3 _ | | +| | O LD4 |_| | | O LD4 |_| | | +| | | | | | +| | GND O--|-----------------|--O GND | | +| |____________________| |____________________| | +| | +| | +*------------------------------------------------------------------------------* +@endverbatim + +- Software Description + +This example requires two boards(Master and Slave) + + - Phase 1: + In master board I2C peripheral is configured in Master Transmitter with DMA + where in Slave board I2C peripheral is configured in Slave Receiver with DMA. + The master will send Data to Slave according to the defined buffer size. + + - Phase 2: + In master board I2C peripheral is configured in Master Receiver with DMA, + where in Slave board I2C peripheral is configured in Slave Transmitter with + DMA. + Once the master has initiated the communication (Start condition), the slave + will send the defined data in his TxBuffer to the master. + +At the end of the data transfer, a data consistency check will be performed +in master and slave sides. In case of mismatch between sent and received data, +LED2, LED3 and LED4 are OFF. Otherwise LED2, LED3 and LED4 are ON. + +@note As the data transfers is ensured by DMA, the TxBuffer size must be equal + or greater than two bytes. + +The File "I2C/I2C_TwoBoards/DataExchangeDMA/main.h" allows different possibilities +of configuration of this example: + - Addressing mode : 7-bit or 10-bit + - I2C speed: Fast mode or Standard mode + +The SysTick is configured to generate an interrupt each 10ms. A dedicated counter +inside the SysTick ISR is used to toggle the LED1 each 100ms indicating that the +firmware is running. + +A defined communication timeout is insuring that the application will not remain +stuck in case of I2C communication is corrupted. +You can adjust this timeout through the USER_TIMEOUT define inside main.h file +depending on CPU frequency and application conditions (interrupts routines, +number of data to transfer, speed, CPU frequency...). +When a given operation is not finished within the defined timeout, a callback is +made to the function "TimeOut_UserCallback()", this function is used to manage +timeout communication failure. In this example, this callback implements a simple +infinite loop, but user can add his own implementation to manage timeout failure. + + +@par Directory contents + + - I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_conf.h Library Configuration file + - I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_it.c Interrupt handlers + - I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_it.h Interrupt handlers header file + - I2C/I2C_TwoBoards/DataExchangeDMA/main.c Main program + - I2C/I2C_TwoBoards/DataExchangeDMA/main.h Main Header file + - I2C/I2C_TwoBoards/DataExchangeDMA/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB (with no additional + hardware), and can be easily tailored to any other development board. + + - STM322xG-EVAL Set-up + - Connect I2C1 Master SCL pin (PB.06) to I2C1 Slave SCL (PB.06) + - Connect I2C1 Master SDA pin (PB.09) to I2C1 Slave SDA (PB.09) + + @note + - Pull-up resistors should be connected to I2C SCL and SDA Pins in case of + other boards use. + Pull-up resistors are already implemented on the STM322xG-EVAL evaluation + boards. + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_conf.h new file mode 100644 index 000000000..5df8aa912 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_it.c new file mode 100644 index 000000000..343575a4d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_it.c @@ -0,0 +1,190 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2C_DataExchangeDMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint8_t Counter = 0x00; +extern __IO uint32_t TimeOut; +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +#if defined (I2C_MASTER) + /* Decrement the time out value */ + if (TimeOut != 0x0) + { + TimeOut--; + } +#endif /* I2C_MASTER*/ + + if (Counter < 10) + { + Counter++; + } + else + { + Counter = 0x00; + STM_EVAL_LEDToggle(LED1); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_it.h new file mode 100644 index 000000000..7ee61969f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_it.h @@ -0,0 +1,59 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/DataExchangeDMA/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeDMA/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/main.c new file mode 100644 index 000000000..5a7acd8eb --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/main.c @@ -0,0 +1,412 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/DataExchangeInterrupt/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2C_DataExchangeInterrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +I2C_InitTypeDef I2C_InitStructure; +uint8_t TxBuffer[] = "I2C Interrupt Example: Communication between two I2C using Interrupts"; + +__IO uint8_t Tx_Idx = 0x00; +__IO uint8_t Rx_Idx = 0x00; +uint8_t RxBuffer [256]; + +__IO uint8_t NumberOfByteToReceive = RXBUFFERSIZE; +__IO uint8_t NumberOfByteToTransmit = TXBUFFERSIZE; +__IO uint8_t MasterMode = MASTER_MODE_RECEIVER; +__IO uint32_t TimeOut = 0x0; +RCC_ClocksTypeDef RCC_Clocks; + +/* Private function prototypes -----------------------------------------------*/ +static void I2C_Config(void); +static void SysTickConfig(void); +static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength); +static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength); +static void TimeOut_UserCallback(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + +/* I2C configuration ---------------------------------------------------------*/ + I2C_Config(); + + /* Initialize LEDs mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + +/* SysTick configuration -----------------------------------------------------*/ + SysTickConfig(); + +/*************************************Master Code******************************/ +#if defined (I2C_MASTER) + /* I2C De-initialize */ + I2C_DeInit(I2Cx); + + /*!< I2C Struct Initialize */ + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DUTYCYCLE; + I2C_InitStructure.I2C_OwnAddress1 = 0xA0; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + +#ifndef I2C_10BITS_ADDRESS + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +#else + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_10bit; +#endif /* I2C_10BITS_ADDRESS */ + + /* I2C Initialization */ + I2C_Init(I2Cx, &I2C_InitStructure); + + /* Enable Error Interrupt */ + I2C_ITConfig(I2Cx, I2C_IT_ERR , ENABLE); + + /* I2C ENABLE */ + I2C_Cmd(I2Cx, ENABLE); + +/* Master Transmitter --------------------------------------------------------*/ + NumberOfByteToTransmit = TXBUFFERSIZE; + MasterMode = MASTER_MODE_TRANSMITTER; + Tx_Idx = 0x00; + + /* Enable Error and Buffer Interrupts */ + I2C_ITConfig(I2Cx, (I2C_IT_EVT | I2C_IT_BUF), ENABLE); + + /* Generate the Start condition */ + I2C_GenerateSTART(I2Cx, ENABLE); + + /* Data transfer is performed in the I2C interrupt routine */ + /* Wait until end of data transfer or time out */ + TimeOut = USER_TIMEOUT; + while ((Tx_Idx < TXBUFFERSIZE)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + TimeOut = USER_TIMEOUT; + while ((I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } +/* Master Receiver -----------------------------------------------------------*/ + NumberOfByteToReceive = RXBUFFERSIZE; + MasterMode = MASTER_MODE_RECEIVER; + Rx_Idx = 0x00; + + /* Clear the RxBuffer */ + Fill_Buffer(RxBuffer, RXBUFFERSIZE); + + /* Enable Event Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_EVT , ENABLE); + + /* Enable Acknowledge */ + I2C_AcknowledgeConfig(I2Cx, ENABLE); + + /* Generate the Start condition */ + I2C_GenerateSTART(I2Cx, ENABLE); + + /* Data transfer is performed in the I2C interrupt routine */ + /* Wait until end of data transfer */ + while (Rx_Idx < RXBUFFERSIZE) + {} + if (Buffercmp(TxBuffer, RxBuffer, RXBUFFERSIZE) == PASSED) + { + /* LED2, LED3 and LED4 ON */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + } + else + { /* LED2, LED3 and LED4 Off */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + } + +#endif /* I2C_MASTER */ + +/**********************************Slave Code**********************************/ +#if defined (I2C_SLAVE) + + I2C_DeInit(I2Cx); + + /* Initialize I2C peripheral */ + /*!< I2C Init */ + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DUTYCYCLE; + I2C_InitStructure.I2C_OwnAddress1 = SLAVE_ADDRESS; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + +#ifndef I2C_10BITS_ADDRESS + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +#else + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_10bit; +#endif /* I2C_10BITS_ADDRESS */ + + I2C_Init(I2Cx, &I2C_InitStructure); + + /* Enable Error Interrupt */ + I2C_ITConfig(I2Cx, (I2C_IT_ERR | I2C_IT_EVT | I2C_IT_BUF), ENABLE); + + /* I2C ENABLE */ + I2C_Cmd(I2Cx, ENABLE); + +/* Slave Receiver ------------------------------------------------------------*/ + Rx_Idx = 0x00; + Tx_Idx = 0x00; + + /* Clear the RxBuffer */ + Fill_Buffer(RxBuffer, RXBUFFERSIZE); + + /* Wait until end of data transfer */ + while (Rx_Idx < RXBUFFERSIZE) + {} + + TimeOut = USER_TIMEOUT; + while ((I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + +/* Slave Transmitter ---------------------------------------------------------*/ + + /* Wait until end of data transfer */ + while (Tx_Idx < TXBUFFERSIZE) + {} + + if (Buffercmp(TxBuffer, RxBuffer, RXBUFFERSIZE) == PASSED) + { + /* LED2, LED3 and LED4 ON */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + } + else + { /* LED2, LED3 and LED4 are Off */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + } +#endif /* I2C_SLAVE */ + + while(1) + {} +} + +/** + * @brief Enables the I2C Clock and configures the different GPIO ports. + * @param None + * @retval None + */ +static void I2C_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* RCC Configuration */ + /*I2C Peripheral clock enable */ + RCC_APB1PeriphClockCmd(I2Cx_CLK, ENABLE); + + /*SDA GPIO clock enable */ + RCC_AHB1PeriphClockCmd(I2Cx_SDA_GPIO_CLK, ENABLE); + + /*SCL GPIO clock enable */ + RCC_AHB1PeriphClockCmd(I2Cx_SCL_GPIO_CLK, ENABLE); + + /* Reset I2Cx IP */ + RCC_APB1PeriphResetCmd(I2Cx_CLK, ENABLE); + + /* Release reset signal of I2Cx IP */ + RCC_APB1PeriphResetCmd(I2Cx_CLK, DISABLE); + + /* GPIO Configuration */ + /*Configure I2C SCL pin */ + GPIO_InitStructure.GPIO_Pin = I2Cx_SCL_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(I2Cx_SCL_GPIO_PORT, &GPIO_InitStructure); + + /*Configure I2C SDA pin */ + GPIO_InitStructure.GPIO_Pin = I2Cx_SDA_PIN; + GPIO_Init(I2Cx_SDA_GPIO_PORT, &GPIO_InitStructure); + + /* Connect PXx to I2C_SCL */ + GPIO_PinAFConfig(I2Cx_SCL_GPIO_PORT, I2Cx_SCL_SOURCE, I2Cx_SCL_AF); + + /* Connect PXx to I2C_SDA */ + GPIO_PinAFConfig(I2Cx_SDA_GPIO_PORT, I2Cx_SDA_SOURCE, I2Cx_SDA_AF); + + /* NVIC configuration */ + /* Configure the Priority Group to 1 bit */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + + /* Configure the I2C event priority */ + NVIC_InitStructure.NVIC_IRQChannel = I2Cx_EV_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Configure I2C error interrupt to have the higher priority */ + NVIC_InitStructure.NVIC_IRQChannel = I2Cx_ER_IRQn; + NVIC_Init(&NVIC_InitStructure); +} + + +/** + * @brief Configure a SysTick Base time to 10 ms. + * @param None + * @retval None + */ +static void SysTickConfig(void) +{ + /* SysTick end of count event each 10ms */ + RCC_GetClocksFreq(&RCC_Clocks); + SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); + + /* Configure the SysTick handler priority */ + NVIC_SetPriority(SysTick_IRQn, 0x0); +} + +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer1 identical to pBuffer2 + * FAILED: pBuffer1 differs from pBuffer2 + */ +static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} + +/** + * @brief Fills buffer. + * @param pBuffer: pointer on the Buffer to fill + * @param BufferLength: size of the buffer to fill + * @retval None + */ +static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength) +{ + uint16_t index = 0; + + /* Put in global buffer same values */ + for (index = 0; index < BufferLength; index++ ) + { + pBuffer[index] = 0x00; + } +} + +/** + * @brief Basic management of the timeout situation. + * @param None. + * @retval None. + */ +static void TimeOut_UserCallback(void) +{ + /* User can add his own implementation to manage TimeOut Communication failure */ + /* Block communication and all processes */ + while (1) + { + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/main.h new file mode 100644 index 000000000..337015c14 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/main.h @@ -0,0 +1,119 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/DataExchangeInterrupt/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program header + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/* Exported typedef -----------------------------------------------------------*/ +#define countof(a) (sizeof(a) / sizeof(*(a))) +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Exported define ------------------------------------------------------------*/ +/* Uncomment the line below if you will use the I2C peripheral as a Master */ +#define I2C_MASTER +/* Uncomment the line below if you will use the I2C peripheral as a Slave */ +/* #define I2C_SLAVE */ + +/* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral + input clock) must be a multiple of 10 MHz */ +/* Uncomment the line below if you will use the I2C peripheral in Fast Mode */ +/* #define FAST_I2C_MODE */ + +/* Uncomment the line below if you will use the I2C peripheral in 10-bit addressing + mode */ +/* #define I2C_10BITS_ADDRESS */ + +/* Define I2C Speed --------------------------------------------------------*/ +#ifdef FAST_I2C_MODE + #define I2C_SPEED 340000 + #define I2C_DUTYCYCLE I2C_DutyCycle_16_9 +#else /* STANDARD_I2C_MODE*/ + #define I2C_SPEED 100000 + #define I2C_DUTYCYCLE I2C_DutyCycle_2 +#endif /* FAST_I2C_MODE*/ + +/* Define Slave Address ---------------------------------------------------*/ +#ifdef I2C_10BITS_ADDRESS + #define SLAVE_ADDRESS (uint16_t)0x0330 +#else /* I2C_7BITS_ADDRESS */ + #define SLAVE_ADDRESS 0x30 +#endif /* I2C_10BITS_ADDRESS */ + +/* USER_TIMEOUT value for waiting loops. This timeout is just a guarantee that the + application will not remain stuck if the I2C communication is corrupted. + You may modify this timeout value depending on CPU frequency and application + conditions (interrupts routines, number of data to transfer, speed, CPU + frequency...). */ +#define USER_TIMEOUT ((uint32_t)0x64) /* Waiting 1s */ + +/* Master Mode Selected */ +#define MASTER_MODE_TRANSMITTER 0x01 +#define MASTER_MODE_RECEIVER 0x00 + +/* I2Cx Communication boards Interface */ +#define I2Cx I2C1 +#define I2Cx_CLK RCC_APB1Periph_I2C1 +#define I2Cx_EV_IRQn I2C1_EV_IRQn +#define I2Cx_ER_IRQn I2C1_ER_IRQn +#define I2Cx_EV_IRQHANDLER I2C1_EV_IRQHandler +#define I2Cx_ER_IRQHANDLER I2C1_ER_IRQHandler + +#define I2Cx_SDA_GPIO_CLK RCC_AHB1Periph_GPIOB +#define I2Cx_SDA_PIN GPIO_Pin_9 +#define I2Cx_SDA_GPIO_PORT GPIOB +#define I2Cx_SDA_SOURCE GPIO_PinSource9 +#define I2Cx_SDA_AF GPIO_AF_I2C1 + +#define I2Cx_SCL_GPIO_CLK RCC_AHB1Periph_GPIOB +#define I2Cx_SCL_PIN GPIO_Pin_6 +#define I2Cx_SCL_GPIO_PORT GPIOB +#define I2Cx_SCL_SOURCE GPIO_PinSource6 +#define I2Cx_SCL_AF GPIO_AF_I2C1 + +#define TXBUFFERSIZE (countof(TxBuffer) - 1) +#define RXBUFFERSIZE TXBUFFERSIZE +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/readme.txt new file mode 100644 index 000000000..6dbc3e897 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/readme.txt @@ -0,0 +1,155 @@ +/** + @page I2C_DataExchangeInterrupt Two boards I2C Communication: Data Exchange using Interrupts example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file I2C/I2C_TwoBoards/DataExchangeInterrupt/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the I2C Data Exchange between two boards using Interrupts + * example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This is a typical example of how to use the I2C firmware library to ensure the +steps of an I2C communication between slave Receiver/Transmitter and master +Transmitter/Receiver using interrupts. + +- Hardware Description + +To use this example, you need to load it on two STM32 boards (let's call them +Board A and Board B) then connect these two boards through I2C lines and GND. +In the firmware example uncomment the dedicated line in the main.h file to use +the I2C peripheral as STM32 Master device or as STM32 Slave . + +@verbatim +*------------------------------------------------------------------------------* +| BOARD A BOARD B | +| ____________________ ____________________ | +| | | | | | +| | | | | | +| | __________ | | __________ | | +| | |I2C Master|____|_______SDA_______|____|I2C Slave | | | +| | | Device |____|_______SCL_______|____| Device | | | +| | |__________| | | |__________| | | +| | O LD1 | | O LD1 | | +| | O LD2 RESET | | O LD2 RESET | | +| | O LD3 _ | | O LD3 _ | | +| | O LD4 |_| | | O LD4 |_| | | +| | | | | | +| | GND O--|-----------------|--O GND | | +| |____________________| |____________________| | +| | +| | +*------------------------------------------------------------------------------* +@endverbatim + +- Software Description + +This example requires two boards(Master and Slave) + + - Phase 1: + In master board I2C peripheral is configured in Master Transmitter with Interrupt, + where in Slave board I2C peripheral is configured in Slave Receiver with Interrupt. + The master will send Data to Slave according to the defined buffer size. + + - Phase 2: + In master board I2C peripheral is configured in Master Receiver with Interrupt, + where in Slave board I2C peripheral is configured in Slave Transmitter with + Interrupt. + Once the master has initiated the communication (Start condition), the slave + will send back the data to the master according to the defined buffer size. + +At the end of the data transfer, a data consistency check will be performed +in master and slave sides. In case of mismatch between sent and received data, +all LED's are OFF. Otherwise LED2, LED3 and LED4 are ON. + +Communication error are handled in master an slave sides, their occurrence will +be signaled by puting LED3 and LED4 On. + + +The File "I2C/I2C_TwoBoards/DataExchangeInterrupt/main.h" allows different +possibilities of configuration for this example: + - Addressing mode : 7-bit or 10-bit + - I2C speed: Fast mode or Standard mode + +In both boards, the data transfers is managed using I2Cx_EV_IRQHandler +and I2Cx_ER_IRQHandler in stm32f2xx_it.c file. + +The SysTick is configured to generate interrupt each 10ms. A dedicated counter +inside the SysTick ISR is used to toggle the LED1 each 100ms indicating that the +firmware is running. + +A defined communication timeout is insuring that the application will not remain +stuck in case of I2C communication is corrupted. +You can adjust this timeout through the USER_TIMEOUT define inside main.h file +depending on CPU frequency and application conditions (interrupts routines, +number of data to transfer, speed, CPU frequency...). +When a given operation is not finished within the defined timeout, a callback is +made to the function "TimeOut_UserCallback()", this function is used to manage +timeout communication failure. In this example, this callback implements a simple +infinite loop, but user can add his own implementation to manage timeout failure. + + +@par Directory contents + + - I2C/I2C_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c STM32F2xx system clock configuration file + - I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h Library Configuration file + - I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c Interrupt handlers + - I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h Interrupt handlers header file + - I2C/I2C_TwoBoards/DataExchangeInterrupt/main.c Main program + - I2C/I2C_TwoBoards/DataExchangeInterrupt/main.h Main Header file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB (with no additional + hardware), and can be easily tailored to any other development board. + + - STM322xG-EVAL Set-up + - Connect I2C1 Master SCL pin (PB.06) to I2C1 Slave SCL (PB.06) + - Connect I2C1 Master SDA pin (PB.09) to I2C1 Slave SDA (PB.09) + + @note + - Pull-up resistors should be connected to I2C SCL and SDA Pins in case of + other boards use. + Pull-up resistors are already implemented on the STM322xG-EVAL evaluation + boards. + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h new file mode 100644 index 000000000..19701957a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c new file mode 100644 index 000000000..a1cdda4aa --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c @@ -0,0 +1,520 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2C_DataExchangeInterrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern uint8_t TxBuffer[]; +__IO uint8_t Counter = 0x00; +extern __IO uint32_t TimeOut; +__IO uint32_t Event = 0x00; + +uint8_t HEADER_ADDRESS_Write = (((SLAVE_ADDRESS & 0xFF00) >> 7) | 0xF0); +uint8_t HEADER_ADDRESS_Read = (((SLAVE_ADDRESS & 0xFF00) >> 7) | 0xF1); + +extern __IO uint8_t Tx_Idx; +extern __IO uint8_t Rx_Idx; +extern uint8_t NumberOfByteToReceive; +extern uint8_t NumberOfByteToTransmit; +__IO uint8_t GenerateStartStatus = 0x00; +extern uint8_t RxBuffer[]; + +#ifdef I2C_10BITS_ADDRESS +__IO uint8_t Send_HeaderStatus = 0x00; +#endif /* I2C_10BITS_ADDRESS */ + +extern __IO uint8_t MasterMode; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +#if defined (I2C_MASTER) + /* Decrement the time out value */ + if (TimeOut != 0x0) + { + TimeOut--; + } +#endif /* I2C_MASTER*/ + + if (Counter < 10) + { + Counter++; + } + else + { + Counter = 0x00; + STM_EVAL_LEDToggle(LED1); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ +/** + * @brief This function handles I2Cx Error interrupt request. + * @param None + * @retval None + */ +void I2Cx_ER_IRQHANDLER(void) +{ +#if defined (I2C_SLAVE) + + /* Read SR1 register to get I2C error */ + if ((I2C_ReadRegister(I2Cx, I2C_Register_SR1) & 0xFF00) != 0x00) + { + /* Clears error flags */ + I2Cx->SR1 &= 0x00FF; + } +#endif /* I2C_SLAVE*/ + +#if defined (I2C_MASTER) + + /* Read SR1 register to get I2C error */ + if ((I2C_ReadRegister(I2Cx, I2C_Register_SR1) & 0xFF00) != 0x00) + { + /* Clears error flags */ + I2Cx->SR1 &= 0x00FF; + + /* Set LED3 and LED4 */ + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + STM_EVAL_LEDOff(LED2); + } +#endif /* I2C_MASTER*/ +} + + +/** + * @brief This function handles I2Cx event interrupt request. + * @param None + * @retval None + */ +void I2Cx_EV_IRQHANDLER(void) +{ +#if defined (I2C_MASTER) + /* Once the Start condition is sent the master can be master receiver + or master transmitter */ + if (MasterMode == MASTER_MODE_TRANSMITTER) + { + /* Get Last I2C Event */ + Event = I2C_GetLastEvent(I2Cx); + switch (Event) + { + /* ************************************************************************/ + /* Master Transmitter Events */ + /* */ + /* ************************************************************************/ +/* Sending the header sequence for Master Transmitter case ----------------*/ + +#ifdef I2C_10BITS_ADDRESS + /* Check on EV5 */ + case I2C_EVENT_MASTER_MODE_SELECT : + /* Send Header to Slave for write */ + I2C_SendData(I2Cx, HEADER_ADDRESS_Write); + break; + + /* Check on EV9 */ + case I2C_EVENT_MASTER_MODE_ADDRESS10: + /* Send slave Address for write */ + I2C_Send7bitAddress(I2Cx, (uint8_t)SLAVE_ADDRESS, I2C_Direction_Transmitter); + break; + + +#else /* I2C_7BITS_ADDRESS */ + /* Check on EV5 */ + case I2C_EVENT_MASTER_MODE_SELECT : + /* Send slave Address for write */ + I2C_Send7bitAddress(I2Cx, (uint8_t)SLAVE_ADDRESS, I2C_Direction_Transmitter); + break; + +#endif /* I2C_10BITS_ADDRESS */ + + /* Check on EV6 */ + case I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: + /* Transmit the First Data */ + I2C_SendData(I2Cx, TxBuffer[Tx_Idx++]); + break; + + /* Check on EV8 */ + case I2C_EVENT_MASTER_BYTE_TRANSMITTING: + case I2C_EVENT_MASTER_BYTE_TRANSMITTED: + if (Tx_Idx == (uint8_t)NumberOfByteToTransmit) + { + /* Send STOP condition */ + I2C_GenerateSTOP(I2Cx, ENABLE); + I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_BUF, DISABLE); + } + else + { + /* Transmit Data TxBuffer */ + I2C_SendData(I2Cx, TxBuffer[Tx_Idx++]); + } + break; + + default: + break; + } + + } + /*************************************************************************/ + /* Master Receiver Events */ + /* */ + /*************************************************************************/ + else /* MASTER_MODE_RECEIVER */ + { +#ifdef I2C_10BITS_ADDRESS + /* Check on SB Flag and clear it */ + if(I2C_GetITStatus(I2Cx, I2C_IT_SB)== SET) + { + if (Send_HeaderStatus == 0x00) + { + /* Send Header to Slave for write */ + I2C_SendData(I2Cx, HEADER_ADDRESS_Write); + Send_HeaderStatus = 0x01; + GenerateStartStatus = 0x01; + } + else + { + /* Send Header to Slave for Read */ + I2C_SendData(I2Cx, HEADER_ADDRESS_Read); + Send_HeaderStatus = 0x00; + if (NumberOfByteToReceive == 0x03) + { + /* Disable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , DISABLE); + } + else + { + /* Enable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , ENABLE); + } + } + } + /* Check on ADD10 Flag */ + else if(I2C_GetITStatus(I2Cx, I2C_IT_ADD10)== SET) + { + /* Send slave Address */ + I2C_Send7bitAddress(I2Cx, (uint8_t)SLAVE_ADDRESS, I2C_Direction_Transmitter); + } + +#else /* I2C_7BITS_ADDRESS */ + + /* Check on EV5 */ + if(I2C_GetITStatus(I2Cx, I2C_IT_SB)== SET) + { + /* Send slave Address for read */ + I2C_Send7bitAddress(I2Cx, SLAVE_ADDRESS, I2C_Direction_Receiver); + if (NumberOfByteToReceive == 0x03) + { + /* Disable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , DISABLE); + } + else + { + /* Enable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , ENABLE); + } + } +#endif /* I2C_10BITS_ADDRESS */ + + else if(I2C_GetITStatus(I2Cx, I2C_IT_ADDR)== SET) + { + if (NumberOfByteToReceive == 1) + { + I2C_AcknowledgeConfig(I2Cx, DISABLE); + } + /* Clear ADDR Register */ + (void)(I2Cx->SR1); + (void)(I2Cx->SR2); + if (GenerateStartStatus == 0x00) + { + if (NumberOfByteToReceive == 1) + { + I2C_GenerateSTOP(I2Cx, ENABLE); + } + + if (NumberOfByteToReceive == 2) + { + I2C_AcknowledgeConfig(I2Cx, DISABLE); + I2C_NACKPositionConfig(I2Cx, I2C_NACKPosition_Next); + /* Disable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , DISABLE); + } + } + +#ifdef I2C_10BITS_ADDRESS + if (GenerateStartStatus == 0x01) + { + /* Repeated Start */ + I2C_GenerateSTART(I2Cx, ENABLE); + GenerateStartStatus = 0x00; + } + +#endif /* I2C_10BITS_ADDRESS */ + } + else if((I2C_GetITStatus(I2Cx, I2C_IT_RXNE)== SET)&&(I2C_GetITStatus(I2Cx, I2C_IT_BTF)== RESET)) + { + /* Store I2C received data */ + RxBuffer[Rx_Idx++] = I2C_ReceiveData (I2Cx); + NumberOfByteToReceive--; + + if (NumberOfByteToReceive == 0x03) + { + /* Disable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , DISABLE); + } + + if (NumberOfByteToReceive == 0x00) + { + /* Disable Error and Buffer Interrupts */ + I2C_ITConfig(I2Cx, (I2C_IT_EVT | I2C_IT_BUF), DISABLE); + } + } + /* BUSY, MSL and RXNE flags */ + else if(I2C_GetITStatus(I2Cx, I2C_IT_BTF)== SET) + { + /* if Three bytes remaining for reception */ + if (NumberOfByteToReceive == 3) + { + I2C_AcknowledgeConfig(I2Cx, DISABLE); + /* Store I2C received data */ + RxBuffer[Rx_Idx++] = I2C_ReceiveData (I2Cx); + NumberOfByteToReceive--; + } + else if (NumberOfByteToReceive == 2) + { + I2C_GenerateSTOP(I2Cx, ENABLE); + + /* Store I2C received data */ + RxBuffer[Rx_Idx++] = I2C_ReceiveData (I2Cx); + NumberOfByteToReceive--; + /* Store I2C received data */ + RxBuffer[Rx_Idx++] = I2C_ReceiveData (I2Cx); + NumberOfByteToReceive--; + /* Disable Error and Buffer Interrupts */ + I2C_ITConfig(I2Cx, (I2C_IT_EVT | I2C_IT_BUF), DISABLE); + } + else + { + /* Store I2C received data */ + RxBuffer[Rx_Idx++] = I2C_ReceiveData (I2Cx); + NumberOfByteToReceive--; + } + } + } +#endif /* I2C_MASTER*/ + + +#if defined (I2C_SLAVE) + /* Get Last I2C Event */ + Event = I2C_GetLastEvent(I2Cx); + switch (Event) + { + /* ****************************************************************************/ + /* Slave Transmitter Events */ + /* */ + /* ****************************************************************************/ + + /* Check on EV1 */ + case I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: + I2C_SendData(I2Cx, TxBuffer[Tx_Idx++]); + I2C_ITConfig(I2Cx, I2C_IT_BUF , ENABLE); + break; + /* Check on EV3 */ + case I2C_EVENT_SLAVE_BYTE_TRANSMITTING: + case I2C_EVENT_SLAVE_BYTE_TRANSMITTED: + if (Tx_Idx < NumberOfByteToTransmit) + { + I2C_SendData(I2Cx, TxBuffer[Tx_Idx++]); + } + else + { + /* Disable I2C event interrupt */ + I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_BUF, DISABLE); + } + break; + + /* ****************************************************************************/ + /* Slave Receiver Events */ + /* */ + /* ****************************************************************************/ + + /* check on EV1*/ + case I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: + Rx_Idx = 0x00; + break; + + /* Check on EV2*/ + case I2C_EVENT_SLAVE_BYTE_RECEIVED: + case (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_SR1_BTF): + RxBuffer[Rx_Idx++] = I2C_ReceiveData(I2Cx); + break; + + /* Check on EV4 */ + case I2C_EVENT_SLAVE_STOP_DETECTED: + I2C_GetFlagStatus(I2Cx, I2C_FLAG_STOPF); + I2C_Cmd(I2Cx, ENABLE); + break; + + default: + break; + } +#endif /* I2C_SLAVE*/ +} +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h new file mode 100644 index 000000000..b2f7a9155 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h @@ -0,0 +1,63 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void I2Cx_ER_IRQHANDLER(void); +void I2Cx_EV_IRQHANDLER(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/main.c new file mode 100644 index 000000000..70d287cc0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/main.c @@ -0,0 +1,397 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/MasterReceiverInterrupt/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup MasterReceiverInterrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TXBUFFERSIZE (countof(TxBuffer) - 1) +#define RXBUFFERSIZE TXBUFFERSIZE + +/* Private macro -------------------------------------------------------------*/ +#define countof(a) (sizeof(a) / sizeof(*(a))) + +/* Private variables ---------------------------------------------------------*/ +I2C_InitTypeDef I2C_InitStructure; + +uint8_t TxBuffer[] = "Communication between two I2C using Interrupt Example: \ + Slave Transmitter to Master Receiver"; +#if defined (I2C_MASTER) + __IO uint8_t Rx_Idx = 0x00; + uint8_t RxBuffer [RXBUFFERSIZE]; + __IO uint8_t NumberOfByteToReceive = 0x00; + __IO uint32_t TimeOut = 0x0; +#endif + +#if defined (I2C_SLAVE) + uint8_t NbrOfDataToSend = TXBUFFERSIZE; + __IO uint8_t Tx_Idx = 0x00; +#endif /* I2C_SLAVE */ + +RCC_ClocksTypeDef RCC_Clocks; +/* Private function prototypes -----------------------------------------------*/ +static void I2C_Config(void); +static void SysTickConfig(void); +#if defined (I2C_MASTER) + static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength); + static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength); + static void TimeOut_UserCallback(void); + static void delay(__IO uint32_t nCount); +#endif /* I2C_MASTER */ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* I2C configuration ---------------------------------------------------------*/ + I2C_Config(); + + /* Initialize LEDs mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + +/* SysTick configuration -----------------------------------------------------*/ + SysTickConfig(); + +/*************************************Master Code******************************/ +#if defined (I2C_MASTER) + /* I2C De-initialize */ + I2C_DeInit(I2Cx); + + /*I2C Struct Initialize */ + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DUTYCYCLE; + I2C_InitStructure.I2C_OwnAddress1 = 0xA0; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + +#ifndef I2C_10BITS_ADDRESS + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +#else + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_10bit; +#endif /* I2C_10BITS_ADDRESS */ + + /*I2C Initialize */ + I2C_Init(I2Cx, &I2C_InitStructure); + + /* Enable Error Interrupt */ + I2C_ITConfig(I2Cx, I2C_IT_ERR , ENABLE); + + /* I2C ENABLE */ + I2C_Cmd(I2Cx, ENABLE); + + while (1) + { + NumberOfByteToReceive = RXBUFFERSIZE; + Rx_Idx = 0x00; + + /* Clear the RxBuffer */ + Fill_Buffer(RxBuffer, RXBUFFERSIZE); + + /* Enable Event Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_EVT , ENABLE); + + /* Enable Acknowledge */ + I2C_AcknowledgeConfig(I2Cx, ENABLE); + + /* Generate the Start condition */ + I2C_GenerateSTART(I2Cx, ENABLE); + + /* Data transfer is performed in the I2C interrupt routine */ + /* Wait until end of data transfer or time out*/ + TimeOut = USER_TIMEOUT; + while ((Rx_Idx < RXBUFFERSIZE)&&(TimeOut != 0x00)) + {} + + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + if (Buffercmp(TxBuffer, RxBuffer, RXBUFFERSIZE) == PASSED) + { + /* LED2, LED3 and LED4 Toggle */ + STM_EVAL_LEDToggle(LED2); + STM_EVAL_LEDToggle(LED3); + STM_EVAL_LEDToggle(LED4); + } + else + { + /* ED2, LED3 and LED4 On */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + } + delay(10); + } +#endif /* I2C_MASTER */ + +/**********************************Slave Code**********************************/ +#if defined (I2C_SLAVE) + + /*I2Cx DeInitialize*/ + I2C_DeInit(I2Cx); + + /* Initialize I2C peripheral */ + /*I2C Init */ + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DUTYCYCLE; + I2C_InitStructure.I2C_OwnAddress1 = SLAVE_ADDRESS; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + +#ifndef I2C_10BITS_ADDRESS + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +#else + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_10bit; +#endif /* I2C_10BITS_ADDRESS */ + + I2C_Init(I2Cx, &I2C_InitStructure); + + /* Enable Error Interrupt */ + I2C_ITConfig(I2Cx, (I2C_IT_ERR), ENABLE); + + /* I2C ENABLE */ + I2C_Cmd(I2Cx, ENABLE); + + /* Infinite Loop */ + while (1) + { + Tx_Idx = 0x00; + + /* Enable I2C event interrupt */ + I2C_ITConfig(I2Cx, I2C_IT_EVT, ENABLE); + + /* Wait until end of data transfer */ + while (Tx_Idx < TXBUFFERSIZE) + { + } + + /* LED2, LED3 and LED4 Toggle */ + STM_EVAL_LEDToggle(LED2); + STM_EVAL_LEDToggle(LED3); + STM_EVAL_LEDToggle(LED4); + } +#endif /* I2C_SLAVE */ +} + +/** + * @brief Enables the I2C Clock and configures the different GPIO ports. + * @param None + * @retval None + */ +static void I2C_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* RCC Configuration */ + /*I2C Peripheral clock enable */ + RCC_APB1PeriphClockCmd(I2Cx_CLK, ENABLE); + + /*SDA GPIO clock enable */ + RCC_AHB1PeriphClockCmd(I2Cx_SDA_GPIO_CLK, ENABLE); + + /*SCL GPIO clock enable */ + RCC_AHB1PeriphClockCmd(I2Cx_SCL_GPIO_CLK, ENABLE); + + /* Reset I2Cx IP */ + RCC_APB1PeriphResetCmd(I2Cx_CLK, ENABLE); + + /* Release reset signal of I2Cx IP */ + RCC_APB1PeriphResetCmd(I2Cx_CLK, DISABLE); + + /* GPIO Configuration */ + /*Configure I2C SCL pin */ + GPIO_InitStructure.GPIO_Pin = I2Cx_SCL_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(I2Cx_SCL_GPIO_PORT, &GPIO_InitStructure); + + /*Configure I2C SDA pin */ + GPIO_InitStructure.GPIO_Pin = I2Cx_SDA_PIN; + GPIO_Init(I2Cx_SDA_GPIO_PORT, &GPIO_InitStructure); + + /* Connect PXx to I2C_SCL */ + GPIO_PinAFConfig(I2Cx_SCL_GPIO_PORT, I2Cx_SCL_SOURCE, I2Cx_SCL_AF); + + /* Connect PXx to I2C_SDA */ + GPIO_PinAFConfig(I2Cx_SDA_GPIO_PORT, I2Cx_SDA_SOURCE, I2Cx_SDA_AF); + + /* NVIC configuration */ + /* Configure the Priority Group to 1 bit */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + + /* Configure the I2C event priority */ + NVIC_InitStructure.NVIC_IRQChannel = I2Cx_EV_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Configure I2C error interrupt to have the higher priority */ + NVIC_InitStructure.NVIC_IRQChannel = I2Cx_ER_IRQn; + NVIC_Init(&NVIC_InitStructure); +} + + +/** + * @brief Configure a SysTick Base time to 10 ms. + * @param None + * @retval None + */ +static void SysTickConfig(void) +{ + /* SysTick end of count event each 10ms */ + RCC_GetClocksFreq(&RCC_Clocks); + SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); + + /* Configure the SysTick handler priority */ + NVIC_SetPriority(SysTick_IRQn, 0x0); +} + +#if defined (I2C_MASTER) +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer1 identical to pBuffer2 + * FAILED: pBuffer1 differs from pBuffer2 + */ +static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} + +/** + * @brief Fills buffer. + * @param pBuffer: pointer on the Buffer to fill + * @param BufferLength: size of the buffer to fill + * @retval None + */ +static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength) +{ + uint16_t index = 0; + + /* Put in global buffer same values */ + for (index = 0; index < BufferLength; index++ ) + { + pBuffer[index] = 0x00; + } +} + +/** + * @brief Basic management of the timeout situation. + * @param None. + * @retval None. + */ +static void TimeOut_UserCallback(void) +{ + /* User can add his own implementation to manage TimeOut Communication failure */ + /* Block communication and all processes */ + while (1) + { + } +} + +/** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + */ +static void delay(__IO uint32_t nCount) +{ + __IO uint32_t index = 0; + for(index = (34000 * nCount); index != 0; index--) + { + } +} +#endif /* I2C_MASTER */ + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/main.h new file mode 100644 index 000000000..1d91c5b06 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/main.h @@ -0,0 +1,112 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/MasterReceiverInterrupt/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program header + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/* Exported typedef -----------------------------------------------------------*/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Exported define ------------------------------------------------------------*/ +/* Uncomment the line below if you will use the I2C peripheral as a Master */ +#define I2C_MASTER +/* Uncomment the line below if you will use the I2C peripheral as a Slave */ +/* #define I2C_SLAVE */ + +/* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral + input clock) must be a multiple of 10 MHz */ +/* Uncomment the line below if you will use the I2C peripheral in Fast Mode */ +/* #define FAST_I2C_MODE */ + +/* Uncomment the line below if you will use the I2C peripheral in 10-bit addressing + mode */ +#define I2C_10BITS_ADDRESS + +/* Define I2C Speed --------------------------------------------------------*/ +#ifdef FAST_I2C_MODE + #define I2C_SPEED 340000 + #define I2C_DUTYCYCLE I2C_DutyCycle_16_9 +#else /* STANDARD_I2C_MODE*/ + #define I2C_SPEED 100000 + #define I2C_DUTYCYCLE I2C_DutyCycle_2 +#endif /* FAST_I2C_MODE*/ + +/* Define Slave Address ---------------------------------------------------*/ +#ifdef I2C_10BITS_ADDRESS + #define SLAVE_ADDRESS (uint16_t)0x0330 +#else /* I2C_7BITS_ADDRESS */ + #define SLAVE_ADDRESS 0x30 +#endif /* I2C_10BITS_ADDRESS */ + +/* USER_TIMEOUT value for waiting loops. This timeout is just a guarantee that the + application will not remain stuck if the I2C communication is corrupted. + You may modify this timeout value depending on CPU frequency and application + conditions (interrupts routines, number of data to transfer, speed, CPU + frequency...). */ +#define USER_TIMEOUT ((uint32_t)0x64) /* Waiting 1s */ + +/* I2Cx Communication boards Interface */ +#define I2Cx I2C1 +#define I2Cx_CLK RCC_APB1Periph_I2C1 +#define I2Cx_EV_IRQn I2C1_EV_IRQn +#define I2Cx_ER_IRQn I2C1_ER_IRQn +#define I2Cx_EV_IRQHandler I2C1_EV_IRQHandler +#define I2Cx_ER_IRQHandler I2C1_ER_IRQHandler + +#define I2Cx_SDA_GPIO_CLK RCC_AHB1Periph_GPIOB +#define I2Cx_SDA_PIN GPIO_Pin_9 +#define I2Cx_SDA_GPIO_PORT GPIOB +#define I2Cx_SDA_SOURCE GPIO_PinSource9 +#define I2Cx_SDA_AF GPIO_AF_I2C1 + +#define I2Cx_SCL_GPIO_CLK RCC_AHB1Periph_GPIOB +#define I2Cx_SCL_PIN GPIO_Pin_6 +#define I2Cx_SCL_GPIO_PORT GPIOB +#define I2Cx_SCL_SOURCE GPIO_PinSource6 +#define I2Cx_SCL_AF GPIO_AF_I2C1 + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/readme.txt new file mode 100644 index 000000000..1fa5a3f6e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/readme.txt @@ -0,0 +1,155 @@ +/** + @page I2C_MasterReceiverInterrupt I2C Communication between Master in Receiver mode + and slave in Transmitter mode using interrupts example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file I2C/I2C_TwoBoards/MasterReceiverInterrupt/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the Two Boards I2C Communication example: Master receiver + * and Slave Transmitter. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This is a typical example of how to use the I2C firmware library to ensure the +steps of an I2C communication between slave transmitter and master receiver using +interrupt. + +- Hardware Description + +To use this example, you need to load it on two STM32 boards (let's call them +Board A and Board B) then connect these two boards through I2C lines and GND. +In the firmware example uncomment the dedicated line in the main.h file to use +the I2C peripheral as STM32 Master device or as STM32 Slave . + +@verbatim +*------------------------------------------------------------------------------* +| BOARD A BOARD B | +| ____________________ ____________________ | +| | | | | | +| | | | | | +| | __________ | | __________ | | +| | |I2C Master|____|_______SDA_______|____|I2C Slave | | | +| | | Device |____|_______SCL_______|____| Device | | | +| | |__________| | | |__________| | | +| | O LD1 | | O LD1 | | +| | O LD2 RESET | | O LD2 RESET | | +| | O LD3 _ | | O LD3 _ | | +| | O LD4 |_| | | O LD4 |_| | | +| | | | | | +| | GND O--|-----------------|--O GND | | +| |____________________| |____________________| | +| | +| | +*------------------------------------------------------------------------------* +@endverbatim + +- Software Description + +This example requires two boards(Master and Slave) + +In master board I2C peripheral is configured in Master Receiver with interrupt, +where in Slave board I2C peripheral is configured in Slave Transmitter with +Interrupt. + +Once the master has initiated the communication (Start condition), the slave +will send the defined TxBuffer. + +At the end of the data transfer, a data consistency check will be performed +in master side and in case of mismatch between sent and received data, all LED's +are Off. Otherwise LED2, LED3 and LED4 will toggle. + +Communication error are handled in master side, their occurrence will be signaled +by puting LED3 and LED4 On. + +However, in slave side LED2, LED3 and LED4 will toggle after sending the TxBuffer +without any check. + +The File "I2C/I2C_TwoBoards/MasterReceiverInterrupt/main.h" allows different +possibilities of configuration of this example: + - Addressing mode : 7-bit or 10-bit + - I2C speed: Fast mode or Standard mode + +In both boards, the data transfers is managed using I2Cx_EV_IRQHandler +and I2Cx_ER_IRQHandler in stm32f2xx_it.c file. + +The SysTick is configured to generate interrupt each 10ms. A dedicated counter +inside the SysTick ISR is used to toggle the LED1 each 100ms indicating that the +firmware is running. +These operations are repeated infinitely. + +A defined communication timeout is insuring that the application will not remain +stuck if the I2C Master communication is corrupted. +You can adjust this timeout through the USER_TIMEOUT define inside main.h file +depending on CPU frequency and application conditions (interrupts routines, +number of data to transfer, speed, CPU frequency...). +When a given operation is not finished within the defined timeout, a callback is +made to the function "TimeOut_UserCallback()", this function is used to manage +timeout communication failure. In this example, this callback implements a simple +infinite loop, but user can add his own implementation to manage timeout failure. + + +@par Directory contents + + - I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_conf.h Library Configuration file + - I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_it.c Interrupt handlers + - I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_it.h Interrupt handlers header file + - I2C/I2C_TwoBoards/MasterReceiverInterrupt/main.c Main program + - I2C/I2C_TwoBoards/MasterReceiverInterrupt/main.h Main Header file + - I2C/I2C_TwoBoards/MasterReceiverInterrupt/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB (with no additional + hardware), and can be easily tailored to any other development board. + + - STM322xG-EVAL Set-up + - Connect I2C1 Master SCL pin (PB.06) to I2C1 Slave SCL (PB.06) + - Connect I2C1 Master SDA pin (PB.09) to I2C1 Slave SDA (PB.09) + + @note + - Pull-up resistors should be connected to I2C SCL and SDA Pins in case of + other boards use. + Pull-up resistors are already implemented on the STM322xG-EVAL evaluation + boards. + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_conf.h new file mode 100644 index 000000000..43d027cb1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_it.c new file mode 100644 index 000000000..82e069b15 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_it.c @@ -0,0 +1,436 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup MasterReceiverInterrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +extern uint8_t TxBuffer[]; +__IO uint8_t Counter = 0x00; +__IO uint32_t Event = 0x00; + +#if defined (I2C_MASTER) + uint8_t HEADER_ADDRESS_Write = (((SLAVE_ADDRESS & 0xFF00) >> 7) | 0xF0); + uint8_t HEADER_ADDRESS_Read = (((SLAVE_ADDRESS & 0xFF00) >> 7) | 0xF1); + + extern __IO uint32_t TimeOut; + extern __IO uint8_t Rx_Idx; + extern __IO uint8_t NumberOfByteToReceive; + extern uint8_t RxBuffer[]; + __IO uint8_t GenerateStartStatus = 0x00; + #ifdef I2C_10BITS_ADDRESS + __IO uint8_t Send_HeaderStatus = 0x00; + #endif /* I2C_10BITS_ADDRESS */ +#endif /* I2C_MASTER */ + +#if defined (I2C_SLAVE) + extern __IO uint8_t Tx_Idx; + extern uint8_t NbrOfDataToSend; +#endif /* I2C_SLAVE */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +#if defined (I2C_MASTER) + /* Decrement the time out value */ + if (TimeOut != 0x0) + { + TimeOut--; + } +#endif /* I2C_MASTER*/ + + if (Counter < 10) + { + Counter++; + } + else + { + Counter = 0x00; + STM_EVAL_LEDToggle(LED1); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ +/** + * @brief This function handles I2Cx Error interrupt request. + * @param None + * @retval None + */ +void I2Cx_ER_IRQHandler(void) +{ +#if defined (I2C_SLAVE) + + /* Read SR1 register to get I2C error */ + if ((I2C_ReadRegister(I2Cx, I2C_Register_SR1) & 0xFF00) != 0x00) + { + /* Clears error flags */ + I2Cx->SR1 &= 0x00FF; + Tx_Idx = 0; + } + +#endif /* I2C_SLAVE*/ + +#if defined (I2C_MASTER) + + /* Read SR1 register to get I2C error */ + if ((I2C_ReadRegister(I2Cx, I2C_Register_SR1) & 0xFF00) != 0x00) + { + /* Clears erreur flags */ + I2Cx->SR1 &= 0x00FF; + + /* Set LED3 and LED4 */ + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + STM_EVAL_LEDOff(LED2); + Rx_Idx = 0; + } +#endif /* I2C_MASTER*/ +} + +/** + * @brief This function handles I2Cx event interrupt request. + * @param None + * @retval None + */ +void I2Cx_EV_IRQHandler(void) +{ +#if defined (I2C_SLAVE) + /* Get Last I2C Event */ + Event = I2C_GetLastEvent(I2Cx); + switch (Event) + { + /*****************************************************************************/ + /* Slave Transmitter Events */ + /* */ + /* ***************************************************************************/ + + /* Check on EV1 */ + case I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: + I2C_SendData(I2Cx, TxBuffer[Tx_Idx++]); + /* Enable I2C event interrupt */ + I2C_ITConfig(I2Cx, I2C_IT_BUF, ENABLE); + break; + + /* Check on EV3 */ + case I2C_EVENT_SLAVE_BYTE_TRANSMITTING: + case I2C_EVENT_SLAVE_BYTE_TRANSMITTED: + if (Tx_Idx < NbrOfDataToSend) + I2C_SendData(I2Cx, TxBuffer[Tx_Idx++]); + else + /* Disable I2C event interrupt */ + I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_BUF, DISABLE); + break; + + default: + break; + } +#endif /* I2C_SLAVE*/ + +#if defined (I2C_MASTER) +/*****************************************************************************/ +/* Master Receiver */ +/* */ +/* ***************************************************************************/ +#ifdef I2C_10BITS_ADDRESS + /* Check on SB Flag and clear it */ + if(I2C_GetITStatus(I2Cx, I2C_IT_SB)== SET) + { + if (Send_HeaderStatus == 0x00) + { + /* Send Header to Slave for write */ + I2C_SendData(I2Cx, HEADER_ADDRESS_Write); + Send_HeaderStatus = 0x01; + GenerateStartStatus = 0x01; + } + else + { + /* Send Header to Slave for Read */ + I2C_SendData(I2Cx, HEADER_ADDRESS_Read); + Send_HeaderStatus = 0x00; + if (NumberOfByteToReceive == 0x03) + { + /* Disable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , DISABLE); + } + else + { + /* Enable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , ENABLE); + } + } + } + /* Check on ADD10 Flag */ + else if(I2C_GetITStatus(I2Cx, I2C_IT_ADD10)== SET) + { + /* Send slave Address */ + I2C_Send7bitAddress(I2Cx, (uint8_t)SLAVE_ADDRESS, I2C_Direction_Transmitter); + } + +#else /* I2C_7BITS_ADDRESS */ + + /* Check on EV5 */ + if(I2C_GetITStatus(I2Cx, I2C_IT_SB)== SET) + { + /* Send slave Address for read */ + I2C_Send7bitAddress(I2Cx, SLAVE_ADDRESS, I2C_Direction_Receiver); + if (NumberOfByteToReceive == 0x03) + { + /* Disable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , DISABLE); + } + else + { + /* Enable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , ENABLE); + } + } +#endif /* I2C_10BITS_ADDRESS */ + + else if(I2C_GetITStatus(I2Cx, I2C_IT_ADDR)== SET) + { + if (NumberOfByteToReceive == 1) + { + I2C_AcknowledgeConfig(I2Cx, DISABLE); + } + + /* Clear ADDR Register */ + (void)(I2Cx->SR1); + (void)(I2Cx->SR2); + if (GenerateStartStatus == 0x00) + { + if (NumberOfByteToReceive == 1) + { + I2C_GenerateSTOP(I2Cx, ENABLE); + } + + if (NumberOfByteToReceive == 2) + { + I2C_AcknowledgeConfig(I2Cx, DISABLE); + I2C_PECPositionConfig(I2Cx, I2C_PECPosition_Next); + /* Disable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , DISABLE); + } + } + +#ifdef I2C_10BITS_ADDRESS + if (GenerateStartStatus == 0x01) + { + /* Repeated Start */ + I2C_GenerateSTART(I2Cx, ENABLE); + GenerateStartStatus = 0x00; + } + +#endif /* I2C_10BITS_ADDRESS */ + } + + else if((I2C_GetITStatus(I2Cx, I2C_IT_RXNE)== SET)&&(I2C_GetITStatus(I2Cx, I2C_IT_BTF)== RESET)) + { + /* Store I2C received data */ + RxBuffer[Rx_Idx++] = I2C_ReceiveData (I2Cx); + NumberOfByteToReceive--; + + if (NumberOfByteToReceive == 0x03) + { + /* Disable buffer Interrupts */ + I2C_ITConfig(I2Cx, I2C_IT_BUF , DISABLE); + } + + if (NumberOfByteToReceive == 0x00) + { + /* Disable Error and Buffer Interrupts */ + I2C_ITConfig(I2Cx, (I2C_IT_EVT | I2C_IT_BUF), DISABLE); + } + } + /* BUSY, MSL and RXNE flags */ + else if(I2C_GetITStatus(I2Cx, I2C_IT_BTF)== SET) + { + /* if Three bytes remaining for reception */ + if (NumberOfByteToReceive == 3) + { + I2C_AcknowledgeConfig(I2Cx, DISABLE); + /* Store I2C received data */ + RxBuffer[Rx_Idx++] = I2C_ReceiveData (I2Cx); + NumberOfByteToReceive--; + } + else if (NumberOfByteToReceive == 2) + { + I2C_GenerateSTOP(I2Cx, ENABLE); + + /* Store I2C received data */ + RxBuffer[Rx_Idx++] = I2C_ReceiveData (I2Cx); + NumberOfByteToReceive--; + /* Store I2C received data */ + RxBuffer[Rx_Idx++] = I2C_ReceiveData (I2Cx); + NumberOfByteToReceive--; + /* Disable Error and Buffer Interrupts */ + I2C_ITConfig(I2Cx, (I2C_IT_EVT | I2C_IT_BUF), DISABLE); + } + else + { + /* Store I2C received data */ + RxBuffer[Rx_Idx++] = I2C_ReceiveData (I2Cx); + NumberOfByteToReceive--; + } + } +#endif /* I2C_MASTER*/ +} + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_it.h new file mode 100644 index 000000000..4be5fdd00 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_it.h @@ -0,0 +1,63 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void I2Cx_ER_IRQHANDLER(void); +void I2Cx_EV_IRQHANDLER(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterReceiverInterrupt/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/main.c new file mode 100644 index 000000000..3fb20f607 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/main.c @@ -0,0 +1,527 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/MasterTransmitterInterrupt/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup MasterTransmitterInterrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +I2C_InitTypeDef I2C_InitStructure; +uint8_t TxBuffer[] = "I2C Interrupt Example: Communication between two I2C using Interrupt"; +__IO uint8_t NumberOfByte = 0x00; + +#if defined (I2C_SLAVE) + __IO uint8_t CmdReceived = 0x00; + __IO uint8_t Rx_Idx = 0x00; + uint8_t RxBuffer [RXBUFFERSIZE]; +#endif /* I2C_SLAVE */ + +#if defined (I2C_MASTER) + __IO uint32_t TimeOut = 0x0; + __IO uint8_t CmdTransmitted = 0x00; + __IO JOYState_TypeDef PressedButton = JOY_NONE; + __IO uint8_t Tx_Idx = 0x00; +#endif /* I2C_MASTER */ +RCC_ClocksTypeDef RCC_Clocks; + +/* Private function prototypes -----------------------------------------------*/ +static void I2C_Config(void); +static void SysTickConfig(void); + +#if defined (I2C_MASTER) + static void TimeOut_UserCallback(void); +#endif /* I2C_MASTER */ + +#if defined (I2C_SLAVE) + static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength); + static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength); +#endif /* I2C_SLAVE */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* I2C configuration ---------------------------------------------------------*/ + I2C_Config(); + + /* Initialize LEDs mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + +#if defined (I2C_MASTER) + /* Initialize push-buttons mounted on STM322xG-EVAL board */ + TimeOut = USER_TIMEOUT; + while ((IOE_Config() != IOE_OK) && (TimeOut != 0x00)) + {} + + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } +#endif /* I2C_MASTER */ + + /* SysTick configuration -----------------------------------------------------*/ + SysTickConfig(); + +/*************************************Master Code******************************/ +#if defined (I2C_MASTER) + /* I2C De-initialize */ + I2C_DeInit(I2Cx); + + /*!< I2C Struct Initialize */ + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DUTYCYCLE; + I2C_InitStructure.I2C_OwnAddress1 = 0xA0; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + +#ifndef I2C_10BITS_ADDRESS + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +#else + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_10bit; +#endif /* I2C_10BITS_ADDRESS */ + + /*!< I2C Initialize */ + I2C_Init(I2Cx, &I2C_InitStructure); + + /* Enable Error Interrupt */ + I2C_ITConfig(I2Cx, I2C_IT_ERR , ENABLE); + + /* I2C ENABLE */ + I2C_Cmd(I2Cx, ENABLE); + + while (1) + { + CmdTransmitted = 0x00; + NumberOfByte = 0x00; + Tx_Idx = 0x00; + + /* Clear PressedButton by reading joystick */ + PressedButton = IOE_JoyStickGetState(); + + /* Waiting joystick pressed */ + while (PressedButton == JOY_NONE) + { + PressedButton = IOE_JoyStickGetState(); + } + + /* I2C in Master Transmitter Mode ----------------------------------------*/ + switch (PressedButton) + { + /* JOY_RIGHT button pressed */ + case JOY_RIGHT: + NumberOfByte = CMD_RIGHT_SIZE; + CmdTransmitted = CMD_RIGHT; + break; + /* JOY_LEFT button pressed */ + case JOY_LEFT: + NumberOfByte = CMD_LEFT_SIZE; + CmdTransmitted = CMD_LEFT; + break; + /* JOY_UP button pressed */ + case JOY_UP: + NumberOfByte = CMD_UP_SIZE; + CmdTransmitted = CMD_UP; + break; + /* JOY_DOWN button pressed */ + case JOY_DOWN: + NumberOfByte = CMD_DOWN_SIZE; + CmdTransmitted = CMD_DOWN; + break; + /* JOY_SEL button pressed */ + case JOY_SEL: + NumberOfByte = CMD_SEL_SIZE; + CmdTransmitted = CMD_SEL; + break; + default: + break; + } + + if (CmdTransmitted != 0x00) + { + /* Enable Error and Buffer Interrupts */ + I2C_ITConfig(I2Cx, (I2C_IT_EVT | I2C_IT_BUF), ENABLE); + /* Generate the Start condition */ + I2C_GenerateSTART(I2Cx, ENABLE); + /* Data transfer is performed in the I2C interrupt routine */ + /* Wait until end of data transfer or time out */ + TimeOut = USER_TIMEOUT; + while ((Tx_Idx < GetVar_NbrOfDataToTransfer())&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + TimeOut = USER_TIMEOUT; + while ((I2C_GetFlagStatus(I2Cx, I2C_FLAG_BUSY))&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + } + } +#endif /* I2C_MASTER */ + + + /**********************************Slave Code**********************************/ +#if defined (I2C_SLAVE) + + I2C_DeInit(I2Cx); + + /* Initialize I2C peripheral */ + /*!< I2C Init */ + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DUTYCYCLE; + I2C_InitStructure.I2C_OwnAddress1 = SLAVE_ADDRESS; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + +#ifndef I2C_10BITS_ADDRESS + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +#else + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_10bit; +#endif /* I2C_10BITS_ADDRESS */ + + I2C_Init(I2Cx, &I2C_InitStructure); + + /* Enable Error Interrupt */ + I2C_ITConfig(I2Cx, (I2C_IT_ERR | I2C_IT_EVT | I2C_IT_BUF), ENABLE); + + /* I2C ENABLE */ + I2C_Cmd(I2Cx, ENABLE); + + /* Infinite Loop */ + while (1) + { + CmdReceived = 0x00; + NumberOfByte = 0x00; + + /* Clear the RxBuffer */ + Fill_Buffer(RxBuffer, RXBUFFERSIZE); + + while (CmdReceived == 0x00) + {} + + /* Wait until end of data transfer */ + while (Rx_Idx < GetVar_NbrOfDataToReceive()) + {} + + /* I2C in Slave Receiver Mode --------------------------------------------*/ + if (CmdReceived != 0x00) + { + switch (Rx_Idx) + { + /* Right button pressed */ + case CMD_RIGHT_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_RIGHT_SIZE) == PASSED) + { + /* Turn ON LED2 and LED3 */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + /* Turn all other LEDs off */ + STM_EVAL_LEDOff(LED4); + } + break; + /* Left button pressed*/ + case CMD_LEFT_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_LEFT_SIZE) == PASSED) + { + /* Turn ON LED4 */ + STM_EVAL_LEDOn(LED4); + /* Turn all other LEDs off */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + } + break; + /* Up button pressed */ + case CMD_UP_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_UP_SIZE) == PASSED) + { + /* Turn ON LED2 */ + STM_EVAL_LEDOn(LED2); + /* Turn all other LEDs off */ + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + } + break; + /* Down button pressed */ + case CMD_DOWN_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_DOWN_SIZE) == PASSED) + { + /* Turn ON LED3 */ + STM_EVAL_LEDOn(LED3); + /* Turn all other LEDs off */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED4); + } + break; + /* Sel button pressed */ + case CMD_SEL_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_SEL_SIZE) == PASSED) + { + /* Turn ON all LEDs */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + } + break; + default: + break; + } + } + } +#endif /* I2C_SLAVE */ +} + +/** + * @brief Enables the I2C Clock and configures the different GPIO ports. + * @param None + * @retval None + */ +static void I2C_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* RCC Configuration */ + /*I2C Peripheral clock enable */ + RCC_APB1PeriphClockCmd(I2Cx_CLK, ENABLE); + + /*SDA GPIO clock enable */ + RCC_AHB1PeriphClockCmd(I2Cx_SDA_GPIO_CLK, ENABLE); + + /*SCL GPIO clock enable */ + RCC_AHB1PeriphClockCmd(I2Cx_SCL_GPIO_CLK, ENABLE); + + /* Reset I2Cx IP */ + RCC_APB1PeriphResetCmd(I2Cx_CLK, ENABLE); + + /* Release reset signal of I2Cx IP */ + RCC_APB1PeriphResetCmd(I2Cx_CLK, DISABLE); + + /* GPIO Configuration */ + /*Configure I2C SCL pin */ + GPIO_InitStructure.GPIO_Pin = I2Cx_SCL_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(I2Cx_SCL_GPIO_PORT, &GPIO_InitStructure); + + /*Configure I2C SDA pin */ + GPIO_InitStructure.GPIO_Pin = I2Cx_SDA_PIN; + GPIO_Init(I2Cx_SDA_GPIO_PORT, &GPIO_InitStructure); + + /* Connect PXx to I2C_SCL */ + GPIO_PinAFConfig(I2Cx_SCL_GPIO_PORT, I2Cx_SCL_SOURCE, I2Cx_SCL_AF); + + /* Connect PXx to I2C_SDA */ + GPIO_PinAFConfig(I2Cx_SDA_GPIO_PORT, I2Cx_SDA_SOURCE, I2Cx_SDA_AF); + + /* NVIC configuration */ + /* Configure the Priority Group to 1 bit */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + + /* Configure the I2C event priority */ + NVIC_InitStructure.NVIC_IRQChannel = I2Cx_EV_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Configure I2C error interrupt to have the higher priority */ + NVIC_InitStructure.NVIC_IRQChannel = I2Cx_ER_IRQn; + NVIC_Init(&NVIC_InitStructure); +} + +/** + * @brief Configure a SysTick Base time to 10 ms. + * @param None + * @retval None + */ +static void SysTickConfig(void) +{ + /* SysTick end of count event each 10ms */ + RCC_GetClocksFreq(&RCC_Clocks); + SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); + + /* Configure the SysTick handler priority */ + NVIC_SetPriority(SysTick_IRQn, 0x0); +} + +#if defined (I2C_MASTER) +/** + * @brief Returns NbrOfDataToTransfer value. + * @param None + * @retval Tx Buffer Size (NbrOfDataToTransfer). + */ +uint8_t GetVar_NbrOfDataToTransfer(void) +{ + return NumberOfByte; +} + +/** + * @brief Basic management of the timeout situation. + * @param None. + * @retval None. + */ +static void TimeOut_UserCallback(void) +{ + /* User can add his own implementation to manage TimeOut Communication failure */ + /* Block communication and all processes */ + while (1) + { + } +} +#endif /* I2C_MASTER */ + +#if defined (I2C_SLAVE) +/** + * @brief Returns NbrOfDataToReceive value. + * @param None + * @retval Rx Buffer Size (NumberOfByte). + */ +uint8_t GetVar_NbrOfDataToReceive(void) +{ + switch (CmdReceived) + { + case CMD_RIGHT: + NumberOfByte = CMD_RIGHT_SIZE; + break; + case CMD_LEFT: + NumberOfByte = CMD_LEFT_SIZE; + break; + case CMD_UP: + NumberOfByte = CMD_UP_SIZE; + break; + case CMD_DOWN: + NumberOfByte = CMD_DOWN_SIZE; + break; + case CMD_SEL: + NumberOfByte = CMD_SEL_SIZE; + break; + default: + break; + } + return NumberOfByte; +} + +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer1 identical to pBuffer2 + * FAILED: pBuffer1 differs from pBuffer2 + */ +static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} + +/** + * @brief Fills buffer. + * @param pBuffer: pointer on the Buffer to fill + * @param BufferLength: size of the buffer to fill + * @retval None + */ +static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength) +{ + uint16_t index = 0; + + /* Put in global buffer same values */ + for (index = 0; index < BufferLength; index++ ) + { + pBuffer[index] = 0x00; + } +} +#endif /* I2C_SLAVE */ + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/main.h new file mode 100644 index 000000000..2e9d4cb34 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/main.h @@ -0,0 +1,141 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/MasterTransmitterInterrupt/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program header + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stm322xg_eval_ioe.h" + +/* Exported typedef -----------------------------------------------------------*/ +#define countof(a) (sizeof(a) / sizeof(*(a))) +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Exported define ------------------------------------------------------------*/ +/* Uncomment the line below if you will use the I2C peripheral as a Master */ +#define I2C_MASTER +/* Uncomment the line below if you will use the I2C peripheral as a Slave */ +/* #define I2C_SLAVE */ + +/* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral + input clock) must be a multiple of 10 MHz */ +/* Uncomment the line below if you will use the I2C peripheral in Fast Mode */ +/* #define FAST_I2C_MODE */ + +/* Uncomment the line below if you will use the I2C peripheral in 10-bit addressing + mode */ +/* #define I2C_10BITS_ADDRESS */ + +/* Define I2C Speed --------------------------------------------------------*/ +#ifdef FAST_I2C_MODE + #define I2C_SPEED 340000 + #define I2C_DUTYCYCLE I2C_DutyCycle_16_9 +#else /* STANDARD_I2C_MODE*/ + #define I2C_SPEED 100000 + #define I2C_DUTYCYCLE I2C_DutyCycle_2 +#endif /* FAST_I2C_MODE*/ + +/* Define Slave Address ---------------------------------------------------*/ +#ifdef I2C_10BITS_ADDRESS + #define SLAVE_ADDRESS (uint16_t)0x0330 +#else /* I2C_7BITS_ADDRESS */ + #define SLAVE_ADDRESS 0x30 +#endif /* I2C_10BITS_ADDRESS */ + +/* USER_TIMEOUT value for waiting loops. This timeout is just a guarantee that the + application will not remain stuck if the I2C communication is corrupted. + You may modify this timeout value depending on CPU frequency and application + conditions (interrupts routines, number of data to transfer, speed, CPU + frequency...). */ +#define USER_TIMEOUT ((uint32_t)0x64) /* Waiting 1s */ + +#define TXBUFFERSIZE (countof(TxBuffer) - 1) +#define RXBUFFERSIZE TXBUFFERSIZE + +/* I2Cx Communication boards Interface */ +#define I2Cx I2C1 +#define I2Cx_CLK RCC_APB1Periph_I2C1 +#define I2Cx_EV_IRQn I2C1_EV_IRQn +#define I2Cx_ER_IRQn I2C1_ER_IRQn +#define I2Cx_EV_IRQHandler I2C1_EV_IRQHandler +#define I2Cx_ER_IRQHandler I2C1_ER_IRQHandler + +#define I2Cx_SDA_GPIO_CLK RCC_AHB1Periph_GPIOB +#define I2Cx_SDA_PIN GPIO_Pin_9 +#define I2Cx_SDA_GPIO_PORT GPIOB +#define I2Cx_SDA_SOURCE GPIO_PinSource9 +#define I2Cx_SDA_AF GPIO_AF_I2C1 + +#define I2Cx_SCL_GPIO_CLK RCC_AHB1Periph_GPIOB +#define I2Cx_SCL_PIN GPIO_Pin_6 +#define I2Cx_SCL_GPIO_PORT GPIOB +#define I2Cx_SCL_SOURCE GPIO_PinSource6 +#define I2Cx_SCL_AF GPIO_AF_I2C1 + +/* Joystick Commands */ +#define CMD_RIGHT 0x55 +#define CMD_LEFT 0xAA +#define CMD_UP 0x33 +#define CMD_DOWN 0xCC +#define CMD_SEL 0xFF + +#define CMD_ACK 0x66 + +/* Define numbers of bytes to transmit from TxBuffer */ +#define CMD_RIGHT_SIZE 0x01 +#define CMD_LEFT_SIZE 0x05 +#define CMD_UP_SIZE 0x14 +#define CMD_DOWN_SIZE 0x1E +#define CMD_SEL_SIZE TXBUFFERSIZE + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#if defined (I2C_MASTER) +uint8_t GetVar_NbrOfDataToTransfer(void); +#endif /* I2C_MASTER */ + +#if defined (I2C_SLAVE) +uint8_t GetVar_NbrOfDataToReceive(void); +#endif /* I2C_SLAVE */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/readme.txt new file mode 100644 index 000000000..5686b1adf --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/readme.txt @@ -0,0 +1,155 @@ +/** + @page I2C_MasterTransmitterInterrupt I2C Communication between Master in mode transmitter + and slave in mode Receiver using interrupts example + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file I2C/I2C_TwoBoards/MasterTransmitterInterrupt/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the Two boards I2C Communication example: Master transmitter + * and Slave and receiver. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a small application in which joystick buttons are used +to trigger I2C communication using interrupt and though using I2C firmware library. + +- Hardware Description + +To use this example, you need to load it in two STM32 boards (let's call them +Board A and Board B) then connect these two boards through I2C lines and GND. +In the firmware example uncomment the dedicated line in the main.h file to use +the I2C peripheral as STM32 Master device or as STM32 Slave . + +@verbatim +*------------------------------------------------------------------------------* +| BOARD A BOARD B | +| ____________________ ____________________ | +| | | | | | +| | | | | | +| | __________ | | __________ | | +| | |I2C Master|____|_______SDA_______|____|I2C Slave | | | +| | | Device |____|_______SCL_______|____| Device | | | +| | |__________| | | |__________| | | +| | O LD1 | | O LD1 | | +| | O LD2 Joystick | | O LD2 | | +| | O LD3 _ | | O LD3 | | +| | O LD4 |_| | | O LD4 | | +| | | | | | +| | GND O--|-----------------|--O GND | | +| |____________________| |____________________| | +| | +| | +*------------------------------------------------------------------------------* +@endverbatim + +- Software Description + +This example requires two boards(Master and Slave) + +In master board, I2C peripheral is configured as Master Transmitter with Interrupt, +whereas in Slave board, I2C peripheral is configured as Slave Receiver with Interrupt. +According to the pushed joystick button in the master board a specific LED will +be ON in the slave board. + +At each joystick position press + - The master sends the defined NumberOfByte from TxBuffer to the slave + - The Slave compares the NumberOfByte received data with the defined ones into TxBuffer + +Received data correctness is signaled by LED lightening and though as follow: + - Joystick RIGHT and data correctly received ==> LD2, LD3 ON and LD4 OFF + - Joystick LEFT and data correctly received ==> LD4 ON, LD2 and LD3 are OFF + - Joystick UP and data correctly received ==> LD2 ON, LD3 and LD4 are OFF + - Joystick DOWN and data correctly received ==> LD3 ON, LD2 and LD4 are OFF + - Joystick SEL and data correctly received ==> LD2, LD3 and LD4 are ON + +Communication error are handled in both Master and Slave sides, their occurrence +will be signaled respectively by puting LED3 and LED4 On. + +The File "I2C/I2C_TwoBoards/MasterTransmitterInterrupt/main.h" allows different +possibilities of configuration of this example: + - Addressing mode : 7-bit or 10-bit + - I2C speed: Fast mode or Standard mode + - Buffer size also can be configured + +In both boards, the data transfers is managed using I2Cx_EV_IRQHandler +and I2Cx_ER_IRQHandler in stm32f2xx_it.c file. + +The SysTick is configured to generate interrupt each 10ms. A dedicated counter +inside the SysTick ISR is used to toggle the LD1 each 100ms indicating that the +firmware is running. +These operations can be repeated infinitely. + +A defined communication timeout is insuring that the application will not remain +stuck if the I2C Master communication is corrupted. +You can adjust this timeout through the USER_TIMEOUT define inside main.h file +depending on CPU frequency and application conditions (interrupts routines, +number of data to transfer, speed, CPU frequency...). +When a given operation is not finished within the defined timeout, a callback is +made to the function "TimeOut_UserCallback()", this function is used to manage +timeout communication failure. In this example, this callback implements a simple +infinite loop, but user can add his own implementation to manage timeout failure. + + +@par Directory contents + + - I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_conf.h Library Configuration file + - I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_it.c Interrupt handlers + - I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_it.h Interrupt handlers header file + - I2C/I2C_TwoBoards/MasterTransmitterInterrupt/main.c Main program + - I2C/I2C_TwoBoards/MasterTransmitterInterrupt/main.h Main Header file + - I2C/I2C_TwoBoards/MasterTransmitterInterrupt/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB (with no additional + hardware), and can be easily tailored to any other development board. + + - STM322xG-EVAL Set-up + - Connect I2C1 Master SCL pin (PB.06) to I2C1 Slave SCL (PB.06) + - Connect I2C1 Master SDA pin (PB.09) to I2C1 Slave SDA (PB.09) + + @note + - Pull-up resistors should be connected to I2C SCL and SDA Pins in case of + other boards use. + Pull-up resistors are already implemented on the STM322xG-EVAL evaluation + boards. + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_conf.h new file mode 100644 index 000000000..43d027cb1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/MasterReceiverInterrupt/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_it.c new file mode 100644 index 000000000..ebee9c191 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_it.c @@ -0,0 +1,331 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup MasterTransmitterInterrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern uint8_t TxBuffer[]; +__IO uint8_t Counter = 0x00; +extern __IO uint8_t NumberOfByte; + +#if defined (I2C_SLAVE) + __IO uint32_t Event = 0x00; + extern uint8_t RxBuffer[]; + extern __IO uint8_t Rx_Idx; + extern __IO uint8_t CmdReceived; +#endif /* I2C_SLAVE */ + +#if defined (I2C_MASTER) + uint8_t HEADER_ADDRESS_Write = (((SLAVE_ADDRESS & 0xFF00) >> 7) | 0xF0); + extern __IO uint8_t PressedButton; + extern __IO uint8_t Tx_Idx; + extern __IO uint32_t TimeOut; + extern __IO uint8_t CmdTransmitted; +#endif /* I2C_MASTER */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +#if defined (I2C_MASTER) + /* Decrement the time out value */ + if (TimeOut != 0x0) + { + TimeOut--; + } +#endif /* I2C_MASTER*/ + + if (Counter < 10) + { + Counter++; + } + else + { + Counter = 0x00; + STM_EVAL_LEDToggle(LED1); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ +/** + * @brief This function handles I2Cx Error interrupt request. + * @param None + * @retval None + */ +void I2Cx_ER_IRQHandler(void) +{ +#if defined (I2C_SLAVE) + + /* Read SR1 register to get I2C error */ + if ((I2C_ReadRegister(I2Cx, I2C_Register_SR1) & 0xFF00) != 0x00) + { + /* Clears erreur flags */ + I2Cx->SR1 &= 0x00FF; + } +#endif /* I2C_SLAVE*/ + +#if defined (I2C_MASTER) + + /* Read SR1 register to get I2C error */ + if ((I2C_ReadRegister(I2Cx, I2C_Register_SR1) & 0xFF00) != 0x00) + { + /* Clears erreur flags */ + I2Cx->SR1 &= 0x00FF; + + /* Set LED3 and LED4 */ + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + STM_EVAL_LEDOff(LED2); + } +#endif /* I2C_MASTER*/ +} + +/** + * @brief This function handles I2Cx event interrupt request. + * @param None + * @retval None + */ +void I2Cx_EV_IRQHandler(void) +{ +#if defined (I2C_MASTER) + + switch (I2C_GetLastEvent(I2Cx)) + { + /* EV5 */ + case I2C_EVENT_MASTER_MODE_SELECT : +#ifdef I2C_10BITS_ADDRESS + /* Send Header to Slave for write */ + I2C_SendData(I2Cx, HEADER_ADDRESS_Write); + break; + + /* EV9 */ + case I2C_EVENT_MASTER_MODE_ADDRESS10: +#endif /* I2C_10BITS_ADDRESS */ + + /* Send slave Address for write */ + I2C_Send7bitAddress(I2Cx, (uint8_t)SLAVE_ADDRESS, I2C_Direction_Transmitter); + break; + + /* EV6 */ + case I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: + /* Send the I2C transaction code */ + I2C_SendData(I2Cx, CmdTransmitted); + break; + + /* EV8 */ + case I2C_EVENT_MASTER_BYTE_TRANSMITTING: + case I2C_EVENT_MASTER_BYTE_TRANSMITTED: + if (Tx_Idx == GetVar_NbrOfDataToTransfer()) + { + /* Send STOP condition */ + I2C_GenerateSTOP(I2Cx, ENABLE); + I2C_ITConfig(I2Cx, I2C_IT_EVT | I2C_IT_BUF, DISABLE); + } + else + { + /* Transmit Data TxBuffer */ + I2C_SendData(I2Cx, TxBuffer[Tx_Idx++]); + } + break; + + default: + break; + } + +#endif /* I2C_MASTER*/ + +#if defined (I2C_SLAVE) + + /* Get Last I2C Event */ + Event = I2C_GetLastEvent(I2Cx); + + switch (Event) + { + /* Check on EV1*/ + case I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: + Rx_Idx = 0x00; + break; + + /* Check on EV2*/ + case I2C_EVENT_SLAVE_BYTE_RECEIVED: + case (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_SR1_BTF): + if (CmdReceived == 0x00) + { + CmdReceived = I2C_ReceiveData(I2Cx); + } + else + { + RxBuffer[Rx_Idx++] = I2C_ReceiveData(I2Cx); + } + break; + + /* Check on EV4 */ + case (I2C_EVENT_SLAVE_STOP_DETECTED): + I2C_GetFlagStatus(I2Cx, I2C_FLAG_STOPF); + I2C_Cmd(I2Cx, ENABLE); + break; + + default: + break; + } +#endif /* I2C_SLAVE*/ +} + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_it.h new file mode 100644 index 000000000..a89f7d981 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_it.h @@ -0,0 +1,63 @@ +/** + ****************************************************************************** + * @file I2C/I2C_TwoBoards/MasterTransmitterInterrupt/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void I2Cx_ER_IRQHANDLER(void); +void I2Cx_EV_IRQHANDLER(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/I2C_TwoBoards/MasterTransmitterInterrupt/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/main.c new file mode 100644 index 000000000..aa5848339 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/main.c @@ -0,0 +1,276 @@ +/** + ****************************************************************************** + * @file I2C/IOE/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2C_IOE + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static __IO uint32_t TimingDelay; +RCC_ClocksTypeDef RCC_Clocks; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* SysTick end of count event each 10ms */ + RCC_GetClocksFreq(&RCC_Clocks); + SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); + + /* Initialize LEDs and push-buttons mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Select the Button test mode (polling or interrupt) BUTTON_MODE in main.h */ + STM_EVAL_PBInit(BUTTON_WAKEUP, BUTTON_MODE); + STM_EVAL_PBInit(BUTTON_TAMPER, BUTTON_MODE); + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE); + + /* Initialize the LCD */ + STM322xG_LCD_Init(); + + /* Clear the LCD */ + LCD_Clear(White); + /* Set the LCD Back Color */ + LCD_SetBackColor(Blue); + /* Set the LCD Text Color */ + LCD_SetTextColor(White); + + LCD_DisplayStringLine(Line0, (uint8_t *)" STM322xG-EVAL "); + LCD_DisplayStringLine(Line1, (uint8_t *)" Example on how to "); + LCD_DisplayStringLine(Line2, (uint8_t *)" use the IO Expander"); + + /* Configure the IO Expander */ + if (IOE_Config() == IOE_OK) + { + LCD_DisplayStringLine(Line4, (uint8_t *)" IO Expander OK "); + } + else + { + LCD_DisplayStringLine(Line4, (uint8_t *)"IO Expander FAILED "); + LCD_DisplayStringLine(Line5, (uint8_t *)" Please Reset the "); + LCD_DisplayStringLine(Line6, (uint8_t *)" board and start "); + LCD_DisplayStringLine(Line7, (uint8_t *)" again "); + while(1); + } + + /* Leds Control blocks */ + LCD_SetTextColor(Blue); + LCD_DrawRect(180, 310, 40, 60); + LCD_SetTextColor(Red); + LCD_DrawRect(180, 230, 40, 60); + LCD_SetTextColor(Yellow); + LCD_DrawRect(180, 150, 40, 60); + LCD_SetTextColor(Green); + LCD_DrawRect(180, 70, 40, 60); + +#ifdef IOE_INTERRUPT_MODE + /* Enable the Touch Screen and Joystick interrupts */ + IOE_ITConfig(IOE_ITSRC_JOYSTICK | IOE_ITSRC_TSC); +#endif /* IOE_INTERRUPT_MODE */ + + + while(1) + { +#ifdef IOE_POLLING_MODE + static JOY_State_TypeDef JoyState = JOY_NONE; + static TS_STATE* TS_State; + + /* Get the Joystick State */ + JoyState = IOE_JoyStickGetState(); + + switch (JoyState) + { + case JOY_NONE: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: ---- "); + break; + case JOY_UP: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: UP "); + break; + case JOY_DOWN: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: DOWN "); + break; + case JOY_LEFT: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: LEFT "); + break; + case JOY_RIGHT: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: RIGHT "); + break; + case JOY_CENTER: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: CENTER "); + break; + default: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: ERROR "); + break; + } + + /* Update the structure with the current position */ + TS_State = IOE_TS_GetState(); + + if ((TS_State->TouchDetected) && (TS_State->Y < 220) && (TS_State->Y > 180)) + { + if ((TS_State->X > 10) && (TS_State->X < 70)) + { + LCD_DisplayStringLine(Line6, (uint8_t *)" LD4 "); + STM_EVAL_LEDOn(LED4); + } + else if ((TS_State->X > 90) && (TS_State->X < 150)) + { + LCD_DisplayStringLine(Line6, (uint8_t *)" LD3 "); + STM_EVAL_LEDOn(LED3); + } + else if ((TS_State->X > 170) && (TS_State->X < 230)) + { + LCD_DisplayStringLine(Line6, (uint8_t *)" LD2 "); + STM_EVAL_LEDOn(LED2); + } + else if ((TS_State->X > 250) && (TS_State->X < 310)) + { + LCD_DisplayStringLine(Line6, (uint8_t *)" LD1 "); + STM_EVAL_LEDOn(LED1); + } + } + else + { + STM_EVAL_LEDOff(LED1); + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + } +#endif /* IOE_POLLING_MODE */ + +#ifdef BUTTON_POLLING_MODE + /* Insert 10 ms delay */ + Delay(1); + + if (STM_EVAL_PBGetState(BUTTON_KEY) == 0) + { + /* Toggle LD1 */ + STM_EVAL_LEDToggle(LED1); + + LCD_DisplayStringLine(Line4, (uint8_t *)"Pol: KEY Pressed "); + } + + if (STM_EVAL_PBGetState(BUTTON_TAMPER) == 0) + { + /* Toggle LD2 */ + STM_EVAL_LEDToggle(LED2); + + LCD_DisplayStringLine(Line4, (uint8_t *)"Pol: TAMPER Pressed "); + } + + if (STM_EVAL_PBGetState(BUTTON_WAKEUP) != 0) + { + /* Toggle LD3 */ + STM_EVAL_LEDToggle(LED3); + LCD_DisplayStringLine(Line4, (uint8_t *)"Pol: WAKEUP Pressed "); + } +#endif + } +} + +/** + * @brief Inserts a delay time. + * @param nTime: specifies the delay time length, in 10 ms. + * @retval None + */ +void Delay(uint32_t nTime) +{ + TimingDelay = nTime; + + while(TimingDelay != 0); +} + +/** + * @brief Decrements the TimingDelay variable. + * @param None + * @retval None + */ +void TimingDelay_Decrement(void) +{ + if (TimingDelay != 0x00) + { + TimingDelay--; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + LCD_DisplayStringLine(Line0, "assert_param error!!"); + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/main.h new file mode 100644 index 000000000..e148ecb47 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/main.h @@ -0,0 +1,59 @@ +/** + ****************************************************************************** + * @file I2C/IOE/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" +#include "stm322xg_eval_lcd.h" +#include "stm322xg_eval_ioe.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +//#define BUTTON_POLLING_MODE +#define BUTTON_INTERRUPT_MODE + +//#define IOE_POLLING_MODE +#define IOE_INTERRUPT_MODE + +#ifdef BUTTON_POLLING_MODE + #define BUTTON_MODE BUTTON_MODE_GPIO +#else + #define BUTTON_MODE BUTTON_MODE_EXTI +#endif /* BUTTON_POLLING_MODE */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TimingDelay_Decrement(void); +void Delay(__IO uint32_t nTime); + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/readme.txt new file mode 100644 index 000000000..4522e45c1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/readme.txt @@ -0,0 +1,100 @@ +/** + @page I2C_IOE Example on how to use the IO Expander + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file I2C/IOE/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the I2C IOExpander example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This firmware provides an example of configuring and using the IO Expander STMPE811 +in order to control input Joystick IOs, output IOs and the Touch Screen feature. +This example provides the elementary steps to control the following modules and +use them in an application: +The IO pins are used for: + - Getting Joystick pins status (Polling and interrupt) only for STM3210C-EVAL. + - The Touch Screen controller is used to get the Touched area detection information + in a single point mode (Polling and interrupt). + +The input information can be used either in Polling mode (uncomment the define +#define IOE_POLLING_MODE) or in Interrupt mode (uncomment the define #define +IOE_INTERRUPT_MODE). These defines are in main.h file. + +After configuring the IO Expander modules and Interrupts (if needed), the output +IOs are set to their default state. These operations are done by the functions: +IOE_Config() and IOE_ITConfig(). If the IO Expander is not operational (or the +I2C pins are not in the correct level) the IOE_Config() function returns a value +different from 0 and a message is displayed on the LCD screen. + +To get the status of an input: + - IOE_JoyStickGetState() function is used for Joystick and returns a JOY_State_TypeDef + value indicating the currently pressed key. This information is used to update + the LCD display (the Joystick pressed key name is displayed). + - IOE_TS_GetState() function is used for Touch Screen and returns a pointer to + a structure holding the Touch Screen status (did a Touch Detection happened, + X, Y, and Z positions). Only detection into the drawn rectangles areas is + considered and used to update the LEDs status and LCD display (corresponding + LED turned ON when its rectangle is touched, and the LED name is displayed on + the LCD screen). + +Besides, the examples checks the status of the other Push-Buttons implemented on +the board (Key, Tamper and WakeUp push-buttons). They are checked in parallel +with the IO Expander IOs and the LCD display and LEDs are updated according to +the push buttons state. + + +@par Directory contents + + - I2C/IOE/system_stm32f2xx.c STM32F2xx system clock configuration file + - I2C/IOE/stm32f2xx_conf.h Library Configuration file + - I2C/IOE/stm32f2xx_it.c Interrupt handlers + - I2C/IOE/stm32f2xx_it.h Interrupt handlers header file + - I2C/IOE/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB (with no + additional hardware), and can be easily tailored to any other development board. + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/stm32f2xx_conf.h new file mode 100644 index 000000000..542804676 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file I2C/IOE/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/stm32f2xx_it.c new file mode 100644 index 000000000..244953b23 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/stm32f2xx_it.c @@ -0,0 +1,320 @@ +/** + ****************************************************************************** + * @file I2C/IOE/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2C_IOE + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + TimingDelay_Decrement(); +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles External line 0 interrupt request. + * @param None + * @retval None + */ +void EXTI0_IRQHandler(void) +{ + if(EXTI_GetITStatus(WAKEUP_BUTTON_EXTI_LINE) != RESET) + { + /* Toggle LD3 */ + STM_EVAL_LEDToggle(LED3); + + LCD_DisplayStringLine(Line4, (uint8_t *)"IT: WAKEUP Pressed "); + + EXTI_ClearITPendingBit(WAKEUP_BUTTON_EXTI_LINE); + } +} + +/** + * @brief This function handles External line 2 interrupt request. + * @param None + * @retval None + */ +void EXTI2_IRQHandler(void) +{ + if(EXTI_GetITStatus(IOE_IT_EXTI_LINE) != RESET) + { + +#ifdef IOE_INTERRUPT_MODE + static JOY_State_TypeDef JoyState = JOY_NONE; + static TS_STATE* TS_State; + + /* Check if the interrupt source is the Touch Screen */ + if (IOE_GetGITStatus(IOE_1_ADDR, IOE_TS_IT) & IOE_TS_IT) + { + /* Update the structure with the current position */ + TS_State = IOE_TS_GetState(); + + if ((TS_State->TouchDetected) && (TS_State->Y < 220) && (TS_State->Y > 180)) + { + if ((TS_State->X > 10) && (TS_State->X < 70)) + { + LCD_DisplayStringLine(Line6, (uint8_t *)" LD4 "); + STM_EVAL_LEDOn(LED4); + } + else if ((TS_State->X > 90) && (TS_State->X < 150)) + { + LCD_DisplayStringLine(Line6, (uint8_t *)" LD3 "); + STM_EVAL_LEDOn(LED3); + } + else if ((TS_State->X > 170) && (TS_State->X < 230)) + { + LCD_DisplayStringLine(Line6, (uint8_t *)" LD2 "); + STM_EVAL_LEDOn(LED2); + } + else if ((TS_State->X > 250) && (TS_State->X < 310)) + { + LCD_DisplayStringLine(Line6, (uint8_t *)" LD1 "); + STM_EVAL_LEDOn(LED1); + } + } + else + { + STM_EVAL_LEDOff(LED1); + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + } + + /* Clear the interrupt pending bits */ + IOE_ClearGITPending(IOE_1_ADDR, IOE_TS_IT); + } + else if (IOE_GetGITStatus(IOE_2_ADDR, IOE_GIT_GPIO)) + { + /* Get the Joytick State */ + JoyState = IOE_JoyStickGetState(); + + switch (JoyState) + { + case JOY_NONE: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: IT ---- "); + break; + case JOY_UP: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: IT UP "); + break; + case JOY_DOWN: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: IT DOWN "); + break; + case JOY_LEFT: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: IT LEFT "); + break; + case JOY_RIGHT: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: IT RIGHT "); + break; + case JOY_CENTER: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: IT CENTER "); + break; + default: + LCD_DisplayStringLine(Line5, (uint8_t *)"JOY: IT ERROR "); + break; + } + + /* Clear the interrupt pending bits */ + IOE_ClearGITPending(IOE_2_ADDR, IOE_GIT_GPIO); + IOE_ClearIOITPending(IOE_2_ADDR, IOE_JOY_IT); + } + else + { + IOE_ClearGITPending(IOE_1_ADDR, ALL_IT); + IOE_ClearGITPending(IOE_2_ADDR, ALL_IT); + } +#endif /* IOE_INTERRUPT_MODE */ + + EXTI_ClearITPendingBit(IOE_IT_EXTI_LINE); + } +} + +/** + * @brief This function handles External lines 15 to 10 interrupt request. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET) + { + /* Toggle LD1 */ + STM_EVAL_LEDToggle(LED1); + + LCD_DisplayStringLine(Line4, (uint8_t *)"IT: KEY Pressed "); + + EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); + } + + if(EXTI_GetITStatus(TAMPER_BUTTON_EXTI_LINE) != RESET) + { + /* Toggle LD2 */ + STM_EVAL_LEDToggle(LED2); + + LCD_DisplayStringLine(Line4, (uint8_t *)"IT: TAMPER Pressed "); + + EXTI_ClearITPendingBit(TAMPER_BUTTON_EXTI_LINE); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/stm32f2xx_it.h new file mode 100644 index 000000000..6a721ee18 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/stm32f2xx_it.h @@ -0,0 +1,63 @@ +/** + ****************************************************************************** + * @file I2C/IOE/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void EXTI0_IRQHandler(void); +void EXTI9_5_IRQHandler(void); +void EXTI15_10_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/IOE/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/readme.txt new file mode 100644 index 000000000..f884aec06 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2C/readme.txt @@ -0,0 +1,41 @@ +/** + @page I2C_EXAMPLES I2C EXAMPLES + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file I2C/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Reference to the I2C CPAL (UM1029). + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +In Addition to the I2C examples provided within this repository, ST is providing +a Communication peripheral application library (CPAL) for all STM32 I2C peripherals. +CPAL provides a high layer API, drivers for each STM32 device, a project template +allowing users to build a new project from scratch, and some examples showing how +to use and customize the CPAL library. + +For more details please refer to "Communication peripheral application library (CPAL) UM1029" +available for download on ST Microcontrollers . + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/audio_sample.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/audio_sample.c new file mode 100644 index 000000000..f4bfa17fc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/audio_sample.c @@ -0,0 +1,45622 @@ +#include "stm32f2xx.h" + +/* + The provided sample audio file (stored in internal flash memory) is extracted from: + - Title: artofgardens-instr + - Artist/Composer: Dan O'Connor + - Creative Commons license: Attribution 3.0 United States + Please read the license following this link: + http://creativecommons.org/licenses/by/3.0/us/ +*/ + +const uint16_t AUDIO_SAMPLE[] = { +0x4952, 0x4646, 0x4f6e, 0xf, 0x4157, 0x4556, 0x6d66, 0x2074, 0x12, 0, 0x1, +0x2, 0xbb80, 0, 0xee00, 0x2, 0x4, 0x10, 0, 0x6166, 0x7463, 0x4, +0, 0xd3cf, 0x3, 0x6164, 0x6174, 0x4f3c, 0xf, 0, 0, 0, 0, +0, 0, 0, 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****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2S_Audio + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define MESSAGE1 " STM32F2xx " +#define MESSAGE2 " Device running on " +#define MESSAGE3 " STM322xG-EVAL " + +/* Audio file size and start address are defined here since the audio file is + stored in Flash memory as a constant table of 16-bit data */ +#define AUDIO_FILE_SZE 990000 +#define AUIDO_START_ADDRESS 58 /* Offset relative to audio file header size */ + +__IO uint32_t cmd = AUDIO_PAUSE; +__IO uint32_t volume = 70; + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +static __IO uint32_t TimingDelay; +RCC_ClocksTypeDef RCC_Clocks; + +/* Variable to indicate that push buttons will be used for switching between + Headphone and Speaker output modes. */ +uint32_t SpHpSwitch = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs, Key Button, LCD available on + STM322xG-EVAL board ******************************************************/ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Initialize the Push buttons */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); /* Key button for Pause/Resume */ + STM_EVAL_PBInit(BUTTON_WAKEUP, BUTTON_MODE_GPIO); /* Key button for Volume High */ + STM_EVAL_PBInit(BUTTON_TAMPER, BUTTON_MODE_GPIO); /* Key button for Volume Low */ + + /* Initialize the LCD */ + STM322xG_LCD_Init(); + + /* Display message on STM322xG-EVAL LCD *************************************/ + /* Clear the LCD */ + LCD_Clear(LCD_COLOR_BLUE); + + /* Set the LCD Back Color */ + LCD_SetBackColor(Blue); + /* Set the LCD Text Color */ + LCD_SetTextColor(White); + LCD_DisplayStringLine(Line0, MESSAGE1); + LCD_DisplayStringLine(Line1, MESSAGE2); + LCD_DisplayStringLine(Line2, MESSAGE3); + + /* Turn on leds available on STM322xG-EVAL **********************************/ + STM_EVAL_LEDOn(LED1); + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + + /* SysTick end of count event each 10ms */ + RCC_GetClocksFreq(&RCC_Clocks); + SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); + + /* Initialize the Audio codec and all related peripherals (I2S, I2C, IOExpander, IOs...) */ + if (EVAL_AUDIO_Init(OUTPUT_DEVICE_AUTO, volume, I2S_AudioFreq_48k) == 0) + { + LCD_DisplayStringLine(Line3, "===================="); + LCD_DisplayStringLine(Line4, "Key : Play/Pause "); + LCD_DisplayStringLine(Line5, "Tamper: Vol+/Headph"); + LCD_DisplayStringLine(Line6, "Wakeup: Vol-/Spkr "); + LCD_DisplayStringLine(Line7, "===================="); + LCD_DisplayStringLine(Line8, " AUDIO CODEC OK "); + } + else + { + LCD_DisplayStringLine(Line4, " AUDIO CODEC FAIL "); + LCD_DisplayStringLine(Line5, " Try to reset board "); + } + + + /* + Normal mode description: + Start playing the audio file (using DMA stream) . + Using this mode, the application can run other tasks in parallel since + the DMA is handling the Audio Transfer instead of the CPU. + The only task remaining for the CPU will be the management of the DMA + Transfer Complete interrupt or the Half Transfer Complete interrupt in + order to load again the buffer and to calculate the remaining data. + Circular mode description: + Start playing the file from a circular buffer, once the DMA is enabled it + always run. User has to fill periodically the buffer with the audio data + using Transfer complete and/or half transfer complete interrupts callbacks + (EVAL_AUDIO_TransferComplete_CallBack() or EVAL_AUDIO_HalfTransfer_CallBack()... + In this case the audio data file is smaller than the DMA max buffer + size 65535 so there is no need to load buffer continuously or manage the + transfer complete or Half transfer interrupts callbacks. */ + EVAL_AUDIO_Play((uint16_t*)(AUDIO_SAMPLE + AUIDO_START_ADDRESS), (AUDIO_FILE_SZE - AUIDO_START_ADDRESS)); + + /* Display the state on the screen */ + LCD_DisplayStringLine(Line8, " PLAYING "); + + /* Infinite loop */ + while (1) + { + /* Check on the Pause/Resume button */ + if (STM_EVAL_PBGetState(BUTTON_KEY) != Bit_SET) + { + /* wait to avoid rebound */ + while (STM_EVAL_PBGetState(BUTTON_KEY) != Bit_SET); + + EVAL_AUDIO_PauseResume(cmd); + if (cmd == AUDIO_PAUSE) + { + /* Display the current state of the player */ + LCD_DisplayStringLine(Line8, " PAUSED "); + + /* Next time Resume command should be processed */ + cmd = AUDIO_RESUME; + + /* Push buttons will be used to switch between Speaker and Headphone modes */ + SpHpSwitch = 1; + } + else + { + /* Display the current state of the player */ + LCD_DisplayStringLine(Line8, " PLAYING "); + + /* Next time Pause command should be processed */ + cmd = AUDIO_PAUSE; + + /* Push buttons will be used to control volume level */ + SpHpSwitch = 0; + } + } + + /* Check on the Volume high button */ + if (STM_EVAL_PBGetState(BUTTON_WAKEUP) == Bit_SET) + { + /* Check if the current state is paused (push buttons are used for volume control or for + speaker/headphone mode switching) */ + if (SpHpSwitch) + { + /* Set output to Speaker */ + Codec_SwitchOutput(OUTPUT_DEVICE_SPEAKER); + + /* Display the current state of the player */ + LCD_DisplayStringLine(Line9, " SPEAKER "); + } + else + { + /* wait to avoid rebound */ + while (STM_EVAL_PBGetState(BUTTON_WAKEUP) == Bit_SET); + + /* Decrease volume by 5% */ + if (volume > 5) + volume -= 5; + else + volume = 0; + + /* Apply the new volume to the codec */ + EVAL_AUDIO_VolumeCtl(volume); + LCD_DisplayStringLine(Line9, " VOL: - "); + } + } + + /* Check on the Volume high button */ + if (STM_EVAL_PBGetState(BUTTON_TAMPER) != Bit_SET) + { + /* Check if the current state is paused (push buttons are used for volume control or for + speaker/headphone mode switching) */ + if (SpHpSwitch) + { + /* Set output to Headphone */ + Codec_SwitchOutput(OUTPUT_DEVICE_HEADPHONE); + + /* Display the current state of the player */ + LCD_DisplayStringLine(Line9, " HEADPHONE "); + } + else + { + /* wait to avoid rebound */ + while (STM_EVAL_PBGetState(BUTTON_TAMPER) != Bit_SET); + + /* Increase volume by 5% */ + if (volume < 95) + volume += 5; + else + volume = 100; + + /* Apply the new volume to the codec */ + EVAL_AUDIO_VolumeCtl(volume); + LCD_DisplayStringLine(Line9, " VOL: + "); + } + } + + /* Toggle LD4 */ + STM_EVAL_LEDToggle(LED3); + + /* Insert 50 ms delay */ + Delay(5); + + /* Toggle LD2 */ + STM_EVAL_LEDToggle(LED2); + + /* Insert 50 ms delay */ + Delay(5); + } +} + +/*-------------------------------- + Callbacks implementation: + the callbacks prototypes are defined in the stm322xg_eval_audio_codec.h file + and their implementation should be done in the user coed if they are needed. + Below some examples of callback implementations. + --------------------------------------------------------*/ +/** + * @brief Calculates the remaining file size and new position of the pointer. + * @param None + * @retval None + */ +void EVAL_AUDIO_TransferComplete_CallBack(uint32_t pBuffer, uint32_t Size) +{ + /* Calculate the remaining audio data in the file and the new size + for the DMA transfer. If the Audio files size is less than the DMA max + data transfer size, so there is no calculation to be done, just restart + from the beginning of the file ... */ + /* Check if the end of file has been reached */ + +#ifdef AUDIO_MAL_MODE_NORMAL + + /* Replay from the beginning */ + EVAL_AUDIO_Play((uint16_t*)(AUDIO_SAMPLE + AUIDO_START_ADDRESS), (AUDIO_FILE_SZE - AUIDO_START_ADDRESS)); + +#else /* #ifdef AUDIO_MAL_MODE_CIRCULAR */ + + /* Display message on the LCD screen */ + LCD_DisplayStringLine(Line8, " All Buffer Reached "); + +#endif /* AUDIO_MAL_MODE_CIRCULAR */ +} + +/** + * @brief Manages the DMA Half Transfer complete interrupt. + * @param None + * @retval None + */ +void EVAL_AUDIO_HalfTransfer_CallBack(uint32_t pBuffer, uint32_t Size) +{ +#ifdef AUDIO_MAL_MODE_CIRCULAR + + /* Display message on the LCD screen */ + LCD_DisplayStringLine(Line8, " 1/2 Buffer Reached "); + +#endif /* AUDIO_MAL_MODE_CIRCULAR */ + + /* Generally this interrupt routine is used to load the buffer when + a streaming scheme is used: When first Half buffer is already transferred load + the new data to the first half of buffer while DMA is transferring data from + the second half. And when Transfer complete occurs, load the second half of + the buffer while the DMA is transferring from the first half ... */ + /* + ........... + */ +} + +/** + * @brief Manages the DMA FIFO error interrupt. + * @param None + * @retval None + */ +void EVAL_AUDIO_Error_CallBack(void* pData) +{ + /* Display message on the LCD screen */ + LCD_SetBackColor(Red); + LCD_DisplayStringLine(Line8, " DMA ERROR "); + + /* Stop the program with an infinite loop */ + while (1) + {} + + /* could also generate a system reset to recover from the error */ + /* .... */ +} + +#ifndef USE_DEFAULT_TIMEOUT_CALLBACK +/** + * @brief Basic management of the timeout situation. + * @param None. + * @retval None. + */ +uint32_t Codec_TIMEOUT_UserCallback(void) +{ + /* Display message on the LCD screen */ + LCD_DisplayStringLine(Line8, " CODEC I2C ERROR "); + + /* Block communication and all processes */ + while (1) + { + } +} +#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */ +/*----------------------------------------------------------------------------*/ + +/** + * @brief Inserts a delay time. + * @param nTime: specifies the delay time length, in 10 ms. + * @retval None + */ +void Delay(__IO uint32_t nTime) +{ + TimingDelay = nTime; + + while(TimingDelay != 0); +} + +/** + * @brief Decrements the TimingDelay variable. + * @param None + * @retval None + */ +void TimingDelay_Decrement(void) +{ + if (TimingDelay != 0x00) + { + TimingDelay--; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/main.h new file mode 100644 index 000000000..00a4e316b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/main.h @@ -0,0 +1,54 @@ +/** + ****************************************************************************** + * @file I2S/Audio/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stm322xg_eval_lcd.h" +#include + +#include "stm322xg_eval_audio_codec.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* This is an audio file stored in the Flash memory as a constant table of 16-bit data. + The audio format should be WAV (raw / PCM) 16-bits, Stereo (sampling rate may be modified) */ +extern uint16_t AUDIO_SAMPLE[]; + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TimingDelay_Decrement(void); +void Delay(__IO uint32_t nTime); + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/readme.txt new file mode 100644 index 000000000..ed0dacd9d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/readme.txt @@ -0,0 +1,118 @@ +/** + @page I2S_AUDIO How to use the Audio features with I2S peripheral + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file I2S/Audio/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the I2S Audio Example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides basic implementation of audio features. +It allows to play an audio file through the I2S peripheral and using the external +codec implemented on the STM322xG-EVAL board. + +In this example the I2S input clock, provided by a dedicated PLL (PLLI2S), is +configured to have an audio sampling frequency at 48 KHz with Master clock enabled. + +This example uses an audio codec driver which consists of three independent layers: + - Codec Hardware layer: which controls and communicates with the audio codec + (CS43L22) implemented on the evaluation board. + - MAL (Media Access Layer): which controls and interfaces with storage media + storing or providing the audio file/stream. + - The high layer: which implements overall control and interfacing API allowing + to perform basic audio operations (Init, Play, Pause, Resume, Stop, Volume + control and audio file pointer management) + +In this example the audio file is stored in the internal flash memory (Stereo, +16-bit, 48 KHz). The analog output device is automatically detected (Speaker or +Headphone) when the Headphone is plugged/unplugged in/from the audio jack of the +evaluation board. The example also manages information display and control interface +through push buttons: + - When the application is Playing audio file: + + Key : Pause + + Tamper: Volume UP + + Wakeup: Volume DOWN + - When the application is Paused: + + Key : Play + + Tamper: Switch output target to Headphone + + Wakeup: Switch output target to Speaker + +This example plays the audio file stored in internal flash memory and replay it +when it reach end of file. But it can be tailored to used different media storage +devices; SDCard (through SDIO), external Memory (through FSMC) ...) or to play +in streaming mode (ie. from USB port in device or host mode). In this case, Circular +DMA mode should be preferred (by enabling the define AUDIO_MAL_MODE_CIRCULAR in +stm322xg_eval_audio_codec.h file). + +List of Known Limitations and more detailed user notes are provided in file +stm322xg_eval_audio_codec.c (under Utilities\STM32_EVAL\STM322xG_EVAL) + +The provided sample audio file (stored in internal flash memory) is extracted from: + - Title: artofgardens-instr + - Artist/Composer: Dan O'Connor + - Creative Commons license: Attribution 3.0 United States + Please read the license following this link: + http://creativecommons.org/licenses/by/3.0/us/ + + +@par Directory contents + + - I2S/Audio/system_stm32f2xx.c STM32F2xx system clock configuration file + - I2S/Audio/stm32f2xx_conf.h Library Configuration file + - I2S/Audio/stm32f2xx_it.c Interrupt handlers + - I2S/Audio/stm32f2xx_it.h Interrupt handlers header file + - I2S/Audio/main.c Main program + - I2S/Audio/audio_sample.c Audio Sample file (in tab format) + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs only on STM32F2xx Devices Revision B and Revision Y. + + - This example has been tested with STM322xG-EVAL RevB (with no additional + hardware), and can be easily tailored to any other development board. + + - STM322xG-EVAL Set-up + - Make sure the jumper JP16 is in position 2<->3 + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Add the files "audio_sample.c" and "stm322xg_eval_audio_codec.c" to the project source list + - "stm322xg_eval_audio_codec.c" file is located under Utilities\STM32_EVAL\STM322xG_EVAL + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/stm32f2xx_conf.h new file mode 100644 index 000000000..86744cda7 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file I2S/Audio/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/stm32f2xx_it.c new file mode 100644 index 000000000..894bbf38e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/stm32f2xx_it.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file I2S/Audio/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup I2S_Audio + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + TimingDelay_Decrement(); +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/stm32f2xx_it.h new file mode 100644 index 000000000..736cce29c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file I2S/Audio/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/system_stm32f2xx.c new file mode 100644 index 000000000..d4f8f8f30 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/I2S/Audio/system_stm32f2xx.c @@ -0,0 +1,564 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * STM32f2xx_Clock_Configuration_V1.0.0.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | 344 + *----------------------------------------------------------------------------- + * PLLI2S_R | 7 + *----------------------------------------------------------------------------- + * I2S input clock(Hz) | 49142857 + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVALboard as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N + I2SCLK = PLLI2S_VCO / PLLI2S_R */ +#define PLLI2S_N 344 +#define PLLI2S_R 7 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + + +/******************************************************************************/ +/* I2S clock configuration (For devices Rev B and Y) */ +/******************************************************************************/ + /* PLLI2S clock used as I2S clock source */ + RCC->CFGR &= ~RCC_CFGR_I2SSRC; + + /* Configure PLLI2S */ + RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28); + + /* Enable PLLI2S */ + RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON); + + /* Wait till PLLI2S is ready */ + while((RCC->CR & RCC_CR_PLLI2SRDY) == 0) + { + } +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/main.c new file mode 100644 index 000000000..7d8cf3931 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/main.c @@ -0,0 +1,259 @@ +/** + ****************************************************************************** + * @file IWDG/IWDG_Example/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup IWDG_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t TimingDelay = 0; +__IO uint32_t LsiFreq = 0; +__IO uint32_t CaptureNumber = 0, PeriodValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +void Delay(__IO uint32_t nTime); +uint32_t GetLSIFrequency(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LED1, LED2 and Key Button mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI); + + /* Setup SysTick Timer for 1 msec interrupts */ + if (SysTick_Config(SystemCoreClock / 1000)) + { + /* Capture error */ + while (1); + } + + /* Check if the system has resumed from IWDG reset */ + if (RCC_GetFlagStatus(RCC_FLAG_IWDGRST) != RESET) + { + /* IWDGRST flag set */ + /* Turn on LED1 */ + STM_EVAL_LEDOn(LED1); + + /* Clear reset flags */ + RCC_ClearFlag(); + } + else + { + /* IWDGRST flag is not set */ + /* Turn off LED1 */ + STM_EVAL_LEDOff(LED1); + } + + /* Get the LSI frequency: TIM5 is used to measure the LSI frequency */ + LsiFreq = GetLSIFrequency(); + + /* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency + dispersion) */ + /* Enable write access to IWDG_PR and IWDG_RLR registers */ + IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); + + /* IWDG counter clock: LSI/32 */ + IWDG_SetPrescaler(IWDG_Prescaler_32); + + /* Set counter reload value to obtain 250ms IWDG TimeOut. + Counter Reload Value = 250ms/IWDG counter clock period + = 250ms / (LSI/32) + = 0.25s / (LsiFreq/32) + = LsiFreq/(32 * 4) + = LsiFreq/128 + */ + IWDG_SetReload(LsiFreq/128); + + /* Reload IWDG counter */ + IWDG_ReloadCounter(); + + /* Enable IWDG (the LSI oscillator will be enabled by hardware) */ + IWDG_Enable(); + + while (1) + { + /* Toggle LED2 */ + STM_EVAL_LEDToggle(LED2); + + /* Insert 240 ms delay */ + Delay(240); + + /* Reload IWDG counter */ + IWDG_ReloadCounter(); + } +} + +/** + * @brief Configures TIM5 to measure the LSI oscillator frequency. + * @param None + * @retval LSI Frequency + */ +uint32_t GetLSIFrequency(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + TIM_ICInitTypeDef TIM_ICInitStructure; + RCC_ClocksTypeDef RCC_ClockFreq; + + /* Enable the LSI oscillator ************************************************/ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + {} + + /* TIM5 configuration *******************************************************/ + /* Enable TIM5 clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE); + + /* Connect internally the TIM5_CH4 Input Capture to the LSI clock output */ + TIM_RemapConfig(TIM5, TIM5_LSI); + + /* Configure TIM5 presclaer */ + TIM_PrescalerConfig(TIM5, 0, TIM_PSCReloadMode_Immediate); + + /* TIM5 configuration: Input Capture mode --------------------- + The LSI oscillator is connected to TIM5 CH4 + The Rising edge is used as active edge, + The TIM5 CCR4 is used to compute the frequency value + ------------------------------------------------------------ */ + TIM_ICInitStructure.TIM_Channel = TIM_Channel_4; + TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV8; + TIM_ICInitStructure.TIM_ICFilter = 0; + TIM_ICInit(TIM5, &TIM_ICInitStructure); + + /* Enable TIM5 Interrupt channel */ + NVIC_InitStructure.NVIC_IRQChannel = TIM5_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Enable TIM5 counter */ + TIM_Cmd(TIM5, ENABLE); + + /* Reset the flags */ + TIM5->SR = 0; + + /* Enable the CC4 Interrupt Request */ + TIM_ITConfig(TIM5, TIM_IT_CC4, ENABLE); + + + /* Wait until the TIM5 get 2 LSI edges (refer to TIM5_IRQHandler() in + stm32f2xx_it.c file) ******************************************************/ + while(CaptureNumber != 2) + { + } + /* Deinitialize the TIM5 peripheral registers to their default reset values */ + TIM_DeInit(TIM5); + + + /* Compute the LSI frequency, depending on TIM5 input clock frequency (PCLK1)*/ + /* Get SYSCLK, HCLK and PCLKx frequency */ + RCC_GetClocksFreq(&RCC_ClockFreq); + + /* Get PCLK1 prescaler */ + if ((RCC->CFGR & RCC_CFGR_PPRE1) == 0) + { + /* PCLK1 prescaler equal to 1 => TIMCLK = PCLK1 */ + return ((RCC_ClockFreq.PCLK1_Frequency / PeriodValue) * 8); + } + else + { /* PCLK1 prescaler different from 1 => TIMCLK = 2 * PCLK1 */ + return (((2 * RCC_ClockFreq.PCLK1_Frequency) / PeriodValue) * 8) ; + } +} + +/** + * @brief Inserts a delay time. + * @param nTime: specifies the delay time length, in milliseconds. + * @retval None + */ +void Delay(__IO uint32_t nTime) +{ + TimingDelay = nTime; + + while(TimingDelay != 0); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/readme.txt new file mode 100644 index 000000000..8317afb6f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/readme.txt @@ -0,0 +1,108 @@ +/** + @page IWDG_Example IWDG_Example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file IWDG/IWDG_Example/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the IWDG Example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to update at regular period the IWDG reload counter and +how to simulate a software fault generating an MCU IWDG reset on expiry of a +programmed time period. + +The IWDG timeout is set to 250 ms (the timeout may varies due to LSI frequency +dispersion). + +First, the TIM5 timer is configured to measure the LSI frequency as the +LSI is internally connected to TIM5 CH4, in order to adjust the IWDG clock. + +The LSI measurement using the TIM5 is described below: + - Configure the TIM5 to remap internally the TIM5 CH4 Input Capture to the LSI + clock output. + - Enable the TIM5 Input Capture interrupt: after one cycle of LSI clock, the + period value is stored in a variable and compared to the HCLK clock to get + its real value. + +Then, the IWDG reload counter is configured to obtain 250 ms according to the +measured LSI frequency. + +The IWDG reload counter is refreshed each 240 ms in the main program infinite loop +to prevent a IWDG reset. +LED2 is also toggled each 240 ms indicating that the program is running. + +An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt +on the rising edge of the signal. + +The EXTI Line is used to simulate a software failure: once the EXTI Line event +occurs, by pressing the Key push-button, the corresponding interrupt is served. +In the ISR, a write to invalid address generates a Hardfault exception containing +an infinite loop and preventing to return to main program (the IWDG reload counter +is not refreshed). +As a result, when the IWDG counter reaches 00h, the IWDG reset occurs. +If the IWDG reset is generated, after the system resumes from reset, LED1 turns on. + +If the EXTI Line event does not occur, the IWDG counter is indefinitely refreshed +in the main program infinite loop, and there is no IWDG reset. + + +@par Directory contents + + - IWDG_Example/system_stm32f2xx.c STM32F2xx system clock configuration file + - IWDG_Example/stm32f2xx_conf.h Library Configuration file + - IWDG_Example/stm32f2xx_it.c Interrupt handlers + - IWDG_Example/stm32f2xx_it.h Header for stm32f2xx_it.c + - IWDG_Example/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + + - STM322xG-EVAL Set-up + - Use LD1 and LD2 leds connected respectively to PG.06 and PG.08 pins + - Use the KEY push button connected to PG.15 pin (EXTI Line15). + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/stm32f2xx_conf.h new file mode 100644 index 000000000..1fbf4b908 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file IWDG/IWDG_Example/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/stm32f2xx_it.c new file mode 100644 index 000000000..d72eb4e45 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/stm32f2xx_it.c @@ -0,0 +1,222 @@ +/** + ****************************************************************************** + * @file IWDG/IWDG_Example/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup IWDG_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern __IO uint32_t TimingDelay; +extern __IO uint32_t PeriodValue; +extern __IO uint32_t CaptureNumber; +uint16_t tmpCC4[2] = {0, 0}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + TimingDelay--; +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles External line 15 to 10 interrupt request. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + if (EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET) + { + /* Clear the Key Button EXTI Line Pending Bit */ + EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); + + /* As the following address is invalid (not mapped), a Hardfault exception + will be generated with an infinite loop and when the IWDG counter reaches 0 + the IWDG reset occurs */ + *(__IO uint32_t *) 0xA0001000 = 0xFF; + } +} + +/** + * @brief This function handles TIM5 global interrupt request. + * @param None + * @retval None + */ +void TIM5_IRQHandler(void) +{ + if (TIM_GetITStatus(TIM5, TIM_IT_CC4) != RESET) + { + /* Get the Input Capture value */ + tmpCC4[CaptureNumber++] = TIM_GetCapture4(TIM5); + + /* Clear CC4 Interrupt pending bit */ + TIM_ClearITPendingBit(TIM5, TIM_IT_CC4); + + if (CaptureNumber >= 2) + { + /* Compute the period length */ + PeriodValue = (uint16_t)(0xFFFF - tmpCC4[0] + tmpCC4[1] + 1); + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/stm32f2xx_it.h new file mode 100644 index 000000000..0fdd0d020 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file IWDG/IWDG_Example/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/IWDG/IWDG_Example/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/main.c new file mode 100644 index 000000000..26557d53f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/main.c @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file Lib_DEBUG/Lib_DEBUG_Example/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm32f2xx_ip_dbg.h" +#include "stm322xg_eval.h" +#include + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup Lib_DEBUG_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +USART_InitTypeDef USART_InitStructure; + +/* Private function prototypes -----------------------------------------------*/ +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + GPIO_InitTypeDef GPIOA_InitStructure; + + /* USARTx configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit(COM1, &USART_InitStructure); + + /* Initialize all peripherals pointers */ + IP_Debug(); + + printf("\r\n STM32F2xx Firmware Library compiled with FULL ASSERT function... \n\r"); + printf("...Run-time checking enabled \n\r"); + + /* Simulate wrong parameter passed to library function ---------------------*/ + /* To enable SPI1 clock, RCC_APB2PeriphClockCmd() function must be used and + not RCC_APB1PeriphClockCmd() */ + RCC_APB1PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); + + /* Some member of GPIOA_InitStructure structure are not initialized */ + GPIOA_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIOA_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + /*GPIOA_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;*/ + GPIOA_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIOA_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOA, &GPIOA_InitStructure); + + while (1) + { + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number */ + + printf("\n\r Wrong parameter value detected on\r\n"); + printf(" file %s\r\n", file); + printf(" line %d\r\n", line); + + /* Infinite loop */ + /* while (1) + { + } */ +} +#endif + +/** + * @brief Retargets the C library printf function to the USART. + * @param None + * @retval None + */ +PUTCHAR_PROTOTYPE +{ + /* Place your implementation of fputc here */ + /* e.g. write a character to the USART */ + USART_SendData(EVAL_COM1, (uint8_t) ch); + + /* Loop until the end of transmission */ + while(USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) + { + } + + return ch; +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/readme.txt new file mode 100644 index 000000000..108a388d5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/readme.txt @@ -0,0 +1,105 @@ +/** + @page Lib_DEBUG_Example Lib DEBUG example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file Lib_DEBUG/Lib_DEBUG_Example/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the Lib DEBUG example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example demonstrates how to declare a dynamic peripherals pointers used for +Debug mode. + +To use Debug mode you have to add the stm32f2xx_ip_dbg.c file to your application. +This creates a pointer to the peripheral structure in SRAM. Debugging consequently +becomes easier and all register settings can be obtained by dumping a peripheral +variable. + +When the "USE_FULL_ASSERT" label is uncommented (in stm32f2xx_conf.h file), +the assert_param macro is expanded and run-time checking is enabled in the firmware +library code. The run-time checking allows checking that all the library functions +input value lies within the parameter allowed values. + +The associated program simulates wrong parameter passed to library function and the +source of the error is printed on Hyperterminal (through USART). + +@note +The Debug mode increases the code size and reduces the code performance. For this +reason, it is recommended to used it only when debugging the application and to +remove it from the final application code. + +@par Directory contents + + - Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_conf.h Library Configuration file + - Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_it.c Interrupt handlers + - Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_it.h Interrupt handlers header file + - Lib_DEBUG/Lib_DEBUG_Example/main.c Main program + - Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_ip_dbg.c Peripherals pointers initialization + - Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_ip_dbg.h Header for stm32f2xx_ip_dbg.c + - Lib_DEBUG/Lib_DEBUG_Example/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 and PC serial port. + - Make sure that JP22 is in position 1<->2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Add the required example files + - stm32f2xx_ip_dbg.c + - Rebuild all files and load your image into target memory + - Run the example + +@note + - The free Lite version of TrueSTUDIO do not support printf() redirection. + For more information, see "note.txt" under "STM32F2xx_StdPeriph_Template\TrueSTUDIO". + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_conf.h new file mode 100644 index 000000000..e7ab62abe --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +#define USE_FULL_ASSERT 1 + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_ip_dbg.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_ip_dbg.c new file mode 100644 index 000000000..3ab5a604d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_ip_dbg.c @@ -0,0 +1,277 @@ +/** + ****************************************************************************** + * @file Lib_DEBUG/Lib_DEBUG_Example/stm32f21xx_ip_dbg.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file provides all peripherals pointers initialization. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_ip_dbg.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup Lib_DEBUG_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +ADC_Common_TypeDef * ADC_DBG; +ADC_TypeDef * ADC1_DBG; +ADC_TypeDef * ADC2_DBG; +ADC_TypeDef * ADC3_DBG; +CAN_TypeDef * CAN1_DBG; +CAN_TypeDef * CAN2_DBG; +CRC_TypeDef * CRC_DBG; +CRYP_TypeDef * CRYP_DBG; +DAC_TypeDef * DAC_DBG; +DBGMCU_TypeDef * DBGMCU_DBG; +DCMI_TypeDef * DCMI_DBG; +DMA_TypeDef * DMA1_DBG; +DMA_Stream_TypeDef * DMA1_Stream0_DBG; +DMA_Stream_TypeDef * DMA1_Stream1_DBG; +DMA_Stream_TypeDef * DMA1_Stream2_DBG; +DMA_Stream_TypeDef * DMA1_Stream3_DBG; +DMA_Stream_TypeDef * DMA1_Stream4_DBG; +DMA_Stream_TypeDef * DMA1_Stream5_DBG; +DMA_Stream_TypeDef * DMA1_Stream6_DBG; +DMA_Stream_TypeDef * DMA1_Stream7_DBG; +DMA_TypeDef * DMA2_DBG; +DMA_Stream_TypeDef * DMA2_Stream0_DBG; +DMA_Stream_TypeDef * DMA2_Stream1_DBG; +DMA_Stream_TypeDef * DMA2_Stream2_DBG; +DMA_Stream_TypeDef * DMA2_Stream3_DBG; +DMA_Stream_TypeDef * DMA2_Stream4_DBG; +DMA_Stream_TypeDef * DMA2_Stream5_DBG; +DMA_Stream_TypeDef * DMA2_Stream6_DBG; +DMA_Stream_TypeDef * DMA2_Stream7_DBG; +EXTI_TypeDef * EXTI_DBG; +ETH_TypeDef * ETH_DBG; +FLASH_TypeDef * FLASH_DBG; +FSMC_Bank1_TypeDef * FSMC_Bank1_DBG; +FSMC_Bank1E_TypeDef * FSMC_Bank1E_DBG; +FSMC_Bank2_TypeDef * FSMC_Bank2_DBG; +FSMC_Bank3_TypeDef * FSMC_Bank3_DBG; +FSMC_Bank4_TypeDef * FSMC_Bank4_DBG; +GPIO_TypeDef * GPIOA_DBG; +GPIO_TypeDef * GPIOB_DBG; +GPIO_TypeDef * GPIOC_DBG; +GPIO_TypeDef * GPIOD_DBG; +GPIO_TypeDef * GPIOE_DBG; +GPIO_TypeDef * GPIOF_DBG; +GPIO_TypeDef * GPIOG_DBG; +GPIO_TypeDef * GPIOH_DBG; +GPIO_TypeDef * GPIOI_DBG; +HASH_TypeDef * HASH_DBG; +I2C_TypeDef * I2C1_DBG; +I2C_TypeDef * I2C2_DBG; +I2C_TypeDef * I2C3_DBG; +IWDG_TypeDef * IWDG_DBG; +PWR_TypeDef * PWR_DBG; +RCC_TypeDef * RCC_DBG; +RNG_TypeDef * RNG_DBG; +RTC_TypeDef * RTC_DBG; +SDIO_TypeDef * SDIO_DBG; +SPI_TypeDef * SPI1_DBG; +SPI_TypeDef * SPI2_DBG; +SPI_TypeDef * SPI3_DBG; +SYSCFG_TypeDef * SYSCFG_DBG; +TIM_TypeDef * TIM1_DBG; +TIM_TypeDef * TIM2_DBG; +TIM_TypeDef * TIM3_DBG; +TIM_TypeDef * TIM4_DBG; +TIM_TypeDef * TIM5_DBG; +TIM_TypeDef * TIM6_DBG; +TIM_TypeDef * TIM7_DBG; +TIM_TypeDef * TIM8_DBG; +TIM_TypeDef * TIM9_DBG; +TIM_TypeDef * TIM10_DBG; +TIM_TypeDef * TIM11_DBG; +TIM_TypeDef * TIM12_DBG; +TIM_TypeDef * TIM13_DBG; +TIM_TypeDef * TIM14_DBG; +USART_TypeDef * USART1_DBG; +USART_TypeDef * USART2_DBG; +USART_TypeDef * USART3_DBG; +USART_TypeDef * UART4_DBG; +USART_TypeDef * UART5_DBG; +USART_TypeDef * USART6_DBG; +WWDG_TypeDef * WWDG_DBG; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function initialize peripherals pointers.. + * @param None + * @retval None + */ +void IP_Debug(void) +{ +/************************************* ADC ************************************/ + ADC_DBG = (ADC_Common_TypeDef *) ADC_BASE; + ADC1_DBG = (ADC_TypeDef *) ADC1_BASE; + ADC2_DBG = (ADC_TypeDef *) ADC2_BASE; + ADC3_DBG = (ADC_TypeDef *) ADC3_BASE; + +/************************************* CAN ************************************/ + CAN1_DBG = (CAN_TypeDef *) CAN1_BASE; + CAN2_DBG = (CAN_TypeDef *) CAN2_BASE; + +/************************************* CRC ************************************/ + CRC_DBG = (CRC_TypeDef *) CRC_BASE; + +/************************************* CRYP ***********************************/ + CRYP_DBG = (CRYP_TypeDef *) CRYP_BASE; + +/************************************* DAC ************************************/ + DAC_DBG = (DAC_TypeDef *) DAC_BASE; + +/************************************* DBGMCU *********************************/ + DBGMCU_DBG = (DBGMCU_TypeDef *) DBGMCU_BASE; + +/************************************* DCMI ***********************************/ + DCMI_DBG = (DCMI_TypeDef *) DCMI_BASE; + +/************************************* DMA ************************************/ + DMA1_DBG = (DMA_TypeDef *) DMA1_BASE; + DMA1_Stream0_DBG = (DMA_Stream_TypeDef *) DMA1_Stream0_BASE; + DMA1_Stream1_DBG = (DMA_Stream_TypeDef *) DMA1_Stream1_BASE; + DMA1_Stream2_DBG = (DMA_Stream_TypeDef *) DMA1_Stream2_BASE; + DMA1_Stream3_DBG = (DMA_Stream_TypeDef *) DMA1_Stream3_BASE; + DMA1_Stream4_DBG = (DMA_Stream_TypeDef *) DMA1_Stream4_BASE; + DMA1_Stream5_DBG = (DMA_Stream_TypeDef *) DMA1_Stream5_BASE; + DMA1_Stream6_DBG = (DMA_Stream_TypeDef *) DMA1_Stream6_BASE; + DMA1_Stream7_DBG = (DMA_Stream_TypeDef *) DMA1_Stream7_BASE; + DMA2_DBG = (DMA_TypeDef *) DMA2_BASE; + DMA2_Stream0_DBG = (DMA_Stream_TypeDef *) DMA2_Stream0_BASE; + DMA2_Stream1_DBG = (DMA_Stream_TypeDef *) DMA2_Stream1_BASE; + DMA2_Stream2_DBG = (DMA_Stream_TypeDef *) DMA2_Stream2_BASE; + DMA2_Stream3_DBG = (DMA_Stream_TypeDef *) DMA2_Stream3_BASE; + DMA2_Stream4_DBG = (DMA_Stream_TypeDef *) DMA2_Stream4_BASE; + DMA2_Stream5_DBG = (DMA_Stream_TypeDef *) DMA2_Stream5_BASE; + DMA2_Stream6_DBG = (DMA_Stream_TypeDef *) DMA2_Stream6_BASE; + DMA2_Stream7_DBG = (DMA_Stream_TypeDef *) DMA2_Stream7_BASE; + +/************************************* EXTI ***********************************/ + EXTI_DBG = (EXTI_TypeDef *) EXTI_BASE; + +/************************************* ETH ************************************/ + ETH_DBG = (ETH_TypeDef *) ETH_BASE; + +/************************************* FLASH **********************************/ + FLASH_DBG = (FLASH_TypeDef *) FLASH_R_BASE; + +/************************************* FSMC ***********************************/ + FSMC_Bank1_DBG = (FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE; + FSMC_Bank1E_DBG = (FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE; + FSMC_Bank2_DBG = (FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE; + FSMC_Bank3_DBG = (FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE; + FSMC_Bank4_DBG = (FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE; + +/************************************* GPIO ***********************************/ + GPIOA_DBG = (GPIO_TypeDef *) GPIOA_BASE; + GPIOB_DBG = (GPIO_TypeDef *) GPIOB_BASE; + GPIOC_DBG = (GPIO_TypeDef *) GPIOC_BASE; + GPIOD_DBG = (GPIO_TypeDef *) GPIOD_BASE; + GPIOE_DBG = (GPIO_TypeDef *) GPIOE_BASE; + GPIOF_DBG = (GPIO_TypeDef *) GPIOF_BASE; + GPIOG_DBG = (GPIO_TypeDef *) GPIOG_BASE; + GPIOH_DBG = (GPIO_TypeDef *) GPIOH_BASE; + GPIOI_DBG = (GPIO_TypeDef *) GPIOI_BASE; + +/************************************* HASH ***********************************/ + HASH_DBG = (HASH_TypeDef *) HASH_BASE; + +/************************************* I2C ************************************/ + I2C1_DBG = (I2C_TypeDef *) I2C1_BASE; + I2C2_DBG = (I2C_TypeDef *) I2C2_BASE; + I2C3_DBG = (I2C_TypeDef *) I2C3_BASE; + +/************************************* IWDG ***********************************/ + IWDG_DBG = (IWDG_TypeDef *) IWDG_BASE; + +/************************************* PWR ************************************/ + PWR_DBG = (PWR_TypeDef *) PWR_BASE; + +/************************************* RCC ************************************/ + RCC_DBG = (RCC_TypeDef *) RCC_BASE; + +/************************************* RNG ************************************/ + RNG_DBG = (RNG_TypeDef *) RNG_BASE; + +/************************************* RTC ************************************/ + RTC_DBG = (RTC_TypeDef *) RTC_BASE; + +/************************************* SDIO ***********************************/ + SDIO_DBG = (SDIO_TypeDef *) SDIO_BASE; + +/************************************* SPI ************************************/ + SPI1_DBG = (SPI_TypeDef *) SPI1_BASE; + SPI2_DBG = (SPI_TypeDef *) SPI2_BASE; + SPI3_DBG = (SPI_TypeDef *) SPI3_BASE; + +/************************************* SYSCFG *********************************/ + SYSCFG_DBG = (SYSCFG_TypeDef *) SYSCFG_BASE; + +/************************************* TIM ************************************/ + TIM1_DBG = (TIM_TypeDef *) TIM1_BASE; + TIM2_DBG = (TIM_TypeDef *) TIM2_BASE; + TIM3_DBG = (TIM_TypeDef *) TIM3_BASE; + TIM4_DBG = (TIM_TypeDef *) TIM4_BASE; + TIM5_DBG = (TIM_TypeDef *) TIM5_BASE; + TIM6_DBG = (TIM_TypeDef *) TIM6_BASE; + TIM7_DBG = (TIM_TypeDef *) TIM7_BASE; + TIM8_DBG = (TIM_TypeDef *) TIM8_BASE; + TIM9_DBG = (TIM_TypeDef *) TIM9_BASE; + TIM10_DBG = (TIM_TypeDef *) TIM10_BASE; + TIM11_DBG = (TIM_TypeDef *) TIM11_BASE; + TIM12_DBG = (TIM_TypeDef *) TIM12_BASE; + TIM13_DBG = (TIM_TypeDef *) TIM13_BASE; + TIM14_DBG = (TIM_TypeDef *) TIM14_BASE; + +/************************************* USART **********************************/ + USART1_DBG = (USART_TypeDef *) USART1_BASE; + USART2_DBG = (USART_TypeDef *) USART2_BASE; + USART3_DBG = (USART_TypeDef *) USART3_BASE; + UART4_DBG = (USART_TypeDef *) UART4_BASE; + UART5_DBG = (USART_TypeDef *) UART5_BASE; + USART6_DBG = (USART_TypeDef *) USART6_BASE; + +/************************************* WWDG************************************/ + WWDG_DBG = (WWDG_TypeDef *) WWDG_BASE; +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_ip_dbg.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_ip_dbg.h new file mode 100644 index 000000000..2084630d8 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_ip_dbg.h @@ -0,0 +1,44 @@ +/** + ****************************************************************************** + * @file Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_ip_dbg.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for stm32f2xx_ip_dbg.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2XX_IP_DBG_H +#define __STM32F2XX_IP_DBG_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void IP_Debug(void); + +#endif /* __STM32F2XX_IP_DBG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_it.c new file mode 100644 index 000000000..5ddb064ee --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SysTick_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_it.h new file mode 100644 index 000000000..2168a19dc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file Lib_DEBUG/Lib_DEBUG_Example/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Lib_DEBUG/Lib_DEBUG_Example/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Library_Examples.html b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Library_Examples.html new file mode 100644 index 000000000..4ea62a6d2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Library_Examples.html @@ -0,0 +1,1567 @@ + + + + + + + + + + + +STM32F2xx Standard Peripherals Library: Peripheral’s examples + + + + + + + +
+ +

 

+ +
+ + + + + +
+ + + + +
+

STM32F2xx + Standard Peripherals Library: Peripheral’s examples

+

 

+

Copyright 2012 + STMicroelectronics

+

+
+

 

+ + + + +
+ + + + +
+ + + + +
+

The STM32F2xx + Standard Peripherals library provides a rich set of examples + covering the main features of each peripheral. All the examples are + independent from the software toolchain. These examples run on + STMicroelectronics STM322xG-EVAL evaluation board and can be easily + tailored to any other supported device and development board. Only + source files are provided for each example and user can tailor the + provided project template to run the selected example with his + preferred toolchain.

+

How to proceed?

+ +
    +
  • Copy the files main.c, main.h + (if exists), stm32f2xx_it.c, system_stm32f2xx.c, stm32f2xx_it.h, + stm32f2xx_conf.h and any other source files from the specified + example to your toolchain folder under Project\STM32F2xx_StdPeriph_Template. + This project folder contains already all toolchain files needed for + creating projects for STM32F2xx microcontrollers.
    • +
  • Open your preferred toolchain
    • +
  • If needed, add in the project list + the additional files required to run the example (refer to your example + readme file)
    • +
  • Rebuild all files and load your image + into target memory
    • +
  • Run the example
    • +
+ + + + + +

STM32F2xx +  StdPeriph_Lib + Examples

+

The package + contains the following examples:

+

ADC - CAN - CortexM3 - CRC - CRYP - DAC - DCMI - DMA - EXTI - FLASH - FSMC - GPIO - HASH - I2C - I2S - IWDG - Lib_DEBUG - NVIC - PWR - RCC - RNG - RTC - SDIO - SPI - SysTick - TIM - USART - WWDG -

+

 

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

IP/Module

+ 		+

Example

+
+

Name

+ 		+

 Brief description

+
+

 ADC

+ 		+

ADC3_DMA

+ 		+

This + example describes how to use the ADC3 and DMA to transfer + continuously converted data from ADC3 to memory. The ADC3 is + configured to convert continuously channel7.

+
+

DualADC_Interleaved_DMAmode3

+ 		+

This example provides a short + description of how to use the ADC peripheral to convert a regular + channel in Dual interleaved mode using DMA in mode 3 with 5Msps.

+
+

DualADC_RegulSimu_DMAmode1

+ 		+

This example provides a short + description of how to use the ADC peripheral to convert regular + channels simultaneously in dual mode using DMA in mode 1.

+
+

TripleADC_Interleaved_DMAmode2

+ 		+

This example provides a short + description of how to use the ADC peripheral to convert a regular + channel in Triple interleaved mode using DMA in mode 2 with 6Msps.

+
+

VBAT_Measurement

+ 		+

This example describes how to + measure VBAT voltage using ADC1 regular channel 18. In fact, the + measured value correspond to VBAT/2; as the VBAT voltage could be + higher than VDDA, to ensure the correct operation of the ADC, the + VBAT pin is internally connected to a bridge divider by 2.

+
+

CAN

+ 		+

LoopBack

+ 		+

This + example provides a description of how to set a communication with the + CAN in loopback mode.

+
+

Networking

+ 		+

This example shows how to configure + the CAN peripheral to send and receive CAN frames in normal mode. The + sent frames are used to control Leds by pressing key push button.

+
+

CortexM3

+ 		+

BitBand

+ 		+

This + example shows how to use CortexM3 Bit-Band access to perform atomic + read-modify-write and read operations on a variable in SRAM.

+
+

Mode_Privilege

+ 		+

This example shows how to modify + CortexM3 Thread mode privilege access and stack.
+ CortexM3 Thread mode is entered on Reset, and can be entered as a + result of an exception return.

+
+

MPU

+ 		+

This example presents the MPU + features on STM32F2xx devices and it can be easily ported to any + other STM32 device supporting MPU.

+
+

CRC

+ 		+

CRC_Example

+ 		+

This + example shows how to use CRC (cyclic redundancy check) calculation + unit to get a CRC code of a given buffer of data word (32-bit), based + on a fixed generator polynomial (0x4C11DB7).

+
+

CRYP

+ 		+

AES_ECBmode_DMA

+ 		+

This + example provides a short description of how to use the CRYPTO + peripheral to encrypt and decrypt data using AES-128 Algorithm.

+
+

AES_modes

+ 		+

This example provides a short + description of how to use the CRYPTO peripheral to encrypt and + decrypt data using AES in all modes (ECB, CBC, CTR) and all key sizes (128, 192, 256) Algorithm.

+
+

DES_TDES_modes

+ 		+

This example provides a short + description of how to use the CRYPTO peripheral to encrypt and decrypt + data using DES and TDES in all modes (ECB, CBC) Algorithm.

+
+

TDES_ECBmode_DMA

+ 		+

This example provides a short + description of how to use the CRYPTO peripheral to encrypt and + decrypt data using TDES Algorithm.

+
+

 DAC

+ 		+

DAC_SignalsGeneration

+ 		+

This + example provides a short description of how to use the DAC peripheral + to generate several signals using DMA controller.

+
+

DCMI

+ 		+

Camera

+ 		+

This example +shows how to use the DCMI to control the OV9655 or OV2640 Camera module mounted on  STM322xG-EVAL board RevB.

+
+

DMA

+ 		+

FLASH_RAM

+ 		+

This + example provides a description of how to use a DMA channel to + transfer a word data buffer from FLASH memory to embedded SRAM + memory.

+
+

EXTI

+ 		+

EXTI_Example

+ 		+

This + example shows how to configure external interrupt lines. In this + example, 2 EXTI lines (EXTI Line0 and Line15) are configured to + generate an interrupt on each rising and falling edge, + respectively.  In the interrupt routine a led connected to a + specific GPIO pin is toggled.

+
+

FLASH

+ 		+

Program

+ 		+

This + example provides a description of how to program the STM32F2xx FLASH.

+
+

Write_Protection

+ 		+

This example provides a description + of how to enable and disable the write protection for the STM32F2xx + FLASH.

+
+

FSMC

+ 		+

OneNAND

+ 		+

This + example shows how to configure the FSMC to drive the + KFG1216U2A/B-DIB6 OneNAND memory mounted on STM322xG-EVAL evaluation + board (MB786) RevA.

+
+

SRAM

+ 		+

This example shows how to configure + the FSMC to drive the CY7C1071DV33-12BAXI SRAM memory mounted on + STM322xG-EVAL evaluation board (MB786) RevB.

+
+

SRAM_DataMemory

+ 		+

This example shows how to use the + external SRAM mounted on STM322xG-EVAL RevB as program data memory + (including heap and stack).

+
+

GPIO

+ 		+

IOToggle

+ 		+

GPIO + ports are connected on AHB bus, using BSRRH and BSRRL registers one + cycle is required to set a pin and another cycle to reset it. So GPIO + pins can toggle at AHB clock divided by 2.

+
+

JTAG_Remap

+ 		+

This example provides a short + description of how to use the JTAG/SWD IOs as standard GPIOs and + gives a configuration sequence.

+
+

HASH

+ 		+

Context_Swap

+ 		+

This + example provides a short description of how to use the HASH + peripheral to save and restore hash context to serve a high priority + hash operation.

+
+

HASH_SHA1_MD5

+ 		+

This example provides a short + description of how to use the HASH peripheral to hash data using + SHA-1 and MD5 Algorithms.

+
+

HMAC_SHA1_MD5

+ 		+

This example provides a short + description of how to use the HASH peripheral to hash data using HMAC + SHA-1 and HMAC MD5 Algorithms.

+
+

SHA1_MD5_DMA

+ 		+

This example provides a short + description of how to use the HASH peripheral to hash data using + SHA-1 and MD5 Algorithms.

+
+

 I2C

+ 		+

EEPROM

+ 		+

This + firmware provides a basic example of how to use the I2C firmware + library and an associate I2C EEPROM driver to communicate with an I2C + EEPROM device (here the example is interfacing with M24C64 EEPROM)

+
+

IOE

+ 		+

This firmware provides an example + of configuring and using the IO Expander STMPE811 in order to control + input Joystick IOs, output IOs and the Touch Screen feature.

+
+

DataExchangeDMA

+ 		+

This is a typical example of how to + use the I2C firmware library to ensure the steps of an I2C + communication between slave Receiver/Transmitter and master Transmitter/Receiver + using DMA.

+
+

DataExchangeInterrupt

+ 		+

This is a typical example of how to + use the I2C firmware library to ensure the steps of an I2C + communication between slave Receiver/Transmitter and master + Transmitter/Receiver using interrupts.

+
+

MasterReceiverInterrupt

+ 		+

This is a typical example of how to + use the I2C firmware library to ensure the steps of an I2C + communication between slave transmitter and master receiver using + interrupt.

+
+

MasterTransmitterInterrupt

+ 		+

This example provides a small + application in which joystick buttons are used to trigger I2C + communication using interrupt and though using I2C firmware library.

+
+

 I2S

+ 		+

I2S_Audio

+ 		+

This + example provides basic implementation of audio features. It allows + playing an audio file through the I2S peripheral and using the + external codec implemented on the STM322xG-EVAL board.

+
+

 IWDG

+ 		+

IWDG_Example

+ 		+

This + example shows how to update at regular period the IWDG reload counter + and how to simulate a software fault generating an MCU IWDG reset on + expiry of a programmed time period.

+
+

Lib_DEBUG

+ 		+

Lib_DEBUG_Example

+ 		+

This + example demonstrates how to declare dynamic peripherals pointers used + for Debug mode.

+
+

NVIC

+ 		+

DMA_WFIMode

+ 		+

This + example shows how to enter the system to WFI mode with DMA transfer + enabled and wake-up from this mode by the DMA End of Transfer + interrupt.

+
+

IRQ_Mask

+ 		+

This example demonstrates the use + of the Nested Vectored Interrupt Controller (NVIC) IRQ Channels + configuration and how to mask/activate different IRQs.

+
+

IRQ_Priority

+ 		+

This example demonstrates the use + of the Nested Vectored Interrupt Controller (NVIC) and how to + configure their priorities.

+
+

VectorTable_Relocation

+ 		+

This example describes how to + relocate the CortexM3 vector table in a specific address other than + the default Flash memory base address.

+
+

 PWR

+ 		+

BOR

+ 		+

This + example shows how to configure the programmable BOR thresholds using + the FLASH option bytes.

+
+

CurrentConsumption

+ 		+

This example shows how to configure + the STM32F2xx system to measure different Low Power modes current + consumption.

+
+

PVD

+ 		+

This example shows how to configure + the programmable voltage detector using an external interrupt line. + In this example, EXTI line 16 is configured to generate an interrupt + on each rising or falling edge of the PVD output signal (which + indicates that the Vdd voltage is below the PVD threshold).

+
+

STANDBY

+ 		+

This example shows how to enter the + system to STANDBY mode and wake-up from this mode using: external + RESET, RTC Alarm A or WKUP pin.

+
+

STOP

+ 		+

This example shows how to enter the + system to STOP mode and wake-up from this mode using RTC Wakeup Timer + Event connected to EXTI Line 22.

+
+

RCC

+ 		+

RCC_Example

+ 		+

This + example shows how to use, for debug purpose, the RCC_GetClocksFreq + function to retrieve the current status and frequencies of different + on chip clocks. You can see the RCC_ClockFreq structure content, + which hold the frequencies of different on chip clocks, using your + toolchain debugger.

+
+

RNG

+ 		+

RNG_MultiRNG

+ 		+

This + example provides a short description of how to use the RNG peripheral + to generate Random 32bit numbers.

+
+

RTC

+ 		+

BKP_Domain

+ 		+

This + example demonstrates and explains how to use the peripherals available + on Backup Domain. These peripherals are: the RCC BDCR register + containing the LSE Osc configuration and the RTC Clock enable/disable + bits. It embeds also the RTC peripheral with its associated Backup + Data registers. And finally the Backup SRAM (4KB) with its low power + regulator allowing preserving its contents when the product is + powered by VBAT pin.

+
+

HW_Calendar

+ 		+

This example demonstrates and + explains how to use the RTC peripheral. As an application example, it + demonstrates how to setup the RTC peripheral, in terms of prescaler + and interrupts, to be used to keep time and to generate alarm + interrupt.

+
+

RTC_LSI

+ 		+

This example demonstrates and + explains how to use the LSI clock source auto calibration to get a + precise RTC clock.  As an application example, it demonstrates + how to configure the TIM5 timer internally connected to LSI clock + output, in order to adjust the RTC prescaler.

+
+

Tamper

+ 		+

This example shows how to + write/read data to/from RTC Backup data registers and demonstrates + the Tamper detection feature.

+
+

TimeStamp

+ 		+

This example provides a short + description of how to use the RTC peripheral and the Time Stamp + feature.

+
+

SDIO

+ 		+

uSDCard

+ 		+

This + example provides a basic example of how to use the SDIO firmware + library and an associate driver to perform read/write operations on + the SD Card memory (SD Card V1.0, V1.1, V2.0 and SDHC (High Capacity) + protocol) that could be mounted on the STM322xG_EVAL board.

+
+

SPI

+ 		+

SPI_FLASH

+ 		This +example provides a basic example of how to use the SPI firmware library +and an associated driver "spi_flash.c" to communicate with an M25P64 +SPI FLASH.
+

SPI_DataExchangeInterrupt

+ 		+
This +example provides a small application in which joystick buttons are used +to trigger SPI communication using interrupts and though using SPI +firmware library.
+ +
+

SysTick

+ 		+

SysTick_Example

+ 		+

This + example shows how to configure the SysTick to generate a time base + equal to 1 ms. The system clock is set to 120 MHz, the SysTick is + clocked by the AHB clock (HCLK).

+
+

TIM

+ 		+

6Steps

+ 		This +example shows how to configure the TIM1 peripheral to generate 6 Steps. +The STM32F2xx TIM1 peripheral offers the possibility to program in +advance the configuration for the next TIM1 outputs behaviour (step) +and change the configuration of all the channels at the same time. This +operation is possible when the COM (commutation) event is used.
+
+

7PWM_Output

+ 		+

This example shows how to configure + the TIM1 peripheral to generate 7 PWM signals with 4 different duty + cycles (50%, 37.5%, 25% and 12.5%).

+
+

Cascade_Synchro

+ 		+
This example shows how to synchronize TIM peripherals in cascade mode.
+ +
+

ComplementarySignals

+ 		+
This +example shows how to configure the TIM1 peripheral to generate three +complementary TIM1 signals, to insert a defined dead time value, to use +the break feature and to lock the desired parameters.
+ +
+

DMA

+ 		+

This example provides a description + of how to use DMA with TIM1 Update request to transfer Data from + memory to TIM1 Capture Compare Register3.

+
+

DMABurst

+ 		+
This example shows how to update the TIM1 channel1 period and the duty cycle using the TIM1 DMA burst feature.
+ +
+

ExtTrigger_Synchro

+ 		+
This example shows how to synchronize TIM peripherals in cascade mode with an external trigger.
+ +
+

InputCapture

+ 		+
This example shows how to use the TIM peripheral to measure the frequency of an external signal.
+ +
+

OCActive

+ 		+

This example shows how to configure + the TIM peripheral to generate four different signals with four + different delays.

+
+

OCInactive

+ 		+

This example shows how to configure + the TIM peripheral in Output Compare Inactive mode with the + corresponding Interrupt requests for each channel.

+
+

OCToggle

+ 		+

This example shows how to configure + the TIM3 peripheral to generate four different signals with four + different frequencies.

+
+

OnePulse

+ 		+
This +example shows how to use the TIM peripheral to generate a One pulse +Mode after a Rising edge of an external signal is received in Timer +Input pin.
+ +
+

Parallel_Synchro

+ 		+
This example shows how to synchronize TIM peripherals in parallel mode.
+ +
+

PWM_Input

+ 		+

This example shows how to use the + TIM peripheral to measure the frequency and duty cycle of an external + signal.

+
+

PWM_Output

+ 		+

This example shows how to configure + the TIM peripheral in PWM (Pulse Width Modulation) mode.

+
+

TIM10_PWMOutput

+ 		+

This example shows how to configure + the TIM peripheral in PWM (Pulse Width Modulation)
+ mode.

+
+

TIM1_Synchro

+ 		+
This example shows how to synchronize TIM1 and Timers (TIM3 and TIM4) in parallel mode.
+ +
+

TIM9_OCToggle

+ 		+

This example shows how to configure + the TIM9 peripheral to generate four different signals with four + different frequencies.

+
+

TimeBase

+ 		+

This example shows how to configure + the TIM peripheral in Output Compare Timing mode with the + corresponding Interrupt requests for each channel in order to generate + 4 different time bases.

+
+

USART

+ 		+

HyperTerminal_Interrupt

+ 		+

This + example provides a description of how to use the EVAL_COM1 Transmit + and Receive interrupts to communicate with the hyperterminal.

+
+

Printf

+ 		+

This example shows how to retarget + the C library printf function to the USART.  This implementation + output the printf message on the Hyperterminal using USART3.

+
+

Smartcard

+ 		+

This example describes a firmware + Smartcard Interface based on the STM32F2xx USART peripheral. The main + purpose of this firmware example is to provide resources facilitating + the development of an application using the USART peripheral in + smartcard mode.

+
+

DataExchangeDMA

+ 		+

This example provides a small + application in which joystick buttons are used to trigger USART + communications using DMA and though using USART firmware library.

+
+

DataExchangeInterrupt

+ 		+

This example provides a small + application in which joystick buttons are used to trigger USART + communication using interrupts and though using USART firmware + library.

+
+

 WWDG

+ 		+

WWDG_Example

+ 		+

This + example shows how to update at regular period the WWDG counter and + how to simulate a software fault generating an MCU WWDG reset on + expiry of a programmed time period.

+
+
+

Back to Top

+
+

 

+ + + + +
+

 

+

For complete + documentation on STM32 Microcontrollers visit www.st.com/STM32

+
+

+
+
+ +
+ +
+ + + +
+ + \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c new file mode 100644 index 000000000..79433cfbc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c @@ -0,0 +1,238 @@ +/** + ****************************************************************************** + * @file NVIC/DMA_WFIMode/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DMA_WFIMode + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define USART3_DR_ADDRESS ((uint32_t)0x40004804) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t LowPowerMode = 0; +uint16_t DstBuffer[10]= {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +/* Private function prototypes -----------------------------------------------*/ +void DMA_Config(void); +void USART_Config(void); +uint8_t Buffercmp16(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength); +void Delay(__IO uint32_t nCount); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize Leds and Key Button mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI); + + /* DMA1 Stream1 channel4 (connected to USART3_RX) configuration ------------*/ + DMA_Config(); + + /* EVAL_COM1 (USART3) configuration ----------------------------------------*/ + USART_Config(); + + while (1) + { + if(LowPowerMode == 1) + { + /* Turn Off LED2 and LED3 */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + + /* Request to enter WFI mode */ + __WFI(); + LowPowerMode = 0; + } + + Delay(0xFFFFF); + STM_EVAL_LEDToggle(LED1); + } +} + +/** + * @brief Configures the EVAL_COM1 (USART3). + * @param None + * @retval None + */ +void USART_Config(void) +{ + /* EVAL_COM1 configuration ---------------------------------------------------*/ + /* EVAL_COM1 configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitTypeDef USART_InitStructure; + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit(COM1, &USART_InitStructure); + + /* Enable DMA Rx request */ + USART_DMACmd(EVAL_COM1, USART_DMAReq_Rx, ENABLE); +} + +/** + * @brief Configures DMA1 Stream1 channel4 to handle USART3_RX DMA request. + * @param None + * @retval None + */ +void DMA_Config(void) +{ + DMA_InitTypeDef DMA_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* Enable DMA1 clock ********************************************************/ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE); + + /* DMA1 Stream1 channel4 configuration **************************************/ + DMA_InitStructure.DMA_Channel = DMA_Channel_4; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)USART3_DR_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)DstBuffer; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + DMA_InitStructure.DMA_BufferSize = 10; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(DMA1_Stream1, &DMA_InitStructure); + DMA_Cmd(DMA1_Stream1, ENABLE); + + /* Enable DMA1_Stream1 Transfer complete interrupt */ + DMA_ITConfig(DMA1_Stream1, DMA_IT_TC, ENABLE); + + /* Enable DMA1_Stream1 */ + DMA_Cmd(DMA1_Stream1, ENABLE); + + /* Enable DMA1_Stream1 IRQn Interrupt ***************************************/ + NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream1_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval 0: pBuffer1 identical to pBuffer2 + * 1: pBuffer1 differs from pBuffer2 + */ +uint8_t Buffercmp16(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength) +{ + while(BufferLength--) + { + if(*pBuffer1 != *pBuffer2) + { + return 1; + } + + pBuffer1++; + pBuffer2++; + } + return 0; +} + +/** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + */ +void Delay(__IO uint32_t nCount) +{ + for(; nCount != 0; nCount--); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/readme.txt new file mode 100644 index 000000000..ea3e58504 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/readme.txt @@ -0,0 +1,99 @@ +/** + @page NVIC_DMA_WFIMode NVIC DMA in WFI mode example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file NVIC/NVIC_DMA_WFIMode/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the NVIC DMA in WFI mode example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to enter the system to WFI mode with DMA transfer enabled +and wake-up from this mode by the DMA End of Transfer interrupt. + +In the associated software, the system clock is set to 120 MHz, the DMA1 Stream1 +channel4 is configured to transfer 10 data from the EVAL_COM1 (USART3) data register +to a predefined buffer, DST_Buffer, and to generate an interrupt at the end of +the transfer. The EVAL_COM1 (USART3) receives data from Hyperterminal. +LED1 is toggled with a frequency depending on the system clock, this is used +to indicate whether the MCU is in WFI or RUN mode. + +Pressing key push button (generates rising edge on EXTI Line15) will put the core +in the WFI mode, causing the LED1 to stop toggling. +To wake-up from WFI mode you have to send the sequence (0, 1, 2, 3, 4, 5, 6, 7, 8, 9) +from the Hyperterminal to the EVAL_COM1 (USART3). These bytes will be transferred +by the DMA from the EVAL_COM1 (USART3) receive data register to the predefined buffer, +then generates an interrupt which exits the system from WFI mode. +The LED1 restarts toggling and a LED2 will toggle if the buffer is correctly +received else a LED3 is toggled. + + +@par Directory contents + + - NVIC/DMA_WFIMode/stm32f2xx_conf.h Library Configuration file + - NVIC/DMA_WFIMode/stm32f2xx_it.c Interrupt handlers + - NVIC/DMA_WFIMode/stm32f2xx_it.h Interrupt handlers header file + - NVIC/DMA_WFIMode/main.c Main program + - NVIC/DMA_WFIMode/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily + tailored to any other development board. + + - STM322xG-EVAL Set-up + - Use the Key push-button connected to pin PG15 (EXTI Line15) + - Use LED1, LED2 and LED3 connected respectively to PG.06, PG.08 and PC.07 pins + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port if you want to display data on the HyperTerminal. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f2xx_conf.h new file mode 100644 index 000000000..ed06dbe8b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file NVIC/DMA_WFIMode/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f2xx_it.c new file mode 100644 index 000000000..0aabdc4f5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f2xx_it.c @@ -0,0 +1,220 @@ +/** + ****************************************************************************** + * @file NVIC/DMA_WFIMode/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup DMA_WFIMode + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint8_t TestStatus = 0; +uint16_t SrcBuffer[10] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39}; +extern uint16_t DstBuffer[10]; +extern __IO uint32_t LowPowerMode; +extern uint8_t Buffercmp16(uint16_t*, uint16_t*, uint16_t); + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles DMA1 Stream1 interrupt request. + * @param None + * @retval None + */ +void DMA1_Stream1_IRQHandler(void) +{ + if(DMA_GetITStatus(DMA1_Stream1, DMA_IT_TCIF1)) + { + DMA_ClearITPendingBit(DMA1_Stream1, DMA_IT_TCIF1); + + /* Check the received buffer */ + TestStatus = Buffercmp16(SrcBuffer, DstBuffer, 10); + + if(TestStatus == 0) + { + STM_EVAL_LEDToggle(LED2); + } + else + { + STM_EVAL_LEDToggle(LED3); + } + } +} + +/** + * @brief This function handles External lines 15 to 10 interrupt request. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET) + { + EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); + + LowPowerMode = 1; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f2xx_it.h new file mode 100644 index 000000000..29c660aaf --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f2xx_it.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file NVIC/DMA_WFIMode/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void DMA1_Stream1_IRQHandler(void); +void EXTI15_10_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/main.c new file mode 100644 index 000000000..318e78baf --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/main.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file NVIC/IRQ_Mask/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup IRQ_Mask + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize Leds mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Initialize the KEY and SEL buttons mounted on STM322xG-EVAL board */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); + STM_EVAL_PBInit(BUTTON_TAMPER, BUTTON_MODE_EXTI); + + /* TIM configuration -------------------------------------------------------*/ + TIM_Config(); + + while (1) + { + /* Wait until KEY button is pressed. */ + while(STM_EVAL_PBGetState(BUTTON_KEY) == RESET) + { + } + while(STM_EVAL_PBGetState(BUTTON_KEY) != RESET) + { + } + + /* This instruction raises the execution priority to 0. This prevents all + exceptions with configurable priority from activating, other than through + the HardFault fault escalation mechanism. */ + __disable_irq(); + + /* Turn LED4 ON */ + STM_EVAL_LEDOn(LED4); + + /* Wait until KEY button is pressed. */ + while(STM_EVAL_PBGetState(BUTTON_KEY) == RESET) + { + } + while(STM_EVAL_PBGetState(BUTTON_KEY) != RESET) + { + } + + /* This instruction will allow all exceptions with configurable priority to + be activated. */ + __enable_irq(); + + /* Turn LED4 OFF */ + STM_EVAL_LEDOff(LED4); + } +} + +/** + * @brief Configures the used Timers. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + TIM_OCInitTypeDef TIM_OCInitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* Enable TIM2, TIM3 and TIM4 clocks */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | + RCC_APB1Periph_TIM4, ENABLE); + + /* TIM2 configuration */ + TIM_TimeBaseStructure.TIM_Period = 0x4AF; + TIM_TimeBaseStructure.TIM_Prescaler = ((SystemCoreClock/1200) - 1); + TIM_TimeBaseStructure.TIM_ClockDivision = 0x0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure); + TIM_OCStructInit(&TIM_OCInitStructure); + + /* Output Compare Timing Mode configuration: Channel1 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStructure.TIM_Pulse = 0x0; + TIM_OC1Init(TIM2, &TIM_OCInitStructure); + + /* TIM3 configuration */ + TIM_TimeBaseStructure.TIM_Period = 0x95F; + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); + + /* Output Compare Timing Mode configuration: Channel1 */ + TIM_OC1Init(TIM3, &TIM_OCInitStructure); + + /* TIM4 configuration */ + TIM_TimeBaseStructure.TIM_Period = 0xE0F; + TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); + + /* Output Compare Timing Mode configuration: Channel1 */ + TIM_OC1Init(TIM4, &TIM_OCInitStructure); + + /* Immediate load of TIM2,TIM3 and TIM4 Precaler values */ + TIM_PrescalerConfig(TIM2, ((SystemCoreClock/1200) - 1), TIM_PSCReloadMode_Immediate); + TIM_PrescalerConfig(TIM3, ((SystemCoreClock/1200) - 1), TIM_PSCReloadMode_Immediate); + TIM_PrescalerConfig(TIM4, ((SystemCoreClock/1200) - 1), TIM_PSCReloadMode_Immediate); + + /* Clear TIM2, TIM3 and TIM4 update pending flags */ + TIM_ClearFlag(TIM2, TIM_FLAG_Update); + TIM_ClearFlag(TIM3, TIM_FLAG_Update); + TIM_ClearFlag(TIM4, TIM_FLAG_Update); + + /* Configure two bits for preemption priority */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + + /* Enable the TIM2 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Enable the TIM3 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_Init(&NVIC_InitStructure); + + /* Enable the TIM4 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_Init(&NVIC_InitStructure); + + /* Enable TIM2, TIM3 and TIM4 Update interrupts */ + TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE); + TIM_ITConfig(TIM3, TIM_IT_Update, ENABLE); + TIM_ITConfig(TIM4, TIM_IT_Update, ENABLE); + + /* TIM2, TIM3 and TIM4 enable counters */ + TIM_Cmd(TIM2, ENABLE); + TIM_Cmd(TIM3, ENABLE); + TIM_Cmd(TIM4, ENABLE); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/readme.txt new file mode 100644 index 000000000..5e34e5a1b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/readme.txt @@ -0,0 +1,125 @@ +/** + @page NVIC_IRQ_Mask NVIC IRQ Channels Mask example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file NVIC/IRQ_Mask/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the NVIC IRQ Channels Mask example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example demontrates the use of the Nested Vectored Interrupt Controller (NVIC) +IRQ Channels configuration and how to mask/activate different IRQs: + +- Configuration of 3 TIM (TIM2..TIM4) timers to generate an interrupt on each + counter update event. + +- The three timers are linked to their correspondant Update IRQ channel. + +- Assignment of a ascendant IRQ priority for each IRQ channel : + - TIM2 has a preemption priority of 0 + - TIM3 has a preemption priority of 1 + - TIM4 has a preemption priority of 2 +- In each interrupt routine: + - TIM2 toggles a LED1 each 1s + - TIM3 toggles a LED2 each 2s + - TIM4 toggles a LED3 each 3s + +- The KEY and SEL buttons are used to boost the execution priority as follows: + + - The KEY button is used in GPIO mode and at each KEY button press, the execution + priority is raised to 0 and turn LED4 ON. This prevents all exceptions with + configurable priority from activating, other than through the HardFault fault + escalation mechanism. As consequence, all LEDs stop toggling as TIM2, TIM3 + and TIM4 IRQs are prevented from activation. + + Pressing again the KEY button will release the priority boosting, turn LED4 + OFF and will allow all exceptions with configurable priority to be activated + and TIM2, TIM3 and TIM4 can be generated again and the LEDs restart toggling. + + This execution priority is made using the CMSIS functions "__disable_irq()" + and "__enable_irq()". + These two functions are managing the Cortex-M3 PRIMASK special register. + + - The TAMPER button is used in EXTI mode and at each TAMPER button press, the + execution priority is masked to 0x40 using the BASEPRI register. + A non-zero value will act as a priority mask, affecting the execution priority + when the priority defined by BASEPRI is the same or higher than the current + executing priority. + As consequence, LED2 and LED3 stop toggling as TIM3 and TIM4 IRQs are + prevented from activation. + Pressing again the TAMPER button will configure the BASEPRI register to 0, + thus it has no effect on the current priority and TIM3 and TIM4 can be + generated again and LED2 and LED3 restart toggling. + + This execution priority is made using the CMSIS functions "__set_BASEPRI()". + This function is managing the Cortex-M3 BASEPRI special register. + Setting the BASEPRI register has no effect when the execution priority is + raised to 0 using the "__disable_irq()" function. + +@note These mechanisms only affect the group priority. They have no effect on + the sub-priority. The sub-priority is only used to sort pending exception + priorities, and does not affect active exceptions. + + +@par Directory contents + + - NVIC/IRQ_Mask/stm32f2xx_conf.h Library Configuration file + - NVIC/IRQ_Mask/stm32f2xx_it.c Interrupt handlers + - NVIC/IRQ_Mask/stm32f2xx_it.h Interrupt handlers header file + - NVIC/IRQ_Mask/main.c Main program + - NVIC/IRQ_Mask/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily + tailored to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + - Use the KEY push-button connected to pin PG15 (EXTI Line15) + - Use the TAMPER push-button connected to pin PC13 (EXTI Line13) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f2xx_conf.h new file mode 100644 index 000000000..733de915a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file NVIC/IRQ_Mask/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f2xx_it.c new file mode 100644 index 000000000..ddf0d905c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f2xx_it.c @@ -0,0 +1,250 @@ +/** + ****************************************************************************** + * @file NVIC/IRQ_Mask/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup IRQ_Mask + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t index = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles EXTI Lines 15 to 10 interrupts requests. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + if(EXTI_GetITStatus(TAMPER_BUTTON_EXTI_LINE) != RESET) + { + if(index == 0) + { + /* Configure the BASEPRI register to 0x40 (Preemption priority = 1). + Only IRQ with higher preemption priority than 1 are permitted. + This will mask TIM3 and TIM4 IRQ from generation. */ + __set_BASEPRI(0x40); + index++; + } + else + { + /* Configure the BASEPRI register to 0x00 (Preemption priority = 0). + When this BASEPRI register is set to 0, it has no effect on the current + priority. + TIM2, TIM3 and TIM4 generation is controlled by NVIC priority registers. */ + __set_BASEPRI(0x00); + index = 0; + } + + /* Clears the TAMPER Button EXTI line pending bit */ + EXTI_ClearITPendingBit(TAMPER_BUTTON_EXTI_LINE); + } +} + +/** + * @brief This function handles TIM2 global interrupt request. + * @param None + * @retval None + */ +void TIM2_IRQHandler(void) +{ + /* Clear TIM2 update interrupt */ + TIM_ClearITPendingBit(TIM2, TIM_IT_Update); + + /* Toggle LED1 */ + STM_EVAL_LEDToggle(LED1); +} + +/** + * @brief This function handles TIM3 global interrupt request. + * @param None + * @retval None + */ +void TIM3_IRQHandler(void) +{ + /* Clear TIM3 update interrupt */ + TIM_ClearITPendingBit(TIM3, TIM_IT_Update); + + /* Toggle LED2 */ + STM_EVAL_LEDToggle(LED2); +} + +/** + * @brief This function handles TIM4 global interrupt request. + * @param None + * @retval None + */ +void TIM4_IRQHandler(void) +{ + /* Clear TIM4 update interrupt */ + TIM_ClearITPendingBit(TIM4, TIM_IT_Update); + + /* Toggle LED3 */ + STM_EVAL_LEDToggle(LED3); +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f2xx_it.h new file mode 100644 index 000000000..7a7415ed9 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f2xx_it.h @@ -0,0 +1,64 @@ +/** + ****************************************************************************** + * @file NVIC/IRQ_Mask/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TIM4_IRQHandler(void); +void TIM3_IRQHandler(void); +void TIM2_IRQHandler(void); +void EXTI15_10_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/main.c new file mode 100644 index 000000000..b19aac7ab --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/main.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file NVIC/IRQ_Priority/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup IRQ_Priority + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint8_t PreemptionOccured = 0; +__IO uint8_t PreemptionPriorityValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +void NVIC_Config(void); +void Delay(__IO uint32_t nCount); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* NVIC configuration ------------------------------------------------------*/ + NVIC_Config(); + + /* Initialize LEDs and push-button mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI); + STM_EVAL_PBInit(BUTTON_WAKEUP, BUTTON_MODE_EXTI); + + /* Configure the SysTick Handler Priority: Preemption priority and subpriority */ + NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), !PreemptionPriorityValue, 0)); + + while (1) + { + if(PreemptionOccured != 0) + { + /* Toggel The lED1 */ + STM_EVAL_LEDToggle(LED1); + + /* Insert delay Time */ + Delay(0x5FFFF); + + STM_EVAL_LEDToggle(LED2); + + Delay(0x5FFFF); + + STM_EVAL_LEDToggle(LED3); + + Delay(0x5FFFF); + + STM_EVAL_LEDToggle(LED4); + + Delay(0x5FFFF); + } + } +} + +/** + * @brief Configures the NVIC interrupts. + * @param None + * @retval None + */ +void NVIC_Config(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + /* Configure the preemption priority and subpriority: + - 1 bits for pre-emption priority: possible value are 0 or 1 + - 3 bits for subpriority: possible value are 0..7 + - Lower values gives higher priority + */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + + /* Enable the WAKEUP_BUTTON_EXTI_IRQn Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = WAKEUP_BUTTON_EXTI_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = PreemptionPriorityValue; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Enable the KEY_BUTTON_EXTI_IRQn Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = KEY_BUTTON_EXTI_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +/** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + */ +void Delay(__IO uint32_t nCount) +{ + for(; nCount != 0; nCount--); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/readme.txt new file mode 100644 index 000000000..4bd8b268b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/readme.txt @@ -0,0 +1,110 @@ +/** + @page NVIC_IRQ_Priority NVIC IRQ Priority example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file NVIC/IRQ_Priority/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the NVIC IRQ Priority example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example demonstrates the use of the Nested Vectored Interrupt Controller (NVIC): + +- Configuration of 2 EXTI Lines (WAKEUP button EXTI Line & KEY button EXTI Line) + to generate an interrupt on each falling edge and use the SysTick interrupt. +- These interrupts are configured with the following parameters: + - WAKEUP button EXTI Line: + - PreemptionPriority = PreemptionPriorityValue + - SubPriority = 0 + - KEY button EXTI Line: + - PreemptionPriority = 0 + - SubPriority = 1 + - SysTick Handler: + - PreemptionPriority = !PreemptionPriorityValue + - SubPriority = 0 +First, the PreemptionPriorityValue is equal to 0, the WAKEUP button EXTI Line +has higher preemption priority than the SysTick handler. + +In the KEY button EXTI Line interrupt routine the WAKEUP button EXTI Line and +SysTick preemption priorities are inverted. +In the WAKEUP button EXTI Line interrupt routine the pending bit of the SysTick +interrupt is set this will cause SysTick ISR to preempt the WAKEUP button EXTI +Line ISR only if it has higher preemption priority. + +The system behaves as following: + +1) The first time KEY button EXTI Line interrupt occurs the SysTick preemption +become higher than WAKEUP button EXTI Line one. So when the WAKEUP button EXTI +Line interrupt occurs, the SysTick ISR is executed and the PreemptionOccured +variable become TRUE and the four leds (LED1, LED2, LED3, LED4) start toggling. + +2) When the next KEY button EXTI Line interrupt occurs the SysTick preemption +become lower than WAKEUP button EXTI Line one. So when the WAKEUP button EXTI Line +interrupt occurs, the PreemptionOccured variable became FALSE and the four leds +(LED1, LED2, LED3, LED4) stop toggling. + +Then this behavior is repeated from point 1) in an infinite loop. + + +@par Directory contents + + - NVIC/IRQ_Priority/stm32f2xx_conf.h Library Configuration file + - NVIC/IRQ_Priority/stm32f2xx_it.c Interrupt handlers + - NVIC/IRQ_Priority/stm32f2xx_it.h Interrupt handlers header file + - NVIC/IRQ_Priority/main.c Main program + - NVIC/IRQ_Priority/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily + tailored to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + - Use the WAKEUP push-button connected to pin PA.00 (EXTI Line0). + - Use the KEY push-button connected to pin PG15 (EXTI Line15) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f2xx_conf.h new file mode 100644 index 000000000..733de915a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file NVIC/IRQ_Mask/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f2xx_it.c new file mode 100644 index 000000000..b90faeeca --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f2xx_it.c @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file NVIC/IRQ_Priority/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup IRQ_Priority + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern __IO uint8_t PreemptionOccured; +extern __IO uint8_t PreemptionPriorityValue; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + /* If the WAKEUP_BUTTON_EXTI IRQ Handler (EXTI0_IRQHandler) was preempted + by SysTick Handler */ + if(NVIC_GetActive(WAKEUP_BUTTON_EXTI_IRQn) != 0) + { + PreemptionOccured = 1; + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles External line 0 interrupt request. + * @param None + * @retval None + */ +void EXTI0_IRQHandler(void) +{ + /* Generate SysTick exception */ + SCB->ICSR |= 0x04000000; + + /* Clear WAKEUP_BUTTON_EXTI_LINE pending bit */ + EXTI_ClearITPendingBit(WAKEUP_BUTTON_EXTI_LINE); +} + +/** + * @brief This function handles External lines 15 to 10 interrupt request. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET) + { + PreemptionPriorityValue = !PreemptionPriorityValue; + PreemptionOccured = 0; + + /* Modify the WAKEUP_BUTTON_EXTI_IRQn Interrupt Preemption Priority */ + NVIC_InitStructure.NVIC_IRQChannel = WAKEUP_BUTTON_EXTI_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = PreemptionPriorityValue; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Configure the SysTick Handler Priority: Preemption priority and subpriority */ + NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), !PreemptionPriorityValue, 0)); + + /* Clear KEY_BUTTON_EXTI_LINE pending bit */ + EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f2xx_it.h new file mode 100644 index 000000000..ee21e79a9 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f2xx_it.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file NVIC/IRQ_Priority/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void EXTI0_IRQHandler(void); +void EXTI15_10_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/EWARM/stm32f2xx_flash_offset.icf b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/EWARM/stm32f2xx_flash_offset.icf new file mode 100644 index 000000000..e8dbdae89 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/EWARM/stm32f2xx_flash_offset.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08004000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08004000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20020000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/RIDE/stm32f2xx_flash_offset.ld b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/RIDE/stm32f2xx_flash_offset.ld new file mode 100644 index 000000000..42a8f15c3 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/RIDE/stm32f2xx_flash_offset.ld @@ -0,0 +1,242 @@ +/* +Linker script for STM32F2xx_1024K_128K with flash offset. +*/ + +/* +These are used by the startup in order to allocate stacks for the different modes. +*/ +__Stack_Size = 1024 ; + +PROVIDE ( _Stack_Size = __Stack_Size ) ; + +__Stack_Init = _estack - __Stack_Size ; + +/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/ +PROVIDE ( _Stack_Init = __Stack_Init ) ; + +/* +There will be a link error if there is not this amount of RAM free at the end. +*/ +_Minimum_Stack_Size = 0x100 ; + + +/* include the memory spaces definitions sub-script */ +/* +Linker subscript for STM32F2xx definitions with 1024K Flash and 96K RAM */ + +/* Memory Spaces Definitions */ + +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + FLASH (rx) : ORIGIN = 0x8004000, LENGTH = 1024K-0x4000 + FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 +} + +/* higher address of the user mode stack */ +_estack = 0x20020000; + + + +/* include the sections management sub-script for FLASH mode */ +/* +Common part of the linker scripts for STR71x devices in FLASH mode +(that is, the FLASH is seen at 0) +Copyright RAISONANCE 2005 +You can use, modify and distribute thisfile freely, but without any waranty. +*/ + + + +/* Sections Definitions */ + +SECTIONS +{ + /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */ + .flashtext : + { + . = ALIGN(4); + *(.flashtext) /* Startup code */ + . = ALIGN(4); + } >FLASH + + + /* the program code is stored in the .text section, which goes to Flash */ + .text : + { + . = ALIGN(4); + + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + + . = ALIGN(4); + _etext = .; + /* This is used by the startup in order to initialize the .data secion */ + _sidata = _etext; + } >FLASH + + + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + + + /* This is the uninitialized data section */ + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* This is the user stack section + This is just to check that there is enough RAM left for the User mode stack + It should generate an error if it's full. + */ + ._usrstack : + { + . = ALIGN(4); + _susrstack = . ; + + . = . + _Minimum_Stack_Size ; + + . = ALIGN(4); + _eusrstack = . ; + } >RAM + + + + /* this is the FLASH Bank1 */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + .b1text : + { + *(.b1text) /* remaining code */ + *(.b1rodata) /* read-only data (constants) */ + *(.b1rodata*) + } >FLASHB1 + + /* this is the EXTMEM */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + + /* EXTMEM Bank0 */ + .eb0text : + { + *(.eb0text) /* remaining code */ + *(.eb0rodata) /* read-only data (constants) */ + *(.eb0rodata*) + } >EXTMEMB0 + + /* EXTMEM Bank1 */ + .eb1text : + { + *(.eb1text) /* remaining code */ + *(.eb1rodata) /* read-only data (constants) */ + *(.eb1rodata*) + } >EXTMEMB1 + + /* EXTMEM Bank2 */ + .eb2text : + { + *(.eb2text) /* remaining code */ + *(.eb2rodata) /* read-only data (constants) */ + *(.eb2rodata*) + } >EXTMEMB2 + + /* EXTMEM Bank0 */ + .eb3text : + { + *(.eb3text) /* remaining code */ + *(.eb3rodata) /* read-only data (constants) */ + *(.eb3rodata*) + } >EXTMEMB3 + + + + /* after that it's only debugging information. */ + + /* remove the debugging information from the standard libraries */ + DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TASKING/stm32f2xx_flash_offset.lsl b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TASKING/stm32f2xx_flash_offset.lsl new file mode 100644 index 000000000..c1561e162 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TASKING/stm32f2xx_flash_offset.lsl @@ -0,0 +1,221 @@ +//////////////////////////////////////////////////////////////////////////// +// +// File : stm32f2xx.lsl +// +// Version : @(#)stm32f2xx.lsl 1.1 10/11/03 +// +// Description : LSL file for the STMicroelectronics STM32F2xx +// +// Copyright 2010 Altium BV +// +// Macros specific to control this LSL file +// +// __MEMORY Define this macro to suppress definition of on-chip +// memory. Must be defined when you want to define on-chip +// in your project's LSL file. +// __FLASH_SIZE Specifies the size of flash memory to be allocated +// __SRAM_SIZE Specifies the size of the SRAM memory to be allocated +// __NO_DEFAULT_AUTO_VECTORS +// When enabled the interrup vector table will not be +// generated +// __COPY_VECTOR_TABLE Define this macro to enable copying the vector table +// at startup from ROM to RAM +// __VECTOR_TABLE_RAM_COPY +// Define this macro to enable copying the vector table +// at startup from ROM to RAM. It is also required to +// define the macro __VECTOR_TABLE_RAM_SPACE +// __VECTOR_TABLE_RAM_SPACE +// Define size of the RAM space for the vector table when +// it is copied from ROM to RAM +// __VECTOR_TABLE_ROM_ADDR +// Specify the vector table address in ROM +// __VECTOR_TABLE_RAM_ADDR +// Specify the vector table address in RAM when the the +// it is copied from ROM to RAM (__COPY_VECTOR_TABLE) +// +// See arm_arch.lsl for more available macros. +// +// Notes: +// In the STM32F2xx, 3 different boot modes can be selected +// - User Flash memory is selected as boot space +// - SystemMemory is selected as boot space +// - Embedded SRAM is selected as boot space +// +// This aliases the physical memory associated with each boot mode to Block +// 000 (0x00000000 boot memory). Even when aliased in the boot memory space, +// the related memory (Flash memory or SRAM) is still accessible at its +// original memory space. +// +//////////////////////////////////////////////////////////////////////////// + +#ifndef __NO_DEFAULT_AUTO_VECTORS +// Suppress the vectors as defined arm_arch.lsl, because we define our +// own vectors for CMIS +#define __CMSIS_VECTORS 1 +#define __NO_DEFAULT_AUTO_VECTORS 1 +#define __NR_OF_VECTORS 97 +#endif + +#ifndef __VECTOR_TABLE_ROM_ADDR +# define __VECTOR_TABLE_ROM_ADDR 0x08004000 +#endif + +#ifndef __VECTOR_TABLE_RAM_ADDR +# define __VECTOR_TABLE_RAM_ADDR 0x00000000 +#endif + + +#ifndef __STACK +# define __STACK 4k +#endif + +#ifndef __HEAP +# define __HEAP 2k +#endif + +#include + +// +// If no memory is defined yet use the following memory settings +// +#ifndef __MEMORY + +// Specify default size for Flash and SRAM +#ifndef __FLASH_SIZE +# define __FLASH_SIZE 1024k +#endif +#ifndef __SRAM_SIZE +# define __SRAM_SIZE 128k +#endif + +memory STM32F2xx_Flash +{ + mau = 8; + type = rom; + size = 1008k; + map ( size = 1008k, dest_offset=0x08004000, dest=bus:ARM:local_bus); +} + +memory STM32F2xx_SRAM +{ + mau = 8; + type = ram; + size = __SRAM_SIZE; + map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus); +} + +#endif /* __MEMORY */ + + +// +// Define the vector table for CMSIS +// +#ifdef __CMSIS_VECTORS +section_setup ::linear +{ + // vector table with handler addresses + vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR, + template = ".text.handler_address", + template_symbol = "_lc_vector_handler", + vector_prefix = "_vector_", + fill = loop, + no_inline + ) + { + vector ( id = 0, fill = "_lc_ub_stack" ); // Top of Stack + vector ( id = 1, fill = "_START" ); // Reset Handler + vector ( id = 2, optional, fill = "NMI_Handler" ); // NMI Handler + vector ( id = 3, optional, fill = "HardFault_Handler" ); // Hard Fault Handler + vector ( id = 4, optional, fill = "MemManage_Handler" ); // MPU Fault Handler + vector ( id = 5, optional, fill = "BusFault_Handler" ); // Bus Fault Handler + vector ( id = 6, optional, fill = "UsageFault_Handler" ); // Usage Fault Handler + vector ( id = 11, optional, fill = "SVC_Handler" ); // SVCall Handler + vector ( id = 12, optional, fill = "DebugMon_Handler" ); // Debug Monitor Handler + vector ( id = 14, optional, fill = "PendSV_Handler" ); // PendSV Handler + vector ( id = 15, optional, fill = "SysTick_Handler" ); // SysTick Handler + + // External Interrupts : + vector ( id = 16, optional, fill = "WWDG_IRQHandler" ); // Window Watchdog + vector ( id = 17, optional, fill = "PVD_IRQHandler" ); // PVD through EXTI Line detect + vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" ); // Tamper amd TimeStanp through EXTI + vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" ); // RTC Wakeup through the EXTI line + vector ( id = 20, optional, fill = "FLASH_IRQHandler" ); // Flash global interrupt + vector ( id = 21, optional, fill = "RCC_IRQHandler" ); // RCC global interrupt + vector ( id = 22, optional, fill = "EXTI0_IRQHandler" ); // EXTI Line 0 interrupt + vector ( id = 23, optional, fill = "EXTI1_IRQHandler" ); // EXTI Line 1 interrupt + vector ( id = 24, optional, fill = "EXTI2_IRQHandler" ); // EXTI Line 2 interrupt + vector ( id = 25, optional, fill = "EXTI3_IRQHandler" ); // EXTI Line 3 interrupt + vector ( id = 26, optional, fill = "EXTI4_IRQHandler" ); // EXTI Line 4 interrupt + vector ( id = 27, optional, fill = "DMA1_Stream0_IRQHandler" ); // DMA1 Stream 0 interrupt + vector ( id = 28, optional, fill = "DMA1_Stream1_IRQHandler" ); // DMA1 Stream 1 interrupt + vector ( id = 29, optional, fill = "DMA1_Stream2_IRQHandler" ); // DMA1 Stream 2 interrupt + vector ( id = 30, optional, fill = "DMA1_Stream3_IRQHandler" ); // DMA1 Stream 3 interrupt + vector ( id = 31, optional, fill = "DMA1_Stream4_IRQHandler" ); // DMA1 Stream 4 interrupt + vector ( id = 32, optional, fill = "DMA1_Stream5_IRQHandler" ); // DMA1 Stream 5 interrupt + vector ( id = 33, optional, fill = "DMA1_Stream6_IRQHandler" ); // DMA1 Stream 6 interrupt + vector ( id = 34, optional, fill = "ADC_IRQHandler" ); // ADC_IRQHandler interrupts + vector ( id = 35, optional, fill = "CAN1_TX_IRQHandler" ); // CAN1 TX interrupts + vector ( id = 36, optional, fill = "CAN1_RX0_IRQHandler" ); // CAN1 RX0 interrupts + vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" ); // CAN1 RX1 interrupt + vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" ); // CAN1 SCE interrupt + vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" ); // EXTI Line 9..5 interrupts + vector ( id = 40, optional, fill = "TIM1_BRK_TIM9_IRQHandler" ); // TIM1 Break irq and TIM9 global interrupt + vector ( id = 41, optional, fill = "TIM1_UP_TIM10_IRQHandler" ); // TIM1 Update irq and TIM10 global interrupt + vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM11_IRQHandler" ); // TIM1 Trigger and Commutation irqs and TIM10 global irq + vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" ); // TIM1 Capture Compare + vector ( id = 44, optional, fill = "TIM2_IRQHandler" ); // TIM2 global interrupt + vector ( id = 45, optional, fill = "TIM3_IRQHandler" ); // TIM3 global interrupt + vector ( id = 46, optional, fill = "TIM4_IRQHandler" ); // TIM4 global interrupt + vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" ); // I2C1 Event + vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" ); // I2C1 Error + vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" ); // I2C2 Event + vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" ); // I2C2 Error + vector ( id = 51, optional, fill = "SPI1_IRQHandler" ); // SPI1 global interrupt + vector ( id = 52, optional, fill = "SPI2_IRQHandler" ); // SPI2 global interrupt + vector ( id = 53, optional, fill = "USART1_IRQHandler" ); // USART1 global interrupt + vector ( id = 54, optional, fill = "USART2_IRQHandler" ); // USART2 global interrupt + vector ( id = 55, optional, fill = "USART3_IRQHandler" ); // USART3 global interrupt + vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" ); // EXTI Line 15..10 interrupts + vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" ); // RTC Alarm through EXTI Line + vector ( id = 58, optional, fill = "OTG_FS_WKUP_IRQHandler" ); // USB On-The-Go FS Wakeup throught EXTI + vector ( id = 59, optional, fill = "TIM8_BRK_TIM12_IRQHandler" ); // TIM8 Break irq and TIM12 global irq + vector ( id = 60, optional, fill = "TIM8_UP_TIM13_IRQHandler" ); // TIM8 Update irq and TIM13 global irq + vector ( id = 61, optional, fill = "TIM8_TRG_COM_TIM14_IRQHandler" ); // TIM8 trigger and Comm. irqs and TIM14 global irq + vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" ); // TIM8 Capture Compare irq + vector ( id = 63, optional, fill = "DMA1_Stream7_IRQHandler" ); // DMA1 Stream7 global interrupt + vector ( id = 64, optional, fill = "FSMC_IRQHandler" ); // FSMC global interrupt + vector ( id = 65, optional, fill = "SDIO_IRQHandler" ); // SDIO global interrupt + vector ( id = 66, optional, fill = "TIM5_IRQHandler" ); // TIM5 global interrupt + vector ( id = 67, optional, fill = "SPI3_IRQHandler" ); // SPI3 global interrupt + vector ( id = 68, optional, fill = "UART4_IRQHandler" ); // UART4 global interrupt + vector ( id = 69, optional, fill = "UART5_IRQHandler" ); // UART5 global interrupt + vector ( id = 70, optional, fill = "TIM6_DAC_IRQHandler" ); // TIM6 glbl irq, DAC1 and DAC2 underrun err irqs + vector ( id = 71, optional, fill = "TIM7_IRQHandler" ); // TIM7 global interrupt + vector ( id = 72, optional, fill = "DMA2_Stream0_IRQHandler" ); // DMA2 Stream0 global interrupt + vector ( id = 73, optional, fill = "DMA2_Stream1_IRQHandler" ); // DMA2 Stream1 global interrupt + vector ( id = 74, optional, fill = "DMA2_Stream2_IRQHandler" ); // DMA2 Stream2 global interrupt + vector ( id = 75, optional, fill = "DMA2_Stream3_IRQHandler" ); // DMA2 Stream3 global interrupt + vector ( id = 76, optional, fill = "DMA2_Stream4_IRQHandler" ); // DMA2 Stream4 global interrupt + vector ( id = 77, optional, fill = "ETH_IRQHandler" ); // Ethernet global interrupt + vector ( id = 78, optional, fill = "ETH_WKUP_IRQHandler" ); // Ethernet Wakeup through EXTI line irq + vector ( id = 79, optional, fill = "CAN2_TX_IRQHandler" ); // CAN2 TX interrupts + vector ( id = 80, optional, fill = "CAN2_RX0_IRQHandler" ); // CAN2 RX0 interrupts + vector ( id = 81, optional, fill = "CAN2_RX1_IRQHandler" ); // CAN2 RX1 interrupt + vector ( id = 82, optional, fill = "CAN2_SCE_IRQHandler" ); // CAN2 SCE interrupt + vector ( id = 83, optional, fill = "OTG_FS_IRQHandler" ); // USB On The Go FS global interrupt + vector ( id = 84, optional, fill = "DMA2_Stream5_IRQHandler" ); // DMA2 Stream5 global interrupt + vector ( id = 85, optional, fill = "DMA2_Stream6_IRQHandler" ); // DMA2 Stream6 global interrupt + vector ( id = 86, optional, fill = "DMA2_Stream7_IRQHandler" ); // DMA2 Stream7 global interrupt + vector ( id = 87, optional, fill = "USART6_IRQHandler" ); // USART6 global interrupt + vector ( id = 88, optional, fill = "I2C3_EV_IRQHandler" ); // I2C3 event interrupt + vector ( id = 89, optional, fill = "I2C3_ER_IRQHandler" ); // I2C3 error interrupt + vector ( id = 90, optional, fill = "OTG_HS_EP1_OUT_IRQHandler" ); // USB On The Go HS End Point 1 OUT global irq + vector ( id = 91, optional, fill = "OTG_HS_EP1_IN_IRQHandler" ); // USB On The Go HS End Point 1 In global irq + vector ( id = 92, optional, fill = "OTG_HS_WKUP_IRQHandler" ); // USB On The Go HS Wakeup through EXTI irq + vector ( id = 93, optional, fill = "OTG_HS_IRQHandler" ); // USB On The Go HS global interrupt + vector ( id = 94, optional, fill = "DCMI_IRQHandler" ); // DCMI global interrupt + vector ( id = 95, optional, fill = "CRYP_IRQHandler" ); // CRYP crypto global interrupt + vector ( id = 96, optional, fill = "HASH_RNG_IRQHandler" ); // Hash and Rng global interrupt + } +} +#endif /* __CMSIS_VECTORS */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TrueSTUDIO/stm32f2xx_flash_offset.ld b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TrueSTUDIO/stm32f2xx_flash_offset.ld new file mode 100644 index 000000000..7d87bfd41 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TrueSTUDIO/stm32f2xx_flash_offset.ld @@ -0,0 +1,170 @@ +/* +***************************************************************************** +** +** File : stm32f2xx_flash_offset.ld +** +** Abstract : Linker script for STM32F207IG Device with +** 1MByte FLASH, 128KByte SRAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the Atollic TrueSTUDIO(R) toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of 128K SRAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x200; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08004000, LENGTH = 1024K - 0x4000 + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c new file mode 100644 index 000000000..c9424b54f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c @@ -0,0 +1,182 @@ +/** + ****************************************************************************** + * @file NVIC/VectorTable_Relocation/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup VectorTable_Relocation + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static __IO uint32_t TimingDelay; + +/* Private function prototypes -----------------------------------------------*/ +void Delay(__IO uint32_t nTime); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Set the Vector Table base location at 0x08004000 + (this is already done in system_stm32f2xx.c file) */ + //NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x4000); + + /* Initialize Leds mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Turn on LED1 and LED3 */ + STM_EVAL_LEDOn(LED1); + STM_EVAL_LEDOn(LED3); + + /* Setup SysTick Timer for 1 msec interrupts. + ------------------------------------------ + 1. The SysTick_Config() function is a CMSIS function which configure: + - The SysTick Reload register with value passed as function parameter. + - Configure the SysTick IRQ priority to the lowest value (0x0F). + - Reset the SysTick Counter register. + - Configure the SysTick Counter clock source to be Core Clock Source (HCLK). + - Enable the SysTick Interrupt. + - Start the SysTick Counter. + + 2. You can change the SysTick Clock source to be HCLK_Div8 by calling the + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8) just after the + SysTick_Config() function call. The SysTick_CLKSourceConfig() is defined + inside the misc.c file. + + 3. You can change the SysTick IRQ priority by calling the + NVIC_SetPriority(SysTick_IRQn,...) just after the SysTick_Config() function + call. The NVIC_SetPriority() is defined inside the core_cm3.h file. + + 4. To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + + - Reload Value is the parameter to be passed for SysTick_Config() function + - Reload Value should not exceed 0xFFFFFF + */ + if (SysTick_Config(SystemCoreClock / 1000)) + { + /* Capture error */ + while (1); + } + + while (1) + { + /* Toggle LED2 and LED4 */ + STM_EVAL_LEDToggle(LED2); + STM_EVAL_LEDToggle(LED4); + + /* Insert 50 ms delay */ + Delay(50); + + /* Toggle LED1 and LED3 */ + STM_EVAL_LEDToggle(LED1); + STM_EVAL_LEDToggle(LED3); + + /* Insert 100 ms delay */ + Delay(100); + } +} + +/** + * @brief Inserts a delay time. + * @param nTime: specifies the delay time length, in milliseconds. + * @retval None + */ +void Delay(__IO uint32_t nTime) +{ + TimingDelay = nTime; + + while(TimingDelay != 0); +} + +/** + * @brief Decrements the TimingDelay variable. + * @param None + * @retval None + */ +void TimingDelay_Decrement(void) +{ + if (TimingDelay != 0x00) + { + TimingDelay--; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.h new file mode 100644 index 000000000..7bad6dbda --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.h @@ -0,0 +1,44 @@ +/** + ****************************************************************************** + * @file NVIC/VectorTable_Relocation/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TimingDelay_Decrement(void); + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/readme.txt new file mode 100644 index 000000000..e2bebab86 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/readme.txt @@ -0,0 +1,121 @@ +/** + @page NVIC_VectorTable_Relocation NVIC Vector Table Relocation example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file NVIC/VectorTable_Relocation/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the NVIC Vector Table Relocation example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example describes how to relocate the CortexM3 vector table in a specific +address other than the default Flash memory base address. +This can be used to build program which will be loaded into Flash memory by an +application previously programmed from the Flash memory base address. +Such application can be In-Application Programming (IAP) through USART, Ethernet +or USB (Device Firmware Upgrade, DFU). +These applications are available for download from the ST microcontrollers +website: ST Microcontrollers + +To build such application, some special configuration has to be performed: +1. Set the application load address, using your toolchain linker file +2. In the application code, relocate the vector table at the application load + address using the "NVIC_SetVectorTable" function from the misc.h/.c driver or + by modifying the value of the constant "VECT_TAB_OFFSET" defined + in system_stm32f2xx.c file. +For example, when building an application to be loaded with the IAP through USART +the application load address and vector table address must be set to 0x08004000. + +In this example, the associated program implements a "Delay" function based on +SysTick end of count interrupt, and toggles four leds with timing defined by the +"Delay" function. + + +@par Directory contents + + - NVIC/VectorTable_Relocation/stm32f2xx_conf.h Library Configuration file + - NVIC/VectorTable_Relocation/stm32f2xx_it.c Interrupt handlers + - NVIC/VectorTable_Relocation/stm32f2xx_it.h Interrupt handlers header file + - NVIC/VectorTable_Relocation/main.c Main program + - NVIC/VectorTable_Relocation/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily + tailored to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain and setup your project configuration as follows +
    +
  • MDK-ARM + - In the project option menu, select 'Target' window and enter 0x08004000 + as IROM1 start address + - In the project option menu, select 'Linker' window and enter 0x08004000 + as R/O base address + +
  • EWARM + - Use "stm32f2xx_flash_offset.icf" as linker file + +
  • RIDE + - In the Application options -> script menu, set "Use Default Script File" + to "No" and use "stm32f2xx_flash_offset.ld" as Script File. + This linker is configured for STM32F2xx. It should be updated to use it + with other STM32 devices. + +
  • TASKING + -In the project properties window, select C/C++ Build->settings node then + the "Linker->Script file" and use "stm32f2xx_flash_offset.lsl" as Script File. + This linker is configured for STM32F2xx. It should be updated to be used + with other STM32 devices. + +
  • TrueSTUDIO + - In the project properties window, select C/C++ Build->settings node then + the C Linker->General node and use "stm32f2xx_flash_offset.ld" as Script File. + This linker is configured for STM32F2xx. It should be updated to be used + with other STM32 devices. + +
+ + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f2xx_conf.h new file mode 100644 index 000000000..c3f917976 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file NVIC/VectorTable_Relocation/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f2xx_it.c new file mode 100644 index 000000000..610d322d9 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f2xx_it.c @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file NVIC/VectorTable_Relocation/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup VectorTable_Relocation + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + TimingDelay_Decrement(); +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f2xx_it.h new file mode 100644 index 000000000..7bee1427c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file NVIC/VectorTable_Relocation/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f2xx.c new file mode 100644 index 000000000..48468bed3 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/NVIC/VectorTable_Relocation/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x4000 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/main.c new file mode 100644 index 000000000..0b1194eff --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/main.c @@ -0,0 +1,134 @@ +/** + ****************************************************************************** + * @file PWR/BOR/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup PWR_BOR + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Uncomment the corresponding line to select the BOR level */ +#define BOR_LEVEL OB_BOR_OFF /*!< BOR Reset threshold levels for 1.62V - 2.10V VDD power supply */ +//#define BOR_LEVEL OB_BOR_LEVEL1 /*!< BOR Reset threshold levels for 2.10V - 2.40V VDD power supply */ +//#define BOR_LEVEL OB_BOR_LEVEL2 /*!< BOR Reset threshold levels for 2.40V - 2.70V VDD power supply */ +//#define BOR_LEVEL OB_BOR_LEVEL3 /*!< BOR Reset threshold levels for 2.70V - 3.60V VDD power supply */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t Counter = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LED1 on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + + /* Initialize Key Button mounted on STM322xG-EVAL board */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); + + /* Test if Key push-button on STM322xG-EVAL Board is pressed */ + if (STM_EVAL_PBGetState(BUTTON_KEY) == 0x00) + { + /* Get BOR Option Bytes */ + if((FLASH_OB_GetBOR() & 0x0C) != BOR_LEVEL) + { + /* Unlocks the option bytes block access */ + FLASH_OB_Unlock(); + + /* Select the desired V(BOR) Level -------------------------------------*/ + FLASH_OB_BORConfig(BOR_LEVEL); + + /* Launch the option byte loading */ + FLASH_OB_Launch(); + + /* Locks the option bytes block access */ + FLASH_OB_Lock(); + } + } + + while (1) + { + /* Toggle The LED1 */ + STM_EVAL_LEDToggle(LED1); + + /* Inserted Delay */ + for(Counter = 0; Counter < 0x5FFFF; Counter++); + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/readme.txt new file mode 100644 index 000000000..be8aac270 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/readme.txt @@ -0,0 +1,78 @@ +/** + @page PWR_BOR PWR Brown Out Reset (BOR) example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file PWR/BOR/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the PWR Brown Out Reset (BOR) example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the programmable BOR thresholds using the +FLASH option bytes. + +By maintaining the Key push-button pressed at Reset, the new BOR level will be +programmed. To modify the BOR threshold, select the voltage range using the +appropriate line "#define BOR_LEVEL OB_BOR_XXXX" in main.c file. + +LED1 is toggling to indicate that the reset is released and the system is in RUN +mode otherwise the BOR is maintaining the reset. + + +@par Directory contents + + - PWR/BOR/stm32f2xx_conf.h Library Configuration file + - PWR/BOR/stm32f2xx_it.c Interrupt handlers + - PWR/BOR/stm32f2xx_it.h Interrupt handlers header file + - PWR/BOR/main.c Main program + - PWR/BOR/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1 led connected to PG.06 pin + - Use the Key push-button connected to pin PG15 (EXTI Line15) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/stm32f2xx_conf.h new file mode 100644 index 000000000..651360b3a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file PWR/BOR/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/stm32f2xx_it.c new file mode 100644 index 000000000..6647d903d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/stm32f2xx_it.c @@ -0,0 +1,174 @@ +/** + ****************************************************************************** + * @file PWR/BOR/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup PWR_BOR + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/stm32f2xx_it.h new file mode 100644 index 000000000..176cd7f19 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file PWR/BOR/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/BOR/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/main.c new file mode 100644 index 000000000..e10cf2258 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/main.c @@ -0,0 +1,196 @@ +/** + ****************************************************************************** + * @file PWR/CurrentConsumption/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stm32f2xx_lp_modes.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup PWR_CurrentConsumption + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t Counter = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Enable PWR APB1 Clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Allow access to Backup */ + PWR_BackupAccessCmd(ENABLE); + + /* Reset RTC Domain */ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); + + /* Check that the system was resumed from StandBy mode */ + if(PWR_GetFlagStatus(PWR_FLAG_SB) != RESET) + { + /* Clear SB Flag */ + PWR_ClearFlag(PWR_FLAG_SB); + + /* Initialize LED1 on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + + /* Infinite loop */ + while (1) + { + /* Toggle The LED1 */ + STM_EVAL_LEDToggle(LED1); + + /* Inserted Delay */ + for(Counter = 0; Counter < 0x5FFFF; Counter++); + } + } + + /* Configure Key Button */ + STM_EVAL_PBInit(BUTTON_KEY,BUTTON_MODE_GPIO); + + /* Wait until Key button is pressed to enter the Low Power mode */ + while(STM_EVAL_PBGetState(BUTTON_KEY) != RESET) + { + } + /* Loop while Key button is maintained pressed */ + while(STM_EVAL_PBGetState(BUTTON_KEY) == RESET) + { + } + +#if defined (SLEEP_MODE) + /* Sleep Mode Entry + - System Running at PLL (120MHz) + - Flash 3 wait state + - Prefetch and Cache enabled + - Code running from Internal FLASH + - All peripherals disabled. + - Wakeup using EXTI Line (Key Button PG.15) + */ + SleepMode_Measure(); +#elif defined (STOP_MODE) + /* STOP Mode Entry + - RTC Clocked by LSE/LSI + - Regulator in LP mode + - HSI, HSE OFF and LSI OFF if not used as RTC Clock source + - No IWDG + - FLASH in deep power down mode + - Automatic Wakeup using RTC clocked by LSE/LSI (after ~20s) + */ + StopMode_Measure(); +#elif defined (STANDBY_MODE) + /* STANDBY Mode Entry + - Backup SRAM and RTC OFF + - IWDG and LSI OFF + - Wakeup using WakeUp Pin (PA.00) + */ + StandbyMode_Measure(); +#elif defined (STANDBY_RTC_MODE) + /* STANDBY Mode with RTC on LSE/LSI Entry + - RTC Clocked by LSE or LSI + - IWDG OFF and LSI OFF if not used as RTC Clock source + - Backup SRAM OFF + - Automatic Wakeup using RTC clocked by LSE/LSI (after ~20s) + */ + StandbyRTCMode_Measure(); +#elif defined (STANDBY_RTC_BKPSRAM_MODE) + /* STANDBY Mode with RTC on LSE/LSI Entry + - RTC Clocked by LSE/LSI + - Backup SRAM ON + - IWDG OFF + - Automatic Wakeup using RTC clocked by LSE/LSI (after ~20s) + */ + StandbyRTCBKPSRAMMode_Measure(); +#else + + /* Initialize LED1 on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + + /* Infinite loop */ + while (1) + { + /* Toggle The LED1 */ + STM_EVAL_LEDToggle(LED1); + + /* Inserted Delay */ + for(Counter = 0; Counter < 0x5FF; Counter++); + } +#endif +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/readme.txt new file mode 100644 index 000000000..8a0c334be --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/readme.txt @@ -0,0 +1,152 @@ +/** + @page PWR_CurrentConsumption PWR Current Consumption example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file PWR/CurrentConsumption/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the PWR Current Consumption example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the STM32F2xx system to measure different +Low Power modes current consumption. The Low Power modes are: + - Sleep Mode + - STOP mode with RTC + - STANDBY mode without RTC and BKPSRAM + - STANDBY mode with RTC + - STANDBY mode with RTC and BKPSRAM + +To run this example, user has to follow the following steps: + 1. Select the Low power modes to be measured by uncommenting the corresponding + line inside the stm32f2xx_lp_modes.h file. + @code + /*#define SLEEP_MODE*/ + /*#define STOP_MODE*/ + /*#define STANDBY_MODE*/ + #define STANDBY_RTC_MODE + /*#define STANDBY_RTC_BKPSRAM_MODE*/ + @endcode + + 2. Use an external amperemeter to measure the IDD current. + + 3. This example can not be used in DEBUG mode,this is due to the fact that the + Cortex™-M3 core is no longer clocked during low power mode so debugging + features are disbaled + +Here below a detailed description of the example code: + + @verbatim + + 1. After reset, the program waits for Key button connected to the PG.15 to be + pressed to enter the selected low power mode. + - When the RTC is not used in the low power mode configuration, press + again the Key button to exit the low power mode. + - When the RTC is used, the wakeup from low power mode is automatically + generated by the RTC (after 4s). + + 2. Low power modes description: + + - Sleep Mode + ============ + - System Running at PLL (120MHz) + - Flash 3 wait state + - Prefetch and Cache enabled + - Code running from Internal FLASH + - All peripherals disabled. + - Wakeup using EXTI Line (Key Button PG.15) + + - STOP Mode + =========== + - RTC Clocked by LSE or LSI + - Regulator in LP mode + - HSI, HSE OFF and LSI if not used as RTC Clock source + - No IWDG + - FLASH in deep power down mode + - Automatic Wakeup using RTC clocked by LSE/LSI (after ~20s) + + - STANDBY Mode + ============== + - Backup SRAM and RTC OFF + - IWDG and LSI OFF + - Wakeup using WakeUp Pin (PA.00) + + - STANDBY Mode with RTC clocked by LSE/LSI + ========================================== + - RTC Clocked by LSE or LSI + - IWDG OFF and LSI OFF if not used as RTC Clock source + - Backup SRAM OFF + - Automatic Wakeup using RTC clocked by LSE/LSI (after ~20s) + + - STANDBY Mode with RTC clocked by LSE/LSI and BKPSRAM + ====================================================== + - RTC Clocked by LSE or LSI + - Backup SRAM ON + - IWDG OFF + - Automatic Wakeup using RTC clocked by LSE/LSI (after ~20s) + + @endverbatim + + +@par Directory contents + + - PWR/CurrentConsumption/stm32f2xx_conf.h Library Configuration file + - PWR/CurrentConsumption/stm32f2xx_it.c Interrupt handlers + - PWR/CurrentConsumption/stm32f2xx_it.h Interrupt handlers header file + - PWR/CurrentConsumption/main.c Main program + - PWR/CurrentConsumption/system_stm32f2xx.c STM32F2xx system source file + - PWR/CurrentConsumption/stm32f2xx_lp_modes.c STM32F2xx Low Power Modes source file + - PWR/CurrentConsumption/stm32f2xx_lp_modes.h STM32F2xx Low Power Modes header file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices revision B and revision Y + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1 connected to PG.06 pin. + - Use Key Button connected to PG.15 pin + - Make sure that JP31 is not fitted. + - Connect an amperemeter to JP32 to measure the IDD current + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Add the file stm32f2xx_lp_modes.c to the project source list + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_conf.h new file mode 100644 index 000000000..44b7aaf25 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file PWR/CurrentConsumption/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_it.c new file mode 100644 index 000000000..836b13e21 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_it.c @@ -0,0 +1,209 @@ +/** + ****************************************************************************** + * @file PWR/CurrentConsumption/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup PWR_CurrentConsumption + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles RTC Auto wake-up interrupt request. + * @param None + * @retval None + */ +void RTC_WKUP_IRQHandler(void) +{ + if(RTC_GetITStatus(RTC_IT_WUT) != RESET) + { + /* Toggle LED1 */ + STM_EVAL_LEDToggle(LED1); + RTC_ClearITPendingBit(RTC_IT_WUT); + EXTI_ClearITPendingBit(EXTI_Line22); + } +} + +/** + * @brief This function handles EXTI Lines 10 to 15 interrupts requests. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET) + { + /* Clear the Key Button EXTI line pending bit */ + EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_it.h new file mode 100644 index 000000000..2b296e810 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_it.h @@ -0,0 +1,54 @@ +/** + ****************************************************************************** + * @file PWR/CurrentConsumption/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void RTC_WKUP_IRQHandler(void); +void EXTI15_10_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_lp_modes.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_lp_modes.c new file mode 100644 index 000000000..d20010ae1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_lp_modes.c @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * @file PWR/CurrentConsumption/stm32f2xx_lp_modes.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the STM32F2xx Low Power Modes: + * - Sleep Mode + * - STOP mode with RTC + * - STANDBY mode without RTC and BKPSRAM + * - STANDBY mode with RTC + * - STANDBY mode with RTC and BKPSRAM + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_lp_modes.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup PWR_CurrentConsumption + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Uncomment the corresponding line to select the RTC Clock source */ +#define RTC_CLOCK_SOURCE_LSE /* LSE used as RTC source clock */ +/* #define RTC_CLOCK_SOURCE_LSI */ /* LSI used as RTC source clock. The RTC Clock + may varies due to LSI frequency dispersion. */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the system to enter Sleep mode for + * current consumption measurement purpose. + * Sleep Mode + * ========== + * - System Running at PLL (120MHz) + * - Flash 3 wait state + * - Prefetch and Cache enabled + * - Code running from Internal FLASH + * - All peripherals disabled. + * - Wakeup using EXTI Line (Key Button PG.15) + * @param None + * @retval None + */ +void SleepMode_Measure(void) +{ + __IO uint32_t index = 0; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure all GPIO as analog to reduce current consumption on non used IOs */ + /* Enable GPIOs clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | + RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | + RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOI, ENABLE); + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_Init(GPIOE, &GPIO_InitStructure); + GPIO_Init(GPIOF, &GPIO_InitStructure); + GPIO_Init(GPIOG, &GPIO_InitStructure); + GPIO_Init(GPIOH, &GPIO_InitStructure); + GPIO_Init(GPIOI, &GPIO_InitStructure); + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Disable GPIOs clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | + RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | + RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOI, DISABLE); + + /* Configure Key Button */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI); + + /* Request to enter SLEEP mode */ + __WFI(); + + /* Initialize LED1 on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + + /* Infinite loop */ + while (1) + { + /* Toggle The LED1 */ + STM_EVAL_LEDToggle(LED1); + + /* Inserted Delay */ + for(index = 0; index < 0x5FFFF; index++); + } +} + +/** + * @brief This function configures the system to enter Stop mode with RTC + * clocked by LSE or LSI for current consumption measurement purpose. + * STOP Mode with RTC clocked by LSE/LSI + * ===================================== + * - RTC Clocked by LSE or LSI + * - Regulator in LP mode + * - HSI, HSE OFF and LSI OFF if not used as RTC Clock source + * - No IWDG + * - FLASH in deep power down mode + * - Automatic Wakeup using RTC clocked by LSE/LSI (~20s) + * @param None + * @retval None + */ +void StopMode_Measure(void) +{ + __IO uint32_t index = 0; + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); + +#if defined (RTC_CLOCK_SOURCE_LSI) /* LSI used as RTC source clock*/ +/* The RTC Clock may varies due to LSI frequency dispersion. */ + /* Enable the LSI OSC */ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + +#elif defined (RTC_CLOCK_SOURCE_LSE) /* LSE used as RTC source clock */ + /* Enable the LSE OSC */ + RCC_LSEConfig(RCC_LSE_ON); + + /* Wait till LSE is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + +#else + #error Please select the RTC Clock source inside the main.c file +#endif /* RTC_CLOCK_SOURCE_LSI */ + + + /* Enable the RTC Clock */ + RCC_RTCCLKCmd(ENABLE); + + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); + + /* Configure all GPIO as analog to reduce current consumption on non used IOs */ + /* Enable GPIOs clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | + RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | + RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOI, ENABLE); + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_Init(GPIOE, &GPIO_InitStructure); + GPIO_Init(GPIOF, &GPIO_InitStructure); + GPIO_Init(GPIOG, &GPIO_InitStructure); + GPIO_Init(GPIOH, &GPIO_InitStructure); + GPIO_Init(GPIOI, &GPIO_InitStructure); + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Disable GPIOs clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | + RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | + RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOI, DISABLE); + + /* EXTI configuration *******************************************************/ + EXTI_ClearITPendingBit(EXTI_Line22); + EXTI_InitStructure.EXTI_Line = EXTI_Line22; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Enable the RTC Wakeup Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = RTC_WKUP_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* RTC Wakeup Interrupt Generation: Clock Source: RTCCLK_Div16, Wakeup Time Base: ~20s + RTC Clock Source LSE 32.768KHz or LSI ~32KHz + + Wakeup Time Base = (16 / (LSE or LSI)) * WakeUpCounter + */ + RTC_WakeUpClockConfig(RTC_WakeUpClock_RTCCLK_Div16); + RTC_SetWakeUpCounter(0xA000-1); + + /* Enable the Wakeup Interrupt */ + RTC_ITConfig(RTC_IT_WUT, ENABLE); + + /* Enable Wakeup Counter */ + RTC_WakeUpCmd(ENABLE); + + /* FLASH Deep Power Down Mode enabled */ + PWR_FlashPowerDownCmd(ENABLE); + + /* Enter Stop Mode */ + PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI); + + /* Initialize LED1 on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + + /* Infinite loop */ + while (1) + { + /* Toggle The LED1 */ + STM_EVAL_LEDToggle(LED1); + + /* Inserted Delay */ + for(index = 0; index < 0x5FF; index++); + } +} + +/** + * @brief This function configures the system to enter Standby mode for + * current consumption measurement purpose. + * STANDBY Mode + * ============ + * - Backup SRAM and RTC OFF + * - IWDG and LSI OFF + * - Wakeup using WakeUp Pin (PA.00) + * @param None + * @retval None + */ +void StandbyMode_Measure(void) +{ + /* Enable WKUP pin 1 */ + PWR_WakeUpPinCmd(ENABLE); + + /* Request to enter STANDBY mode (Wake Up flag is cleared in PWR_EnterSTANDBYMode function) */ + PWR_EnterSTANDBYMode(); + + /* Infinite loop */ + while (1) + { + } +} + +/** + * @brief This function configures the system to enter Standby mode with RTC + * clocked by LSE or LSI for current consumption measurement purpose. + * STANDBY Mode with RTC clocked by LSE/LSI + * ======================================== + * - RTC Clocked by LSE/LSI + * - IWDG OFF + * - Backup SRAM OFF + * - Automatic Wakeup using RTC clocked by LSE/LSI (after ~20s) + * @param None + * @retval None + */ +void StandbyRTCMode_Measure(void) +{ + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); + +#if defined (RTC_CLOCK_SOURCE_LSI) /* LSI used as RTC source clock*/ +/* The RTC Clock may varies due to LSI frequency dispersion. */ + /* Enable the LSI OSC */ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + +#elif defined (RTC_CLOCK_SOURCE_LSE) /* LSE used as RTC source clock */ + /* Enable the LSE OSC */ + RCC_LSEConfig(RCC_LSE_ON); + + /* Wait till LSE is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + +#else + #error Please select the RTC Clock source inside the main.c file +#endif /* RTC_CLOCK_SOURCE_LSI */ + + /* Enable the RTC Clock */ + RCC_RTCCLKCmd(ENABLE); + + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); + + /* RTC Wakeup Interrupt Generation: Clock Source: RTCCLK_Div16, Wakeup Time Base: ~20s + RTC Clock Source LSE 32.768KHz or LSI ~32KHz + + Wakeup Time Base = (16 / (LSE or LSI)) * WakeUpCounter + */ + RTC_WakeUpClockConfig(RTC_WakeUpClock_RTCCLK_Div16); + RTC_SetWakeUpCounter(0xA000-1); + + /* Enable the Wakeup Interrupt */ + RTC_ITConfig(RTC_IT_WUT, ENABLE); + + /* Enable Wakeup Counter */ + RTC_WakeUpCmd(ENABLE); + + /* Clear WakeUp (WUTF) pending flag */ + RTC_ClearFlag(RTC_FLAG_WUTF); + + /* Request to enter STANDBY mode (Wake Up flag is cleared in PWR_EnterSTANDBYMode function) */ + PWR_EnterSTANDBYMode(); + + /* Infinite loop */ + while (1) + { + } +} + +/** + * @brief This function configures the system to enter Standby mode with RTC + * clocked by LSE or LSI and with Backup SRAM ON for current consumption + * measurement purpose. + * STANDBY Mode with RTC clocked by LSE/LSI and BKPSRAM + * ==================================================== + * - RTC Clocked by LSE or LSI + * - Backup SRAM ON + * - IWDG OFF + * - Automatic Wakeup using RTC clocked by LSE/LSI (after ~20s) + * @param None + * @retval None + */ +void StandbyRTCBKPSRAMMode_Measure(void) +{ + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); + +#if defined (RTC_CLOCK_SOURCE_LSI) /* LSI used as RTC source clock*/ +/* The RTC Clock may varies due to LSI frequency dispersion. */ + /* Enable the LSI OSC */ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + +#elif defined (RTC_CLOCK_SOURCE_LSE) /* LSE used as RTC source clock */ + /* Enable the LSE OSC */ + RCC_LSEConfig(RCC_LSE_ON); + + /* Wait till LSE is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + +#else + #error Please select the RTC Clock source inside the main.c file +#endif /* RTC_CLOCK_SOURCE_LSI */ + + /* Enable the RTC Clock */ + RCC_RTCCLKCmd(ENABLE); + + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); + +/* Backup SRAM ***************************************************************/ + /* Enable BKPRAM Clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_BKPSRAM, ENABLE); + + /* Enable the Backup SRAM low power Regulator */ + PWR_BackupRegulatorCmd(ENABLE); + + /* Wait until the Backup SRAM low power Regulator is ready */ + while(PWR_GetFlagStatus(PWR_FLAG_BRR) == RESET) + { + } + + /* RTC Wakeup Interrupt Generation: Clock Source: RTCCLK_Div16, Wakeup Time Base: ~20s + RTC Clock Source LSE 32.768KHz or LSI ~32KHz + + Wakeup Time Base = (16 / (LSE or LSI)) * WakeUpCounter + */ + RTC_WakeUpClockConfig(RTC_WakeUpClock_RTCCLK_Div16); + RTC_SetWakeUpCounter(0xA000-1); + + /* Enable the Wakeup Interrupt */ + RTC_ITConfig(RTC_IT_WUT, ENABLE); + + /* Enable Wakeup Counter */ + RTC_WakeUpCmd(ENABLE); + + /* Clear WakeUp (WUTF) pending flag */ + RTC_ClearFlag(RTC_FLAG_WUTF); + + /* Request to enter STANDBY mode (Wake Up flag is cleared in PWR_EnterSTANDBYMode function) */ + PWR_EnterSTANDBYMode(); + + /* Infinite loop */ + while (1) + { + } +} + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_lp_modes.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_lp_modes.h new file mode 100644 index 000000000..3b8da3f07 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/stm32f2xx_lp_modes.h @@ -0,0 +1,63 @@ +/** + ****************************************************************************** + * @file PWR/CurrentConsumption/stm32f2xx_lp_modes.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for stm32f2xx_lp_modes.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_LP_MODES_H +#define __STM32F2xx_LP_MODES_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#if !defined (SLEEP_MODE) && !defined (STOP_MODE) && !defined (STANDBY_MODE)\ + && !defined (STANDBY_RTC_MODE) && !defined (STANDBY_RTC_BKPSRAM_MODE) +/* Uncomment the corresponding line to select the STM32F2xx Low Power mode */ +#define SLEEP_MODE +//#define STOP_MODE +//#define STANDBY_MODE +//#define STANDBY_RTC_MODE +//#define STANDBY_RTC_BKPSRAM_MODE +#endif + +#if !defined (SLEEP_MODE) && !defined (STOP_MODE) && !defined (STANDBY_MODE)\ + && !defined (STANDBY_RTC_MODE) && !defined (STANDBY_RTC_BKPSRAM_MODE) + #error "Please select first the target STM32F2xx Low Power mode to be measured (in stm32f2xx_lp_modes.h file)" +#endif + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SleepMode_Measure(void); +void StopMode_Measure(void); +void StandbyMode_Measure(void); +void StandbyRTCMode_Measure(void); +void StandbyRTCBKPSRAMMode_Measure(void); + +#endif /* __STM32F2xx_LP_MODES_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/CurrentConsumption/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/main.c new file mode 100644 index 000000000..6c90c330a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/main.c @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file PWR/PVD/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup PWR_PVD + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t i = 0; + +/* Private function prototypes -----------------------------------------------*/ +void PVD_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + + /* Configure the PVD */ + PVD_Config(); + + while (1) + { + /* Toggle The LED2 */ + STM_EVAL_LEDToggle(LED2); + + /* Inserted Delay */ + for(i = 0; i < 0x5FFFF; i++); + } +} + +/** + * @brief Configures the PVD resources. + * @param None + * @retval None + */ +void PVD_Config(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + /* Enable PWR clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Configure one bit for preemption priority */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + + /* Enable the PVD Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = PVD_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Configure EXTI Line16(PVD Output) to generate an interrupt on rising and + falling edges */ + EXTI_ClearITPendingBit(EXTI_Line16); + EXTI_InitStructure.EXTI_Line = EXTI_Line16; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Configure the PVD Level to 3 (PVD detection level set to 2.5V, refer to the + electrical characteristics of you device datasheet for more details) */ + PWR_PVDLevelConfig(PWR_PVDLevel_3); + + /* Enable the PVD Output */ + PWR_PVDCmd(ENABLE); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/readme.txt new file mode 100644 index 000000000..06d7217a3 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/readme.txt @@ -0,0 +1,76 @@ +/** + @page PWR_PVD PWR Programmable Voltage Detector (PVD) example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file PWR/PVD/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the PWR Programmable Voltage Detector (PVD) example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the programmable voltage detector using +an external interrupt line. In this example, EXTI line 16 is configured to generate +an interrupt on each rising or falling edge of the PVD output signal (which +indicates that the Vdd voltage is below the PVD threshold). +In the interrupt routine a led connected to a specific GPIO pin is toggled every +time the voltage drops below or above the target threshold. + +A LED connected to a specific GPIO pin is toggling to indicate that the system +is in RUN. + +@par Directory contents + + - PWR/PVD/stm32f2xx_conf.h Library Configuration file + - PWR/PVD/stm32f2xx_it.c Interrupt handlers + - PWR/PVD/stm32f2xx_it.h Interrupt handlers header file + - PWR/PVD/main.c Main program + - PWR/PVD/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - HW Set-up + - Connect a LED to PG.06 pin (will be referred to by LED1 in the example code) + - Connect a LED to PG.08 pin (will be referred to by LED2 in the example code) + @note This example can't run on the STM322xG-EVAL board. + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/stm32f2xx_conf.h new file mode 100644 index 000000000..3c3939ea2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file PWR/PVD/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/stm32f2xx_it.c new file mode 100644 index 000000000..b93c3a947 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/stm32f2xx_it.c @@ -0,0 +1,196 @@ +/** + ****************************************************************************** + * @file PWR/PVD/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup PWR_PVD + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles the PVD Output interrupt request. + * @param None + * @retval None + */ +void PVD_IRQHandler(void) +{ + if(EXTI_GetITStatus(EXTI_Line16) != RESET) + { + /* Toggle LED1 */ + STM_EVAL_LEDToggle(LED1); + + /* Clear the Key Button EXTI line pending bit */ + EXTI_ClearITPendingBit(EXTI_Line16); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/stm32f2xx_it.h new file mode 100644 index 000000000..08f6302be --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file PWR/PVD/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void PVD_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/PVD/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/main.c new file mode 100644 index 000000000..1e91d785c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/main.c @@ -0,0 +1,254 @@ +/** + ****************************************************************************** + * @file PWR/STANDBY/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup PWR_STANDBY + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Uncomment the corresponding line to select the RTC Clock source */ +#define RTC_CLOCK_SOURCE_LSE /* LSE used as RTC source clock */ +/* #define RTC_CLOCK_SOURCE_LSI */ /* LSI used as RTC source clock. The RTC Clock + may varies due to LSI frequency dispersion. */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +RTC_InitTypeDef RTC_InitStructure; +RTC_TimeTypeDef RTC_TimeStructure; +__IO uint32_t AsynchPrediv = 0, SynchPrediv = 0; + +/* Private function prototypes -----------------------------------------------*/ +void RTC_Config(void); +void SysTick_Configuration(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs and Key Button mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI); + + /* RTC configuration */ + RTC_Config(); + + /* Turn on LED1 */ + STM_EVAL_LEDOn(LED1); + + /* Enable WKUP pin */ + PWR_WakeUpPinCmd(ENABLE); + + /* Configure the SysTick to generate an interrupt each 250 ms */ + SysTick_Configuration(); + + while (1) + { + } +} + +/** + * @brief Configures the RTC. + * @param None + * @retval None + */ +void RTC_Config(void) +{ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Allow access to BKP Domain */ + PWR_BackupAccessCmd(ENABLE); + + /* Clear Wakeup flag */ + PWR_ClearFlag(PWR_FLAG_WU); + + /* Check if the StandBy flag is set */ + if (PWR_GetFlagStatus(PWR_FLAG_SB) != RESET) + { + /* Clear StandBy flag */ + PWR_ClearFlag(PWR_FLAG_SB); + + /* Wait for RTC APB registers synchronisation (needed after start-up from Reset)*/ + RTC_WaitForSynchro(); + /* No need to configure the RTC as the RTC config(clock source, enable, + prescaler,...) are kept after wake-up from STANDBY */ + } + else + { + /* RTC Configuration ******************************************************/ + /* Reset Backup Domain */ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); + +#if defined (RTC_CLOCK_SOURCE_LSI) /* LSI used as RTC source clock*/ +/* The RTC Clock may varies due to LSI frequency dispersion. */ + /* Enable the LSI OSC */ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; + +#elif defined (RTC_CLOCK_SOURCE_LSE) /* LSE used as RTC source clock */ + /* Enable the LSE OSC */ + RCC_LSEConfig(RCC_LSE_ON); + + /* Wait till LSE is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; + +#else + #error Please select the RTC Clock source inside the main.c file +#endif /* RTC_CLOCK_SOURCE_LSI */ + + /* Enable the RTC Clock */ + RCC_RTCCLKCmd(ENABLE); + + /* Wait for RTC APB registers synchronisation (needed after start-up from Reset)*/ + RTC_WaitForSynchro(); + + /* Set the RTC time base to 1s */ + RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; + RTC_InitStructure.RTC_AsynchPrediv = 0x7F; + RTC_InitStructure.RTC_SynchPrediv = 0x00FF; + + if (RTC_Init(&RTC_InitStructure) == ERROR) + { + /* Turn on LED2 */ + STM_EVAL_LEDOn(LED2); + + /* User can add here some code to deal with this error */ + while(1); + } + + /* Set the time to 01h 00mn 00s AM */ + RTC_TimeStructure.RTC_H12 = RTC_H12_AM; + RTC_TimeStructure.RTC_Hours = 0x01; + RTC_TimeStructure.RTC_Minutes = 0x00; + RTC_TimeStructure.RTC_Seconds = 0x00; + + if(RTC_SetTime(RTC_Format_BCD, &RTC_TimeStructure) == ERROR) + { + /* Turn on LED2 */ + STM_EVAL_LEDOn(LED2); + + /* User can add here some code to deal with this error */ + while(1); + } + } + + /* Clear RTC Alarm Flag */ + RTC_ClearFlag(RTC_FLAG_ALRAF); +} + +/** + * @brief Configures the SysTick to generate an interrupt each 250 ms. + * @param None + * @retval None + */ +void SysTick_Configuration(void) +{ + /* SysTick interrupt each 250 ms */ + if (SysTick_Config((SystemCoreClock/8) / 4)) + { + /* Capture error */ + while (1); + } + + /* Select AHB clock(HCLK) divided by 8 as SysTick clock source */ + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8); + + /* Set SysTick Preemption Priority to 1 */ + NVIC_SetPriority(SysTick_IRQn, 0x04); +} + + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/readme.txt new file mode 100644 index 000000000..59a4e6a62 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/readme.txt @@ -0,0 +1,102 @@ +/** + @page PWR_STANDBY PWR_STANDBY + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file PWR/STANDBY/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the PWR STANDBY example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to enters the system to STANDBY mode and wake-up from this +mode using: external RESET, RTC Alarm A or WKUP pin. + +In the associated software, the system clock is set to 120 MHz, an EXTI line +is configured to generate an interrupt on falling edge and the SysTick is programmed +to generate an interrupt each 250 ms. In the SysTick interrupt handler, the LED1 is +toggled, this is used to indicate whether the MCU is in STANDBY or RUN mode. + +When a falling edge is detected on the EXTI line an interrupt is generated. In the +EXTI handler routine the RTC is configured to generate an Alarm event in 5 second +then the system enters STANDBY mode causing the LED1 to stop toggling. +A rising edge on WKUP pin or an external RESET will wake-up the system from +STANDBY. If within 5 second neither rising edge on WKUP pin nor external RESET +are generated, the RTC Alarm A will wake-up the system. + +After wake-up from STANDBY mode, program execution restarts in the same way as after +a RESET, the RTC configuration (clock source, prescaler,...) is kept and LED1 restarts +toggling. As result there is no need to configure the RTC. + +two leds LED1 and LED2 are used to monitor the system state as following: + - LED2 ON: RTC configuration failed (system will go to an infinite loop) + - LED1 toggling: system in RUN mode + - LED1 off : system in STANDBY mode + +These Steps are repeated in an infinite loop. + +@note To measure the current consumption in STANDBY mode, please refer to + @subpage PWR_CurrentConsumption example. + +@note This example can not be used in DEBUG mode, this is due to the fact + that the Cortex™-M3 core is no longer clocked during low power mode + so debugging features are disbaled + + +@par Directory contents + + - PWR/STANDBY/system_stm32f2xx.c STM32F2xx system clock configuration file + - PWR/STANDBY/stm32f2xx_conf.h Library Configuration file + - PWR/STANDBY/stm32f2xx_it.c Interrupt handlers + - PWR/STANDBY/stm32f2xx_it.h Header for stm32f2xx_it.c + - PWR/STANDBY/main.c Main program + + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1 and LED2 connected to PG.06 and PG.08 pins + - Use the Key push-button connected to pin PG15 (EXTI Line15) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/stm32f2xx_conf.h new file mode 100644 index 000000000..0ddfe78cb --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file PWR/STANDBY/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/stm32f2xx_it.c new file mode 100644 index 000000000..d372836a6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/stm32f2xx_it.c @@ -0,0 +1,222 @@ +/** + ****************************************************************************** + * @file PWR/STANDBY/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup PWR_STANDBY + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +RTC_AlarmTypeDef RTC_AlarmStructure; +extern RTC_TimeTypeDef RTC_TimeStructure; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + /* Toggle LED1 */ + STM_EVAL_LEDToggle(LED1); +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles External lines 9 to 5 interrupt request. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET) + { + + /* Clear the SEL Button EXTI line pending bit */ + EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); + + /* Disable the Alarm A */ + RTC_AlarmCmd(RTC_Alarm_A, DISABLE); + + RTC_GetTime(RTC_Format_BIN, &RTC_TimeStructure); + + /* Set the alarm to current time + 5s */ + RTC_AlarmStructure.RTC_AlarmTime.RTC_H12 = RTC_TimeStructure.RTC_H12; + RTC_AlarmStructure.RTC_AlarmTime.RTC_Hours = RTC_TimeStructure.RTC_Hours; + RTC_AlarmStructure.RTC_AlarmTime.RTC_Minutes = RTC_TimeStructure.RTC_Minutes; + RTC_AlarmStructure.RTC_AlarmTime.RTC_Seconds = (RTC_TimeStructure.RTC_Seconds + 0x5) % 60; + RTC_AlarmStructure.RTC_AlarmDateWeekDay = 0x31; + RTC_AlarmStructure.RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; + RTC_AlarmStructure.RTC_AlarmMask = RTC_AlarmMask_DateWeekDay | RTC_AlarmMask_Hours | RTC_AlarmMask_Minutes; + RTC_SetAlarm(RTC_Format_BIN, RTC_Alarm_A, &RTC_AlarmStructure); + + /* Enable RTC Alarm A Interrupt: this Interrupt will wake-up the system from + STANDBY mode (RTC Alarm IT not enabled in NVIC) */ + RTC_ITConfig(RTC_IT_ALRA, ENABLE); + + /* Enable the Alarm A */ + RTC_AlarmCmd(RTC_Alarm_A, ENABLE); + + /* Clear RTC Alarm Flag */ + RTC_ClearFlag(RTC_FLAG_ALRAF); + + /* Request to enter STANDBY mode (Wake Up flag is cleared in PWR_EnterSTANDBYMode function) */ + PWR_EnterSTANDBYMode(); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/stm32f2xx_it.h new file mode 100644 index 000000000..c19395a1d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file PWR/STANDBY/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void EXTI15_10_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STANDBY/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/main.c new file mode 100644 index 000000000..344616905 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/main.c @@ -0,0 +1,289 @@ +/** + ****************************************************************************** + * @file PWR/STOP/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup PWR_STOP + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Uncomment the corresponding line to select the RTC Clock source */ +#define RTC_CLOCK_SOURCE_LSE /* LSE used as RTC source clock */ +/* #define RTC_CLOCK_SOURCE_LSI */ /* LSI used as RTC source clock. The RTC Clock + may varies due to LSI frequency dispersion. */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern __IO uint32_t TimingDelay; + +/* Private function prototypes -----------------------------------------------*/ +void RTC_Config(void); +void SysTick_Configuration(void); +void Delay(__IO uint32_t nTime); +void SYSCLKConfig_STOP(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Configure the SysTick to generate an interrupt each 250 ms */ + SysTick_Configuration(); + + /* Initialize LEDs and Key Button mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED4); + + /* Key button (EXTI_Line15) will be used to wakeup ths system from STOP mode */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI); + + /* RTC configuration */ + RTC_Config(); + + while (1) + { + /* Insert 5 second delay */ + Delay(20); + + /* Turn OFF LED2 */ + STM_EVAL_LEDOff(LED2); + + /* Enable Wakeup Counter */ + RTC_WakeUpCmd(ENABLE); + + /* Enter Stop Mode */ + PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI); + + /* Disable Wakeup Counter */ + RTC_WakeUpCmd(DISABLE); + + /* Configures system clock after wake-up from STOP: enable HSE, PLL and select + PLL as system clock source (HSE and PLL are disabled in STOP mode) */ + SYSCLKConfig_STOP(); + } +} + +/** + * @brief Configures the RTC clock source. + * @param None + * @retval None + */ +void RTC_Config(void) +{ + EXTI_InitTypeDef EXTI_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + __IO uint32_t AsynchPrediv = 0, SynchPrediv = 0; + + /* Enable the PWR clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); + +#if defined (RTC_CLOCK_SOURCE_LSI) /* LSI used as RTC source clock*/ +/* The RTC Clock may varies due to LSI frequency dispersion. */ + /* Enable the LSI OSC */ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; + +#elif defined (RTC_CLOCK_SOURCE_LSE) /* LSE used as RTC source clock */ + /* Enable the LSE OSC */ + RCC_LSEConfig(RCC_LSE_ON); + + /* Wait till LSE is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; + +#else + #error Please select the RTC Clock source inside the main.c file +#endif /* RTC_CLOCK_SOURCE_LSI */ + + /* Enable the RTC Clock */ + RCC_RTCCLKCmd(ENABLE); + + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); + + /* RTC Wakeup Interrupt Generation: Clock Source: RTCCLK_Div16, Wakeup Time Base: ~4s + + Wakeup Time Base = (16 / (LSE or LSI)) * WakeUpCounter + */ + RTC_WakeUpClockConfig(RTC_WakeUpClock_RTCCLK_Div16); + RTC_SetWakeUpCounter(0x1FFF); + + /* Enable the Wakeup Interrupt */ + RTC_ITConfig(RTC_IT_WUT, ENABLE); + + /* Connect EXTI_Line22 to the RTC Wakeup event */ + EXTI_ClearITPendingBit(EXTI_Line22); + EXTI_InitStructure.EXTI_Line = EXTI_Line22; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Enable the RTC Wakeup Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = RTC_WKUP_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + +} + +/** + * @brief Configures system clock after wake-up from STOP: enable HSE, PLL + * and select PLL as system clock source. + * @param None + * @retval None + */ +void SYSCLKConfig_STOP(void) +{ + /* After wake-up from STOP reconfigure the system clock */ + /* Enable HSE */ + RCC_HSEConfig(RCC_HSE_ON); + + /* Wait till HSE is ready */ + while (RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET) + {} + + /* Enable PLL */ + RCC_PLLCmd(ENABLE); + + /* Wait till PLL is ready */ + while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) + {} + + /* Select PLL as system clock source */ + RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); + + /* Wait till PLL is used as system clock source */ + while (RCC_GetSYSCLKSource() != 0x08) + {} +} + +/** + * @brief Configures the SysTick to generate an interrupt each 250 millisecond. + * @param None + * @retval None + */ +void SysTick_Configuration(void) +{ + /* SysTick interrupt each 250 ms */ + if (SysTick_Config((SystemCoreClock/8) / 4)) + { + /* Capture error */ + while (1); + } + + /* Select AHB clock(HCLK) divided by 8 as SysTick clock source */ + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8); + + /* Set SysTick Preemption Priority to 1 */ + NVIC_SetPriority(SysTick_IRQn, 0x04); +} + +/** + * @brief Inserts a delay time. + * @param nTime: specifies the delay time length, with a base of 250 milliseconds. + * @retval None + */ +void Delay(__IO uint32_t nTime) +{ + TimingDelay = nTime; + + while(TimingDelay != 0); + +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/readme.txt new file mode 100644 index 000000000..19e5d2a3d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/readme.txt @@ -0,0 +1,101 @@ +/** + @page PWR_STOP PWR_STOP + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file PWR/STOP/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the PWR STOP example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to enters the system to STOP mode and wake-up from this +mode using RTC Wakeup Timer Event connected to EXTI Line 22. + +In the associated software + - the system clock is set to 120 MHz + - the EXTI_Line15 is configured to generate interrupt on falling edge + - the EXTI_Line22 connected internally to the RTC Wakeup event is configured + to generate an interrupt on rising edge each 4s + - the SysTick is programmed to generate an interrupt each 250 ms +In the SysTick interrupt handler, LED2 is toggled, this is used to indicate whether +the MCU is in STOP or RUN mode. + +The system enters STOP mode and will wait for the RTC Wakeup event to be +generated each 4s, or Key push button is pressed. + - If the RTC WakeUp event (EXTI_Line22) is the source of wakeup from STOP, LED1 is toggled. + - If the Key button (EXTI_Line15) is the source of wakeup from STOP, LED4 is toggled. + +This behavior is repeated in an infinite loop. + +LEDs are used to monitor the system state as following: + - LED2 toggling: system in RUN mode + - LED1 toggled: system woken up from STOP using RTC WakeUp Interrupt + - LED4 toggled: system woken up from STOP using EXTI_Line15 (KEY push button) + + @note To measure the current consumption in STOP mode, please refer to + @subpage PWR_CurrentConsumption example. + + @note This example can not be used in DEBUG mode, this is due to the fact + that the Cortex™-M3 core is no longer clocked during low power mode + so debugging features are disbaled + + + +@par Directory contents + + - PWR/STOP/system_stm32f2xx.c STM32F2xx system clock configuration file + - PWR/STOP/stm32f2xx_conf.h Library Configuration file + - PWR/STOP/stm32f2xx_it.c Interrupt handlers + - PWR/STOP/stm32f2xx_it.h Header for stm32f2xx_it.c + - PWR/STOP/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2 and LED4 connected respectively to PG.06, PG.08 and PC.07 pins + - Use the Key push-button connected to pin PG15 (EXTI_Line15) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/stm32f2xx_conf.h new file mode 100644 index 000000000..9ae5b4d0d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file PWR/STOP/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/stm32f2xx_it.c new file mode 100644 index 000000000..fa5cb23cb --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/stm32f2xx_it.c @@ -0,0 +1,215 @@ +/** + ****************************************************************************** + * @file PWR/STOP/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup PWR_STOP + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t TimingDelay = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + TimingDelay--; + /* Toggle LED2 */ + STM_EVAL_LEDToggle(LED2); +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ +/** + * @brief This function handles RTC Auto wake-up interrupt request. + * @param None + * @retval None + */ +void RTC_WKUP_IRQHandler(void) +{ + if(RTC_GetITStatus(RTC_IT_WUT) != RESET) + { + /* Toggle LED1 */ + STM_EVAL_LEDToggle(LED1); + RTC_ClearITPendingBit(RTC_IT_WUT); + EXTI_ClearITPendingBit(EXTI_Line22); + } +} + +/** + * @brief This function handles External lines 15 to 10 interrupt request. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET) + { + /* Clear the Key Button EXTI line pending bit */ + EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); + + /* Toggle LED4 */ + STM_EVAL_LEDToggle(LED4); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx_md.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/stm32f2xx_it.h new file mode 100644 index 000000000..f84583680 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/stm32f2xx_it.h @@ -0,0 +1,54 @@ +/** + ****************************************************************************** + * @file PWR/STOP/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void EXTI9_5_IRQHandler(void); +void RTC_WKUP_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/PWR/STOP/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/main.c new file mode 100644 index 000000000..f6d1dbb49 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/main.c @@ -0,0 +1,170 @@ +/** + ****************************************************************************** + * @file RCC/RCC_Example/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup RCC_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +void Delay (uint32_t nCount); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + RCC_ClocksTypeDef RCC_ClockFreq; + + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs mounted on STM322xG-EVAL board ***************************/ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Turn on LED1 and LED3 */ + STM_EVAL_LEDOn(LED1); + STM_EVAL_LEDOn(LED3); + + /* This function fills the RCC_ClockFreq structure with the current + frequencies of different on chip clocks (for debug purpose) **************/ + RCC_GetClocksFreq(&RCC_ClockFreq); + + /* Enable Clock Security System(CSS): this will generate an NMI exception + when HSE clock fails *****************************************************/ + RCC_ClockSecuritySystemCmd(ENABLE); + + /* Enable and configure RCC global IRQ channel, will be used to manage HSE ready + and PLL ready interrupts. + These interrupts are enabled in stm32f2xx_it.c file **********************/ + NVIC_InitStructure.NVIC_IRQChannel = RCC_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Output HSE clock on MCO1 pin(PA8) ****************************************/ + /* Enable the GPIOA peripheral */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + + /* Configure MCO1 pin(PA8) in alternate function */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* HSE clock selected to output on MCO1 pin(PA8)*/ + RCC_MCO1Config(RCC_MCO1Source_HSE, RCC_MCO1Div_1); + + while (1) + { + /* Toggle LED2 and LED4 */ + STM_EVAL_LEDToggle(LED2); + STM_EVAL_LEDToggle(LED4); + + /* Insert a delay */ + Delay(0x7FFFF); + + /* Toggle LED1 and LED3 */ + STM_EVAL_LEDToggle(LED1); + STM_EVAL_LEDToggle(LED3); + + /* Insert a delay */ + Delay(0x7FFFF); + } +} + +/** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + */ +void Delay(__IO uint32_t nCount) +{ + /* Decrement nCount value */ + while (nCount != 0) + { + nCount--; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/readme.txt new file mode 100644 index 000000000..7f611c2bf --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/readme.txt @@ -0,0 +1,87 @@ +/** + @page RCC_Example RCC example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file RCC/RCC_Example/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the RCC example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to use, for debug purpose, the RCC_GetClocksFreq function +to retrieve the current status and frequencies of different on chip clocks. +You can see the RCC_ClockFreq structure content, which hold the frequencies of +different on chip clocks, using your toolchain debugger. + +This example handles also the High Speed External clock (HSE) failure detection: +when the HSE clock disappears (broken or disconnected external Quartz); HSE, PLL +are disabled (but no change on PLL config), HSI selected as system clock source +and an interrupt (NMI) is generated. In the NMI ISR, the HSE, HSE ready interrupt +are enabled and once HSE clock recover, the HSERDY interrupt is generated and in +the RCC ISR routine the system clock is reconfigured to its previous state (before +HSE clock failure). You can monitor the HSE clock on MCO1 pin(PA8). + +Four LEDs are toggled with a timing defined by the Delay function. + +@note On the STM322xG-EVAL board, to genertate the HSE failure you can remove + the HSE quartz from the socket. + + +@par Directory contents + + - RCC/RCC_Example/system_stm32f2xx.c STM32F2xx system clock configuration file + - RCC/RCC_Example/stm32f2xx_conf.h Library Configuration file + - RCC/RCC_Example/stm32f2xx_it.c Interrupt handlers + - RCC/RCC_Example/stm32f2xx_it.h Interrupt handlers header file + - RCC/RCC_Example/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily + tailored to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/stm32f2xx_conf.h new file mode 100644 index 000000000..d0ba82f9a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file RCC/RCC_Example/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/stm32f2xx_it.c new file mode 100644 index 000000000..aa6aef667 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/stm32f2xx_it.c @@ -0,0 +1,228 @@ +/** + ****************************************************************************** + * @file RCC/RCC_Example/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup RCC_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + /* This interrupt is generated when HSE clock fails */ + + if (RCC_GetITStatus(RCC_IT_CSS) != RESET) + { + /* At this stage: HSE, PLL are disabled (but no change on PLL config) and HSI + is selected as system clock source */ + + /* Enable HSE */ + RCC_HSEConfig(RCC_HSE_ON); + + /* Enable HSE Ready and PLL Ready interrupts */ + RCC_ITConfig(RCC_IT_HSERDY | RCC_IT_PLLRDY, ENABLE); + + /* Clear Clock Security System interrupt pending bit */ + RCC_ClearITPendingBit(RCC_IT_CSS); + + /* Once HSE clock recover, the HSERDY interrupt is generated and in the RCC ISR + routine the system clock will be reconfigured to its previous state (before + HSE clock failure) */ + } +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles RCC interrupt request. + * @param None + * @retval None + */ +void RCC_IRQHandler(void) +{ + if(RCC_GetITStatus(RCC_IT_HSERDY) != RESET) + { + /* Clear HSERDY interrupt pending bit */ + RCC_ClearITPendingBit(RCC_IT_HSERDY); + + /* Check if the HSE clock is still available */ + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + /* Enable PLL: once the PLL is ready the PLLRDY interrupt is generated */ + RCC_PLLCmd(ENABLE); + } + } + + if(RCC_GetITStatus(RCC_IT_PLLRDY) != RESET) + { + /* Clear PLLRDY interrupt pending bit */ + RCC_ClearITPendingBit(RCC_IT_PLLRDY); + + /* Check if the PLL is still locked */ + if (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) != RESET) + { + /* Select PLL as system clock source */ + RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/stm32f2xx_it.h new file mode 100644 index 000000000..66c0b7a3e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/stm32f2xx_it.h @@ -0,0 +1,61 @@ +/** + ****************************************************************************** + * @file RCC/RCC_Example/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void RCC_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RCC/RCC_Example/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/main.c new file mode 100644 index 000000000..7c9eddebf --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/main.c @@ -0,0 +1,268 @@ +/** + ****************************************************************************** + * @file RNG/RNG_MultiRNG/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stm322xg_eval_lcd.h" +#include + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup RNG_MultiRNG + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ + +//#define PRINT_ON_USART +#define PRINT_ON_LCD + +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +void RNG_Config(void); +void Display_Init(void); +void Display(uint32_t rng, uint8_t line); + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + uint32_t random32bit = 0; + uint8_t Counter = 0; + + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Display init (LCD or/and USART)*/ + Display_Init(); + + /* Key Button configuration */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); + + /* RNG configuration */ + RNG_Config(); + + while (1) + { + /* Wait until Key button is pressed */ + while(STM_EVAL_PBGetState(BUTTON_KEY) != RESET) + { + } + /* Loop while Key button is maintained pressed */ + while(STM_EVAL_PBGetState(BUTTON_KEY) == RESET) + { + } + + for(Counter = 0; Counter < 8; Counter++) + { + /* Wait until one RNG number is ready */ + while(RNG_GetFlagStatus(RNG_FLAG_DRDY)== RESET) + { + } + + /* Get a 32bit Random number */ + random32bit = RNG_GetRandomNumber(); + + /* Display the Random number value on the LCD or/and USART */ + Display(random32bit, Counter+1); + } + } +} + +/** + * @brief RNG configuration + * @param None + * @retval None + */ +void RNG_Config(void) +{ + /* Enable RNG clock source */ + RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE); + + /* RNG Peripheral enable */ + RNG_Cmd(ENABLE); +} + +/** + * @brief Display Init (LCD or/and USART) + * @param None + * @retval None + */ +void Display_Init(void) +{ +#ifdef PRINT_ON_USART + + USART_InitTypeDef USART_InitStructure; + /* USARTx configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit(COM1, &USART_InitStructure); + + printf("\n\r ========================================\n"); + printf("\n\r ==== Multiple RNG Generator Example ====\n"); + printf("\n\r ======================================== \n\n\r"); + printf("\n\r Press key button to generate 8 x 32bit random number\n"); +#endif + +#ifdef PRINT_ON_LCD +/* Initialize the LCD */ + STM322xG_LCD_Init(); + + /* Clear the LCD */ + LCD_Clear(White); + + /* Set the LCD Text size */ + LCD_SetFont(&Font8x12); + + /* Set the LCD Back Color and Text Color*/ + LCD_SetBackColor(Blue); + LCD_SetTextColor(White); + + LCD_DisplayStringLine(LINE(0x13), " To generate 8x32bit RNG, Press Key >>"); + + /* Set the LCD Text size */ + LCD_SetFont(&Font16x24); + + LCD_DisplayStringLine(LINE(0), "*** RNG Example ***"); + + /* Set the LCD Back Color and Text Color*/ + LCD_SetBackColor(White); + LCD_SetTextColor(Blue); + + LCD_DisplayStringLine(LINE(3)," Press KEY button "); + LCD_DisplayStringLine(LINE(5)," to START "); +#endif +} + +/** + * @brief Display the Random number value on LCD or/and USART + * @param rnumber: random number to display + * @param line: LCD line number + * @retval None + */ +void Display(uint32_t rnumber, uint8_t line) +{ +#ifdef PRINT_ON_LCD + uint8_t text[50]; +#endif + +#ifdef PRINT_ON_USART + printf("\r [ 0x%08x ]\n", rnumber); + if (line == 8) + { + printf("\n\r Press key button to generate 8 x 32bit random number\n"); + } +#endif + +#ifdef PRINT_ON_LCD + sprintf((char*)text," [ 0x%08X ] ", rnumber); + LCD_DisplayStringLine(LINE(line),text); +#endif +} + +/** + * @brief Retargets the C library printf function to the USART. + * @param None + * @retval None + */ +PUTCHAR_PROTOTYPE +{ + /* Place your implementation of fputc here */ + /* e.g. write a character to the USART */ + USART_SendData(EVAL_COM1, (uint8_t) ch); + + /* Loop until the end of transmission */ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) + {} + + return ch; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/readme.txt new file mode 100644 index 000000000..a52184193 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/readme.txt @@ -0,0 +1,96 @@ +/** + @page RNG_MultiRNG Multiple Random Number Generator Example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file RNG/RNG_MultiRNG/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of Multiple Random Number Generator Example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the RNG peripheral to +generate Random 32bit numbers. + +For this example, an interactive human interface is developed to allow user to +display 8 (arbitrary value, which can be updated by user) random 32bit numbers +using the eval board LCD and/or USART (CN16) with PC HyperTerminal, using +PRINT_ON_LCD and PRINT_ON_USART defines in main.c + +After startup, user is asked to press key button. +The 8 Random 32bit numbers are displayed as soon as the key is pressed. + +The USARTx is configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + + +@par Directory contents + + - RNG/RNG_MultiRNG/system_stm32f2xx.c STM32F2xx system clock configuration file + - RNG/RNG_MultiRNG/stm32f2xx_conf.h Library Configuration file + - RNG/RNG_MultiRNG/stm32f2xx_it.h Interrupt handlers header file + - RNG/RNG_MultiRNG/stm32f2xx_it.c Interrupt handlers + - RNG/RNG_MultiRNG/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port if you want to display data on the HyperTerminal. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/stm32f2xx_conf.h new file mode 100644 index 000000000..46000243b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file RNG/RNG_MultiRNG/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/stm32f2xx_it.c new file mode 100644 index 000000000..811c2ece1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file RNG/RNG_MultiRNG/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup RNG_MultiRNG + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/stm32f2xx_it.h new file mode 100644 index 000000000..4e0409742 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file RNG/RNG_MultiRNG/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RNG/RNG_MultiRNG/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/lcd_log_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/lcd_log_conf.h new file mode 100644 index 000000000..bd2f2a966 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/lcd_log_conf.h @@ -0,0 +1,114 @@ +/** + ****************************************************************************** + * @file RTC/BKP_Domain/lcd_log_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief lcd_log configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __LCD_LOG_CONF_H__ +#define __LCD_LOG_CONF_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" +#include + +#ifdef USE_STM322xG_EVAL + #include "stm322xg_eval_lcd.h" +#endif + +/** @addtogroup LCD_LOG + * @{ + */ + +/** @defgroup LCD_LOG + * @brief This file is the + * @{ + */ + + +/** @defgroup LCD_LOG_CONF_Exported_Defines + * @{ + */ + +/* Define the LCD default text color */ +#define LCD_LOG_DEFAULT_COLOR White + +/* Comment the line below to disable the scroll back and forward features */ +#define LCD_SCROLL_ENABLED + +/* Define the display window settings */ +#define YWINDOW_MIN 3 +#define YWINDOW_SIZE 12 +#define XWINDOW_MAX 50 + +/* Define the cache depth */ +#define CACHE_SIZE 50 + +/** @defgroup LCD_LOG_CONF_Exported_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup LCD_LOG_Exported_Macros + * @{ + */ + + +/** + * @} + */ + +/** @defgroup LCD_LOG_CONF_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup LCD_LOG_CONF_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ + + +#endif /* __LCD_LOG_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/main.c new file mode 100644 index 000000000..9e4c794ae --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/main.c @@ -0,0 +1,722 @@ +/** + ****************************************************************************** + * @file RTC/BKP_Domain/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup BKP_Domain + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Uncomment the corresponding line to select the RTC Clock source */ +#define RTC_CLOCK_SOURCE_LSE /* LSE used as RTC source clock */ +/* #define RTC_CLOCK_SOURCE_LSI */ /* LSI used as RTC source clock. The RTC Clock + may varies due to LSI frequency dispersion. */ +#define RTC_BKP_DR_NUMBER 0x14 +#define FIRST_DATA 0x32F2 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +RTC_InitTypeDef RTC_InitStructure; +RTC_TimeTypeDef RTC_TimeStructure; +RTC_DateTypeDef RTC_DateStructure; +__IO uint32_t AsynchPrediv = 0, SynchPrediv = 0; +__IO uint32_t TimeDisplay = 0; +uint32_t errorindex = 0, i = 0; + +uint32_t BKPDataReg[RTC_BKP_DR_NUMBER] = + { + RTC_BKP_DR0, RTC_BKP_DR1, RTC_BKP_DR2, + RTC_BKP_DR3, RTC_BKP_DR4, RTC_BKP_DR5, + RTC_BKP_DR6, RTC_BKP_DR7, RTC_BKP_DR8, + RTC_BKP_DR9, RTC_BKP_DR10, RTC_BKP_DR11, + RTC_BKP_DR12, RTC_BKP_DR13, RTC_BKP_DR14, + RTC_BKP_DR15, RTC_BKP_DR16, RTC_BKP_DR17, + RTC_BKP_DR18, RTC_BKP_DR19 + }; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + /* Configure the external interrupt "WAKEUP", "KEY" and "TAMPER" buttons */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); + STM_EVAL_PBInit(BUTTON_TAMPER , BUTTON_MODE_GPIO); + STM_EVAL_PBInit(BUTTON_WAKEUP , BUTTON_MODE_GPIO); + + /* Initialize the LCD */ + STM322xG_LCD_Init(); + + /* Configure the LCD Log Module */ + LCD_LOG_Init(); + LCD_LOG_SetHeader("RTC Backup Domain Example"); + LCD_LOG_SetFooter (" Copyright (c) STMicroelectronics" ); + + /* Display the default RCC BDCR and RTC TAFCR Registers */ + LCD_UsrLog ("Entry Point \n"); + LCD_UsrLog ("RCC BDCR = 0x%x\n", RCC->BDCR); + LCD_UsrLog ("RTC TAFCR = 0x%x\n", RTC->TAFCR); + + /* Enable the PWR APB1 Clock Interface */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Allow access to BKP Domain */ + PWR_BackupAccessCmd(ENABLE); + + /* Configure one bit for preemption priority */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + + /* Enable the RTC Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = RTC_WKUP_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* EXTI configuration *******************************************************/ + EXTI_ClearITPendingBit(EXTI_Line22); + EXTI_InitStructure.EXTI_Line = EXTI_Line22; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + if(RTC_ReadBackupRegister(RTC_BKP_DR0) != FIRST_DATA) + { + LCD_UsrLog ("RTC Config PLZ Wait. \n"); + + /* RTC Configuration */ + RTC_Config(); + + /* Adjust Current Time */ + Time_Adjust(); + + /* Adjust Current Date */ + Date_Adjust(); + } + else + { + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); + RTC_ClearITPendingBit(RTC_IT_WUT); + EXTI_ClearITPendingBit(EXTI_Line22); + +/* Backup SRAM ***************************************************************/ + /* Enable BKPSRAM Clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_BKPSRAM, ENABLE); + + /* Check the written Data */ + for (i = 0x0; i < 0x1000; i += 4) + { + if ((*(__IO uint32_t *) (BKPSRAM_BASE + i)) != i) + { + errorindex++; + } + } + if(errorindex) + { + LCD_ErrLog ("BKP SRAM Number of errors = %d\n", errorindex); + } + else + { + LCD_UsrLog ("BKP SRAM Content OK \n"); + } +/* RTC Backup Data Registers **************************************************/ + /* Check if RTC Backup DRx registers data are correct */ + if (CheckBackupReg(FIRST_DATA) == 0x00) + { + /* OK, RTC Backup DRx registers data are correct */ + LCD_UsrLog ("OK, RTC Backup DRx registers data are correct. \n"); + } + else + { + /* Error, RTC Backup DRx registers data are not correct */ + LCD_ErrLog ("RTC Backup DRx registers data are not correct\n"); + } + } + + /* Infinite loop */ + Calendar_Show(); + + while (1) + { + } +} + +/** + * @brief Configure the RTC peripheral by selecting the clock source. + * @param None + * @retval None + */ +void RTC_Config(void) +{ + /* Enable the PWR clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); + +#if defined (RTC_CLOCK_SOURCE_LSI) /* LSI used as RTC source clock*/ +/* The RTC Clock may varies due to LSI frequency dispersion. */ + /* Enable the LSI OSC */ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; + +#elif defined (RTC_CLOCK_SOURCE_LSE) /* LSE used as RTC source clock */ + /* Enable the LSE OSC */ + RCC_LSEConfig(RCC_LSE_ON); + + /* Wait till LSE is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; + +#else + #error Please select the RTC Clock source inside the main.c file +#endif /* RTC_CLOCK_SOURCE_LSI */ + + /* Enable the RTC Clock */ + RCC_RTCCLKCmd(ENABLE); + + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); + + /* Write to the first RTC Backup Data Register */ + RTC_WriteBackupRegister(RTC_BKP_DR0, FIRST_DATA); + + /* Display the new RCC BDCR and RTC TAFCR Registers */ + LCD_UsrLog ("RTC Reconfig \n"); + LCD_UsrLog ("RCC BDCR = 0x%x\n", RCC->BDCR); + LCD_UsrLog ("RTC TAFCR = 0x%x\n", RTC->TAFCR); + + /* Set the Time */ + RTC_TimeStructure.RTC_Hours = 0x08; + RTC_TimeStructure.RTC_Minutes = 0x00; + RTC_TimeStructure.RTC_Seconds = 0x00; + + /* Set the Date */ + RTC_DateStructure.RTC_Month = RTC_Month_March; + RTC_DateStructure.RTC_Date = 0x18; + RTC_DateStructure.RTC_Year = 0x11; + RTC_DateStructure.RTC_WeekDay = RTC_Weekday_Friday; + + /* Calendar Configuration */ + RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv; + RTC_InitStructure.RTC_SynchPrediv = SynchPrediv; + RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; + RTC_Init(&RTC_InitStructure); + + /* Set Current Time and Date */ + RTC_SetTime(RTC_Format_BCD, &RTC_TimeStructure); + RTC_SetDate(RTC_Format_BCD, &RTC_DateStructure); + + /* Configure the RTC Wakeup Clock source and Counter (Wakeup event each 1 second) */ + RTC_WakeUpClockConfig(RTC_WakeUpClock_RTCCLK_Div16); + RTC_SetWakeUpCounter(0x7FF); + + /* Enable the Wakeup Interrupt */ + RTC_ITConfig(RTC_IT_WUT, ENABLE); + + /* Enable Wakeup Counter */ + RTC_WakeUpCmd(ENABLE); + +/* Backup SRAM ***************************************************************/ + /* Enable BKPRAM Clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_BKPSRAM, ENABLE); + + /* Write to Backup SRAM with 32-Bit Data */ + for (i = 0x0; i < 0x1000; i += 4) + { + *(__IO uint32_t *) (BKPSRAM_BASE + i) = i; + } + /* Check the written Data */ + for (i = 0x0; i < 0x1000; i += 4) + { + if ((*(__IO uint32_t *) (BKPSRAM_BASE + i)) != i) + { + errorindex++; + } + } + + if(errorindex) + { + LCD_ErrLog ("BKP SRAM Number of errors = %d\n", errorindex); + } + else + { + LCD_UsrLog ("BKP SRAM write OK \n"); + } + + /* Enable the Backup SRAM low power Regulator to retain it's content in VBAT mode */ + PWR_BackupRegulatorCmd(ENABLE); + + /* Wait until the Backup SRAM low power Regulator is ready */ + while(PWR_GetFlagStatus(PWR_FLAG_BRR) == RESET) + { + } + +/* RTC Backup Data Registers **************************************************/ + /* Write to RTC Backup Data Registers */ + WriteToBackupReg(FIRST_DATA); +} + +/** + * @brief Reads digit entered by user, using menu navigation keys. + * @param None + * @retval Digit value + */ +uint8_t ReadDigit(uint16_t LineBegin, uint16_t ColBegin, uint8_t CountBegin, uint8_t ValueMax, uint8_t ValueMin) +{ + uint8_t tmpValue = 0; + Button_TypeDef keystate = (Button_TypeDef)10; + + /* Set the Back Color */ + LCD_SetBackColor(LCD_COLOR_RED); + + /* Set the Text Color */ + LCD_SetTextColor(LCD_COLOR_WHITE); + + /* Initialize tmpValue */ + tmpValue = CountBegin; + + /* Display */ + LCD_DisplayChar(LineBegin, ColBegin, (tmpValue + 0x30)); + + /* Endless loop */ + while(1) + { + /* Get the Joytick State */ + keystate = ReadKey(); + + /* If "BUTTON_TAMPER" push button is pressed */ + if(keystate == BUTTON_TAMPER) + { + /* Increase the value of the digit */ + if(tmpValue == ValueMax) + { + tmpValue = (ValueMin - 1); + } + /* Display new value */ + LCD_DisplayChar(LineBegin, ColBegin,((++tmpValue) + 0x30)); + } + /* If "BUTTON_WAKEUP" push button is pressed */ + if(keystate == BUTTON_WAKEUP) + { + /* Decrease the value of the digit */ + if(tmpValue == ValueMin) + { + tmpValue = (ValueMax + 1); + } + /* Display new value */ + LCD_DisplayChar(LineBegin, ColBegin,((--tmpValue) + 0x30)); + } + /* If "BUTTON_KEY" push button is pressed */ + if(keystate == BUTTON_KEY) + { + /* Set the Back Color */ + LCD_SetBackColor(LCD_COLOR_WHITE); + /* Set the Text Color */ + LCD_SetTextColor(LCD_COLOR_RED); + /* Display new value */ + LCD_DisplayChar(LineBegin, ColBegin, (tmpValue + 0x30)); + /* Return the digit value and exit */ + return tmpValue; + } + } +} + +/** + * @brief Returns the time entered by user, using menu navigation keys. + * @param None + * @retval Current time RTC counter value + */ +void Time_Regulate(void) +{ + uint8_t Tmp_HH = 0, Tmp_MM = 0, Tmp_SS = 0; + + LCD_DisplayStringLine(LCD_LINE_12, "Set time: hh:mm:ss"); + + /* Read time hours */ + Tmp_HH = ReadDigit(LCD_LINE_13, 244, (RTC_TimeStructure.RTC_Hours / 10), 0x2, 0x0); + + if(Tmp_HH == 2) + { + if((RTC_TimeStructure.RTC_Hours % 10) > 3) + { + RTC_TimeStructure.RTC_Hours = 0; + } + Tmp_HH = Tmp_HH * 10 + ReadDigit(LCD_LINE_13, 228, (RTC_TimeStructure.RTC_Hours % 10), 0x3, 0x0); + } + else + { + Tmp_HH = Tmp_HH * 10 + ReadDigit(LCD_LINE_13, 228, (RTC_TimeStructure.RTC_Hours % 10), 0x9, 0x0); + } + /* Read time minutes */ + Tmp_MM = ReadDigit(LCD_LINE_13, 196, (RTC_TimeStructure.RTC_Minutes / 10), 5, 0x0); + Tmp_MM = Tmp_MM * 10 + ReadDigit(LCD_LINE_13, 182, (RTC_TimeStructure.RTC_Minutes % 10), 0x9, 0x0); + + /* Read time seconds */ + Tmp_SS = ReadDigit(LCD_LINE_13, 150, (RTC_TimeStructure.RTC_Seconds / 10), 5, 0x0); + Tmp_SS = Tmp_SS * 10 + ReadDigit(LCD_LINE_13, 134, (RTC_TimeStructure.RTC_Seconds % 10), 0x9, 0x0); + + RTC_TimeStructure.RTC_Hours = Tmp_HH; + RTC_TimeStructure.RTC_Minutes = Tmp_MM; + RTC_TimeStructure.RTC_Seconds = Tmp_SS; + RTC_SetTime(RTC_Format_BIN, &RTC_TimeStructure); + + /* Set the Back Color */ + LCD_SetBackColor(LCD_COLOR_BLACK); + + /* Set the Text Color */ + LCD_SetTextColor(LCD_COLOR_WHITE); + + /* Clear Line12 */ + LCD_ClearLine(LCD_LINE_12); +} + +/** + * @brief Returns the time entered by user, using demo board keys. + * @param None + * @retval None + */ +void Time_Adjust(void) +{ + /* Display the current time */ + Time_Display(); + + /* Change the current time */ + Time_Regulate(); +} + +/** + * @brief Displays the current time. + * @param None + * @retval None + */ +void Time_Display(void) +{ + /* Clear Line13 */ + LCD_ClearLine(LCD_LINE_13); + + /* Display time separators ":" on Line4 */ + LCD_DisplayChar(LCD_LINE_13, 212, ':'); + LCD_DisplayChar(LCD_LINE_13, 166, ':'); + + /* Get the current Time */ + RTC_GetTime(RTC_Format_BIN, &RTC_TimeStructure); + + /* Display time hours */ + LCD_DisplayChar(LCD_LINE_13, 244,((RTC_TimeStructure.RTC_Hours / 10) + 0x30)); + LCD_DisplayChar(LCD_LINE_13, 228,((RTC_TimeStructure.RTC_Hours % 10) + 0x30)); + + /* Display time minutes */ + LCD_DisplayChar(LCD_LINE_13, 196,((RTC_TimeStructure.RTC_Minutes /10) + 0x30)); + LCD_DisplayChar(LCD_LINE_13, 182,((RTC_TimeStructure.RTC_Minutes % 10) + 0x30)); + + /* Display time seconds */ + LCD_DisplayChar(LCD_LINE_13, 150,((RTC_TimeStructure.RTC_Seconds / 10) + 0x30)); + LCD_DisplayChar(LCD_LINE_13, 134,((RTC_TimeStructure.RTC_Seconds % 10) + 0x30)); +} + +/** + * @brief Returns the time entered by user, using menu navigation keys. + * @param None + * @retval Current date value + */ +void Date_Regulate(void) +{ + uint8_t weekday = 0, date = 0, month = 0, year = 0; + + LCD_DisplayStringLine(LCD_LINE_15, "Set date: Weekday / Date / Month / Year"); + + /* Read Date Weekday */ + weekday = ReadDigit(LCD_LINE_16, 276, (RTC_DateStructure.RTC_WeekDay / 10), 0x7, 0x1); + + /* Read Date Day */ + date = ReadDigit(LCD_LINE_16, 244, (RTC_DateStructure.RTC_Date / 10), 3, 0x0); + + if(date == 3) + { + if((RTC_DateStructure.RTC_Date % 10) > 1) + { + RTC_DateStructure.RTC_Date = 0; + } + date = date * 10 + ReadDigit(LCD_LINE_16, 228, (RTC_DateStructure.RTC_Date % 10), 0x1, 0x0); + } + else + { + date = date * 10 + ReadDigit(LCD_LINE_16, 228, (RTC_DateStructure.RTC_Date % 10), 0x9, 0x0); + } + + /* Read Date Month */ + month = ReadDigit(LCD_LINE_16, 196, (RTC_DateStructure.RTC_Month / 10), 1, 0x0); + + if(month == 1) + { + if((RTC_DateStructure.RTC_Month % 10) > 2) + { + RTC_DateStructure.RTC_Month = 0; + } + month = month * 10 + ReadDigit(LCD_LINE_16, 182, (RTC_DateStructure.RTC_Month % 10), 0x2, 0x0); + } + else + { + month = month * 10 + ReadDigit(LCD_LINE_16, 182, (RTC_DateStructure.RTC_Month % 10), 0x9, 0x0); + } + + /* Read Date Year */ + LCD_DisplayChar(LCD_LINE_16, 150, '2'); + LCD_DisplayChar(LCD_LINE_16, 134, '0'); + year = ReadDigit(LCD_LINE_16, 118, (RTC_DateStructure.RTC_Year / 10), 0x9, 0x0); + year = year * 10 + ReadDigit(LCD_LINE_16, 102, (RTC_DateStructure.RTC_Year % 10), 0x9, 0x0); + + RTC_DateStructure.RTC_WeekDay = weekday; + RTC_DateStructure.RTC_Date = date; + RTC_DateStructure.RTC_Month = month; + RTC_DateStructure.RTC_Year = year; + RTC_SetDate(RTC_Format_BIN, &RTC_DateStructure); + + /* Set the Back Color */ + LCD_SetBackColor(LCD_COLOR_BLACK); + + /* Set the Text Color */ + LCD_SetTextColor(LCD_COLOR_WHITE); + + /* Clear Line15 */ + LCD_ClearLine(LCD_LINE_15); +} + +/** + * @brief Returns the date entered by user, using demoboard keys. + * @param None + * @retval None + */ +void Date_Adjust(void) +{ + /* Display the current Date */ + Date_Display(); + + /* Change the current Date */ + Date_Regulate(); +} + +/** + * @brief Displays the current date. + * @param None + * @retval None + */ +void Date_Display(void) +{ + /* Clear Line16 */ + LCD_ClearLine(LCD_LINE_16); + + /* Display time separators "/" on Line14 */ + LCD_DisplayChar(LCD_LINE_16, 260, '/'); + LCD_DisplayChar(LCD_LINE_16, 212, '/'); + LCD_DisplayChar(LCD_LINE_16, 166, '/'); + + /* Get the current Date */ + RTC_GetDate(RTC_Format_BIN, &RTC_DateStructure); + + /* Display Date WeekDay */ + LCD_DisplayChar(LCD_LINE_16, 276,((RTC_DateStructure.RTC_WeekDay) + 0x30)); + + /* Display Date Day */ + LCD_DisplayChar(LCD_LINE_16, 244,((RTC_DateStructure.RTC_Date /10) + 0x30)); + LCD_DisplayChar(LCD_LINE_16, 228,((RTC_DateStructure.RTC_Date % 10) + 0x30)); + + /* Display Date Month */ + LCD_DisplayChar(LCD_LINE_16, 196,((RTC_DateStructure.RTC_Month / 10) + 0x30)); + LCD_DisplayChar(LCD_LINE_16, 182,((RTC_DateStructure.RTC_Month % 10) + 0x30)); + + /* Display Date Year */ + LCD_DisplayChar(LCD_LINE_16, 150, '2'); + LCD_DisplayChar(LCD_LINE_16, 134, '0'); + LCD_DisplayChar(LCD_LINE_16, 118,((RTC_DateStructure.RTC_Year / 10) + 0x30)); + LCD_DisplayChar(LCD_LINE_16, 102,((RTC_DateStructure.RTC_Year % 10) + 0x30)); +} + +/** + * @brief Shows the current time and date on LCD. + * @param None + * @retval None + */ +void Calendar_Show(void) +{ + while(1) + { + /* If 1s has elapsed */ + if (TimeDisplay == 1) + { + /* Display current time */ + Time_Display(); + + /* Display current date */ + Date_Display(); + + TimeDisplay = 0; + } + } +} + +/** + * @brief Writes data to all Backup data registers. + * @param FirstBackupData: data to write to first backup data register. + * @retval None + */ +void WriteToBackupReg(uint16_t FirstBackupData) +{ + uint32_t index = 0; + + for (index = 0; index < RTC_BKP_DR_NUMBER; index++) + { + RTC_WriteBackupRegister(BKPDataReg[index], FirstBackupData + (index * 0x5A)); + } + +} + +/** + * @brief Checks if the Backup data registers values are correct or not. + * @param FirstBackupData: data to read from first backup data register + * @retval - 0: All Backup DRx registers data are correct + * - Value different from 0: Number of the first Backup register which + * value is not correct + */ +uint32_t CheckBackupReg(uint16_t FirstBackupData) +{ + uint32_t index = 0; + + for (index = 0; index < RTC_BKP_DR_NUMBER; index++) + { + if (RTC_ReadBackupRegister(BKPDataReg[index]) != (FirstBackupData + (index * 0x5A))) + { + return (index + 1); + } + } + + return 0; +} + +/** + * @brief Reads key from demoboard. + * @param None + * @retval Return KEY, TAMPER, WAKEUP. + */ +Button_TypeDef ReadKey(void) +{ + /* "BUTTON_TAMPER" key is pressed */ + if (!STM_EVAL_PBGetState(BUTTON_TAMPER)) + { + while (STM_EVAL_PBGetState(BUTTON_TAMPER) == Bit_RESET); + return BUTTON_TAMPER; + } + /* "BUTTON_KEY" key is pressed */ + if (!STM_EVAL_PBGetState(BUTTON_KEY)) + { + while (STM_EVAL_PBGetState(BUTTON_KEY) == Bit_RESET); + return BUTTON_KEY; + } + /* "BUTTON_WAKEUP" key is pressed */ + if (STM_EVAL_PBGetState(BUTTON_WAKEUP)) + { + while (STM_EVAL_PBGetState(BUTTON_WAKEUP) != Bit_RESET); + return BUTTON_WAKEUP; + } + /* No key is pressed */ + else + { + return (Button_TypeDef)10; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/main.h new file mode 100644 index 000000000..3c46ee6f3 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/main.h @@ -0,0 +1,56 @@ +/** + ****************************************************************************** + * @file RTC/BKP_Domain/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "lcd_log.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RTC_Config(void); +uint8_t ReadDigit(uint16_t LineBegin, uint16_t ColBegin, uint8_t CountBegin, uint8_t ValueMax, uint8_t ValueMin); +void Time_Regulate(void); +void Time_Adjust(void); +void Time_Display(void); +void Date_Regulate(void); +void Date_Adjust(void); +void Date_Display(void); +void Calendar_Show(void); +void WriteToBackupReg(uint16_t FirstBackupData); +uint32_t CheckBackupReg(uint16_t FirstBackupData); +Button_TypeDef ReadKey(void); + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/readme.txt new file mode 100644 index 000000000..64166c133 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/readme.txt @@ -0,0 +1,142 @@ +/** + @page BKP_Domain RTC Backup domain example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file RTC/BKP_Domain/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the RTC Backup domain example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example demonstrates and explains how to use the peripherals available on +Backup Domain. These peripherals are: the RCC BDCR register containing the LSE Osc +configuration and the RTC Clock enable/disable bits. It embeds also the RTC +peripheral with its associated Backup Data registers. And finally the Backup SRAM (4KB) +with its low power regulator allowing to preserve its contents when the +product is powered by VBAT pin. + +As an application example, it demonstrates how to setup the RTC hardware calendar, +RTC Backup Data registers read/write and BKPSRAM read/write operations. + +One from the following clock can be used as RTC clock source (uncomment the +corresponding define in main.c): + - LSE oscillator clock usually delivered by a 32.768 kHz quartz. + - LSI oscillator clock + +The Backup (BKP) domain, still powered by VBAT when VDD is switched off, so its +content is not lost if a battery is connected to the VBAT pin. +A key value is written in backup data register 0 to indicate if the Backup Domain +is already configured. + +The program behaves as follows: + +1. After startup the program checks the backup data register 0 value: + - BKP_DR0 value not correct: (RTC_BKP_DR0 value is not correct or has not yet + been programmed when the program is executed for the first time) the RTC is + configured and the user is asked to set the time and date (entered on + TFT-LCD) and the RTC Backup Data registers and BKPSRAM are written. + + - BKP_DR0 value correct: this means that the RTC is configured and the time + and date are displayed on LCD. The content of RTC Backup Data registers + and BKPSRAM is checked and the result is displayed on color LCD. + +2. When an External Reset occurs the BKP domain is not reset. + +3. When power on reset occurs: + - If a battery is connected to the VBAT pin: the BKP domain is not reset and + the RTC configuration is not lost. + + - If no battery is connected to the VBAT pin: the BKP domain is reset and the + RTC configuration is lost. + +4. When an RTC Wakeup event occurs the RTC Wakeup interrupt is generated and the + current Time/Date is refreshed on LCD. + +The example uses TFT-LCD and push-button to configure the RTC clock and display +the current calendar: + + - When the Backup domain is not yet configured: + - The RCC BDCR Register value is displayed on LCD before and after the Backup + domain configuration. + - All RTC Backup Data Registers are written and checked. + - All BKP SRAM content is written and checked. + - User asked for RTC Calendar Configuration using the Tamper/Wakeup/Key buttons: + - Use WAKEUP button to decrement the current value. + - Use TAMPER button to increment the current value. + - Use KEY button to validate the current value. + - Once configured, the RTC Calendar is displayed on the LCD each second using + the RTC Wakeup Interrupt. + + - When the Backup domain is already configured: + - No need to reconfigure the RTC Clock and Calendar. + - All RTC Backup Data Registers are checked. + - All BKP SRAM content is checked. If the Low power regulator is enabled, the + BKPSRAM content is not lost. + - The RTC Calendar is displayed on the LCD each second using + the RTC Wakeup Interrupt. + + +@par Directory contents + + - RTC/BKP_Domain/system_stm32f2xx.c STM32F2xx system clock configuration file + - RTC/BKP_Domain/stm32f2xx_conf.h Library Configuration file + - RTC/BKP_Domain/stm32f2xx_it.c Interrupt handlers + - RTC/BKP_Domain/stm32f2xx_it.h Header for stm32f2xx_it.c + - RTC/BKP_Domain/main.c Main program + - RTC/BKP_Domain/main.h Main header file + - RTC/BKP_Domain/lcd_log_conf.h lcd_log configuration file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use the TAMPER push button connected to PC.13 pin (EXTI Line13). + - Use the KEY push button connected to PG.15 pin (EXTI Line15). + - Use the WAKEUP push button connected to PA.00 pin (EXTI Line0). + - All messages are displayed on the TFT-LCD. + - Make sure that jumper JP19 is in position 2-3 to connect the 3V battery to VBAT pin + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Add the file "lcd_log.c" (under Utilities\STM32_EVAL\Common) to the project source list + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/stm32f2xx_conf.h new file mode 100644 index 000000000..f894acbaf --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file RTC/BKP_Domain/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/stm32f2xx_it.c new file mode 100644 index 000000000..3eb4954fe --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/stm32f2xx_it.c @@ -0,0 +1,196 @@ +/** + ****************************************************************************** + * @file RTC/BKP_Domain/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup BKP_Domain + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern __IO uint32_t TimeDisplay; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles RTC Wakeup Timer Handler. + * @param None + * @retval None + */ +void RTC_WKUP_IRQHandler(void) +{ + if(RTC_GetITStatus(RTC_IT_WUT) != RESET) + { + TimeDisplay = 1; + RTC_ClearITPendingBit(RTC_IT_WUT); + EXTI_ClearITPendingBit(EXTI_Line22); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/stm32f2xx_it.h new file mode 100644 index 000000000..3f8ba56af --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/stm32f2xx_it.h @@ -0,0 +1,61 @@ +/** + ****************************************************************************** + * @file RTC/BKP_Domain/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void RTC_WKUP_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/BKP_Domain/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/main.c new file mode 100644 index 000000000..0b574363a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/main.c @@ -0,0 +1,441 @@ +/** + ****************************************************************************** + * @file RTC/HW_Calendar/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "main.h" +#include + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup HW_Calendar + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Uncomment the corresponding line to select the RTC Clock source */ +#define RTC_CLOCK_SOURCE_LSE /* LSE used as RTC source clock */ +/* #define RTC_CLOCK_SOURCE_LSI */ /* LSI used as RTC source clock. The RTC Clock + may varies due to LSI frequency dispersion. */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +USART_InitTypeDef USART_InitStructure; +RTC_TimeTypeDef RTC_TimeStructure; +RTC_InitTypeDef RTC_InitStructure; +RTC_AlarmTypeDef RTC_AlarmStructure; + +__IO uint32_t AsynchPrediv = 0, SynchPrediv = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + /* USARTx configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit(COM1, &USART_InitStructure); + + /* Output a message on Hyperterminal using printf function */ + printf("\n\r *********************** RTC Hardware Calendar Example ***********************\n\r"); + + if (RTC_ReadBackupRegister(RTC_BKP_DR0) != 0x32F2) + { + /* RTC configuration */ + RTC_Config(); + + /* Configure the RTC data register and RTC prescaler */ + RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv; + RTC_InitStructure.RTC_SynchPrediv = SynchPrediv; + RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; + + /* Check on RTC init */ + if (RTC_Init(&RTC_InitStructure) == ERROR) + { + printf("\n\r /!\\***** RTC Prescaler Config failed ********/!\\ \n\r"); + } + + /* Configure the time register */ + RTC_TimeRegulate(); + } + else + { + /* Check if the Power On Reset flag is set */ + if (RCC_GetFlagStatus(RCC_FLAG_PORRST) != RESET) + { + printf("\r\n Power On Reset occurred....\n\r"); + } + /* Check if the Pin Reset flag is set */ + else if (RCC_GetFlagStatus(RCC_FLAG_PINRST) != RESET) + { + printf("\r\n External Reset occurred....\n\r"); + } + + printf("\n\r No need to configure RTC....\n\r"); + + /* Enable the PWR clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); + + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); + + /* Clear the RTC Alarm Flag */ + RTC_ClearFlag(RTC_FLAG_ALRAF); + + /* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */ + EXTI_ClearITPendingBit(EXTI_Line17); + + /* Display the RTC Time and Alarm */ + RTC_TimeShow(); + RTC_AlarmShow(); + } + + /* Configure the external interrupt "WAKEUP", "KEY" and "TAMPER" buttons */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI); + STM_EVAL_PBInit(BUTTON_TAMPER , BUTTON_MODE_EXTI); + STM_EVAL_PBInit(BUTTON_WAKEUP , BUTTON_MODE_EXTI); + + /* Configure LEDx */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + + /* Turn LED1 ON */ + STM_EVAL_LEDOn(LED2); + + /* RTC Alarm A Interrupt Configuration */ + /* EXTI configuration *********************************************************/ + EXTI_ClearITPendingBit(EXTI_Line17); + EXTI_InitStructure.EXTI_Line = EXTI_Line17; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Enable the RTC Alarm Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = RTC_Alarm_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + while (1) + { + } +} + +/** + * @brief Configure the RTC peripheral by selecting the clock source. + * @param None + * @retval None + */ +void RTC_Config(void) +{ + /* Enable the PWR clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); + +#if defined (RTC_CLOCK_SOURCE_LSI) /* LSI used as RTC source clock*/ +/* The RTC Clock may varies due to LSI frequency dispersion. */ + /* Enable the LSI OSC */ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; + +#elif defined (RTC_CLOCK_SOURCE_LSE) /* LSE used as RTC source clock */ + /* Enable the LSE OSC */ + RCC_LSEConfig(RCC_LSE_ON); + + /* Wait till LSE is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; + +#else + #error Please select the RTC Clock source inside the main.c file +#endif /* RTC_CLOCK_SOURCE_LSI */ + + /* Enable the RTC Clock */ + RCC_RTCCLKCmd(ENABLE); + + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); +} + +/** + * @brief Returns the time entered by user, using Hyperterminal. + * @param None + * @retval None + */ +void RTC_TimeRegulate(void) +{ + uint32_t tmp_hh = 0xFF, tmp_mm = 0xFF, tmp_ss = 0xFF; + + printf("\n\r==============Time Settings=====================================\n\r"); + RTC_TimeStructure.RTC_H12 = RTC_H12_AM; + printf(" Please Set Hours:\n\r"); + while (tmp_hh == 0xFF) + { + tmp_hh = USART_Scanf(23); + RTC_TimeStructure.RTC_Hours = tmp_hh; + } + printf(" %0.2d\n\r", tmp_hh); + + printf(" Please Set Minutes:\n\r"); + while (tmp_mm == 0xFF) + { + tmp_mm = USART_Scanf(59); + RTC_TimeStructure.RTC_Minutes = tmp_mm; + } + printf(" %0.2d\n\r", tmp_mm); + + printf(" Please Set Seconds:\n\r"); + while (tmp_ss == 0xFF) + { + tmp_ss = USART_Scanf(59); + RTC_TimeStructure.RTC_Seconds = tmp_ss; + } + printf(" %0.2d\n\r", tmp_ss); + + /* Configure the RTC time register */ + if(RTC_SetTime(RTC_Format_BIN, &RTC_TimeStructure) == ERROR) + { + printf("\n\r>> !! RTC Set Time failed. !! <<\n\r"); + } + else + { + printf("\n\r>> !! RTC Set Time success. !! <<\n\r"); + RTC_TimeShow(); + /* Indicator for the RTC configuration */ + RTC_WriteBackupRegister(RTC_BKP_DR0, 0x32F2); + } + + tmp_hh = 0xFF; + tmp_mm = 0xFF; + tmp_ss = 0xFF; + + /* Disable the Alarm A */ + RTC_AlarmCmd(RTC_Alarm_A, DISABLE); + + printf("\n\r==============Alarm A Settings=====================================\n\r"); + RTC_AlarmStructure.RTC_AlarmTime.RTC_H12 = RTC_H12_AM; + printf(" Please Set Alarm Hours:\n\r"); + while (tmp_hh == 0xFF) + { + tmp_hh = USART_Scanf(23); + RTC_AlarmStructure.RTC_AlarmTime.RTC_Hours = tmp_hh; + } + printf(" %0.2d\n\r", tmp_hh); + + printf(" Please Set Alarm Minutes:\n\r"); + while (tmp_mm == 0xFF) + { + tmp_mm = USART_Scanf(59); + RTC_AlarmStructure.RTC_AlarmTime.RTC_Minutes = tmp_mm; + } + printf(" %0.2d\n\r", tmp_mm); + + printf(" Please Set Alarm Seconds:\n\r"); + while (tmp_ss == 0xFF) + { + tmp_ss = USART_Scanf(59); + RTC_AlarmStructure.RTC_AlarmTime.RTC_Seconds = tmp_ss; + } + printf(" %0.2d", tmp_ss); + + /* Set the Alarm A */ + RTC_AlarmStructure.RTC_AlarmDateWeekDay = 0x31; + RTC_AlarmStructure.RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; + RTC_AlarmStructure.RTC_AlarmMask = RTC_AlarmMask_DateWeekDay; + + /* Configure the RTC Alarm A register */ + RTC_SetAlarm(RTC_Format_BIN, RTC_Alarm_A, &RTC_AlarmStructure); + printf("\n\r>> !! RTC Set Alarm success. !! <<\n\r"); + RTC_AlarmShow(); + + /* Enable the RTC Alarm A Interrupt */ + RTC_ITConfig(RTC_IT_ALRA, ENABLE); + + /* Enable the alarm A */ + RTC_AlarmCmd(RTC_Alarm_A, ENABLE); +} + +/** + * @brief Display the current time on the Hyperterminal. + * @param None + * @retval None + */ +void RTC_TimeShow(void) +{ + /* Get the current Time */ + RTC_GetTime(RTC_Format_BIN, &RTC_TimeStructure); + printf("\n\r The current time is : %0.2d:%0.2d:%0.2d \n\r", RTC_TimeStructure.RTC_Hours, RTC_TimeStructure.RTC_Minutes, RTC_TimeStructure.RTC_Seconds); +} + +/** + * @brief Display the current time on the Hyperterminal. + * @param None + * @retval None + */ +void RTC_AlarmShow(void) +{ + /* Get the current Alarm */ + RTC_GetAlarm(RTC_Format_BIN, RTC_Alarm_A, &RTC_AlarmStructure); + printf("\n\r The current alarm is : %0.2d:%0.2d:%0.2d \n\r", RTC_AlarmStructure.RTC_AlarmTime.RTC_Hours, RTC_AlarmStructure.RTC_AlarmTime.RTC_Minutes, RTC_AlarmStructure.RTC_AlarmTime.RTC_Seconds); +} + + +/** + * @brief Gets numeric values from the hyperterminal. + * @param None + * @retval None + */ +uint8_t USART_Scanf(uint32_t value) +{ + uint32_t index = 0; + uint32_t tmp[2] = {0, 0}; + + while (index < 2) + { + /* Loop until RXNE = 1 */ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_RXNE) == RESET) + {} + tmp[index++] = (USART_ReceiveData(EVAL_COM1)); + if ((tmp[index - 1] < 0x30) || (tmp[index - 1] > 0x39)) + { + printf("\n\r Please enter valid number between 0 and 9 \n\r"); + index--; + } + } + /* Calculate the Corresponding value */ + index = (tmp[1] - 0x30) + ((tmp[0] - 0x30) * 10); + /* Checks */ + if (index > value) + { + printf("\n\r Please enter valid number between 0 and %d \n\r", value); + return 0xFF; + } + return index; +} + +/** + * @brief Retargets the C library printf function to the USART. + * @param None + * @retval None + */ +PUTCHAR_PROTOTYPE +{ + /* Place your implementation of fputc here */ + /* e.g. write a character to the USART */ + USART_SendData(EVAL_COM1, (uint8_t) ch); + + /* Loop until the end of transmission */ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) + {} + + return ch; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/main.h new file mode 100644 index 000000000..a6a40949b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/main.h @@ -0,0 +1,56 @@ +/** + ****************************************************************************** + * @file RTC/HW_Calendar/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RTC_Config(void); +void RTC_TimeRegulate(void); +void RTC_TimeShow(void); +void RTC_AlarmShow(void); +uint8_t USART_Scanf(uint32_t value); + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/readme.txt new file mode 100644 index 000000000..38f1bdf3f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/readme.txt @@ -0,0 +1,130 @@ +/** + @page HW_Calendar RTC Hardware Calendar example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file RTC/HW_Calendar/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the RTC Hardware Calendar example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example demonstrates and explains how to use the RTC peripheral. +As an application example, it demonstrates how to setup the RTC peripheral, in +terms of prescaler and interrupts, to be used to keep time and to generate +alarm interrupt. + +One from the following clock can be used as RTC clock source (uncomment the +corresponding define in main.c): + - LSE oscillator clock usually delivered by a 32.768 kHz quartz. + - LSI oscillator clock + +The RTC is in the backup (BKP) domain, still powered by VBAT when VDD is switched off, +so the RTC configuration is not lost if a battery is connected to the VBAT pin. +A key value is written in backup data register 0 to indicate if the RTC is already +configured. + +The program behaves as follows: + +1. After startup the program checks the backup data register 0 value: + - BKP_DR0 value not correct: (RTC_BKP_DR0 value is not correct or has not yet + been programmed when the program is executed for the first time) the RTC is + configured and the user is asked to set the time and alarm (entered on + HyperTerminal). + + - BKP_DR0 value correct: this means that the RTC is configured and the time + and Alarm A are displayed on HyperTerminal. + +2. When an External Reset occurs the BKP domain is not reset and the RTC configuration + is not lost. + +3. When power on reset occurs: + - If a battery is connected to the VBAT pin: the BKP domain is not reset and + the RTC configuration is not lost. + + - If no battery is connected to the VBAT pin: the BKP domain is reset and the + RTC configuration is lost. + +4. When an RTC Alarm A event occurs the RTC Alarm interrupt is generated and the + LED1 is toggled. + +The example uses HyperTerminal to configure the RTC clock and display the current time: + - When Tamper button is pressed, a menu is displayed to configure the RTC Time + and Alarm A registers. + - When Key button is pressed, the current time is displayed. + - When WakeUp button is pressed, the current alarm A is displayed. + +LED2 is truned ON when the RTC configuration is done correctly. + + +@par Directory contents + + - RTC/HW_Calendar/system_stm32f2xx.c STM32F2xx system clock configuration file + - RTC/HW_Calendar/stm32f2xx_conf.h Library Configuration file + - RTC/HW_Calendar/stm32f2xx_it.c Interrupt handlers + - RTC/HW_Calendar/stm32f2xx_it.h Header for stm32f2xx_it.c + - RTC/HW_Calendar/main.c Main program + - RTC/HW_Calendar/main.h Main header file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1 led connected respectively to PG.06 pins. + - Use the TAMPER push button connected to PC.13 pin (EXTI Line13). + - Use the KEY push button connected to PG.15 pin (EXTI Line15). + - Use the WAKEUP push button connected to PA.00 pin (EXTI Line0). + - Make sure that jumper JP19 is in position 1-2 to connect the 3V battery to VBAT pin + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port if you want to display data on the HyperTerminal. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/stm32f2xx_conf.h new file mode 100644 index 000000000..3f3f197ea --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file RTC/HW_Calendar/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/stm32f2xx_it.c new file mode 100644 index 000000000..41fc14f15 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/stm32f2xx_it.c @@ -0,0 +1,237 @@ +/** + ****************************************************************************** + * @file RTC/HW_Calendar/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup HW_Calendar + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles External line 0 interrupt request. + * @param None + * @retval None + */ +void EXTI0_IRQHandler(void) +{ + if(EXTI_GetITStatus(WAKEUP_BUTTON_EXTI_LINE) != RESET) + { + /* Display the current alarm on the Hyperterminal */ + RTC_AlarmShow(); + + /* Clear the Wakeup Button EXTI line pending bit */ + EXTI_ClearITPendingBit(WAKEUP_BUTTON_EXTI_LINE); + } +} + +/** + * @brief This function handles External lines 15 to 10 interrupt request. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET) + { + /* Display the current time on the Hyperterminal */ + RTC_TimeShow(); + + /* Clear the Key Button EXTI line pending bit */ + EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); + } + + if(EXTI_GetITStatus(TAMPER_BUTTON_EXTI_LINE) != RESET) + { + /* Set the new RTC configuration */ + RTC_TimeRegulate(); + + /* Clear the Tamper Button EXTI line pending bit */ + EXTI_ClearITPendingBit(TAMPER_BUTTON_EXTI_LINE); + } +} + +/** + * @brief This function handles RTC Alarms interrupt request. + * @param None + * @retval None + */ +void RTC_Alarm_IRQHandler(void) +{ + if(RTC_GetITStatus(RTC_IT_ALRA) != RESET) + { + STM_EVAL_LEDToggle(LED1); + RTC_ClearITPendingBit(RTC_IT_ALRA); + EXTI_ClearITPendingBit(EXTI_Line17); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/stm32f2xx_it.h new file mode 100644 index 000000000..c96c388f5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/stm32f2xx_it.h @@ -0,0 +1,63 @@ +/** + ****************************************************************************** + * @file RTC/HW_Calendar/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void EXTI0_IRQHandler(void); +void EXTI15_10_IRQHandler(void); +void RTC_Alarm_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/HW_Calendar/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/main.c new file mode 100644 index 000000000..d1ca8bc0c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/main.c @@ -0,0 +1,276 @@ +/** + ****************************************************************************** + * @file RTC/RTC_LSI/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup RTC_LSI + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +RTC_InitTypeDef RTC_InitStructure; +__IO uint32_t LsiFreq = 0; +__IO uint32_t CaptureNumber = 0, PeriodValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +void RTC_Config(void); +uint32_t GetLSIFrequency(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs mounted on STM322xG-EVAL board --------------------------*/ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); + + /* RTC Configuration -------------------------------------------------------*/ + RTC_Config(); + + /* Wait Until KEY BUTTON is pressed */ + while(STM_EVAL_PBGetState(BUTTON_KEY) != RESET) + { + } + + /* Get the LSI frequency: TIM5 is used to measure the LSI frequency */ + LsiFreq = GetLSIFrequency(); + + /* Turn on LED2 */ + STM_EVAL_LEDOn(LED2); + + /* Calendar Configuration */ + RTC_InitStructure.RTC_AsynchPrediv = 0x7F; + RTC_InitStructure.RTC_SynchPrediv = (LsiFreq/128) - 1; + RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; + RTC_Init(&RTC_InitStructure); + + while (1) + { + } +} + +/** + * @brief Configure the RTC peripheral by selecting the clock source. + * @param None + * @retval None + */ +void RTC_Config(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + /* Enable the PWR clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); + +/* LSI used as RTC source clock */ +/* The RTC Clock may varies due to LSI frequency dispersion. */ + /* Enable the LSI OSC */ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + + /* Enable the RTC Clock */ + RCC_RTCCLKCmd(ENABLE); + + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); + + /* Calendar Configuration with LSI supposed at 32KHz */ + RTC_InitStructure.RTC_AsynchPrediv = 0x7F; + RTC_InitStructure.RTC_SynchPrediv = 0xFF; /* (32KHz / 128) - 1 = 0xFF*/ + RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; + RTC_Init(&RTC_InitStructure); + + /* EXTI configuration *******************************************************/ + EXTI_ClearITPendingBit(EXTI_Line22); + EXTI_InitStructure.EXTI_Line = EXTI_Line22; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Enable the RTC Wakeup Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = RTC_WKUP_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Configure the RTC WakeUp Clock source: CK_SPRE (1Hz) */ + RTC_WakeUpClockConfig(RTC_WakeUpClock_CK_SPRE_16bits); + RTC_SetWakeUpCounter(0x0); + + /* Enable the RTC Wakeup Interrupt */ + RTC_ITConfig(RTC_IT_WUT, ENABLE); + + /* Enable Wakeup Counter */ + RTC_WakeUpCmd(ENABLE); +} + +/** + * @brief Configures TIM5 to measure the LSI oscillator frequency. + * @param None + * @retval LSI Frequency + */ +uint32_t GetLSIFrequency(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + TIM_ICInitTypeDef TIM_ICInitStructure; + RCC_ClocksTypeDef RCC_ClockFreq; + + /* Enable the LSI oscillator ************************************************/ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + {} + + /* TIM5 configuration *******************************************************/ + /* Enable TIM5 clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE); + + /* Connect internally the TIM5_CH4 Input Capture to the LSI clock output */ + TIM_RemapConfig(TIM5, TIM5_LSI); + + /* Configure TIM5 presclaer */ + TIM_PrescalerConfig(TIM5, 0, TIM_PSCReloadMode_Immediate); + + /* TIM5 configuration: Input Capture mode --------------------- + The LSI oscillator is connected to TIM5 CH4 + The Rising edge is used as active edge, + The TIM5 CCR4 is used to compute the frequency value + ------------------------------------------------------------ */ + TIM_ICInitStructure.TIM_Channel = TIM_Channel_4; + TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV8; + TIM_ICInitStructure.TIM_ICFilter = 0; + TIM_ICInit(TIM5, &TIM_ICInitStructure); + + /* Enable TIM5 Interrupt channel */ + NVIC_InitStructure.NVIC_IRQChannel = TIM5_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Enable TIM5 counter */ + TIM_Cmd(TIM5, ENABLE); + + /* Reset the flags */ + TIM5->SR = 0; + + /* Enable the CC4 Interrupt Request */ + TIM_ITConfig(TIM5, TIM_IT_CC4, ENABLE); + + + /* Wait until the TIM5 get 2 LSI edges (refer to TIM5_IRQHandler() in + stm32f2xx_it.c file) ******************************************************/ + while(CaptureNumber != 2) + { + } + /* Deinitialize the TIM5 peripheral registers to their default reset values */ + TIM_DeInit(TIM5); + + + /* Compute the LSI frequency, depending on TIM5 input clock frequency (PCLK1)*/ + /* Get SYSCLK, HCLK and PCLKx frequency */ + RCC_GetClocksFreq(&RCC_ClockFreq); + + /* Get PCLK1 prescaler */ + if ((RCC->CFGR & RCC_CFGR_PPRE1) == 0) + { + /* PCLK1 prescaler equal to 1 => TIMCLK = PCLK1 */ + return ((RCC_ClockFreq.PCLK1_Frequency / PeriodValue) * 8); + } + else + { /* PCLK1 prescaler different from 1 => TIMCLK = 2 * PCLK1 */ + return (((2 * RCC_ClockFreq.PCLK1_Frequency) / PeriodValue) * 8) ; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/readme.txt new file mode 100644 index 000000000..1974403cb --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/readme.txt @@ -0,0 +1,97 @@ +/** + @page RTC_LSI RTC Hardware Calendar example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file RTC/RTC_LSI/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the RTC Hardware Calendar example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example demonstrates and explains how to use the LSI clock source auto +calibration to get a precise RTC clock. +As an application example, it demonstrates how to configure the TIM5 timer +internally connected to LSI clock output, in order to adjust the RTC prescaler. + +The Low Speed Internal (LSI) clock is used as RTC clock source. +After reset, the RTC prescaler (asynchronous and synchronous) is set with the +default LSI frequency (32KHz). +The RTC WakeUp is configured to generate an interrupt each 1s. The WakeUp counter +is clocked by the RTC CK_SPRE signal (1Hz) and its counter is set to 0x0. +LED1 connected to PG.06 is toggled inside the RTC WakeUp interrupt each 1s. + +The inaccuracy of the LSI clock causes the RTC WakeUp Interrupt to be inaccurate. +The RTC CK_SPRE signal can be monitored by LED1 which is toggled into the RTC +Wakeup interrupt service routine. + +The program waits until Key Push button is pressed to begin the auto calibration +procedure: + - Configure the TIM5 to remap internally the TIM5 Channel 4 Input Capture to + the LSI clock output. + - Enable the TIM5 Input Capture interrupt: after one cycle of LSI clock, the + period value is stored in a variable and compared to the HCLK clock to get + its real value. + - The RTC prescaler is adjusted with this LSI frequency value so that the RTC + CK_SPRE value become more accurate. + - When calibration is done a led connected to PG.08 is turned ON to indicate the + end of this operation. + + +@par Directory contents + + - RTC/RTC_LSI/system_stm32f2xx.c STM32F2xx system clock configuration file + - RTC/RTC_LSI/stm32f2xx_conf.h Library Configuration file + - RTC/RTC_LSI/stm32f2xx_it.c Interrupt handlers + - RTC/RTC_LSI/stm32f2xx_it.h Header for stm32f2xx_it.c + - RTC/RTC_LSI/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LD1 and LD2 leds connected respectively to PG.06 and PG.08 pins. + - Use the KEY push button connected to PG.15 pin (EXTI Line15). + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/stm32f2xx_conf.h new file mode 100644 index 000000000..82c43e793 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file RTC/RTC_LSI/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/stm32f2xx_it.c new file mode 100644 index 000000000..abcd7f735 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/stm32f2xx_it.c @@ -0,0 +1,222 @@ +/** + ****************************************************************************** + * @file RTC/RTC_LSI/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup RTC_LSI + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern __IO uint32_t PeriodValue; +extern __IO uint32_t CaptureNumber; +uint16_t tmpCC4[2] = {0, 0}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles RTC Wakeup global interrupt request. + * @param None + * @retval None + */ +void RTC_WKUP_IRQHandler(void) +{ + if(RTC_GetITStatus(RTC_IT_WUT) != RESET) + { + /* Toggle on LED1 */ + STM_EVAL_LEDToggle(LED1); + RTC_ClearITPendingBit(RTC_IT_WUT); + EXTI_ClearITPendingBit(EXTI_Line22); + } +} + +/** + * @brief This function handles TIM5 global interrupt request. + * @param None + * @retval None + */ +void TIM5_IRQHandler(void) +{ + if (TIM_GetITStatus(TIM5, TIM_IT_CC4) != RESET) + { + /* Get the Input Capture value */ + tmpCC4[CaptureNumber++] = TIM_GetCapture4(TIM5); + + /* Clear CC4 Interrupt pending bit */ + TIM_ClearITPendingBit(TIM5, TIM_IT_CC4); + + if (CaptureNumber >= 2) + { + /* Compute the period length */ + PeriodValue = (uint16_t)(0xFFFF - tmpCC4[0] + tmpCC4[1] + 1); + } + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/stm32f2xx_it.h new file mode 100644 index 000000000..4e6b13e34 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/stm32f2xx_it.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * @file RTC/RTC_LSI/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void RTC_WKUP_IRQHandler(void); +void TIM5_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/RTC_LSI/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/main.c new file mode 100644 index 000000000..b5d0a352f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/main.c @@ -0,0 +1,281 @@ +/** + ****************************************************************************** + * @file RTC/Tamper/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup RTC_Tamper + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define RTC_BKP_DR_NUMBER 20 /* RTC Backup Data Register Number */ + +/* Uncomment the corresponding line to select the RTC Clock source */ +#define RTC_CLOCK_SOURCE_LSE /* LSE used as RTC source clock */ +/* #define RTC_CLOCK_SOURCE_LSI */ /* LSI used as RTC source clock. The RTC Clock + may varies due to LSI frequency dispersion. */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint32_t RTC_BKP_DR[RTC_BKP_DR_NUMBER] = + { + RTC_BKP_DR0, RTC_BKP_DR1, RTC_BKP_DR2, RTC_BKP_DR3, + RTC_BKP_DR4, RTC_BKP_DR5, RTC_BKP_DR6, RTC_BKP_DR7, + RTC_BKP_DR8, RTC_BKP_DR9, RTC_BKP_DR10, RTC_BKP_DR11, + RTC_BKP_DR12, RTC_BKP_DR13, RTC_BKP_DR14, RTC_BKP_DR15, + RTC_BKP_DR16, RTC_BKP_DR17, RTC_BKP_DR18, RTC_BKP_DR19 + }; + +/* Private function prototypes -----------------------------------------------*/ +void RTC_Config(void); +void WriteToRTC_BKP_DR(uint32_t FirstRTCBackupData); +uint32_t CheckRTC_BKP_DR(uint32_t FirstRTCBackupData); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize Leds mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* RTC configuration */ + RTC_Config(); + + /* Write To RTC Backup Data registers */ + WriteToRTC_BKP_DR(0xA53C); + + /* Check if the written data are correct */ + if(CheckRTC_BKP_DR(0xA53C) == 0x00) + { + /* Turn on LED1 */ + STM_EVAL_LEDOn(LED1); + } + else + { + /* Turn on LED3 */ + STM_EVAL_LEDOn(LED3); + } + + while (1) + { + } +} + +/** + * @brief Configure the RTC peripheral by selecting the clock source. + * @param None + * @retval None + */ +void RTC_Config(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + /* Enable the PWR clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); + + /* Reset BKP Domain */ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); + +#if defined (RTC_CLOCK_SOURCE_LSI) /* LSI used as RTC source clock*/ +/* The RTC Clock may varies due to LSI frequency dispersion. */ + /* Enable the LSI OSC */ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + +#elif defined (RTC_CLOCK_SOURCE_LSE) /* LSE used as RTC source clock */ + /* Enable the LSE OSC */ + RCC_LSEConfig(RCC_LSE_ON); + + /* Wait till LSE is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + +#else + #error Please select the RTC Clock source inside the main.c file +#endif /* RTC_CLOCK_SOURCE_LSI */ + + /* Enable The external line21 interrupt */ + EXTI_ClearITPendingBit(EXTI_Line21); + EXTI_InitStructure.EXTI_Line = EXTI_Line21; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Enable TAMPER IRQChannel */ + NVIC_InitStructure.NVIC_IRQChannel = TAMP_STAMP_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Disable the Tamper 1 detection */ + RTC_TamperCmd(RTC_Tamper_1, DISABLE); + + /* Clear Tamper 1 pin Event(TAMP1F) pending flag */ + RTC_ClearFlag(RTC_FLAG_TAMP1F); + + /* Configure the Tamper 1 Trigger */ + RTC_TamperTriggerConfig(RTC_Tamper_1, RTC_TamperTrigger_FallingEdge); + + /* Enable the Tamper interrupt */ + RTC_ITConfig(RTC_IT_TAMP, ENABLE); + + /* Clear Tamper 1 pin interrupt pending bit */ + RTC_ClearITPendingBit(RTC_IT_TAMP1); + + /* Enable the Tamper 1 detection */ + RTC_TamperCmd(RTC_Tamper_1, ENABLE); +} + +/** + * @brief Writes data RTC Backup DRx registers. + * @param FirstRTCBackupData: data to be written to RTC Backup data registers. + * @retval None + */ +void WriteToRTC_BKP_DR(uint32_t FirstRTCBackupData) +{ + uint32_t index = 0; + + for (index = 0; index < RTC_BKP_DR_NUMBER; index++) + { + /* write To bkp data register */ + RTC_WriteBackupRegister(RTC_BKP_DR[index], FirstRTCBackupData + (index * 0x5A)); + } +} + +/** + * @brief Checks if the RTC Backup DRx registers values are correct or not. + * @param FirstRTCBackupData: data to be compared with RTC Backup data registers. + * @retval - 0: All RTC Backup DRx registers values are correct + * - Value different from 0: Number of the first Backup register + * which value is not correct + */ +uint32_t CheckRTC_BKP_DR(uint32_t FirstRTCBackupData) +{ + uint32_t index = 0; + + for (index = 0; index < RTC_BKP_DR_NUMBER; index++) + { + /* Read from data register */ + if (RTC_ReadBackupRegister(RTC_BKP_DR[index]) != (FirstRTCBackupData + (index * 0x5A))) + { + return (index + 1); + } + } + return 0; +} + +/** + * @brief Checks if the RTC Backup DRx registers are reset or not. + * @param None + * @retval - 0: All RTC Backup DRx registers are reset + * - Value different from 0: Number of the first Backup register + * not reset + */ +uint32_t IsBackupRegReset(void) +{ + uint32_t index = 0; + + for (index = 0; index < RTC_BKP_DR_NUMBER; index++) + { + /* Read from bkp Data Register */ + if (RTC_ReadBackupRegister(RTC_BKP_DR[index]) != 0x0) + { + return (index + 1); + } + } + return 0; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/main.h new file mode 100644 index 000000000..4d8acc0da --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/main.h @@ -0,0 +1,44 @@ +/** + ****************************************************************************** + * @file RTC/Tamper/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +uint32_t IsBackupRegReset(void); + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/readme.txt new file mode 100644 index 000000000..32ffaa85d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/readme.txt @@ -0,0 +1,89 @@ +/** + @page RTC_Tamper RTC Tamper example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file RTC/Tamper/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the RTC Tamper example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to write/read data to/from RTC Backup data registers and +demonstrates the Tamper detection feature. + +One from the following clock can be used as RTC clock source (uncomment the +corresponding define in main.c): + - LSE oscillator clock usually delivered by a 32.768 kHz quartz. + - LSI oscillator clock + +The associated firmware performs the following: +1. It configures the RTC_AF1 pin Tamper to be falling edge, and enables the Tamper + interrupt. +2. It writes the data to all RTC Backup data registers, then check whether the + data were correctly written. If yes, LED1 turns on, otherwise LED3 turns on. +3. On applying a low level on the RTC_AF1 pin (PC.13), the RTC backup data registers + are reset and the Tamper interrupt is generated. The corresponding ISR then checks + whether the RTC Backup data registers are cleared. If yes LED2 turns ON, + otherwise LED4 turns ON. + + +@par Directory contents + + - RTC/Tamper/system_stm32f2xx.c STM32F2xx system clock configuration file + - RTC/Tamper/stm32f2xx_conf.h Library Configuration file + - RTC/Tamper/stm32f2xx_it.c Interrupt handlers + - RTC/Tamper/stm32f2xx_it.h Header for stm32f2xx_it.c + - RTC/Tamper/main.c Main program + - RTC/Tamper/main.h Main header file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LD1, LD2, LD3 and LD4 leds connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins. + - Use the TAMPER push button connected to PC.13 pin (EXTI Line13). + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/stm32f2xx_conf.h new file mode 100644 index 000000000..58326527d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file RTC/Tamper/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/stm32f2xx_it.c new file mode 100644 index 000000000..159dacd4b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/stm32f2xx_it.c @@ -0,0 +1,214 @@ +/** + ****************************************************************************** + * @file RTC/Tamper/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup RTC_Tamper + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles RTC Tamper and Time Stamp interrupts requests. + * @param None + * @retval None + */ +void TAMP_STAMP_IRQHandler(void) +{ + if(RTC_GetFlagStatus(RTC_FLAG_TAMP1F) != RESET) + { + /* Tamper 1 detection event occurred */ + /* Check if RTC Backup Data registers are cleared */ + if(IsBackupRegReset() == 0) + { + /* OK, RTC Backup Data registers are reset as expected */ + /* Toggle LED2 */ + STM_EVAL_LEDToggle(LED2); + } + else + { + /* RTC Backup Data registers are not reset */ + /* Toggle LED4 */ + STM_EVAL_LEDToggle(LED4); + } + + /* Clear Tamper 1 pin Event(TAMP1F) pending flag */ + RTC_ClearFlag(RTC_FLAG_TAMP1F); + + /* Disable Tamper pin 1 */ + RTC_TamperCmd(RTC_Tamper_1, DISABLE); + + /* Enable Tamper pin */ + RTC_TamperCmd(RTC_Tamper_1, ENABLE); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/stm32f2xx_it.h new file mode 100644 index 000000000..763f58e3c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/stm32f2xx_it.h @@ -0,0 +1,61 @@ +/** + ****************************************************************************** + * @file RTC/Tamper/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TAMP_STAMP_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/Tamper/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/main.c new file mode 100644 index 000000000..34b9e4b42 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/main.c @@ -0,0 +1,445 @@ +/** + ****************************************************************************** + * @file RTC/TimeStamp/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup RTC_TimeStamp + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Uncomment the corresponding line to select the RTC Clock source */ +#define RTC_CLOCK_SOURCE_LSE /* LSE used as RTC source clock */ +/* #define RTC_CLOCK_SOURCE_LSI */ /* LSI used as RTC source clock. The RTC Clock + may varies due to LSI frequency dispersion. */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +USART_InitTypeDef USART_InitStructure; +RTC_InitTypeDef RTC_InitStructure; +RTC_TimeTypeDef RTC_TimeStructure; +RTC_DateTypeDef RTC_DateStructure; +RTC_TimeTypeDef RTC_TimeStampStructure; +RTC_DateTypeDef RTC_TimeStampDateStructure; +__IO uint32_t AsynchPrediv = 0, SynchPrediv = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + /* USARTx configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit(COM1, &USART_InitStructure); + + /* Output a message on Hyperterminal using printf function */ + printf("\n\r *********************** RTC Time Stamp Example ***********************\n\r"); + + if (RTC_ReadBackupRegister(RTC_BKP_DR0) != 0x32F2) + { + /* RTC configuration */ + RTC_Config(); + + /* Configure the RTC data register and RTC prescaler */ + RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv; + RTC_InitStructure.RTC_SynchPrediv = SynchPrediv; + RTC_InitStructure.RTC_HourFormat = RTC_HourFormat_24; + + /* Check on RTC init */ + if (RTC_Init(&RTC_InitStructure) == ERROR) + { + printf("\n\r /!\\***** RTC Prescaler Config failed ********/!\\ \n\r"); + } + + /* Configure the time register */ + RTC_TimeRegulate(); + } + else + { + /* Check if the Power On Reset flag is set */ + if (RCC_GetFlagStatus(RCC_FLAG_PORRST) != RESET) + { + printf("\r\n Power On Reset occurred....\n\r"); + } + /* Check if the Pin Reset flag is set */ + else if (RCC_GetFlagStatus(RCC_FLAG_PINRST) != RESET) + { + printf("\r\n External Reset occurred....\n\r"); + } + + printf("\r\n No need to configure RTC....\n\r"); + + /* Enable the PWR clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); + + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); + + /* Clear the RTC Alarm Flag */ + RTC_ClearFlag(RTC_FLAG_ALRAF); + + /* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */ + EXTI_ClearITPendingBit(EXTI_Line17); + + /* Display the RTC Time/Date and TimeStamp Time/Date */ + RTC_TimeShow(); + RTC_DateShow(); + RTC_TimeStampShow(); + } + + /* Configure the external interrupt "WAKEUP", "KEY" and "TAMPER" buttons */ + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI); + STM_EVAL_PBInit(BUTTON_TAMPER , BUTTON_MODE_EXTI); + STM_EVAL_PBInit(BUTTON_WAKEUP , BUTTON_MODE_EXTI); + + /* Configure LED1 */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDOn(LED1); + + while (1) + { + } +} + +/** + * @brief Configure the RTC peripheral by selecting the clock source. + * @param None + * @retval None + */ +void RTC_Config(void) +{ + /* Enable the PWR clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Allow access to RTC */ + PWR_BackupAccessCmd(ENABLE); + +#if defined (RTC_CLOCK_SOURCE_LSI) /* LSI used as RTC source clock*/ +/* The RTC Clock may varies due to LSI frequency dispersion. */ + /* Enable the LSI OSC */ + RCC_LSICmd(ENABLE); + + /* Wait till LSI is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); + + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; + +#elif defined (RTC_CLOCK_SOURCE_LSE) /* LSE used as RTC source clock */ + /* Enable the LSE OSC */ + RCC_LSEConfig(RCC_LSE_ON); + + /* Wait till LSE is ready */ + while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + } + + /* Select the RTC Clock Source */ + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); + + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; + +#else + #error Please select the RTC Clock source inside the main.c file +#endif /* RTC_CLOCK_SOURCE_LSI */ + + /* Enable the RTC Clock */ + RCC_RTCCLKCmd(ENABLE); + + /* Wait for RTC APB registers synchronisation */ + RTC_WaitForSynchro(); + + /* Enable The TimeStamp */ + RTC_TimeStampCmd(RTC_TimeStampEdge_Falling, ENABLE); +} + +/** + * @brief Returns the time entered by user, using Hyperterminal. + * @param None + * @retval None + */ +void RTC_TimeRegulate(void) +{ + uint32_t tmp_hh = 0xFF, tmp_mm = 0xFF, tmp_ss = 0xFF; + + printf("\n\r==============Time Settings=====================================\n\r"); + RTC_TimeStructure.RTC_H12 = RTC_H12_AM; + printf(" Please Set Hours\n\r"); + while (tmp_hh == 0xFF) + { + tmp_hh = USART_Scanf(0, 23); + RTC_TimeStructure.RTC_Hours = tmp_hh; + } + printf(": %0.2d\n\r", tmp_hh); + + printf(" Please Set Minutes\n\r"); + while (tmp_mm == 0xFF) + { + tmp_mm = USART_Scanf(0, 59); + RTC_TimeStructure.RTC_Minutes = tmp_mm; + } + printf(": %0.2d\n\r", tmp_mm); + + printf(" Please Set Seconds\n\r"); + while (tmp_ss == 0xFF) + { + tmp_ss = USART_Scanf(0, 59); + RTC_TimeStructure.RTC_Seconds = tmp_ss; + } + printf(": %0.2d\n\r", tmp_ss); + + /* Configure the RTC time register */ + if(RTC_SetTime(RTC_Format_BIN, &RTC_TimeStructure) == ERROR) + { + printf("\n\r>> !! RTC Set Time failed. !! <<\n\r"); + } + else + { + printf("\n\r>> !! RTC Set Time success. !! <<\n\r"); + RTC_TimeShow(); + /* Indicator for the RTC configuration */ + RTC_WriteBackupRegister(RTC_BKP_DR0, 0x32F2); + } + + tmp_hh = 0xFF; + tmp_mm = 0xFF; + tmp_ss = 0xFF; + + printf("\n\r==============Date Settings=====================================\n\r"); + + printf(" Please Set WeekDay (01-07)\n\r"); + while (tmp_hh == 0xFF) + { + tmp_hh = USART_Scanf(1, 7); + RTC_DateStructure.RTC_WeekDay = tmp_hh; + } + printf(": %0.2d\n\r", tmp_hh); + tmp_hh = 0xFF; + printf(" Please Set Date (01-31)\n\r"); + while (tmp_hh == 0xFF) + { + tmp_hh = USART_Scanf(1, 31); + RTC_DateStructure.RTC_Date = tmp_hh; + } + printf(": %0.2d\n\r", tmp_hh); + + printf(" Please Set Month (01-12)\n\r"); + while (tmp_mm == 0xFF) + { + tmp_mm = USART_Scanf(1, 12); + RTC_DateStructure.RTC_Month = tmp_mm; + } + printf(": %0.2d\n\r", tmp_mm); + + printf(" Please Set Year (00-99)\n\r"); + while (tmp_ss == 0xFF) + { + tmp_ss = USART_Scanf(0, 99); + RTC_DateStructure.RTC_Year = tmp_ss; + } + printf(": %0.2d\n\r", tmp_ss); + + /* Configure the RTC date register */ + if(RTC_SetDate(RTC_Format_BIN, &RTC_DateStructure) == ERROR) + { + printf("\n\r>> !! RTC Set Date failed. !! <<\n\r"); + } + else + { + printf("\n\r>> !! RTC Set Date success. !! <<\n\r"); + RTC_DateShow(); + /* Indicator for the RTC configuration */ + RTC_WriteBackupRegister(RTC_BKP_DR0, 0x32F2); + } + +} + +/** + * @brief Display the current time on the Hyperterminal. + * @param None + * @retval None + */ +void RTC_TimeShow(void) +{ + /* Get the current Time and Date */ + RTC_GetTime(RTC_Format_BIN, &RTC_TimeStructure); + printf("\n\r============== Current Time Display ============================\n\r"); + printf("\n\r The current time (Hour-Minute-Second) is : %0.2d:%0.2d:%0.2d \n\r", RTC_TimeStructure.RTC_Hours, RTC_TimeStructure.RTC_Minutes, RTC_TimeStructure.RTC_Seconds); + /* Unfreeze the RTC DR Register */ + (void)RTC->DR; +} + +/** + * @brief Display the current date on the Hyperterminal. + * @param None + * @retval None + */ +void RTC_DateShow(void) +{ + /* Get the current Date */ + RTC_GetDate(RTC_Format_BIN, &RTC_DateStructure); + printf("\n\r============== Current Date Display ============================\n\r"); + printf("\n\r The current date (WeekDay-Date-Month-Year) is : %0.2d-%0.2d-%0.2d-%0.2d \n\r", RTC_DateStructure.RTC_WeekDay, RTC_DateStructure.RTC_Date, RTC_DateStructure.RTC_Month, RTC_DateStructure.RTC_Year); +} + + +/** + * @brief Display the current TimeStamp (time and date) on the Hyperterminal. + * @param None + * @retval None + */ +void RTC_TimeStampShow(void) +{ + /* Get the current TimeStamp */ + RTC_GetTimeStamp(RTC_Format_BIN, &RTC_TimeStampStructure, &RTC_TimeStampDateStructure); + printf("\n\r==============TimeStamp Display (Time and Date)=================\n\r"); + printf("\n\r The current time stamp time (Hour-Minute-Second) is : %0.2d:%0.2d:%0.2d \n\r", RTC_TimeStampStructure.RTC_Hours, RTC_TimeStampStructure.RTC_Minutes, RTC_TimeStampStructure.RTC_Seconds); + printf("\n\r The current timestamp date (WeekDay-Date-Month) is : %0.2d-%0.2d-%0.2d \n\r", RTC_TimeStampDateStructure.RTC_WeekDay, RTC_TimeStampDateStructure.RTC_Date, RTC_TimeStampDateStructure.RTC_Month); +} + + +/** + * @brief Gets numeric values from the hyperterminal. + * @param MinValue: minimum value to be used. + * @param MaxValue: maximum value to be used. + * @retval None + */ +uint8_t USART_Scanf(uint32_t MinValue, uint32_t MaxValue) +{ + uint32_t index = 0; + uint32_t tmp[2] = {0, 0}; + + while (index < 2) + { + /* Loop until RXNE = 1 */ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_RXNE) == RESET) + {} + tmp[index++] = (USART_ReceiveData(EVAL_COM1)); + if ((tmp[index - 1] < 0x30) || (tmp[index - 1] > 0x39)) + { + printf("\n\r Please enter valid number between 0 and 9\n\r"); + index--; + } + } + /* Calculate the Corresponding value */ + index = (tmp[1] - 0x30) + ((tmp[0] - 0x30) * 10); + /* Checks the value */ + if ((index < MinValue) || (index > MaxValue)) + { + printf("\n\r Please enter valid number between %d and %d\n\r", MinValue, MaxValue); + return 0xFF; + } + return index; +} + +/** + * @brief Retargets the C library printf function to the USART. + * @param None + * @retval None + */ +PUTCHAR_PROTOTYPE +{ + /* Place your implementation of fputc here */ + /* e.g. write a character to the USART */ + USART_SendData(EVAL_COM1, (uint8_t) ch); + + /* Loop until the end of transmission */ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) + {} + + return ch; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/main.h new file mode 100644 index 000000000..668d3cc3e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/main.h @@ -0,0 +1,58 @@ +/** + ****************************************************************************** + * @file RTC/TimeStamp/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RTC_Config(void); +void RTC_TimeRegulate(void); +void RTC_TimeShow(void); +void RTC_DateShow(void); +void RTC_TimeStampShow(void); +uint8_t USART_Scanf(uint32_t MinValue, uint32_t MaxValue); + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/readme.txt new file mode 100644 index 000000000..a87e6268f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/readme.txt @@ -0,0 +1,126 @@ +/** + @page RTC_TimeStamp RTC TimeStamp example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file RTC/TimeStamp/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the RTC TimeStamp example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a short description of how to use the RTC peripheral and +the Time Stamp feature. + +One from the following clock can be used as RTC clock source (uncomment the +corresponding define in main.c): + - LSE oscillator clock usually delivered by a 32.768 kHz quartz. + - LSI oscillator clock + +The program behaves as follows: + +1. After startup the program checks the backup data register 0 value: + - BKP_DR0 value not correct: (RTC_BKP_DR0 value is not correct or has not yet + been programmed when the program is executed for the first time) the RTC is + configured and the user is asked to set the time and date (entered on + HyperTerminal). + + - BKP_DR0 value correct: this means that the RTC is configured and the time + date and timestamp (time and date) are displayed on HyperTerminal. + +2. When an External Reset occurs the BKP domain is not reset and the RTC configuration + is not lost. + +3. When power on reset occurs: + - If a battery is connected to the VBAT pin: the BKP domain is not reset and + the RTC configuration is not lost. + + - If no battery is connected to the VBAT pin: the BKP domain is reset and the + RTC configuration is lost. + +4. It configures the RTC_AF1 pin TimeStamp to be falling edge and enables the +TimeStamp detection. + +5. On applying a low level on the RTC_AF1 pin (PC.13), the calendar is saved in +the time-stamp registers thanks to the timestamp event detection. + +The example uses HyperTerminal to configure the RTC clock, display the current +time and timestamp registers contents: + - pressing TAMPER push button, the current time and date are saved in RTC TSTR + and TSDR registers. + - When pressing WAKEUP push button, the TimeStamp Calendar is cleared. + - When pressing KEY push button, the current RTC Calendar (Time and date) and + RTC TimeStamp Calendar (Time and date) are displayed. + +@note The RTC_Year member in the TimeStamp Date is always 00 (no years in the RTC_TSDR register) + +@par Directory contents + + - RTC/TimeStamp/system_stm32f2xx.c STM32F2xx system clock configuration file + - RTC/TimeStamp/stm32f2xx_conf.h Library Configuration file + - RTC/TimeStamp/stm32f2xx_it.c Interrupt handlers + - RTC/TimeStamp/stm32f2xx_it.h Header for stm32f2xx_it.c + - RTC/TimeStamp/main.c Main program + - RTC/TimeStamp/main.h Main header file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use the TAMPER push button connected to PC.13 pin (EXTI Line13). + - Use the KEY push button connected to PG.15 pin (EXTI Line15). + - Use the WAKEUP push button connected to PA.00 pin (EXTI Line0). + - Make sure that jumper JP19 is in position 1-2 to connect the 3V battery to VBAT pin + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port if you want to display data on the HyperTerminal. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/stm32f2xx_conf.h new file mode 100644 index 000000000..60601b549 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file RTC/TimeStamp/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/stm32f2xx_it.c new file mode 100644 index 000000000..42d9db323 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/stm32f2xx_it.c @@ -0,0 +1,236 @@ +/** + ****************************************************************************** + * @file RTC/TimeStamp/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup RTC_TimeStamp + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles External line 0 interrupt request. + * @param None + * @retval None + */ +void EXTI0_IRQHandler(void) +{ + /* Clear the TimeStamp registers */ + if(EXTI_GetITStatus(WAKEUP_BUTTON_EXTI_LINE) != RESET) + { + /* Turn LED1 ON and LED2 OFF */ + STM_EVAL_LEDOn(LED1); + STM_EVAL_LEDOff(LED2); + + /* Clear The TSF Flag (Clear TimeStamp Registers) */ + RTC_ClearFlag(RTC_FLAG_TSF); + printf("\r\n******************** TimeStamp Event Cleared ********************"); + /* Clear the Wakeup Button EXTI line pending bit */ + EXTI_ClearITPendingBit(WAKEUP_BUTTON_EXTI_LINE); + } +} + +/** + * @brief This function handles External lines 15 to 10 interrupt request. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + /* TimeStamp Event detected */ + if(EXTI_GetITStatus(TAMPER_BUTTON_EXTI_LINE) != RESET) + { + /* Turn LED4 ON */ + STM_EVAL_LEDOn(LED4); + printf("\r\n******************** TimeStamp Event Occurred ********************"); + /* Clear the TAMPER Button EXTI line pending bit */ + EXTI_ClearITPendingBit(TAMPER_BUTTON_EXTI_LINE); + } + + /* To display Current RTC Time and Date Calendar */ + if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET) + { + /* Turn LED4 ON */ + STM_EVAL_LEDOn(LED4); + + /* Clear the KEY Button EXTI line pending bit */ + EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); + + /* Display the Time */ + RTC_TimeShow(); + /* Display the date */ + RTC_DateShow(); + /* Display the TimeStamp */ + RTC_TimeStampShow(); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/stm32f2xx_it.h new file mode 100644 index 000000000..910e63db9 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file RTC/TimeStamp/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/TimeStamp/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/readme.txt new file mode 100644 index 000000000..a5ab11d1a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/RTC/readme.txt @@ -0,0 +1,34 @@ +/** + @page RTC_EXAMPLES RTC EXAMPLES + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file RTC/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Reference to the Application note AN3371. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +For detailed description about the available examples, refer to the application +note "AN3371 Using the STM32 hardware real-time clock (RTC)" available on ST Microcontrollers . + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Release_Notes.html b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Release_Notes.html new file mode 100644 index 000000000..0d8593e90 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/Release_Notes.html @@ -0,0 +1,164 @@ + + + + + + + + +Release Notes for STM32F2xx Standard Peripherals Library Examples + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
Back to Release page
+

Release +Notes for STM32F2xx Standard Peripherals Library Examples

+

Copyright 2012 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F2xx Standard Peripherals Library +Examples update History
    2. +
  2. License
    3. +
+ + +

STM32F2xx Standard +Peripherals Library Examples update History


V1.1.0 / 13-April-2012

Main +Changes

+
  • All source files: license disclaimer text update and add link to the License file on ST Internet.
  • All +examples: update done to be in line with latest version of +STM32_EVAL architecture; include header +file "stm322xg_eval.h" instead of "stm32_eval.h"
  • ADC examples 
    • ADC configuration: add initialization of the ADC_ExternalTrigConv member of the ADC_InitStructure.
    • DualADC_Interleaved_DMAmode3, DualADC_RegulSimu_DMAmode1 and TripleADC_Interleaved_DMAmode2 examples:
      • Remove call to ADC_DMACmd() function (already done by ADC_MultiModeDMARequestAfterLastTransferCmd() function).
  • CAN examples 
    • Remove CAN_StructInit() function and replace it by an explicit data initialization.
    • Remove reference to CAN_Baudrate_Calculator.xls file inside the readme.txt.
  • CortexM3/MPU example
    • Add the following defines 
#define +MPU_RASR_XN_Pos                          +28  
#define +MPU_RASR_XN_Msk                          +(1UL << +MPU_RASR_XN_Pos)                      + 
#define +MPU_RASR_AP_Pos                          +24  
#define +MPU_RASR_AP_Msk                          +(7UL << MPU_RASR_AP_Pos)
  • CRYP examples 
    • AES_ECBmode_DMA 
      • Update +Crypto and DMA configuration sequence: DMA enabled before Crypto to +avoid flag error (FIFO error) generation during DMA transfer.
      • Replace +"while (DMA_GetFlagStatus(DMA2_Stream6, DMA_FLAG_TCIF5) == RESET);" by +"while (DMA_GetFlagStatus(DMA2_Stream5, DMA_FLAG_TCIF5) == RESET);".
    • TDES_ECBmode_DMA
      • Update Crypto and DMA configuration sequence: DMA enabled before Crypto to avoid flag error (FIFO error) generation during DMA transfer.
      • Replace +"while (DMA_GetFlagStatus(DMA2_Stream6, DMA_FLAG_TCIF5) == RESET);" by +"while (DMA_GetFlagStatus(DMA2_Stream5, DMA_FLAG_TCIF5) == RESET);".
  • DAC example
    • Update +the DMA Stream number for each DAC Channel : DMA1 stream 5 configured +with DAC Channel1 and DMA1 stream 6 with DAC Channel2.
  • DMA example
    • In stm32f2xx_it.c : replace DAM_STREAM_IRQHANDLER macro name by DMA_STREAM_IRQHANDLER.
  • DCMI example
    • Add driver for new camera OV2640 and example enhancement.
    • Change the folder name from "OV9655_Camera" to "Camera".
  • IWDG Example
    • Change EXTI interrupt Line from Line 0 to Line 15.
    • Change Invalid Address from 0x70000000 to 0xA0001000.
  • PWR examples
    • CurrentConsumption example
      • Example +enhancement: when system was resumed from STANDBY mode LED1 start +toggling (same behavior as sleep or stop mode resume). 
      • readme file: add more details about jumper settings
    • Update +readme file for all examples : add the following note "This example can +not be used in DEBUG mode, this is due to the fact that the Cortex™-M3 +core is no longer clocked during low power mode so debugging features +are disabled".
  • SDIO example 
    • In stm32f2xx_it.c : add SD_SDIO_DMA_IRQHANDLER() interrupt function which call SD_ProcessDMAIRQ() function at each DMA end of transfer.
    • In main.c : add the following NVIC configuration
      NVIC_InitStructure.NVIC_IRQChannel = SD_SDIO_DMA_IRQn;
      NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
      NVIC_Init(&NVIC_InitStructure);  
  • SPI examples 
    • SPI_DataExchangeInterrupt : Source Code modularity enhancement. 
  • TIM examples
    • ExtTrigger_Synchro example
      •  In main.c : replace comment "GPIOA Configuration: PA.09(TIM1 CH2)" by "GPIOE Configuration: PE.11(TIM1 CH2)" 
      • In readme.txt : replace "TIM3 CH1 (PB.04)" by "TIM3 CH1 (PC.06)"
    • OCInactive example
      • Add the GPIO configuration en alternate mode for PA0/PA1/PA2/PA3 which correspond respectively to TIM2_CH1/CH2/CH3/CH4.
    • In all examples clarify TIM frequency computation formula.
  • USART examples 
    • DataExchangeDMA : Source Code modularity enhancement.
  • WWDG Example
    • Change EXTI interrupt Line from Line 0 to Line 15
    • Change Invalid Address from 0x70000000 to 0xA0001000
  • I2C Examples: add readme file to refer to the I2C CPAL Library
  • RTC examples: add readme file to refer to the "AN3371 Using the STM32 hardware real-time clock (RTC)"

V1.0.0 / 18-April-2011

Main +Changes

+
  • First official release for STM32F2xx devices
    +
+ + +
    + +
+

License

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License. + +
+
+

For + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32

+
+ +
+
+

 

+
+ \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/main.c new file mode 100644 index 000000000..14ad7fca6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/main.c @@ -0,0 +1,382 @@ +/** + ****************************************************************************** + * @file SDIO/uSDCard/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval_sdio_sd.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SDIO_uSDCard + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Private define ------------------------------------------------------------*/ +#define BLOCK_SIZE 512 /* Block Size in Bytes */ + +#define NUMBER_OF_BLOCKS 100 /* For Multi Blocks operation (Read/Write) */ +#define MULTI_BUFFER_SIZE (BLOCK_SIZE * NUMBER_OF_BLOCKS) + +#define SD_OPERATION_ERASE 0 +#define SD_OPERATION_BLOCK 1 +#define SD_OPERATION_MULTI_BLOCK 2 +#define SD_OPERATION_END 3 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint8_t Buffer_Block_Tx[BLOCK_SIZE], Buffer_Block_Rx[BLOCK_SIZE]; +uint8_t Buffer_MultiBlock_Tx[MULTI_BUFFER_SIZE], Buffer_MultiBlock_Rx[MULTI_BUFFER_SIZE]; +volatile TestStatus EraseStatus = FAILED, TransferStatus1 = FAILED, TransferStatus2 = FAILED; +SD_Error Status = SD_OK; +__IO uint32_t SDCardOperation = SD_OPERATION_ERASE; + +/* Private function prototypes -----------------------------------------------*/ +void NVIC_Configuration(void); +void SD_EraseTest(void); +void SD_SingleBlockTest(void); +void SD_MultiBlockTest(void); +void Fill_Buffer(uint8_t *pBuffer, uint32_t BufferLength, uint32_t Offset); +TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint32_t BufferLength); +TestStatus eBuffercmp(uint8_t* pBuffer, uint32_t BufferLength); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs available on STM322xG-EVAL board *************************/ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Interrupt Config */ + NVIC_Configuration(); + + /*------------------------------ SD Init ---------------------------------- */ + if((Status = SD_Init()) != SD_OK) + { + STM_EVAL_LEDOn(LED4); + } + + while((Status == SD_OK) && (SDCardOperation != SD_OPERATION_END) && (SD_Detect()== SD_PRESENT)) + { + switch(SDCardOperation) + { + /*-------------------------- SD Erase Test ---------------------------- */ + case (SD_OPERATION_ERASE): + { + SD_EraseTest(); + SDCardOperation = SD_OPERATION_BLOCK; + break; + } + /*-------------------------- SD Single Block Test --------------------- */ + case (SD_OPERATION_BLOCK): + { + SD_SingleBlockTest(); + SDCardOperation = SD_OPERATION_MULTI_BLOCK; + break; + } + /*-------------------------- SD Multi Blocks Test --------------------- */ + case (SD_OPERATION_MULTI_BLOCK): + { + SD_MultiBlockTest(); + SDCardOperation = SD_OPERATION_END; + break; + } + } + } + + /* Infinite loop */ + while (1) + {} +} + +/** + * @brief Configures SDIO IRQ channel. + * @param None + * @retval None + */ +void NVIC_Configuration(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + /* Configure the NVIC Preemption Priority Bits */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + + NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + NVIC_InitStructure.NVIC_IRQChannel = SD_SDIO_DMA_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_Init(&NVIC_InitStructure); +} + +/** + * @brief Tests the SD card erase operation. + * @param None + * @retval None + */ +void SD_EraseTest(void) +{ + /*------------------- Block Erase ------------------------------------------*/ + if (Status == SD_OK) + { + /* Erase NumberOfBlocks Blocks of WRITE_BL_LEN(512 Bytes) */ + Status = SD_Erase(0x00, (BLOCK_SIZE * NUMBER_OF_BLOCKS)); + } + + if (Status == SD_OK) + { + Status = SD_ReadMultiBlocks(Buffer_MultiBlock_Rx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS); + + /* Check if the Transfer is finished */ + Status = SD_WaitReadOperation(); + + /* Wait until end of DMA transfer */ + while(SD_GetStatus() != SD_TRANSFER_OK); + } + + /* Check the correctness of erased blocks */ + if (Status == SD_OK) + { + EraseStatus = eBuffercmp(Buffer_MultiBlock_Rx, MULTI_BUFFER_SIZE); + } + + if(EraseStatus == PASSED) + { + STM_EVAL_LEDOn(LED1); + } + else + { + STM_EVAL_LEDOff(LED1); + STM_EVAL_LEDOn(LED4); + } +} + +/** + * @brief Tests the SD card Single Blocks operations. + * @param None + * @retval None + */ +void SD_SingleBlockTest(void) +{ + /*------------------- Block Read/Write --------------------------*/ + /* Fill the buffer to send */ + Fill_Buffer(Buffer_Block_Tx, BLOCK_SIZE, 0x320F); + + if (Status == SD_OK) + { + /* Write block of 512 bytes on address 0 */ + Status = SD_WriteBlock(Buffer_Block_Tx, 0x00, BLOCK_SIZE); + /* Check if the Transfer is finished */ + Status = SD_WaitWriteOperation(); + while(SD_GetStatus() != SD_TRANSFER_OK); + } + + if (Status == SD_OK) + { + /* Read block of 512 bytes from address 0 */ + Status = SD_ReadBlock(Buffer_Block_Rx, 0x00, BLOCK_SIZE); + /* Check if the Transfer is finished */ + Status = SD_WaitReadOperation(); + while(SD_GetStatus() != SD_TRANSFER_OK); + } + + /* Check the correctness of written data */ + if (Status == SD_OK) + { + TransferStatus1 = Buffercmp(Buffer_Block_Tx, Buffer_Block_Rx, BLOCK_SIZE); + } + + if(TransferStatus1 == PASSED) + { + STM_EVAL_LEDOn(LED2); + } + else + { + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOn(LED4); + } +} + +/** + * @brief Tests the SD card Multiple Blocks operations. + * @param None + * @retval None + */ +void SD_MultiBlockTest(void) +{ + /*--------------- Multiple Block Read/Write ---------------------*/ + /* Fill the buffer to send */ + Fill_Buffer(Buffer_MultiBlock_Tx, MULTI_BUFFER_SIZE, 0x0); + + if (Status == SD_OK) + { + /* Write multiple block of many bytes on address 0 */ + Status = SD_WriteMultiBlocks(Buffer_MultiBlock_Tx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS); + /* Check if the Transfer is finished */ + Status = SD_WaitWriteOperation(); + while(SD_GetStatus() != SD_TRANSFER_OK); + } + + if (Status == SD_OK) + { + /* Read block of many bytes from address 0 */ + Status = SD_ReadMultiBlocks(Buffer_MultiBlock_Rx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS); + /* Check if the Transfer is finished */ + Status = SD_WaitReadOperation(); + while(SD_GetStatus() != SD_TRANSFER_OK); + } + + /* Check the correctness of written data */ + if (Status == SD_OK) + { + TransferStatus2 = Buffercmp(Buffer_MultiBlock_Tx, Buffer_MultiBlock_Rx, MULTI_BUFFER_SIZE); + } + + if(TransferStatus2 == PASSED) + { + STM_EVAL_LEDOn(LED3); + } + else + { + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOn(LED4); + } +} + +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer1 identical to pBuffer2 + * FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint32_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} + +/** + * @brief Fills buffer with user predefined data. + * @param pBuffer: pointer on the Buffer to fill + * @param BufferLength: size of the buffer to fill + * @param Offset: first value to fill on the Buffer + * @retval None + */ +void Fill_Buffer(uint8_t *pBuffer, uint32_t BufferLength, uint32_t Offset) +{ + uint16_t index = 0; + + /* Put in global buffer same values */ + for (index = 0; index < BufferLength; index++) + { + pBuffer[index] = index + Offset; + } +} + +/** + * @brief Checks if a buffer has all its values are equal to zero. + * @param pBuffer: buffer to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer values are zero + * FAILED: At least one value from pBuffer buffer is different from zero. + */ +TestStatus eBuffercmp(uint8_t* pBuffer, uint32_t BufferLength) +{ + while (BufferLength--) + { + /* In some SD Cards the erased state is 0xFF, in others it's 0x00 */ + if ((*pBuffer != 0xFF) && (*pBuffer != 0x00)) + { + return FAILED; + } + + pBuffer++; + } + + return PASSED; +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/readme.txt new file mode 100644 index 000000000..ddd462965 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/readme.txt @@ -0,0 +1,123 @@ +/** + @page SDIO_uSDCard How to use the SDIO to drive an SD card memory + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file SDIO/uSDCard/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the SDIO Example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a basic example of how to use the SDIO firmware library and +an associate driver to perform read/write operations on the SD Card memory (SD Card +V1.0, V1.1, V2.0 and SDHC (High Capacity) protocol)that could be mounted on the +STM322xG_EVAL board. +The example provides different SD Card transfer states and operations and here +below a description of each step: + - First the SDIO peripheral and SD Card are initialized using the SD_Init() + function: + - Configure the SDIO according to the desired SDIO_CK clock frequency. + - Reset the SD Card + - Identify the SD Card + - Initializes the SD Card + - Get the SD Card Info + - Select the SD Card + - Enable the Wide Bus mode (4-bit data) + + - SD Card Erase Operation + - Starts an Erase operation: Erase the corresponding blocks using + the SD_Erase() function + - Read the Erased blocks using the SD_ReadMultiBlocks() function + - Test if the corresponding Blocks are well erased: check if the + EraseStatus variable is equal to PASSED. If the erase operation is + passed LED1 is turned ON. + + - SD Card Single Block Operation + - Starts a Write operation: Write a single Block using the SD_WriteBlock() + function + - Read a single Block using the SD_ReadBlock() function + - Compare the written Block and the read one: check if the TransferStatus1 + variable is equal to PASSED. If the Single Block Read/write operation + is passed LED2 is turned ON. + + - SD Card Multiple Block Operation + - Starts a Multiple Write operation: Write a multi Blocks using the + SD_WriteMultiBlocks() function. + - Read a multiple Blocks using the SD_ReadMultiBlocks() function + - Compare the written Blocks and the read one: check if the TransferStatus2 + variable is equal to PASSED. If the Multiple Blocks Read/Write operation + is passed LED3 is turned ON. + +All data transfers are made by DMA. +At each operation, the SD Card presence and status is checked using the SD_GetStatus() +function and a global variable "Status" storing the results of the last operation. + +SD Card Operations and Written/Read data correctness is signaled by LED +lightening and though as follow: + - If the Erase operation is PASSED then LED1 ON else the LED4 is ON and LED1 is OFF + - If the Single Block Write/Read operation is PASSED then LED2 ON else the LED4 is ON and LED2 is OFF + - If the Multi Blocks Write/Read operation is PASSED then LED3 ON else the LED4 is ON and LED3 is OFF + - Any SD Card operation including the SD Initialization error is signaled by + LED4 ON. + +@par Directory contents + + - SDIO/uSDCard/system_stm32f2xx.c STM32F2xx system clock configuration file + - SDIO/uSDCard/stm32f2xx_conf.h Library Configuration file + - SDIO/uSDCard/stm32f2xx_it.c Interrupt handlers + - SDIO/uSDCard/stm32f2xx_it.h Header for stm32f2xx_it.c + - SDIO/uSDCard/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily + tailored to any other development board. + + - STM322xG-EVAL RevB + - Make sure that Jumper JP22 is in position 1<->2 + + - STM322xG-EVAL RevB + - Make sure that Jumpers JP22 and JP16 are in position 1<->2 + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Add the "stm322xg_eval_sdio_sd.c" file (under Utilities\STM32_EVAL\STM322xG_EVAL) to the project source list + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/stm32f2xx_conf.h new file mode 100644 index 000000000..24eb767a2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file SDIO/uSDCard/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/stm32f2xx_it.c new file mode 100644 index 000000000..c3d02b7d9 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/stm32f2xx_it.c @@ -0,0 +1,196 @@ +/** + ****************************************************************************** + * @file SDIO/uSDCard/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval_sdio_sd.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SDIO_uSDCard + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ +/** + * @brief This function handles SDIO global interrupt request. + * @param None + * @retval None + */ +void SDIO_IRQHandler(void) +{ + /* Process All SDIO Interrupt Sources */ + SD_ProcessIRQSrc(); +} + +/** + * @brief This function handles DMA2 Stream3 or DMA2 Stream6 global interrupts + * requests. + * @param None + * @retval None + */ +void SD_SDIO_DMA_IRQHANDLER(void) +{ + /* Process DMA2 Stream3 or DMA2 Stream6 Interrupt Sources */ + SD_ProcessDMAIRQ(); +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/stm32f2xx_it.h new file mode 100644 index 000000000..bd39ede01 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file SDIO/uSDCard/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void SDIO_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SDIO/uSDCard/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/main.c new file mode 100644 index 000000000..802691669 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/main.c @@ -0,0 +1,189 @@ +/** + ****************************************************************************** + * @file SPI/SPI_FLASH/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" +#include "spi_flash.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SPI_FLASH + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Private define ------------------------------------------------------------*/ +#define FLASH_WRITE_ADDRESS 0x700000 +#define FLASH_READ_ADDRESS FLASH_WRITE_ADDRESS +#define FLASH_SECTOR_TO_ERASE FLASH_WRITE_ADDRESS + +#define BufferSize (countof(Tx_Buffer)-1) + +/* Private macro -------------------------------------------------------------*/ +#define countof(a) (sizeof(a) / sizeof(*(a))) + +/* Private variables ---------------------------------------------------------*/ +uint8_t Tx_Buffer[] = "STM32F2xx SPI Firmware Library Example: communication with an M25P SPI FLASH"; +uint8_t Rx_Buffer[BufferSize]; +__IO uint8_t Index = 0x0; +volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = PASSED; +__IO uint32_t FlashID = 0; + +/* Private functions ---------------------------------------------------------*/ +TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength); + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize Leds mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + + /* Initialize the SPI FLASH driver */ + sFLASH_Init(); + + /* Get SPI Flash ID */ + FlashID = sFLASH_ReadID(); + + /* Check the SPI Flash ID */ + if (FlashID == sFLASH_M25P64_ID) + { + /* OK: Turn on LD1 */ + STM_EVAL_LEDOn(LED1); + + /* Perform a write in the Flash followed by a read of the written data */ + /* Erase SPI FLASH Sector to write on */ + sFLASH_EraseSector(FLASH_SECTOR_TO_ERASE); + + /* Write Tx_Buffer data to SPI FLASH memory */ + sFLASH_WriteBuffer(Tx_Buffer, FLASH_WRITE_ADDRESS, BufferSize); + + /* Read data from SPI FLASH memory */ + sFLASH_ReadBuffer(Rx_Buffer, FLASH_READ_ADDRESS, BufferSize); + + /* Check the correctness of written dada */ + TransferStatus1 = Buffercmp(Tx_Buffer, Rx_Buffer, BufferSize); + /* TransferStatus1 = PASSED, if the transmitted and received data by SPI1 + are the same */ + /* TransferStatus1 = FAILED, if the transmitted and received data by SPI1 + are different */ + + /* Perform an erase in the Flash followed by a read of the written data */ + /* Erase SPI FLASH Sector to write on */ + sFLASH_EraseSector(FLASH_SECTOR_TO_ERASE); + + /* Read data from SPI FLASH memory */ + sFLASH_ReadBuffer(Rx_Buffer, FLASH_READ_ADDRESS, BufferSize); + + /* Check the correctness of erasing operation dada */ + for (Index = 0; Index < BufferSize; Index++) + { + if (Rx_Buffer[Index] != 0xFF) + { + TransferStatus2 = FAILED; + } + } + /* TransferStatus2 = PASSED, if the specified sector part is erased */ + /* TransferStatus2 = FAILED, if the specified sector part is not well erased */ + } + else + { + /* Error: Turn on LD2 */ + STM_EVAL_LEDOn(LED2); + } + + while (1) + {} +} + +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer1 identical to pBuffer2 + * FAILED: pBuffer1 differs from pBuffer2 + */ +TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + {} +} + +#endif +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/readme.txt new file mode 100644 index 000000000..9f5662e36 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/readme.txt @@ -0,0 +1,102 @@ +/** + @page SPI_FLASH SPI FLASH example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file SPI/SPI_FLASH/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the SPI FLASH example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a basic example of how to use the SPI firmware library +and an associated driver "spi_flash.c" to communicate with an M25P64 SPI FLASH. + +The first step consist in reading the SPI Flash ID. A comparison between the ID +read from SPI flash and the expected one is done and LED1 is turned on in case +of success otherwise LED2 is turned on. + +Using this driver the program performs an erase of the sector to be accessed, a +write of a Tx_Buffer, defined in the main.c file, to the memory followed by a read +of the written data. Then data read from the memory stored in the Rx_Buffer are +compared with the expected values of the Tx_Buffer. The result of this comparison +is stored in the "TransferStatus1" variable. + +A second erase of the same sector is done at the end, and a test is done to be +sure that all the data written there are erased further to the sector erase. All +the data location are read and checked with 0xFF value. The result of this test +is stored in "TransferStatus2" variable which is FAILED in case of error. + +The FLASH_WRITE_ADDRESS and the FLASH_READ_ADDRESS where the program start the +write and the read operations are defined in the main.c file. + + +@par Directory contents + + - SPI/SPI_FLASH/spi_flash.c SPI M25Pxxx driver + - SPI/SPI_FLASH/spi_flash.h Header for spi_flash.c + - SPI/SPI_FLASH/stm32f2xx_conf.h Library Configuration file + - SPI/SPI_FLASH/stm32f2xx_it.c Interrupt handlers + - SPI/SPI_FLASH/stm32f2xx_it.h Header for stm32f2xx_it.c + - SPI/SPI_FLASH/main.c Main program + - SPI/SPI_FLASH/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx. + + - This example can't be tested with STM322xG-EVAL evaluation board (no SPI + FLASH available). + + - HW platform Set-up + - Connect LED1 and LED2 respectively to PG.06 and PG.08 pins + - Connect both SPI2 and SPI FLASH pins as following: + - Connect SPI2_NSS (PI0) pin to SPI Flash chip select (pin1) + - Connect SPI2_SCK (PI1) pin to SPI Flash serial clock (pin6) + - Connect SPI2_MISO(PI2) pin to SPI Flash serial data output (pin2) + - Connect SPI2_MOSI(PI3) pin to SPI Flash serial data input (pin5) + - Connect SPI Flash Write Protect (pin3) to Vdd + - Connect SPI Flash Hold (pin7) to Vdd + - Connect SPI Flash Vcc (pin8) to Vdd + - Connect SPI Flash Vss (pin4) to Vss + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Add the file "spi_flash.c" to the project source list + - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/spi_flash.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/spi_flash.c new file mode 100644 index 000000000..dd7f937ab --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/spi_flash.c @@ -0,0 +1,579 @@ +/** + ****************************************************************************** + * @file SPI/SPI_FLASH/spi_flash.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file provides a set of functions needed to manage the SPI M25Pxxx + * FLASH memory. + * + * =================================================================== + * Notes: + * - There is no SPI FLASH memory available in STM322xG-EVAL board, + * to use this driver you have to build your own hardware. + * =================================================================== + * + * It implements a high level communication layer for read and write + * from/to this memory. The needed STM32 hardware resources (SPI and + * GPIO) are defined in spi_flash.h file, and the initialization is + * performed in sFLASH_LowLevel_Init() function. + * + * You can easily tailor this driver to any development board, by just + * adapting the defines for hardware resources and sFLASH_LowLevel_Init() + * function. + * + * +-----------------------------------------------------------+ + * | Pin assignment | + * +-----------------------------+---------------+-------------+ + * | STM32 SPI Pins | sFLASH | Pin | + * +-----------------------------+---------------+-------------+ + * | sFLASH_CS_PIN | ChipSelect(/S)| 1 | + * | sFLASH_SPI_MISO_PIN / MISO | DataOut(Q) | 2 | + * | | VCC | 3 (3.3 V)| + * | | GND | 4 (0 V) | + * | sFLASH_SPI_MOSI_PIN / MOSI | DataIn(D) | 5 | + * | sFLASH_SPI_SCK_PIN / SCK | Clock(C) | 6 | + * | | VCC | 7 (3.3 V)| + * | | VCC | 8 (3.3 V)| + * +-----------------------------+---------------+-------------+ + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "spi_flash.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SPI_FLASH + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +void sFLASH_LowLevel_DeInit(void); +void sFLASH_LowLevel_Init(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief DeInitializes the peripherals used by the SPI FLASH driver. + * @param None + * @retval None + */ +void sFLASH_DeInit(void) +{ + sFLASH_LowLevel_DeInit(); +} + +/** + * @brief Initializes the peripherals used by the SPI FLASH driver. + * @param None + * @retval None + */ +void sFLASH_Init(void) +{ + SPI_InitTypeDef SPI_InitStructure; + + sFLASH_LowLevel_Init(); + + /*!< Deselect the FLASH: Chip Select high */ + sFLASH_CS_HIGH(); + + /*!< SPI configuration */ + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; + + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + SPI_Init(sFLASH_SPI, &SPI_InitStructure); + + /*!< Enable the sFLASH_SPI */ + SPI_Cmd(sFLASH_SPI, ENABLE); +} + +/** + * @brief Erases the specified FLASH sector. + * @param SectorAddr: address of the sector to erase. + * @retval None + */ +void sFLASH_EraseSector(uint32_t SectorAddr) +{ + /*!< Send write enable instruction */ + sFLASH_WriteEnable(); + + /*!< Sector Erase */ + /*!< Select the FLASH: Chip Select low */ + sFLASH_CS_LOW(); + /*!< Send Sector Erase instruction */ + sFLASH_SendByte(sFLASH_CMD_SE); + /*!< Send SectorAddr high nibble address byte */ + sFLASH_SendByte((SectorAddr & 0xFF0000) >> 16); + /*!< Send SectorAddr medium nibble address byte */ + sFLASH_SendByte((SectorAddr & 0xFF00) >> 8); + /*!< Send SectorAddr low nibble address byte */ + sFLASH_SendByte(SectorAddr & 0xFF); + /*!< Deselect the FLASH: Chip Select high */ + sFLASH_CS_HIGH(); + + /*!< Wait the end of Flash writing */ + sFLASH_WaitForWriteEnd(); +} + +/** + * @brief Erases the entire FLASH. + * @param None + * @retval None + */ +void sFLASH_EraseBulk(void) +{ + /*!< Send write enable instruction */ + sFLASH_WriteEnable(); + + /*!< Bulk Erase */ + /*!< Select the FLASH: Chip Select low */ + sFLASH_CS_LOW(); + /*!< Send Bulk Erase instruction */ + sFLASH_SendByte(sFLASH_CMD_BE); + /*!< Deselect the FLASH: Chip Select high */ + sFLASH_CS_HIGH(); + + /*!< Wait the end of Flash writing */ + sFLASH_WaitForWriteEnd(); +} + +/** + * @brief Writes more than one byte to the FLASH with a single WRITE cycle + * (Page WRITE sequence). + * @note The number of byte can't exceed the FLASH page size. + * @param pBuffer: pointer to the buffer containing the data to be written + * to the FLASH. + * @param WriteAddr: FLASH's internal address to write to. + * @param NumByteToWrite: number of bytes to write to the FLASH, must be equal + * or less than "sFLASH_PAGESIZE" value. + * @retval None + */ +void sFLASH_WritePage(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite) +{ + /*!< Enable the write access to the FLASH */ + sFLASH_WriteEnable(); + + /*!< Select the FLASH: Chip Select low */ + sFLASH_CS_LOW(); + /*!< Send "Write to Memory " instruction */ + sFLASH_SendByte(sFLASH_CMD_WRITE); + /*!< Send WriteAddr high nibble address byte to write to */ + sFLASH_SendByte((WriteAddr & 0xFF0000) >> 16); + /*!< Send WriteAddr medium nibble address byte to write to */ + sFLASH_SendByte((WriteAddr & 0xFF00) >> 8); + /*!< Send WriteAddr low nibble address byte to write to */ + sFLASH_SendByte(WriteAddr & 0xFF); + + /*!< while there is data to be written on the FLASH */ + while (NumByteToWrite--) + { + /*!< Send the current byte */ + sFLASH_SendByte(*pBuffer); + /*!< Point on the next byte to be written */ + pBuffer++; + } + + /*!< Deselect the FLASH: Chip Select high */ + sFLASH_CS_HIGH(); + + /*!< Wait the end of Flash writing */ + sFLASH_WaitForWriteEnd(); +} + +/** + * @brief Writes block of data to the FLASH. In this function, the number of + * WRITE cycles are reduced, using Page WRITE sequence. + * @param pBuffer: pointer to the buffer containing the data to be written + * to the FLASH. + * @param WriteAddr: FLASH's internal address to write to. + * @param NumByteToWrite: number of bytes to write to the FLASH. + * @retval None + */ +void sFLASH_WriteBuffer(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite) +{ + uint8_t NumOfPage = 0, NumOfSingle = 0, Addr = 0, count = 0, temp = 0; + + Addr = WriteAddr % sFLASH_SPI_PAGESIZE; + count = sFLASH_SPI_PAGESIZE - Addr; + NumOfPage = NumByteToWrite / sFLASH_SPI_PAGESIZE; + NumOfSingle = NumByteToWrite % sFLASH_SPI_PAGESIZE; + + if (Addr == 0) /*!< WriteAddr is sFLASH_PAGESIZE aligned */ + { + if (NumOfPage == 0) /*!< NumByteToWrite < sFLASH_PAGESIZE */ + { + sFLASH_WritePage(pBuffer, WriteAddr, NumByteToWrite); + } + else /*!< NumByteToWrite > sFLASH_PAGESIZE */ + { + while (NumOfPage--) + { + sFLASH_WritePage(pBuffer, WriteAddr, sFLASH_SPI_PAGESIZE); + WriteAddr += sFLASH_SPI_PAGESIZE; + pBuffer += sFLASH_SPI_PAGESIZE; + } + + sFLASH_WritePage(pBuffer, WriteAddr, NumOfSingle); + } + } + else /*!< WriteAddr is not sFLASH_PAGESIZE aligned */ + { + if (NumOfPage == 0) /*!< NumByteToWrite < sFLASH_PAGESIZE */ + { + if (NumOfSingle > count) /*!< (NumByteToWrite + WriteAddr) > sFLASH_PAGESIZE */ + { + temp = NumOfSingle - count; + + sFLASH_WritePage(pBuffer, WriteAddr, count); + WriteAddr += count; + pBuffer += count; + + sFLASH_WritePage(pBuffer, WriteAddr, temp); + } + else + { + sFLASH_WritePage(pBuffer, WriteAddr, NumByteToWrite); + } + } + else /*!< NumByteToWrite > sFLASH_PAGESIZE */ + { + NumByteToWrite -= count; + NumOfPage = NumByteToWrite / sFLASH_SPI_PAGESIZE; + NumOfSingle = NumByteToWrite % sFLASH_SPI_PAGESIZE; + + sFLASH_WritePage(pBuffer, WriteAddr, count); + WriteAddr += count; + pBuffer += count; + + while (NumOfPage--) + { + sFLASH_WritePage(pBuffer, WriteAddr, sFLASH_SPI_PAGESIZE); + WriteAddr += sFLASH_SPI_PAGESIZE; + pBuffer += sFLASH_SPI_PAGESIZE; + } + + if (NumOfSingle != 0) + { + sFLASH_WritePage(pBuffer, WriteAddr, NumOfSingle); + } + } + } +} + +/** + * @brief Reads a block of data from the FLASH. + * @param pBuffer: pointer to the buffer that receives the data read from the FLASH. + * @param ReadAddr: FLASH's internal address to read from. + * @param NumByteToRead: number of bytes to read from the FLASH. + * @retval None + */ +void sFLASH_ReadBuffer(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead) +{ + /*!< Select the FLASH: Chip Select low */ + sFLASH_CS_LOW(); + + /*!< Send "Read from Memory " instruction */ + sFLASH_SendByte(sFLASH_CMD_READ); + + /*!< Send ReadAddr high nibble address byte to read from */ + sFLASH_SendByte((ReadAddr & 0xFF0000) >> 16); + /*!< Send ReadAddr medium nibble address byte to read from */ + sFLASH_SendByte((ReadAddr& 0xFF00) >> 8); + /*!< Send ReadAddr low nibble address byte to read from */ + sFLASH_SendByte(ReadAddr & 0xFF); + + while (NumByteToRead--) /*!< while there is data to be read */ + { + /*!< Read a byte from the FLASH */ + *pBuffer = sFLASH_SendByte(sFLASH_DUMMY_BYTE); + /*!< Point to the next location where the byte read will be saved */ + pBuffer++; + } + + /*!< Deselect the FLASH: Chip Select high */ + sFLASH_CS_HIGH(); +} + +/** + * @brief Reads FLASH identification. + * @param None + * @retval FLASH identification + */ +uint32_t sFLASH_ReadID(void) +{ + uint32_t Temp = 0, Temp0 = 0, Temp1 = 0, Temp2 = 0; + + /*!< Select the FLASH: Chip Select low */ + sFLASH_CS_LOW(); + + /*!< Send "RDID " instruction */ + sFLASH_SendByte(0x9F); + + /*!< Read a byte from the FLASH */ + Temp0 = sFLASH_SendByte(sFLASH_DUMMY_BYTE); + + /*!< Read a byte from the FLASH */ + Temp1 = sFLASH_SendByte(sFLASH_DUMMY_BYTE); + + /*!< Read a byte from the FLASH */ + Temp2 = sFLASH_SendByte(sFLASH_DUMMY_BYTE); + + /*!< Deselect the FLASH: Chip Select high */ + sFLASH_CS_HIGH(); + + Temp = (Temp0 << 16) | (Temp1 << 8) | Temp2; + + return Temp; +} + +/** + * @brief Initiates a read data byte (READ) sequence from the Flash. + * This is done by driving the /CS line low to select the device, then the READ + * instruction is transmitted followed by 3 bytes address. This function exit + * and keep the /CS line low, so the Flash still being selected. With this + * technique the whole content of the Flash is read with a single READ instruction. + * @param ReadAddr: FLASH's internal address to read from. + * @retval None + */ +void sFLASH_StartReadSequence(uint32_t ReadAddr) +{ + /*!< Select the FLASH: Chip Select low */ + sFLASH_CS_LOW(); + + /*!< Send "Read from Memory " instruction */ + sFLASH_SendByte(sFLASH_CMD_READ); + + /*!< Send the 24-bit address of the address to read from -------------------*/ + /*!< Send ReadAddr high nibble address byte */ + sFLASH_SendByte((ReadAddr & 0xFF0000) >> 16); + /*!< Send ReadAddr medium nibble address byte */ + sFLASH_SendByte((ReadAddr& 0xFF00) >> 8); + /*!< Send ReadAddr low nibble address byte */ + sFLASH_SendByte(ReadAddr & 0xFF); +} + +/** + * @brief Reads a byte from the SPI Flash. + * @note This function must be used only if the Start_Read_Sequence function + * has been previously called. + * @param None + * @retval Byte Read from the SPI Flash. + */ +uint8_t sFLASH_ReadByte(void) +{ + return (sFLASH_SendByte(sFLASH_DUMMY_BYTE)); +} + +/** + * @brief Sends a byte through the SPI interface and return the byte received + * from the SPI bus. + * @param byte: byte to send. + * @retval The value of the received byte. + */ +uint8_t sFLASH_SendByte(uint8_t byte) +{ + /*!< Loop while DR register in not emplty */ + while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_TXE) == RESET); + + /*!< Send byte through the SPI1 peripheral */ + SPI_I2S_SendData(sFLASH_SPI, byte); + + /*!< Wait to receive a byte */ + while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_RXNE) == RESET); + + /*!< Return the byte read from the SPI bus */ + return SPI_I2S_ReceiveData(sFLASH_SPI); +} + +/** + * @brief Sends a Half Word through the SPI interface and return the Half Word + * received from the SPI bus. + * @param HalfWord: Half Word to send. + * @retval The value of the received Half Word. + */ +uint16_t sFLASH_SendHalfWord(uint16_t HalfWord) +{ + /*!< Loop while DR register in not emplty */ + while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_TXE) == RESET); + + /*!< Send Half Word through the sFLASH peripheral */ + SPI_I2S_SendData(sFLASH_SPI, HalfWord); + + /*!< Wait to receive a Half Word */ + while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_RXNE) == RESET); + + /*!< Return the Half Word read from the SPI bus */ + return SPI_I2S_ReceiveData(sFLASH_SPI); +} + +/** + * @brief Enables the write access to the FLASH. + * @param None + * @retval None + */ +void sFLASH_WriteEnable(void) +{ + /*!< Select the FLASH: Chip Select low */ + sFLASH_CS_LOW(); + + /*!< Send "Write Enable" instruction */ + sFLASH_SendByte(sFLASH_CMD_WREN); + + /*!< Deselect the FLASH: Chip Select high */ + sFLASH_CS_HIGH(); +} + +/** + * @brief Polls the status of the Write In Progress (WIP) flag in the FLASH's + * status register and loop until write opertaion has completed. + * @param None + * @retval None + */ +void sFLASH_WaitForWriteEnd(void) +{ + uint8_t flashstatus = 0; + + /*!< Select the FLASH: Chip Select low */ + sFLASH_CS_LOW(); + + /*!< Send "Read Status Register" instruction */ + sFLASH_SendByte(sFLASH_CMD_RDSR); + + /*!< Loop as long as the memory is busy with a write cycle */ + do + { + /*!< Send a dummy byte to generate the clock needed by the FLASH + and put the value of the status register in FLASH_Status variable */ + flashstatus = sFLASH_SendByte(sFLASH_DUMMY_BYTE); + + } + while ((flashstatus & sFLASH_WIP_FLAG) == SET); /* Write in progress */ + + /*!< Deselect the FLASH: Chip Select high */ + sFLASH_CS_HIGH(); +} + +/** + * @brief Initializes the peripherals used by the SPI FLASH driver. + * @param None + * @retval None + */ +void sFLASH_LowLevel_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /*!< Enable the SPI clock */ + sFLASH_SPI_CLK_INIT(sFLASH_SPI_CLK, ENABLE); + + /*!< Enable GPIO clocks */ + RCC_AHB1PeriphClockCmd(sFLASH_SPI_SCK_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK | + sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_CS_GPIO_CLK, ENABLE); + + /*!< SPI pins configuration *************************************************/ + + /*!< Connect SPI pins to AF5 */ + GPIO_PinAFConfig(sFLASH_SPI_SCK_GPIO_PORT, sFLASH_SPI_SCK_SOURCE, sFLASH_SPI_SCK_AF); + GPIO_PinAFConfig(sFLASH_SPI_MISO_GPIO_PORT, sFLASH_SPI_MISO_SOURCE, sFLASH_SPI_MISO_AF); + GPIO_PinAFConfig(sFLASH_SPI_MOSI_GPIO_PORT, sFLASH_SPI_MOSI_SOURCE, sFLASH_SPI_MOSI_AF); + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; + + /*!< SPI SCK pin configuration */ + GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN; + GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); + + /*!< SPI MOSI pin configuration */ + GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN; + GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); + + /*!< SPI MISO pin configuration */ + GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN; + GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure sFLASH Card CS pin in output pushpull mode ********************/ + GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @brief DeInitializes the peripherals used by the SPI FLASH driver. + * @param None + * @retval None + */ +void sFLASH_LowLevel_DeInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /*!< Disable the sFLASH_SPI ************************************************/ + SPI_Cmd(sFLASH_SPI, DISABLE); + + /*!< DeInitializes the sFLASH_SPI *******************************************/ + SPI_I2S_DeInit(sFLASH_SPI); + + /*!< sFLASH_SPI Periph clock disable ****************************************/ + sFLASH_SPI_CLK_INIT(sFLASH_SPI_CLK, DISABLE); + + /*!< Configure all pins used by the SPI as input floating *******************/ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + + GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN; + GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN; + GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN; + GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN; + GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure); +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/spi_flash.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/spi_flash.h new file mode 100644 index 000000000..681dbe8ae --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/spi_flash.h @@ -0,0 +1,121 @@ +/** + ****************************************************************************** + * @file spi_flash.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains all the functions prototypes for the spi_flash + * firmware driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPI_FLASH_H +#define __SPI_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* M25P SPI Flash supported commands */ +#define sFLASH_CMD_WRITE 0x02 /* Write to Memory instruction */ +#define sFLASH_CMD_WRSR 0x01 /* Write Status Register instruction */ +#define sFLASH_CMD_WREN 0x06 /* Write enable instruction */ +#define sFLASH_CMD_READ 0x03 /* Read from Memory instruction */ +#define sFLASH_CMD_RDSR 0x05 /* Read Status Register instruction */ +#define sFLASH_CMD_RDID 0x9F /* Read identification */ +#define sFLASH_CMD_SE 0xD8 /* Sector Erase instruction */ +#define sFLASH_CMD_BE 0xC7 /* Bulk Erase instruction */ + +#define sFLASH_WIP_FLAG 0x01 /* Write In Progress (WIP) flag */ + +#define sFLASH_DUMMY_BYTE 0xA5 +#define sFLASH_SPI_PAGESIZE 0x100 + +#define sFLASH_M25P128_ID 0x202018 +#define sFLASH_M25P64_ID 0x202017 + +/* M25P FLASH SPI Interface pins */ +#define sFLASH_SPI SPI2 +#define sFLASH_SPI_CLK RCC_APB1Periph_SPI2 +#define sFLASH_SPI_CLK_INIT RCC_APB1PeriphClockCmd + +#define sFLASH_SPI_SCK_PIN GPIO_Pin_1 +#define sFLASH_SPI_SCK_GPIO_PORT GPIOI +#define sFLASH_SPI_SCK_GPIO_CLK RCC_AHB1Periph_GPIOI +#define sFLASH_SPI_SCK_SOURCE GPIO_PinSource1 +#define sFLASH_SPI_SCK_AF GPIO_AF_SPI2 + +#define sFLASH_SPI_MISO_PIN GPIO_Pin_2 +#define sFLASH_SPI_MISO_GPIO_PORT GPIOI +#define sFLASH_SPI_MISO_GPIO_CLK RCC_AHB1Periph_GPIOI +#define sFLASH_SPI_MISO_SOURCE GPIO_PinSource2 +#define sFLASH_SPI_MISO_AF GPIO_AF_SPI2 + +#define sFLASH_SPI_MOSI_PIN GPIO_Pin_3 +#define sFLASH_SPI_MOSI_GPIO_PORT GPIOI +#define sFLASH_SPI_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOI +#define sFLASH_SPI_MOSI_SOURCE GPIO_PinSource3 +#define sFLASH_SPI_MOSI_AF GPIO_AF_SPI2 + +#define sFLASH_CS_PIN GPIO_Pin_0 +#define sFLASH_CS_GPIO_PORT GPIOI +#define sFLASH_CS_GPIO_CLK RCC_AHB1Periph_GPIOI + +/* Exported macro ------------------------------------------------------------*/ +/* Select sFLASH: Chip Select pin low */ +#define sFLASH_CS_LOW() GPIO_ResetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN) +/* Deselect sFLASH: Chip Select pin high */ +#define sFLASH_CS_HIGH() GPIO_SetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN) + +/* Exported functions ------------------------------------------------------- */ + +/* High layer functions */ +void sFLASH_DeInit(void); +void sFLASH_Init(void); +void sFLASH_EraseSector(uint32_t SectorAddr); +void sFLASH_EraseBulk(void); +void sFLASH_WritePage(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite); +void sFLASH_WriteBuffer(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite); +void sFLASH_ReadBuffer(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead); +uint32_t sFLASH_ReadID(void); +void sFLASH_StartReadSequence(uint32_t ReadAddr); + +/* Low layer functions */ +uint8_t sFLASH_ReadByte(void); +uint8_t sFLASH_SendByte(uint8_t byte); +uint16_t sFLASH_SendHalfWord(uint16_t HalfWord); +void sFLASH_WriteEnable(void); +void sFLASH_WaitForWriteEnd(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_FLASH_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/stm32f2xx_conf.h new file mode 100644 index 000000000..457a05dcd --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file SPI/SPI_FLASH/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/stm32f2xx_it.c new file mode 100644 index 000000000..f41f57016 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file SPI/SPI_FLASH/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SPI_FLASH + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/stm32f2xx_it.h new file mode 100644 index 000000000..cbafabf27 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file SPI/SPI_FLASH/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/main.c new file mode 100644 index 000000000..3ba4272ae --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/main.c @@ -0,0 +1,454 @@ +/** + ****************************************************************************** + * @file SPI/SPI_TwoBoards/DataExchangeInterrupt/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SPI_DataExchangeInterrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +SPI_InitTypeDef SPI_InitStructure; +uint8_t TxBuffer[] = "SPI Interrupt Example: Communication between two SPI using Interrupts"; +__IO uint32_t TimeOut = 0; + +#ifdef SPI_SLAVE + __IO uint8_t RxBuffer [RXBUFFERSIZE]; + __IO uint8_t Rx_Idx = 0; +#endif +#ifdef SPI_MASTER + JOYState_TypeDef ReleasedButton = JOY_NONE; + JOYState_TypeDef PressedButton = JOY_NONE; + __IO uint8_t Tx_Idx = 0; + __IO uint8_t CmdTransmitted = CMD_NONE; + __IO uint8_t CmdStatus = 0x00; + __IO uint8_t NumberOfByte = 0; +#endif + +/* Private function prototypes -----------------------------------------------*/ +static void SPI_Config(void); +static void SysTickConfig(void); + +#ifdef SPI_MASTER + static void TimeOut_UserCallback(void); +#endif + +#ifdef SPI_SLAVE + static TestStatus Buffercmp(uint8_t* pBuffer1, __IO uint8_t* pBuffer2, uint16_t BufferLength); + static void Fill_Buffer(__IO uint8_t *pBuffer, uint16_t BufferLength); +#endif + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* SPI configuration -------------------------------------------------------*/ + SPI_Config(); + + /* SysTick configuration ---------------------------------------------------*/ + SysTickConfig(); + + /* LEDs configuration ------------------------------------------------------*/ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + +#ifdef SPI_MASTER + /* Master board configuration ----------------------------------------------*/ + + /* Initialize push-buttons mounted on STM322xG-EVAL board */ + TimeOut = USER_TIMEOUT; + while ((IOE_Config() != IOE_OK) && (TimeOut != 0x00)) + { + } + + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Initializes the SPI communication */ + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_Init(SPIx, &SPI_InitStructure); + + /* The Data transfer is performed in the SPI interrupt routine */ + /* Enable the SPI peripheral */ + SPI_Cmd(SPIx, ENABLE); + + while (1) + { + /* Prepare Command to be transmitted -------------------------------------*/ + + /* Waiting joystick pressed */ + PressedButton = JOY_NONE; + while (PressedButton == JOY_NONE) + { + PressedButton = IOE_JoyStickGetState(); + } + + /* Waiting joystick released */ + ReleasedButton = IOE_JoyStickGetState(); + while ((PressedButton == ReleasedButton) && (ReleasedButton != JOY_NONE)) + { + ReleasedButton = IOE_JoyStickGetState(); + } + + /* For each joystick state correspond to a Transaction command -----------*/ + CmdTransmitted = CMD_NONE; + switch (PressedButton) + { + /* JOY_RIGHT button pressed */ + case JOY_RIGHT: + CmdTransmitted = CMD_RIGHT; + NumberOfByte = CMD_RIGHT_SIZE; + break; + /* JOY_LEFT button pressed */ + case JOY_LEFT: + CmdTransmitted = CMD_LEFT; + NumberOfByte = CMD_LEFT_SIZE; + break; + /* JOY_UP button pressed */ + case JOY_UP: + CmdTransmitted = CMD_UP; + NumberOfByte = CMD_UP_SIZE; + break; + /* JOY_DOWN button pressed */ + case JOY_DOWN: + CmdTransmitted = CMD_DOWN; + NumberOfByte = CMD_DOWN_SIZE; + break; + /* JOY_SEL button pressed */ + case JOY_SEL: + CmdTransmitted = CMD_SEL; + NumberOfByte = CMD_SEL_SIZE; + break; + default: + break; + } + + /* Master Transmit Command followed by Data Transaction ------------------*/ + CmdStatus = 0x00; + Tx_Idx = 0; + if (CmdTransmitted != CMD_NONE) + { + /* Enable the Tx buffer empty interrupt */ + SPI_I2S_ITConfig(SPIx, SPI_I2S_IT_TXE, ENABLE); + + /* Waiting the end of Data transfer */ + while (Tx_Idx < GetVar_NbrOfData()) + { + } + } + } +#endif /* SPI_MASTER */ + +#ifdef SPI_SLAVE + /* Slave board configuration -----------------------------------------------*/ + + /* Initializes the SPI communication */ + SPI_I2S_DeInit(SPIx); + SPI_InitStructure.SPI_Mode = SPI_Mode_Slave; + SPI_Init(SPIx, &SPI_InitStructure); + /* Enable the Rx buffer not empty interrupt */ + SPI_I2S_ITConfig(SPIx, SPI_I2S_IT_RXNE, ENABLE); + /* Enable the SPI peripheral */ + SPI_Cmd(SPIx, ENABLE); + + /* Infinite Loop */ + while (1) + { + + Rx_Idx = 0; + /* Clear the RxBuffer */ + Fill_Buffer(RxBuffer, TXBUFFERSIZE); + + /* Waiting Transaction Command Byte reception ----------------------------*/ + while (RxBuffer[0] == CMD_NONE) + { + } + + /* Waiting Transaction Data reception ------------------------------------*/ + TimeOut = 1; + while (TimeOut != 0x00) + { + } + + /* Check Transaction data correctness ------------------------------------*/ + switch (RxBuffer[0]) + { + /* CMD_RIGHT command received */ + case CMD_RIGHT: + if (Buffercmp(TxBuffer, &RxBuffer[1], CMD_RIGHT_SIZE) != FAILED) + { + /* Turn ON LED2 and LED3 */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + /* Turn OFF LED4 */ + STM_EVAL_LEDOff(LED4); + } + break; + /* CMD_LEFT command received */ + case CMD_LEFT: + if (Buffercmp(TxBuffer, &RxBuffer[1], CMD_LEFT_SIZE) != FAILED) + { + /* Turn ON LED4 */ + STM_EVAL_LEDOn(LED4); + /* Turn OFF LED2 and LED3 */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + } + break; + /* CMD_UP command received */ + case CMD_UP: + if (Buffercmp(TxBuffer, &RxBuffer[1], CMD_UP_SIZE) != FAILED) + { + /* Turn ON LED2 */ + STM_EVAL_LEDOn(LED2); + /* Turn OFF LED3 and LED4 */ + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + } + break; + /* CMD_DOWN command received */ + case CMD_DOWN: + if (Buffercmp(TxBuffer, &RxBuffer[1], CMD_DOWN_SIZE) != FAILED) + { + /* Turn ON LED3 */ + STM_EVAL_LEDOn(LED3); + /* Turn OFF LED2 and LED4 */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED4); + } + break; + /* CMD_SEL command received */ + case CMD_SEL: + if (Buffercmp(TxBuffer, &RxBuffer[1], CMD_SEL_SIZE) != FAILED) + { + /* Turn ON LED2, LED3 and LED4 */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + } + break; + default: + break; + } + } +#endif /* SPI_SLAVE */ +} + +/** + * @brief Configures the SPI Peripheral. + * @param None + * @retval None + */ +static void SPI_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* Peripheral Clock Enable -------------------------------------------------*/ + /* Enable the SPI clock */ + SPIx_CLK_INIT(SPIx_CLK, ENABLE); + + /* Enable GPIO clocks */ + RCC_AHB1PeriphClockCmd(SPIx_SCK_GPIO_CLK | SPIx_MISO_GPIO_CLK | SPIx_MOSI_GPIO_CLK, ENABLE); + + /* SPI GPIO Configuration --------------------------------------------------*/ + /* Connect SPI pins to AF5 */ + GPIO_PinAFConfig(SPIx_SCK_GPIO_PORT, SPIx_SCK_SOURCE, SPIx_SCK_AF); + GPIO_PinAFConfig(SPIx_MOSI_GPIO_PORT, SPIx_MOSI_SOURCE, SPIx_MOSI_AF); + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; + + /* SPI SCK pin configuration */ + GPIO_InitStructure.GPIO_Pin = SPIx_SCK_PIN; + GPIO_Init(SPIx_SCK_GPIO_PORT, &GPIO_InitStructure); + + /* SPI MOSI pin configuration */ + GPIO_InitStructure.GPIO_Pin = SPIx_MOSI_PIN; + GPIO_Init(SPIx_MOSI_GPIO_PORT, &GPIO_InitStructure); + + /* SPI configuration -------------------------------------------------------*/ + SPI_I2S_DeInit(SPIx); + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + + /* Configure the Priority Group to 1 bit */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + + /* Configure the SPI interrupt priority */ + NVIC_InitStructure.NVIC_IRQChannel = SPIx_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +/** + * @brief Configure a SysTick Base time to 10 ms. + * @param None + * @retval None + */ +static void SysTickConfig(void) +{ + /* Setup SysTick Timer for 10ms interrupts */ + if (SysTick_Config(SystemCoreClock / 100)) + { + /* Capture error */ + while (1); + } + + /* Configure the SysTick handler priority */ + NVIC_SetPriority(SysTick_IRQn, 0x0); +} + +#ifdef SPI_MASTER +/** + * @brief Returns NumberOfByte variable value. + * @param None + * @retval Tx Buffer Size (NumberOfByte). + */ +uint8_t GetVar_NbrOfData(void) +{ + return NumberOfByte; +} +/** +* @brief Basic management of the timeout situation. +* @param None. +* @retval None. +*/ +static void TimeOut_UserCallback(void) +{ + /* User can add his own implementation to manage TimeOut Communication failure */ + /* Block communication and all processes */ + while(1) + { + } +} +#endif + +#ifdef SPI_SLAVE +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer1 identical to pBuffer2 + * FAILED: pBuffer1 differs from pBuffer2 + */ +static TestStatus Buffercmp(uint8_t* pBuffer1, __IO uint8_t* pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} + +/** + * @brief Fills buffer. + * @param pBuffer: pointer on the Buffer to fill + * @param BufferLength: size of the buffer to fill + * @retval None + */ +static void Fill_Buffer(__IO uint8_t *pBuffer, uint16_t BufferLength) +{ + uint32_t index = 0; + + /* Put in global buffer same values */ + for (index = 0; index < BufferLength; index++ ) + { + pBuffer[index] = 0x00; + } +} +#endif /* SPI_SLAVE */ + + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/main.h new file mode 100644 index 000000000..413ac06b5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/main.h @@ -0,0 +1,116 @@ +/** + ****************************************************************************** + * @file SPI/SPI_TwoBoards/DataExchangeInterrupt/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stm322xg_eval_ioe.h" + +/* Exported typedef -----------------------------------------------------------*/ +#define countof(a) (sizeof(a) / sizeof(*(a))) +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Exported define ------------------------------------------------------------*/ +/* Uncomment the line below if you will use the SPI peripheral as a Master */ +/* #define SPI_MASTER */ +/* Uncomment the line below if you will use the SPI peripheral as a Slave */ +#define SPI_SLAVE + +/* USER_TIMEOUT value for waiting loops. This timeout is just guarantee that the + application will not remain stuck if the USART communication is corrupted. + You may modify this timeout value depending on CPU frequency and application + conditions (interrupts routines, number of data to transfer, baudrate, CPU + frequency...). */ +#define USER_TIMEOUT ((uint32_t)0x64) /* Waiting 1s */ + +/* SPIx Communication boards Interface */ +#define SPIx SPI2 +#define SPIx_CLK RCC_APB1Periph_SPI2 +#define SPIx_CLK_INIT RCC_APB1PeriphClockCmd +#define SPIx_IRQn SPI2_IRQn +#define SPIx_IRQHANDLER SPI2_IRQHandler + +#define SPIx_SCK_PIN GPIO_Pin_1 +#define SPIx_SCK_GPIO_PORT GPIOI +#define SPIx_SCK_GPIO_CLK RCC_AHB1Periph_GPIOI +#define SPIx_SCK_SOURCE GPIO_PinSource1 +#define SPIx_SCK_AF GPIO_AF_SPI2 + +#define SPIx_MISO_PIN GPIO_Pin_2 +#define SPIx_MISO_GPIO_PORT GPIOI +#define SPIx_MISO_GPIO_CLK RCC_AHB1Periph_GPIOI +#define SPIx_MISO_SOURCE GPIO_PinSource2 +#define SPIx_MISO_AF GPIO_AF_SPI2 + +#define SPIx_MOSI_PIN GPIO_Pin_3 +#define SPIx_MOSI_GPIO_PORT GPIOI +#define SPIx_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOI +#define SPIx_MOSI_SOURCE GPIO_PinSource3 +#define SPIx_MOSI_AF GPIO_AF_SPI2 + +#define TXBUFFERSIZE (countof(TxBuffer) - 1) +#define RXBUFFERSIZE TXBUFFERSIZE + +/* Joystick Commands */ +#define CMD_RIGHT 0x55 +#define CMD_LEFT 0xAA +#define CMD_UP 0x33 +#define CMD_DOWN 0xCC +#define CMD_SEL 0xFF +#define CMD_NONE 0x00 +#define CMD_ACK 0x66 + +/* Define numbers of bytes to transmit from TxBuffer */ +#define CMD_RIGHT_SIZE 0x01 +#define CMD_LEFT_SIZE 0x05 +#define CMD_UP_SIZE 0x14 +#define CMD_DOWN_SIZE 0x1E +#define CMD_SEL_SIZE TXBUFFERSIZE + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +#ifdef SPI_MASTER + uint8_t GetVar_NbrOfData(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/readme.txt new file mode 100644 index 000000000..f974b02ba --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/readme.txt @@ -0,0 +1,147 @@ +/** + @page SPI_DataExchangeInterrupt SPI Communication Boards Data Exchange using interrupt example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file SPI/SPI_TwoBoards/DataExchangeInterrupt/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the SPI Communication Boards Data Exchange using + * interrupt example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a small application in which joystick buttons are used +to trigger SPI communication using interrupts and though using SPI firmware +library. + +- Hardware Description + +To use this example, you need to load it on two STM32 boards (let's call them +BoardA and BoardB) then connect these two boards through SPI lines and GND. +In the firmware example uncomment the dedicated line in the main.h file to use +the SPI peripheral as STM32 Master device or as STM32 Slave . + +@verbatim +*------------------------------------------------------------------------------* +| BoardA BoardB | +| ____________________ ____________________ | +| | | | | | +| | | | | | +| | __________ | | __________ | | +| | |SPI Master|____|_______SCK_______|____|SPI Slave | | | +| | | Device |____|_______MOSI______|____| Device | | | +| | |__________| | | |__________| | | +| | | | | | +| | O LD1 | | O LD1 | | +| | O LD2 Joystick | | O LD2 Joystick | | +| | O LD3 _ | | O LD3 _ | | +| | O LD4 |_| | | O LD4 |_| | | +| | | | | | +| | GND O--|-----------------|--O GND | | +| |____________________| |____________________| | +| | +| | +*------------------------------------------------------------------------------* +@endverbatim + +@note The connection between the pins should use a short wires and a common Ground. + +- Software Description +In master board, SPI peripheral is configured as Master full duplex with Interrupt, +whereas in Slave board, SPI peripheral is configured as Slave Full duplex with Interrupt. + +At each joystick buttons press: +- The Master sends a specific command to the Slave, the command contains the + transaction code (CMD_RIGHT, CMD_LEFT, CMD_UP, CMD_DOWN or CMD_SEL), then + the defined NumberOfByte from TxBuffer. + + +- The Slave after checking the received command, compares the NumberOfByte received data + with the defined ones into TxBuffer. Received data correctness is signaled by LED + lightening and though as follow: + - Received command CMD_RIGHT and data correctly received --> LD2 and LD3 ON + - Received command CMD_LEFT and data correctly received --> LD4 ON + - Received command CMD_UP and data correctly received --> LD2 ON + - Received command CMD_DOWN and data correctly received --> LD3 ON + - Received command CMD_SEL and data correctly received --> LD2, LD3 and LD4 ON + +In both boards, the data transfers is managed using SPIx_IRQHandler in stm32f2xx_it.c +file. +The SysTick is configured to generate interrupt each 10ms. A dedicated counter +inside the SysTick ISR is used to toggle LD1 each 100ms indicating that the +firmware is running. +These operations can be repeated infinitely. + + +A defined communication timeout is insuring that the application will not remain +stuck if the SPI communication is corrupted. +You can adjust this timeout through the USER_TIMEOUT define inside main.h file +depending on CPU frequency and application conditions (interrupts routines, +number of data to transfer, baudrate, CPU frequency...). +When a given operation is not finished within the defined timeout, a callback is +made to the function "TimeOut_UserCallback()", this function is used to manage +timeout communication failure. In this example, this callback implements a simple +infinite loop, but user can add his own implementation to manage timeout failure. + + +@par Directory contents + + - SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h Library Configuration file + - SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c Interrupt handlers + - SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h Interrupt handlers header file + - SPI/SPI_TwoBoards/DataExchangeInterrupt/main.c Main program + - SPI/SPI_TwoBoards/DataExchangeInterrupt/main.h Main program header file + - SPI/SPI_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool. + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB (with no additional + hardware), and can be easily tailored to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + - Use the Joystick Push Button + - Connect BoardA SPI2 SCK pin (PI1) to BoardB SPI2 SCK pin (PI1) + - Connect BoardA SPI2 MOSI pin (PI3) to BoardB SPI2 MOSI pin (PI3) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h new file mode 100644 index 000000000..3ef5830de --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c new file mode 100644 index 000000000..a3846bf0d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SPI_DataExchangeInterrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +#ifdef SPI_SLAVE + extern __IO uint8_t RxBuffer[]; + extern __IO uint8_t Rx_Idx; +#endif +#ifdef SPI_MASTER + extern __IO uint8_t CmdTransmitted; + extern __IO uint8_t Tx_Idx; + extern __IO uint8_t CmdStatus; +#endif + +extern uint8_t TxBuffer[]; +extern __IO uint32_t TimeOut; +__IO uint8_t Counter = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + /* Decrement the timeout value */ + if (TimeOut != 0) + { + TimeOut--; + } + + if (Counter < 10) + { + Counter++; + } + else + { + Counter = 0; + STM_EVAL_LEDToggle(LED1); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles SPI interrupt request. + * @param None + * @retval None + */ +void SPIx_IRQHANDLER(void) +{ +#ifdef SPI_SLAVE + /* SPI in Slave Receiver mode--------------------------------------- */ + if (SPI_I2S_GetITStatus(SPIx, SPI_I2S_IT_RXNE) == SET) + { + RxBuffer[Rx_Idx++] = SPI_I2S_ReceiveData(SPIx); + } +#endif +#ifdef SPI_MASTER + /* SPI in Master Tramitter mode--------------------------------------- */ + if (SPI_I2S_GetITStatus(SPIx, SPI_I2S_IT_TXE) == SET) + { + if (CmdStatus == 0x00) + { + /* Send Transaction code */ + SPI_I2S_SendData(SPIx, CmdTransmitted); + CmdStatus = 0x01; + } + else + { + if (Tx_Idx < GetVar_NbrOfData()) + { + /* Send Transaction data */ + SPI_I2S_SendData(SPIx, TxBuffer[Tx_Idx++]); + } + else + { + /* Disable the Tx buffer empty interrupt */ + SPI_I2S_ITConfig(SPIx, SPI_I2S_IT_TXE, DISABLE); + } + } + } +#endif /* SPI_SLAVE */ +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h new file mode 100644 index 000000000..ed559f09b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h @@ -0,0 +1,61 @@ +/** + ****************************************************************************** + * @file SPI/SPI_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void SPIx_IRQHANDLER(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SPI/SPI_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/main.c new file mode 100644 index 000000000..841dfd81c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/main.c @@ -0,0 +1,179 @@ +/** + ****************************************************************************** + * @file SysTick/SysTick_Example/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SysTick_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +GPIO_InitTypeDef GPIO_InitStructure; +static __IO uint32_t TimingDelay; + +/* Private function prototypes -----------------------------------------------*/ +void Delay(__IO uint32_t nTime); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize Leds mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Turn on LED1 and LED3 */ + STM_EVAL_LEDOn(LED1); + STM_EVAL_LEDOn(LED3); + + /* Setup SysTick Timer for 1 msec interrupts. + ------------------------------------------ + 1. The SysTick_Config() function is a CMSIS function which configure: + - The SysTick Reload register with value passed as function parameter. + - Configure the SysTick IRQ priority to the lowest value (0x0F). + - Reset the SysTick Counter register. + - Configure the SysTick Counter clock source to be Core Clock Source (HCLK). + - Enable the SysTick Interrupt. + - Start the SysTick Counter. + + 2. You can change the SysTick Clock source to be HCLK_Div8 by calling the + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8) just after the + SysTick_Config() function call. The SysTick_CLKSourceConfig() is defined + inside the misc.c file. + + 3. You can change the SysTick IRQ priority by calling the + NVIC_SetPriority(SysTick_IRQn,...) just after the SysTick_Config() function + call. The NVIC_SetPriority() is defined inside the core_cm3.h file. + + 4. To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + + - Reload Value is the parameter to be passed for SysTick_Config() function + - Reload Value should not exceed 0xFFFFFF + */ + if (SysTick_Config(SystemCoreClock / 1000)) + { + /* Capture error */ + while (1); + } + + while (1) + { + /* Toggle LED2 and LED4 */ + STM_EVAL_LEDToggle(LED2); + STM_EVAL_LEDToggle(LED4); + + /* Insert 50 ms delay */ + Delay(50); + + /* Toggle LED1 and LED3 */ + STM_EVAL_LEDToggle(LED1); + STM_EVAL_LEDToggle(LED3); + + /* Insert 100 ms delay */ + Delay(100); + } +} + +/** + * @brief Inserts a delay time. + * @param nTime: specifies the delay time length, in milliseconds. + * @retval None + */ +void Delay(__IO uint32_t nTime) +{ + TimingDelay = nTime; + + while(TimingDelay != 0); +} + +/** + * @brief Decrements the TimingDelay variable. + * @param None + * @retval None + */ +void TimingDelay_Decrement(void) +{ + if (TimingDelay != 0x00) + { + TimingDelay--; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/main.h new file mode 100644 index 000000000..e038c2c1e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/main.h @@ -0,0 +1,44 @@ +/** + ****************************************************************************** + * @file SysTick/SysTick_Example/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TimingDelay_Decrement(void); + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/readme.txt new file mode 100644 index 000000000..a96f26acc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/readme.txt @@ -0,0 +1,77 @@ +/** + @page SysTick_Example SysTick Configuration example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file SysTick/SysTick_Example/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the SysTick Configuration example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the SysTick to generate a time base equal to +1 ms. The system clock is set to 120 MHz, the SysTick is clocked by the AHB clock +(HCLK). + +A "Delay" function is implemented based on the SysTick end-of-count event. +Four LEDs are toggled with a timing defined by the Delay function. + +@par Directory contents + + - SysTick/SysTick_Example/stm32f2xx_conf.h Library Configuration file + - SysTick/SysTick_Example/stm32f2xx_it.c Interrupt handlers + - SysTick/SysTick_Example/stm32f2xx_it.h Header for stm32f2xx_it.c + - SysTick/SysTick_Example/main.c Main program + - SysTick/SysTick_Example/main.h Header for main.c + - SysTick/SysTick_Example/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/stm32f2xx_conf.h new file mode 100644 index 000000000..c748e304e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file SysTick/SysTick_Example/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/stm32f2xx_it.c new file mode 100644 index 000000000..c4a8345cd --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/stm32f2xx_it.c @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file SysTick/SysTick_Example/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup SysTick_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + TimingDelay_Decrement(); +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/stm32f2xx_it.h new file mode 100644 index 000000000..8520a4528 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file SysTick/SysTick_Example/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/SysTick/SysTick_Example/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/main.c new file mode 100644 index 000000000..6964bc329 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/main.c @@ -0,0 +1,248 @@ +/** + ****************************************************************************** + * @file TIM/6Steps/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_6Steps + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +TIM_BDTRInitTypeDef TIM_BDTRInitStructure; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); +void SysTickConfig(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* SysTick Configuration */ + SysTickConfig(); + + /* TIM1 Configuration */ + TIM_Config(); + + /*---------------------------------------------------------------------------- + The STM32F2xx TIM1 peripheral offers the possibility to program in advance the + configuration for the next TIM1 outputs behaviour (step) and change the configuration + of all the channels at the same time. This operation is possible when the COM + (commutation) event is used. + The COM event can be generated by software by setting the COM bit in the TIM1_EGR + register or by hardware (on TRC rising edge). + In this example, a software COM event is generated each 100 ms: using the SysTick + interrupt. + The TIM1 is configured in Timing Mode, each time a COM event occurs, a new TIM1 + configuration will be set in advance. + + The following Table describes the TIM1 Channels states: + ----------------------------------------------- + | Step1 | Step2 | Step3 | Step4 | Step5 | Step6 | + ---------------------------------------------------------- + |Channel1 | 1 | 0 | 0 | 0 | 0 | 1 | + ---------------------------------------------------------- + |Channel1N | 0 | 0 | 1 | 1 | 0 | 0 | + ---------------------------------------------------------- + |Channel2 | 0 | 0 | 0 | 1 | 1 | 0 | + ---------------------------------------------------------- + |Channel2N | 1 | 1 | 0 | 0 | 0 | 0 | + ---------------------------------------------------------- + |Channel3 | 0 | 1 | 1 | 0 | 0 | 0 | + ---------------------------------------------------------- + |Channel3N | 0 | 0 | 0 | 0 | 1 | 1 | + ---------------------------------------------------------- + ----------------------------------------------------------------------------*/ + + /* Time Base configuration */ + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseStructure.TIM_Period = 4095; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; + + TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); + + /* Channel 1, 2,3 and 4 Configuration in PWM mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; + TIM_OCInitStructure.TIM_Pulse = 2047; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High; + TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set; + TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Set; + + TIM_OC1Init(TIM1, &TIM_OCInitStructure); + + TIM_OCInitStructure.TIM_Pulse = 1023; + TIM_OC2Init(TIM1, &TIM_OCInitStructure); + + TIM_OCInitStructure.TIM_Pulse = 511; + TIM_OC3Init(TIM1, &TIM_OCInitStructure); + + /* Automatic Output enable, Break, dead time and lock configuration*/ + TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable; + TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable; + TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStructure.TIM_DeadTime = 1; + TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable; + TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High; + TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable; + + TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure); + + TIM_CCPreloadControl(TIM1, ENABLE); + + TIM_ITConfig(TIM1, TIM_IT_COM, ENABLE); + + /* TIM1 counter enable */ + TIM_Cmd(TIM1, ENABLE); + + /* Main Output Enable */ + TIM_CtrlPWMOutputs(TIM1, ENABLE); + + while (1) + {} +} + +/** + * @brief Configure the TIM1 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* GPIOA and GPIOB clocks enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOE, ENABLE); + + /* TIM1 clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); + + /* GPIOA Configuration: Channel 1 and 3 as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_10; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* GPIOE Configuration: Channel 1 as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + /* GPIOB Configuration: BKIN, Channel 1N, 2N and 3N as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Connect TIM pins to AF1 */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource14, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_TIM1); + + /* Enable the TIM1 Trigger and commutation interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TIM1_TRG_COM_TIM11_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +/** + * @brief Configures the SysTick. + * @param None + * @retval None + */ +void SysTickConfig(void) +{ + /* Setup SysTick Timer for 100 msec interrupts */ + if (SysTick_Config((SystemCoreClock) / 10)) + { + /* Capture error */ + while (1); + } + + NVIC_SetPriority(SysTick_IRQn, 0x0); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} + +#endif +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/readme.txt new file mode 100644 index 000000000..f911d2036 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/readme.txt @@ -0,0 +1,107 @@ +/** + @page TIM_6Steps TIM 6 Steps example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/6Steps/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM 6 Steps example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the TIM1 peripheral to generate 6 Steps. +The STM32F2xx TIM1 peripheral offers the possibility to program in advance the +configuration for the next TIM1 outputs behaviour (step) and change the configuration +of all the channels at the same time. This operation is possible when the COM +(commutation) event is used. +The COM event can be generated by software by setting the COM bit in the TIM1_EGR +register or by hardware (on TRC rising edge). +In this example, a software COM event is generated each 100 ms: using the SysTick +interrupt. +The TIM1 is configured in Timing Mode, each time a COM event occurs, a new TIM1 +configuration will be set in advance. + +The break Polarity is used at High level. + +The following Table describes the TIM1 Channels states: + @verbatim + ----------------------------------------------- + | Step1 | Step2 | Step3 | Step4 | Step5 | Step6 | + ---------------------------------------------------------- + |Channel1 | 1 | 0 | 0 | 0 | 0 | 1 | + ---------------------------------------------------------- + |Channel1N | 0 | 0 | 1 | 1 | 0 | 0 | + ---------------------------------------------------------- + |Channel2 | 0 | 0 | 0 | 1 | 1 | 0 | + ---------------------------------------------------------- + |Channel2N | 1 | 1 | 0 | 0 | 0 | 0 | + ---------------------------------------------------------- + |Channel3 | 0 | 1 | 1 | 0 | 0 | 0 | + ---------------------------------------------------------- + |Channel3N | 0 | 0 | 0 | 0 | 1 | 1 | + ---------------------------------------------------------- + @endverbatim + +@par Directory contents + + - TIM/6Steps/stm32f2xx_conf.h Library Configuration file + - TIM/6Steps/stm32f2xx_it.c Interrupt handlers + - TIM/6Steps/stm32f2xx_it.h Interrupt handlers header file + - TIM/6Steps/main.c Main program + - TIM/6Steps/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG Set-up + - Connect the TIM1 pins to an oscilloscope to monitor the different waveforms: + - TIM1_CH3 pin (PA.10) + - TIM1_CH1N pin (PB.13) + - TIM1_CH2 pin (PE.11) + - TIM1_CH3N pin (PB.15) + - TIM1_CH1 pin (PA.08) + - TIM1_CH2N pin (PB.14) + - Connect the TIM1 break pin TIM1_BKIN pin (PB.12) to the GND. To generate a + break event, switch this pin level from 0V to 3.3V. + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/stm32f2xx_conf.h new file mode 100644 index 000000000..e02fd80f2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file TIM/6Steps/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/stm32f2xx_it.c new file mode 100644 index 000000000..108f6e73e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/stm32f2xx_it.c @@ -0,0 +1,294 @@ +/** + ****************************************************************************** + * @file TIM/6Steps/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_6Steps + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t step = 1; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + /* Generate TIM1 COM event by software */ + TIM_GenerateEvent(TIM1, TIM_EventSource_COM); +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles TIM1 Trigger and commutation and TIM11 + * global interrupts requests. + * @param None + * @retval None + */ +void TIM1_TRG_COM_TIM11_IRQHandler(void) +{ + /* Clear TIM1 COM pending bit */ + TIM_ClearITPendingBit(TIM1, TIM_IT_COM); + + if (step == 1) + { + /* Next step: Step 2 Configuration -------------------------------------- */ + /* Channel3 configuration */ + TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable); + + /* Channel1 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1); + TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable); + TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Disable); + + /* Channel2 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1 ); + TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Enable); + step++; + } + else if (step == 2) + { + /* Next step: Step 3 Configuration -------------------------------------- */ + /* Channel2 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1); + TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Enable); + + /* Channel3 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1); + TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Enable); + TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable); + + /* Channel1 configuration */ + TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Disable); + step++; + } + else if (step == 3) + { + /* Next step: Step 4 Configuration -------------------------------------- */ + /* Channel3 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1); + TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Enable); + TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable); + + /* Channel2 configuration */ + TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable); + + /* Channel1 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1); + TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Enable); + step++; + } + else if (step == 4) + { + /* Next step: Step 5 Configuration -------------------------------------- */ + /* Channel3 configuration */ + TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable); + + /* Channel1 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1); + TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Enable); + + /* Channel2 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1); + TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Enable); + TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable); + step++; + } + else if (step == 5) + { + /* Next step: Step 6 Configuration -------------------------------------- */ + /* Channel3 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1); + TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Enable); + + /* Channel1 configuration */ + TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Disable); + + /* Channel2 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_OCMode_PWM1); + TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Enable); + TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable); + step++; + } + else + { + /* Next step: Step 1 Configuration -------------------------------------- */ + /* Channel1 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_OCMode_PWM1); + TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable); + TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable); + + /* Channel3 configuration */ + TIM_SelectOCxM(TIM1, TIM_Channel_3, TIM_OCMode_PWM1); + TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Enable); + + /* Channel2 configuration */ + TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Disable); + TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Disable); + step = 1; + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/stm32f2xx_it.h new file mode 100644 index 000000000..37bf40858 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file TIM/6Steps/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TIM1_TRG_COM_TIM11_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/6Steps/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/main.c new file mode 100644 index 000000000..f5b45f337 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/main.c @@ -0,0 +1,215 @@ +/** + ****************************************************************************** + * @file TIM/7PWM_Output/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_7PWM_Output + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +uint16_t TimerPeriod = 0; +uint16_t Channel1Pulse = 0, Channel2Pulse = 0, Channel3Pulse = 0, Channel4Pulse = 0; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + /* TIM1 Configuration --------------------------------------------------- + Generate 7 PWM signals with 4 different duty cycles: + TIM1 input clock (TIM1CLK) is set to 2 * APB2 clock (PCLK2), since APB2 + prescaler is different from 1. + TIM1CLK = 2 * PCLK2 + PCLK2 = HCLK / 2 + => TIM1CLK = 2 * (HCLK / 2) = HCLK = SystemCoreClock + TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock + SystemCoreClock is set to 120 MHz for STM32F2xx devices + + The objective is to generate 7 PWM signal at 17.57 KHz: + - TIM1_Period = (SystemCoreClock / 17570) - 1 + The channel 1 and channel 1N duty cycle is set to 50% + The channel 2 and channel 2N duty cycle is set to 37.5% + The channel 3 and channel 3N duty cycle is set to 25% + The channel 4 duty cycle is set to 12.5% + The Timer pulse is calculated as follows: + - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100 + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + ----------------------------------------------------------------------- */ + /* Compute the value to be set in ARR regiter to generate signal frequency at 17.57 Khz */ + TimerPeriod = (SystemCoreClock / 17570 ) - 1; + /* Compute CCR1 value to generate a duty cycle at 50% for channel 1 and 1N */ + Channel1Pulse = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10); + /* Compute CCR2 value to generate a duty cycle at 37.5% for channel 2 and 2N */ + Channel2Pulse = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000); + /* Compute CCR3 value to generate a duty cycle at 25% for channel 3 and 3N */ + Channel3Pulse = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100); + /* Compute CCR4 value to generate a duty cycle at 12.5% for channel 4 */ + Channel4Pulse = (uint16_t) (((uint32_t) 125 * (TimerPeriod- 1)) / 1000); + + /* TIM1 clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 , ENABLE); + + /* Time Base configuration */ + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseStructure.TIM_Period = TimerPeriod; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; + + TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); + + /* Channel 1, 2,3 and 4 Configuration in PWM mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; + TIM_OCInitStructure.TIM_Pulse = Channel1Pulse; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; + TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High; + TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set; + TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset; + + TIM_OC1Init(TIM1, &TIM_OCInitStructure); + + TIM_OCInitStructure.TIM_Pulse = Channel2Pulse; + TIM_OC2Init(TIM1, &TIM_OCInitStructure); + + TIM_OCInitStructure.TIM_Pulse = Channel3Pulse; + TIM_OC3Init(TIM1, &TIM_OCInitStructure); + + TIM_OCInitStructure.TIM_Pulse = Channel4Pulse; + TIM_OC4Init(TIM1, &TIM_OCInitStructure); + + /* TIM1 counter enable */ + TIM_Cmd(TIM1, ENABLE); + + /* TIM1 Main Output Enable */ + TIM_CtrlPWMOutputs(TIM1, ENABLE); + + while (1) + {} +} + +/** + * @brief Configure the TIM1 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* GPIOA, GPIOB and GPIOE Clocks enable */ + RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOE , ENABLE); + + /* GPIOA Configuration: Channel 1, 3 and 4 as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_10 | GPIO_Pin_11; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource11, GPIO_AF_TIM1); + + /* GPIOE Configuration: Channel 2 as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 ; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11, GPIO_AF_TIM1); + + /* GPIOB Configuration: Channel 1N, 2N and 3N as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource14, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_TIM1); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/readme.txt new file mode 100644 index 000000000..328a482a7 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/readme.txt @@ -0,0 +1,91 @@ +/** + @page TIM_7PWM_Output TIM_7PWM_Output + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/7PWM_Output/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM 7PWM_Output example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the TIM1 peripheral to generate 7 PWM signals +with 4 different duty cycles (50%, 37.5%, 25% and 12.5%). + +TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock +SystemCoreClock is set to 120 MHz for STM32F2xx devices. + +The objective is to generate 7 PWM signal at 17.57 KHz: + - TIM1_Period = (SystemCoreClock / 17570) - 1 +The channel 1 and channel 1N duty cycle is set to 50% +The channel 2 and channel 2N duty cycle is set to 37.5% +The channel 3 and channel 3N duty cycle is set to 25% +The channel 4 duty cycle is set to 12.5% +The Timer pulse is calculated as follows: + - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100 + +The TIM1 waveform can be displayed using an oscilloscope. + + +@par Directory contents + + - TIM/7PWM_Output/stm32f2xx_conf.h Library Configuration file + - TIM/7PWM_Output/stm32f2xx_it.c Interrupt handlers + - TIM/7PWM_Output/stm32f2xx_it.h Interrupt handlers header file + - TIM/7PWM_Output/main.c Main program + - TIM/7PWM_Output/system_stm32f2xx.c STM32F2xx system clock configuration file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the TIM1 pins to an oscilloscope to monitor the different waveforms: + - TIM1_CH1 pin (PA.08) + - TIM1_CH1N pin (PB.13) + - TIM1_CH2 pin (PE.11) + - TIM1_CH2N pin (PB.14) + - TIM1_CH3 pin (PA.10) + - TIM1_CH3N pin (PB.15) + - TIM1_CH4 pin (PA.11) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/stm32f2xx_conf.h new file mode 100644 index 000000000..751495302 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file TIM/7PWM_Output/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/stm32f2xx_it.c new file mode 100644 index 000000000..eb7b1916d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/stm32f2xx_it.c @@ -0,0 +1,164 @@ +/** + ****************************************************************************** + * @file TIM/7PWM_Output/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_7PWM_Output + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/stm32f2xx_it.h new file mode 100644 index 000000000..65be3003c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/7PWM_Output/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/main.c new file mode 100644 index 000000000..6f2070344 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/main.c @@ -0,0 +1,242 @@ +/** + ****************************************************************************** + * @file TIM/Cascade_Synchro/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_Cascade_Synchro + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM2/3/4 Configuration */ + TIM_Config(); + + /* Timers synchronisation in cascade mode ---------------------------- + 1/TIM2 is configured as Master Timer: + - PWM Mode is used + - The TIM2 Update event is used as Trigger Output + + 2/TIM3 is slave for TIM2 and Master for TIM4, + - PWM Mode is used + - The ITR1(TIM2) is used as input trigger + - Gated mode is used, so start and stop of slave counter + are controlled by the Master trigger output signal(TIM2 update event). + - The TIM3 Update event is used as Trigger Output. + + 3/TIM4 is slave for TIM3, + - PWM Mode is used + - The ITR2(TIM3) is used as input trigger + - Gated mode is used, so start and stop of slave counter + are controlled by the Master trigger output signal(TIM3 update event). + + In this example TIM2 input clock (TIM2CLK) is set to 2 * APB1 clock (PCLK1), + since APB1 prescaler is different from 1. + TIM2CLK = 2 * PCLK1 + PCLK1 = HCLK / 4 + => TIM2CLK = HCLK / 2 = SystemCoreClock /2 + + The Master Timer TIM2 is running at TIM2 counter clock: + TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 234.375 KHz + and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%. + + The TIM3 is running: + - At (TIM2 frequency)/ (TIM3 period + 1) = 58.593 KHz and a duty cycle + equal to TIM3_CCR1/(TIM3_ARR + 1) = 25% + + The TIM4 is running: + - At (TIM3 frequency)/ (TIM4 period + 1) = 14.648 KHz and a duty cycle + equal to TIM4_CCR1/(TIM4_ARR + 1) = 25% + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + --------------------------------------------------------------------------- */ + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 255; + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure); + + TIM_TimeBaseStructure.TIM_Period = 3; + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); + + TIM_TimeBaseStructure.TIM_Period = 3; + TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); + + /* Master Configuration in PWM1 Mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 64; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + + TIM_OC1Init(TIM2, &TIM_OCInitStructure); + + /* Select the Master Slave Mode */ + TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Enable); + + /* Master Mode selection */ + TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update); + + /* Slaves Configuration: PWM1 Mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 1; + + TIM_OC1Init(TIM3, &TIM_OCInitStructure); + + TIM_OC1Init(TIM4, &TIM_OCInitStructure); + + /* Slave Mode selection: TIM3 */ + TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated); + TIM_SelectInputTrigger(TIM3, TIM_TS_ITR1); + + /* Select the Master Slave Mode */ + TIM_SelectMasterSlaveMode(TIM3, TIM_MasterSlaveMode_Enable); + + /* Master Mode selection: TIM3 */ + TIM_SelectOutputTrigger(TIM3, TIM_TRGOSource_Update); + + /* Slave Mode selection: TIM4 */ + TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated); + TIM_SelectInputTrigger(TIM4, TIM_TS_ITR2); + + /* TIM enable counter */ + TIM_Cmd(TIM3, ENABLE); + TIM_Cmd(TIM2, ENABLE); + TIM_Cmd(TIM4, ENABLE); + + while (1) + { + } +} + +/** + * @brief Configure the TIM2/3/4 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* TIM2, TIM3 and TIM4 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | + RCC_APB1Periph_TIM4, ENABLE); + + /* GPIOA and GPIOB clocks enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB, ENABLE); + + /* GPIOB Configuration: PB4(TIM3 CH1) as alternate function push-pull ------*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Connect TIM pins to AF2 */ + GPIO_PinAFConfig(GPIOB, GPIO_PinSource4, GPIO_AF_TIM3); + + /* GPIOB Configuration: PB6(TIM4 CH1) as alternate function push-pull ------*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Connect TIM pins to AF2 */ + GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_TIM4); + + /* GPIOA Configuration: PA0(TIM2 CH1) as alternate function push-pull ------*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Connect TIM pins to AF1 */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource0, GPIO_AF_TIM2); + +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt new file mode 100644 index 000000000..a0db5a0bf --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt @@ -0,0 +1,105 @@ +/** + @page TIM_Cascade_Synchro TIM Cascade Synchro example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/Cascade_Synchro/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM Cascade Synchro example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to synchronize TIM peripherals in cascade mode. +In this example three timers are used: + +Timers synchronisation in cascade mode: + +1/TIM2 is configured as Master Timer: + - PWM Mode is used + - The TIM2 Update event is used as Trigger Output + +2/TIM3 is slave for TIM2 and Master for TIM4, + - PWM Mode is used + - The ITR1(TIM2) is used as input trigger + - Gated mode is used, so start and stop of slave counter + are controlled by the Master trigger output signal(TIM2 update event). + - The TIM3 Update event is used as Trigger Output. + +3/TIM4 is slave for TIM3, + - PWM Mode is used + - The ITR2(TIM3) is used as input trigger + - Gated mode is used, so start and stop of slave counter are controlled by the + Master trigger output signal(TIM3 update event). + +The TIM2 counter clock is 60 MHz. + + The Master Timer TIM2 is running at TIM2 frequency : + TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 234.375 KHz + and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%. + + The TIM3 is running at: + (TIM2 frequency)/ (TIM3 period + 1) = 58.593 KHz and a duty cycle equal + to TIM3_CCR1/(TIM3_ARR + 1) = 25% + + The TIM4 is running at: + (TIM3 frequency)/ (TIM4 period + 1) = 14.648 Hz and a duty cycle equal + to TIM4_CCR1/(TIM4_ARR + 1) = 25% + +@par Directory contents + + - TIM/Cascade_Synchro/stm32f2xx_conf.h Library Configuration file + - TIM/Cascade_Synchro/stm32f2xx_it.c Interrupt handlers + - TIM/Cascade_Synchro/stm32f2xx_it.h Interrupt handlers header file + - TIM/Cascade_Synchro/main.c Main program + - TIM/Cascade_Synchro/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG Set-up + - Connect the following pins to an oscilloscope to monitor the different + waveforms: + - TIM2 CH1 (PA.00) + - TIM3 CH1 (PB.04) + - TIM4 CH1 (PB.06) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f2xx_conf.h new file mode 100644 index 000000000..956d52e2c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file TIM/Cascade_Synchro/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f2xx_it.c new file mode 100644 index 000000000..0365835a5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f2xx_it.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file TIM/Cascade_Synchro/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_Cascade_Synchro + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f2xx_it.h new file mode 100644 index 000000000..171c327b6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/Cascade_Synchro/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/main.c new file mode 100644 index 000000000..aca5dbc32 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/main.c @@ -0,0 +1,242 @@ +/** + ****************************************************************************** + * @file TIM/ComplementarySignals/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_ComplementarySignals + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +TIM_BDTRInitTypeDef TIM_BDTRInitStructure; +uint16_t TimerPeriod = 0; +uint16_t Channel1Pulse = 0, Channel2Pulse = 0, Channel3Pulse = 0; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM1 Configuration */ + TIM_Config(); + + /* --------------------------------------------------------------------------- + TIM1 Configuration to: + + 1/ Generate 3 complementary PWM signals with 3 different duty cycles: + + TIM1 input clock (TIM1CLK) is set to 2 * APB2 clock (PCLK2), since APB2 + prescaler is different from 1. + TIM1CLK = 2 * PCLK2 + PCLK2 = HCLK / 2 + => TIM1CLK = 2 * (HCLK / 2) = HCLK = SystemCoreClock + + TIM1CLK is fixed to SystemCoreClock, the TIM1 Prescaler is equal to 0 so the + TIM1 counter clock used is SystemCoreClock (120MHz). + + The objective is to generate PWM signal at 17.57 KHz: + - TIM1_Period = (SystemCoreClock / 17570) - 1 + + The Three Duty cycles are computed as the following description: + + The channel 1 duty cycle is set to 50% so channel 1N is set to 50%. + The channel 2 duty cycle is set to 25% so channel 2N is set to 75%. + The channel 3 duty cycle is set to 12.5% so channel 3N is set to 87.5%. + + The Timer pulse is calculated as follows: + - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100 + + 2/ Insert a dead time equal to (11/SystemCoreClock) ns + + 3/ Configure the break feature, active at High level, and using the automatic + output enable feature + + 4/ Use the Locking parameters level1. + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + --------------------------------------------------------------------------- */ + + /* Compute the value to be set in ARR register to generate signal frequency at 17.57 Khz */ + TimerPeriod = (SystemCoreClock / 17570) - 1; + + /* Compute CCR1 value to generate a duty cycle at 50% for channel 1 */ + Channel1Pulse = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10); + + /* Compute CCR2 value to generate a duty cycle at 25% for channel 2 */ + Channel2Pulse = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100); + + /* Compute CCR3 value to generate a duty cycle at 12.5% for channel 3 */ + Channel3Pulse = (uint16_t) (((uint32_t) 125 * (TimerPeriod - 1)) / 1000); + + /* Time Base configuration */ + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseStructure.TIM_Period = TimerPeriod; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; + + TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); + + /* Channel 1, 2 and 3 Configuration in PWM mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; + TIM_OCInitStructure.TIM_Pulse = Channel1Pulse; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; + TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low; + TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set; + TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset; + + TIM_OC1Init(TIM1, &TIM_OCInitStructure); + + TIM_OCInitStructure.TIM_Pulse = Channel2Pulse; + TIM_OC2Init(TIM1, &TIM_OCInitStructure); + + TIM_OCInitStructure.TIM_Pulse = Channel3Pulse; + TIM_OC3Init(TIM1, &TIM_OCInitStructure); + + /* Automatic Output enable, Break, dead time and lock configuration*/ + TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable; + TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable; + TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_1; + TIM_BDTRInitStructure.TIM_DeadTime = 11; + TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable; + TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High; + TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable; + + TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure); + + /* TIM1 counter enable */ + TIM_Cmd(TIM1, ENABLE); + + /* Main Output Enable */ + TIM_CtrlPWMOutputs(TIM1, ENABLE); + + while (1) + { + } +} + +/** + * @brief Configure the TIM1 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* GPIOA and GPIOB clocks enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOE, ENABLE); + + /* TIM1 clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); + + /* GPIOA Configuration: Channel 1 and 3 as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_10; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* GPIOA Configuration: Channel 2 as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + /* GPIOB Configuration: BKIN, Channel 1N, 2N and 3N as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Connect TIM pins to AF1 */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource14, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_TIM1); + + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11, GPIO_AF_TIM1); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/readme.txt new file mode 100644 index 000000000..0705df2f1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/readme.txt @@ -0,0 +1,97 @@ +/** + @page TIM_ComplementarySignals TIM Complementary Signals example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/ComplementarySignals/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM Complementary Signals example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the TIM1 peripheral to generate three +complementary TIM1 signals, to insert a defined dead time value, to use the break +feature and to lock the desired parameters. + +TIM1CLK is fixed to SystemCoreClock, the TIM1 Prescaler is equal to 0 so the +TIM1 counter clock used is SystemCoreClock (120MHz). + +The objective is to generate PWM signal at 17.57 KHz: + - TIM1_Period = (SystemCoreClock / 17570) - 1 + +The Three Duty cycles are computed as the following description: +The channel 1 duty cycle is set to 50% so channel 1N is set to 50%. +The channel 2 duty cycle is set to 25% so channel 2N is set to 75%. +The channel 3 duty cycle is set to 12.5% so channel 3N is set to 87.5%. +The Timer pulse is calculated as follows: + - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100 + +A dead time equal to 11/SystemCoreClock is inserted between the different +complementary signals, and the Lock level 1 is selected. +The break Polarity is used at High level. + +The TIM1 waveform can be displayed using an oscilloscope. + +@par Directory contents + + - TIM/ComplementarySignals/stm32f2xx_conf.h Library Configuration file + - TIM/ComplementarySignals/stm32f2xx_it.c Interrupt handlers + - TIM/ComplementarySignals/stm32f2xx_it.h Interrupt handlers header file + - TIM/ComplementarySignals/main.c Main program + - TIM/ComplementarySignals/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG Set-up + - Connect the TIM1 pins to an oscilloscope to monitor the different waveforms: + - TIM1_CH1 pin (PA.08) + - TIM1_CH1N pin (PB.13) + - TIM1_CH2 pin (PE.11) + - TIM1_CH2N pin (PB.14) + - TIM1_CH3 pin (PA.10) + - TIM1_CH3N pin (PB.15) + + - Connect the TIM1 break pin TIM1_BKIN pin (PB.12) to the GND. To generate a + break event, switch this pin level from 0V to 3.3V. + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/stm32f2xx_conf.h new file mode 100644 index 000000000..0470f7b12 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file TIM/ComplementarySignals/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/stm32f2xx_it.c new file mode 100644 index 000000000..53049a17d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/stm32f2xx_it.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file TIM/ComplementarySignals/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_ComplementarySignals + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/stm32f2xx_it.h new file mode 100644 index 000000000..ff2a7c8e7 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/ComplementarySignals/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/main.c new file mode 100644 index 000000000..da074a169 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/main.c @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file TIM/DMA/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_DMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TIM1_CCR3_ADDRESS 0x4001003C + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +uint16_t SRC_Buffer[3] = {0, 0, 0}; +uint16_t TimerPeriod = 0; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + /* TIM1 DMA Transfer example ------------------------------------------------- + + TIM1 input clock (TIM1CLK) is set to 2 * APB2 clock (PCLK2), since APB2 + prescaler is different from 1. + TIM1CLK = 2 * PCLK2 + PCLK2 = HCLK / 2 + => TIM1CLK = 2 * (HCLK / 2) = HCLK = SystemCoreClock + + TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock + SystemCoreClock is set to 120 MHz for STM32F2xx devices. + + The objective is to configure TIM1 channel 3 to generate complementary PWM + signal with a frequency equal to 17.57 KHz: + - TIM1_Period = (SystemCoreClock / 17570) - 1 + and a variable duty cycle that is changed by the DMA after a specific number of + Update DMA request. + + The number of this repetitive requests is defined by the TIM1 Repetion counter, + each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new + value defined by the SRC_Buffer . + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + -----------------------------------------------------------------------------*/ + /* Compute the value to be set in ARR regiter to generate signal frequency at 17.57 Khz */ + TimerPeriod = (SystemCoreClock / 17570 ) - 1; + /* Compute CCR1 value to generate a duty cycle at 50% */ + SRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10); + /* Compute CCR1 value to generate a duty cycle at 37.5% */ + SRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000); + /* Compute CCR1 value to generate a duty cycle at 25% */ + SRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100); + + /* TIM1 Peripheral Configuration -------------------------------------------*/ + /* TIM1 clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); + + /* Time Base configuration */ + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseStructure.TIM_Period = TimerPeriod; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_RepetitionCounter = 3; + + TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); + + /* Channel 3 Configuration in PWM mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; + TIM_OCInitStructure.TIM_Pulse = SRC_Buffer[0]; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; + TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low; + TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set; + TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset; + + TIM_OC3Init(TIM1, &TIM_OCInitStructure); + + /* TIM1 counter enable */ + TIM_Cmd(TIM1, ENABLE); + + /* DMA enable*/ + DMA_Cmd(DMA2_Stream6, ENABLE); + + /* TIM1 Update DMA Request enable */ + TIM_DMACmd(TIM1, TIM_DMA_CC3, ENABLE); + + /* Main Output Enable */ + TIM_CtrlPWMOutputs(TIM1, ENABLE); + + while (1) + {} +} + +/** + * @brief Configure the TIM1 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + DMA_InitTypeDef DMA_InitStructure; + + /* GPIOA and GPIOB clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB, ENABLE); + + /* GPIOA Configuration: Channel 3 as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 ; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_TIM1); + + /* GPIOB Configuration: Channel 3N as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_TIM1); + + /* DMA clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2 , ENABLE); + + DMA_DeInit(DMA2_Stream6); + DMA_InitStructure.DMA_Channel = DMA_Channel_6; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(TIM1_CCR3_ADDRESS) ; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)SRC_Buffer; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_BufferSize = 3; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; + DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_HalfWord; + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + + DMA_Init(DMA2_Stream6, &DMA_InitStructure); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/readme.txt new file mode 100644 index 000000000..8952d995d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/readme.txt @@ -0,0 +1,84 @@ +/** + @page TIM_DMA TIM DMA example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/DMA/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM DMA example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a description of how to use DMA with TIM1 Update request +to transfer Data from memory to TIM1 Capture Compare Register3. + +TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock +SystemCoreClock is set to 120 MHz for STM32F2xx Devices RevA, RevZ and RevB. + +The objective is to configure TIM1 channel 3 to generate complementary PWM +signal with a frequency equal to 17.57 KHz: + - TIM1_Period = (SystemCoreClock / 17570) - 1 +and a variable duty cycle that is changed by the DMA after a specific number of +Update DMA request. + +The number of this repetitive requests is defined by the TIM1 Repetion counter, +each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new +value defined by the SRC_Buffer. + + +@par Directory contents + + - TIM/DMA/stm32f2xx_conf.h Library Configuration file + - TIM/DMA/stm32f2xx_it.c Interrupt handlers + - TIM/DMA/stm32f2xx_it.h Interrupt handlers header file + - TIM/DMA/main.c Main program + - TIM/DMA/system_stm32f2xx.c STM32F2xx system clock configuration file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the TIM1 pins to an oscilloscope to monitor the different waveforms: + - TIM1 CH3 (PA.10) + - TIM1 CH3N (PB.15) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/stm32f2xx_conf.h new file mode 100644 index 000000000..bda7e6c6d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file TIM/DMA/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/stm32f2xx_it.c new file mode 100644 index 000000000..8a8e0d906 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/stm32f2xx_it.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file TIM/DMA/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_DMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/stm32f2xx_it.h new file mode 100644 index 000000000..7c76addf2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/DMA/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMA/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/main.c new file mode 100644 index 000000000..54c352d74 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/main.c @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file TIM/DMABurst/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_DMABurst + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TIM1_DMAR_ADDRESS ((uint32_t)0x4001004C) /* TIM DMAR address */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +GPIO_InitTypeDef GPIO_InitStructure; +DMA_InitTypeDef DMA_InitStructure; +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +uint16_t SRC_Buffer[6] = {0x0FFF, 0x0000, 0x0555}; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM1 Configuration */ + TIM_Config(); + + /* Time base configuration */ + /* ----------------------------------------------------------------------- + TIM1 Configuration: generate 1 PWM signal using the DMA burst mode: + + TIM1 input clock (TIM1CLK) is set to 2 * APB2 clock (PCLK2), + since APB2 prescaler is different from 1. + TIM1CLK = 2 * PCLK2 + PCLK2 = HCLK / 2 + => TIM1CLK = 2 * (HCLK / 2) = HCLK = SystemCoreClock + + To get TIM1 counter clock at 24 MHz, the prescaler is computed as follows: + Prescaler = (TIM1CLK / TIM1 counter clock) - 1 + Prescaler = (SystemCoreClock /24 MHz) - 1 + + The TIM1 period is 5.8 KHz: TIM1 Frequency = TIM1 counter clock/(ARR + 1) + = 24 MHz / 4096 = 5.85 KHz + TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR)* 100 = 33.33% + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + ----------------------------------------------------------------------- */ + TIM_TimeBaseStructure.TIM_Period = 0xFFFF; + TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t) (SystemCoreClock / 24000000) - 1; + TIM_TimeBaseStructure.TIM_ClockDivision = 0x0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); + + /* TIM Configuration in PWM Mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 0xFFF; + TIM_OC1Init(TIM1, &TIM_OCInitStructure); + + /* TIM1 DMAR Base register and DMA Burst Length Config */ + TIM_DMAConfig(TIM1, TIM_DMABase_ARR, TIM_DMABurstLength_3Transfers); + + /* TIM1 DMA Update enable */ + TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE); + + /* TIM1 enable */ + TIM_Cmd(TIM1, ENABLE); + + /* TIM1 PWM Outputs Enable */ + TIM_CtrlPWMOutputs(TIM1, ENABLE); + + /* Enable DMA2 Stream5 */ + DMA_Cmd(DMA2_Stream5, ENABLE); + + /* Wait until DMA2 Stream5 end of Transfer */ + while (!DMA_GetFlagStatus(DMA2_Stream5, DMA_FLAG_TCIF5)) + { + } + + /* Infinite loop */ + while(1) + { + } +} + +/** + * @brief Configure the TIM1 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* TIM1 clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); + + /* GPIOA clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + + /* DMA2 clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); + + /* GPIOA Configuration: PA8(TIM1 CH1) as alternate function push-pull ------*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Connect TIM pins to AF1 */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_TIM1); + + /* DeInitialize the DMA2 Stream5 */ + DMA_DeInit(DMA2_Stream5); + + DMA_InitStructure.DMA_Channel = DMA_Channel_6; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_DMAR_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)SRC_Buffer; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_BufferSize = 3; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(DMA2_Stream5, &DMA_InitStructure); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/readme.txt new file mode 100644 index 000000000..9603c9040 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/readme.txt @@ -0,0 +1,95 @@ +/** + @page TIM1_DMABURST TIM1 DMA Burst transfer example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/DMABurst/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM1 DMA Burst transfer example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to update the TIM1 channel1 period and the duty cycle +using the TIM1 DMA burst feature. + +Every update DMA request, the DMA will do 3 transfers of half words into Timer +registers beginning from ARR register. +On the DMA update request, 0x0FFF will be transferred into ARR, 0x0000 +will be transferred into RCR, 0x0555 will be transferred into CCR1. + +The TIM1CLK frequency is set to SystemCoreClock (Hz), to get TIM1 counter +clock at 24 MHz the Prescaler is computed as following: + - Prescaler = (TIM1CLK / TIM1 counter clock) - 1 + +SystemCoreClock is set to 120 MHz. + +The TIM1 period is 5.8 KHz: TIM1 Frequency = TIM1 counter clock/(ARR + 1) + = 24 MHz / 4096 = 5.8 KHz + +The TIM1 CCR1 register value is equal to 0x555, so the TIM1 Channel 1 generates a +PWM signal with a frequency equal to 5.8 KHz and a duty cycle equal to 33.33%: +TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR + 1)* 100 = 33.33% + +The PWM waveform can be displayed using an oscilloscope. + +@note No need of RCR update, but we should do it because of the ARR and CCR1 + mapping. + +@par Directory contents + + - TIM/DMABurst/stm32f2xx_conf.h Library Configuration file + - TIM/DMABurst/stm32f2xx_it.c Interrupt handlers + - TIM/DMABurst/stm32f2xx_it.h Interrupt handlers header file + - TIM/DMABurst/main.c Main program + - TIM/DMABurst/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the following pins to an oscilloscope to monitor the different + waveforms: + - TIM1 CH1 (PA.08) + +@par How to use it ? + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/stm32f2xx_conf.h new file mode 100644 index 000000000..4f254f35d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file TIM/DMABurst/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/stm32f2xx_it.c new file mode 100644 index 000000000..86f54d57e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/stm32f2xx_it.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file TIM/DMABurst/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_DMABurst + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/stm32f2xx_it.h new file mode 100644 index 000000000..de2011e99 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/DMABurst/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/DMABurst/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c new file mode 100644 index 000000000..47b773a5a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c @@ -0,0 +1,277 @@ +/** + ****************************************************************************** + * @file TIM/ExtTrigger_Synchro/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_ExtTrigger_Synchro + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_ICInitTypeDef TIM_ICInitStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + /* Timers synchronisation in cascade mode with an external trigger ----- + 1/TIM1 is configured as Master Timer: + - Toggle Mode is used + - The TIM1 Enable event is used as Trigger Output + + 2/TIM1 is configured as Slave Timer for an external Trigger connected + to TIM1 TI2 pin (TIM1 CH2 configured as input pin): + - The TIM1 TI2FP2 is used as Trigger Input + - Rising edge is used to start and stop the TIM1: Gated Mode. + + 3/TIM3 is slave for TIM1 and Master for TIM4, + - Toggle Mode is used + - The ITR1(TIM1) is used as input trigger + - Gated mode is used, so start and stop of slave counter + are controlled by the Master trigger output signal(TIM1 enable event). + - The TIM3 enable event is used as Trigger Output. + + 4/TIM4 is slave for TIM3, + - Toggle Mode is used + - The ITR2(TIM3) is used as input trigger + - Gated mode is used, so start and stop of slave counter + are controlled by the Master trigger output signal(TIM3 enable event). + + TIM1 input clock (TIM1CLK) is set to 2 * APB2 clock (PCLK2), + since APB2 prescaler is different from 1. + TIM1CLK = 2 * PCLK2 + PCLK2 = HCLK / 2 + => TIM1CLK = 2 * (HCLK / 2) = HCLK = SystemCoreClock + + TIM3/TIM4 input clock (TIM3CLK/TIM4CLK) is set to 2 * APB1 clock (PCLK1), + since APB1 prescaler is different from 1. + TIM3CLK/TIM4CLK = 2 * PCLK1 + PCLK1 = HCLK / 4 + => TIM3CLK/TIM4CLK = HCLK / 2 = SystemCoreClock /2 + + The TIM1CLK is fixed to 120 MHZ, the Prescaler is equal to 4 so the TIMx clock + counter is equal to 24 MHz. + The TIM3CLK and TIM4CLK are fixed to 60 MHZ, the Prescaler is equal to 4 + so the TIMx clock counter is equal to 12 MHz. + The Three Timers are running at: + TIMx frequency = TIMx clock counter/ 2*(TIMx_Period + 1) = 162.1 KHz. + + The starts and stops of the TIM1 counters are controlled by the + external trigger. + The TIM3 starts and stops are controlled by the TIM1, and the TIM4 + starts and stops are controlled by the TIM3. + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + -------------------------------------------------------------------- */ + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 73; + TIM_TimeBaseStructure.TIM_Prescaler = 4; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); + + TIM_TimeBaseStructure.TIM_Period = 36; + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); + + TIM_TimeBaseStructure.TIM_Period = 36; + TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); + + /* Master Configuration in Toggle Mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 64; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + + TIM_OC1Init(TIM1, &TIM_OCInitStructure); + + /* TIM1 Input Capture Configuration */ + TIM_ICInitStructure.TIM_Channel = TIM_Channel_2; + TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStructure.TIM_ICFilter = 0; + + TIM_ICInit(TIM1, &TIM_ICInitStructure); + + /* TIM1 Input trigger configuration: External Trigger connected to TI2 */ + TIM_SelectInputTrigger(TIM1, TIM_TS_TI2FP2); + TIM_SelectSlaveMode(TIM1, TIM_SlaveMode_Gated); + + /* Select the Master Slave Mode */ + TIM_SelectMasterSlaveMode(TIM1, TIM_MasterSlaveMode_Enable); + + /* Master Mode selection: TIM1 */ + TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Enable); + + /* Slaves Configuration: Toggle Mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 10; + TIM_OC1Init(TIM3, &TIM_OCInitStructure); + + TIM_OC1Init(TIM4, &TIM_OCInitStructure); + + /* Slave Mode selection: TIM3 */ + TIM_SelectInputTrigger(TIM3, TIM_TS_ITR0); + TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated); + + /* Select the Master Slave Mode */ + TIM_SelectMasterSlaveMode(TIM3, TIM_MasterSlaveMode_Enable); + + /* Master Mode selection: TIM3 */ + TIM_SelectOutputTrigger(TIM3, TIM_TRGOSource_Enable); + + /* Slave Mode selection: TIM4 */ + TIM_SelectInputTrigger(TIM4, TIM_TS_ITR2); + TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated); + + /* TIM1 Main Output Enable */ + TIM_CtrlPWMOutputs(TIM1, ENABLE); + + /* TIM enable counter */ + TIM_Cmd(TIM1, ENABLE); + TIM_Cmd(TIM3, ENABLE); + TIM_Cmd(TIM4, ENABLE); + + while (1) + {} +} + +/** + * @brief Configure the TIM Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* TIM3 and TIM4 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4, ENABLE); + + /* TIM1 clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); + + /* GPIOA and GPIOB clocks enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOE, ENABLE); + + /* GPIOA Configuration: PA.08(TIM1 CH1) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* GPIOE Configuration: PE.11(TIM1 CH2) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + /* Connect TIM pins to AF1 */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_TIM1); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11, GPIO_AF_TIM1); + + /* GPIOB Configuration: PB.06(TIM4 CH1) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Connect TIM pins to AF2 */ + GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_TIM4); + + /* GPIOC Configuration: PC.06(TIM3 CH1) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Connect TIM pins to AF2 */ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource6, GPIO_AF_TIM3); + + +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/readme.txt new file mode 100644 index 000000000..9c80fe128 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/readme.txt @@ -0,0 +1,108 @@ +/** + @page TIM_ExtTrigger_Synchro TIM External Trigger Synchro example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/ExtTrigger_Synchro/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM External Trigger Synchro example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to synchronize TIM peripherals in cascade mode with an +external trigger. +In this example three timers are used: + +1/TIM1 is configured as Master Timer: + - Toggle Mode is used + - The TIM1 Enable event is used as Trigger Output + +2/TIM1 is configured as Slave Timer for an external Trigger connected to TIM1 + TI2 pin (TIM1 CH2 configured as input pin): + - The TIM1 TI2FP2 is used as Trigger Input + - Rising edge is used to start and stop the TIM1: Gated Mode. + +3/TIM3 is slave for TIM1 and Master for TIM4, + - Toggle Mode is used + - The ITR1(TIM1) is used as input trigger + - Gated mode is used, so start and stop of slave counter + are controlled by the Master trigger output signal(TIM1 enable event). + - The TIM3 enable event is used as Trigger Output. + +4/TIM4 is slave for TIM3, + - Toggle Mode is used + - The ITR2(TIM3) is used as input trigger + - Gated mode is used, so start and stop of slave counter + are controlled by the Master trigger output signal(TIM3 enable event). + + The TIM1CLK is fixed to 120 MHZ, the Prescaler is equal to 4 so the TIMx clock + counter is equal to 24 MHz. + The TIM3CLK and TIM4CLK are fixed to 60 MHZ, the Prescaler is equal to 4 + so the TIMx clock counter is equal to 12 MHz. + The Three Timers are running at: + TIMx frequency = TIMx clock counter/ 2*(TIMx_Period + 1) = 162.1 KHz. + +The starts and stops of the TIM1 counters are controlled by the external trigger. +The TIM3 starts and stops are controlled by the TIM1, and the TIM4 starts and +stops are controlled by the TIM3. + +@par Directory contents + + - TIM/ExtTrigger_Synchro/stm32f2xx_conf.h Library Configuration file + - TIM/ExtTrigger_Synchro/stm32f2xx_it.c Interrupt handlers + - TIM/ExtTrigger_Synchro/stm32f2xx_it.h Interrupt handlers header file + - TIM/ExtTrigger_Synchro/main.c Main program + - TIM/ExtTrigger_Synchro/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect an external trigger, with a frequency <= 40KHz, to the TIM1 CH2 + pin (PE.11). In this example the frequency is equal to 5 KHz. + + - Connect the following pins to an oscilloscope to monitor the different waveforms: + - TIM1 CH1 (PA.08) + - TIM3 CH1 (PC.06) + - TIM4 CH1 (PB.06) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f2xx_conf.h new file mode 100644 index 000000000..f6a50b375 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file TIM/ExtTrigger_Synchro/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f2xx_it.c new file mode 100644 index 000000000..32cefba0b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f2xx_it.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file TIM/ExtTrigger_Synchro/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_ExtTrigger_Synchro + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f2xx_it.h new file mode 100644 index 000000000..4265f5993 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/ExtTrigger_Synchro/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/main.c new file mode 100644 index 000000000..bca6fa0ea --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/main.c @@ -0,0 +1,154 @@ +/** + ****************************************************************************** + * @file TIM/InputCapture/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_Input_Capture + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_ICInitTypeDef TIM_ICInitStructure; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM1 Configuration */ + TIM_Config(); + + /* TIM1 configuration: Input Capture mode --------------------- + The external signal is connected to TIM1 CH2 pin (PE.11) + The Rising edge is used as active edge, + The TIM1 CCR2 is used to compute the frequency value + ------------------------------------------------------------ */ + + TIM_ICInitStructure.TIM_Channel = TIM_Channel_2; + TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStructure.TIM_ICFilter = 0x0; + + TIM_ICInit(TIM1, &TIM_ICInitStructure); + + /* TIM enable counter */ + TIM_Cmd(TIM1, ENABLE); + + /* Enable the CC2 Interrupt Request */ + TIM_ITConfig(TIM1, TIM_IT_CC2, ENABLE); + + while (1); +} + +/** + * @brief Configure the TIM1 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* TIM1 clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); + + /* GPIOA clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE, ENABLE); + + /* TIM1 channel 2 pin (PE.11) configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + /* Connect TIM pins to AF2 */ + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11, GPIO_AF_TIM1); + + /* Enable the TIM1 global Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TIM1_CC_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/readme.txt new file mode 100644 index 000000000..deac62a96 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/readme.txt @@ -0,0 +1,83 @@ +/** + @page TIM_Input_Capture TIM Input Capture example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/InputCapture/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM Input Capture example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to use the TIM peripheral to measure the frequency of an +external signal. + +The TIMxCLK frequency is set to SystemCoreClock /2 (Hz), the Prescaler is 0 so the +TIM1 counter clock is SystemCoreClock (Hz)/2. + +SystemCoreClock is set to 120 MHz. + +TIM1 is configured in Input Capture Mode: the external signal is connected to +TIM1 Channel2 used as input pin. +To measure the frequency we use the TIM1 CC2 interrupt request, +so In the TIM1_CC_IRQHandler routine, the frequency of the external signal is computed. +The "TIM1Freq" variable contains the external signal frequency: +TIM1Freq = TIM1 counter clock / Capture in Hz, +where the Capture is the difference between two consecutive TIM1 captures. + +The minimum frequency value to measure is 1100 Hz. + +@par Directory contents + + - TIM/InputCapture/stm32f2xx_conf.h Library Configuration file + - TIM/InputCapture/stm32f2xx_it.c Interrupt handlers + - TIM/InputCapture/stm32f2xx_it.h Interrupt handlers header file + - TIM/InputCapture/main.c Main program + - TIM/InputCapture/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the external signal to measure to the TIM1 CH2 pin (PE.11). + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/stm32f2xx_conf.h new file mode 100644 index 000000000..ab76fe8d9 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file TIM/InputCapture/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/stm32f2xx_it.c new file mode 100644 index 000000000..37737403f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/stm32f2xx_it.c @@ -0,0 +1,215 @@ +/** + ****************************************************************************** + * @file TIM/InputCapture/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_Input_Capture + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint16_t IC3ReadValue1 = 0, IC3ReadValue2 = 0; +__IO uint16_t CaptureNumber = 0; +__IO uint32_t Capture = 0; +__IO uint32_t TIM1Freq = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ +/** + * @brief This function handles TIM1 global interrupt request. + * @param None + * @retval None + */ +void TIM1_CC_IRQHandler(void) +{ + if(TIM_GetITStatus(TIM1, TIM_IT_CC2) == SET) + { + /* Clear TIM1 Capture compare interrupt pending bit */ + TIM_ClearITPendingBit(TIM1, TIM_IT_CC2); + if(CaptureNumber == 0) + { + /* Get the Input Capture value */ + IC3ReadValue1 = TIM_GetCapture2(TIM1); + CaptureNumber = 1; + } + else if(CaptureNumber == 1) + { + /* Get the Input Capture value */ + IC3ReadValue2 = TIM_GetCapture2(TIM1); + + /* Capture computation */ + if (IC3ReadValue2 > IC3ReadValue1) + { + Capture = (IC3ReadValue2 - IC3ReadValue1); + } + else if (IC3ReadValue2 < IC3ReadValue1) + { + Capture = ((0xFFFF - IC3ReadValue1) + IC3ReadValue2); + } + else + { + Capture = 0; + } + /* Frequency computation */ + TIM1Freq = (uint32_t) SystemCoreClock / Capture; + CaptureNumber = 0; + } + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/stm32f2xx_it.h new file mode 100644 index 000000000..107aed96d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file TIM/InputCapture/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TIM1_CC_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/InputCapture/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/main.c new file mode 100644 index 000000000..35cf13925 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/main.c @@ -0,0 +1,214 @@ +/** + ****************************************************************************** + * @file TIM/OCActive/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_OCActive + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +uint16_t CCR1_Val = 1000; +uint16_t CCR2_Val = 500; +uint16_t CCR3_Val = 250; +uint16_t CCR4_Val = 125; +uint16_t PrescalerValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); + + TIM_OCStructInit(&TIM_OCInitStructure); + + + /* --------------------------------------------------------------------------- + TIM3 Configuration: Output Compare Active Mode: + In this example TIM3 input clock (TIM3CLK) is set to 2 * APB1 clock (PCLK1), + since APB1 prescaler is different from 1. + TIM3CLK = 2 * PCLK1 + PCLK1 = HCLK / 4 + => TIM3CLK = HCLK / 2 = SystemCoreClock /2 + + To get TIM3 counter clock at 1 KHz, the prescaler is computed as follows: + Prescaler = (TIM3CLK / TIM3 counter clock) - 1 + Prescaler = ((SystemCoreClock /2) /1 KHz) - 1 + + Generate 4 signals with 4 different delays: + TIM3_CH1 delay = CCR1_Val/TIM3 counter clock = 1000 ms + TIM3_CH2 delay = CCR2_Val/TIM3 counter clock = 500 ms + TIM3_CH3 delay = CCR3_Val/TIM3 counter clock = 250 ms + TIM3_CH4 delay = CCR4_Val/TIM3 counter clock = 125 ms + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + + --------------------------------------------------------------------------- */ + + /*Compute the prescaler value */ + PrescalerValue = (uint16_t) ((SystemCoreClock / 2) / 1000) - 1; + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 65535; + TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); + + /* Output Compare Active Mode configuration: Channel1 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Active; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR1_Val; + TIM_OC1Init(TIM3, &TIM_OCInitStructure); + + TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Disable); + TIM_ARRPreloadConfig(TIM3, DISABLE); + /* Output Compare Active Mode configuration: Channel2 */ + TIM_OCInitStructure.TIM_Pulse = CCR2_Val; + TIM_OC2Init(TIM3, &TIM_OCInitStructure); + + TIM_OC2PreloadConfig(TIM3, TIM_OCPreload_Disable); + + /* Output Compare Active Mode configuration: Channel3 */ + TIM_OCInitStructure.TIM_Pulse = CCR3_Val; + TIM_OC3Init(TIM3, &TIM_OCInitStructure); + + TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Disable); + + /* Output Compare Active Mode configuration: Channel4 */ + TIM_OCInitStructure.TIM_Pulse = CCR4_Val; + TIM_OC4Init(TIM3, &TIM_OCInitStructure); + + TIM_OC4PreloadConfig(TIM3, TIM_OCPreload_Disable); + + /* TIM3 enable counter */ + TIM_Cmd(TIM3, ENABLE); + + TIM_GenerateEvent(TIM3, TIM_EventSource_Update); + + /* Turn on LED1 */ + STM_EVAL_LEDOn(LED1); + + while (1) + {} +} + +/** + * @brief Configure the TIM3 pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* TIM3 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); + + /* GPIOC clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); + + /* GPIOC Configuration: TIM3 CH1 (PC6), TIM3 CH2 (PC7), TIM3 CH2 (PC8) and TIM3 CH4 (PC9) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Connect TIM Channels to AF2 */ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource6, GPIO_AF_TIM3); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource7, GPIO_AF_TIM3); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_TIM3); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_TIM3); + + /* Initialize Leds mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/readme.txt new file mode 100644 index 000000000..379896369 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/readme.txt @@ -0,0 +1,99 @@ +/** + @page TIM_OCActive TIM_OCActive + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/OCActive/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM OCActive example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the TIM peripheral to generate four different +signals with four different delays. + +The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), and the objective is +to get TIM3 counter clock at 1 KHz so the Prescaler is computed as following: + - Prescaler = (TIM3CLK / TIM3 counter clock) - 1 + +SystemCoreClock is set to 120 MHz for STM32F2xx Devices RevA, RevZ and RevB. + +The TIM3 CCR1 register value is equal to 1000: +TIM3_CH1 delay = CCR1_Val/TIM3 counter clock = 1000 ms +so the TIM3 Channel 1 generates a signal with a delay equal to 1000 ms. + +The TIM3 CCR2 register value is equal to 500: +TIM3_CH2 delay = CCR2_Val/TIM3 counter clock = 500 ms +so the TIM3 Channel 2 generates a signal with a delay equal to 500 ms. + +The TIM3 CCR3 register value is equal to 250: +TIM3_CH3 delay = CCR3_Val/TIM3 counter clock = 250 ms +so the TIM3 Channel 3 generates a signal with a delay equal to 250 ms. + +The TIM3 CCR4 register value is equal to 125: +TIM3_CH4 delay = CCR4_Val/TIM3 counter clock = 125 ms +so the TIM3 Channel 4 generates a signal with a delay equal to 125 ms. + +The delay correspond to the time difference between PG.06 and TIM3_CHx signal +rising edges. + +@par Directory contents + + - TIM/OCActive/stm32f2xx_conf.h Library Configuration file + - TIM/OCActive/stm32f2xx_it.c Interrupt handlers + - TIM/OCActive/stm32f2xx_it.h Interrupt handlers header file + - TIM/OCActive/main.c Main program + - TIM/OCActive/system_stm32f2xx.c STM32F2xx system clock configuration file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the following pins to an oscilloscope to monitor the different + waveforms: + - Use LED1 connected to PG.06 + - PC.06 (TIM3_CH1) + - PC.07 (TIM3_CH2) + - PC.08 (TIM3_CH3) + - PC.09 (TIM3_CH4) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/stm32f2xx_conf.h new file mode 100644 index 000000000..2019d42d3 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file TIM/OCActive/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/stm32f2xx_it.c new file mode 100644 index 000000000..27921146f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/stm32f2xx_it.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file TIM/OCActive/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_OCActive + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/stm32f2xx_it.h new file mode 100644 index 000000000..f953fa58e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/OCActive/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCActive/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/main.c new file mode 100644 index 000000000..bb3831052 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/main.c @@ -0,0 +1,232 @@ +/** + ****************************************************************************** + * @file TIM/OCInactive/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_OCInactive + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +uint16_t CCR1_Val = 1000; +uint16_t CCR2_Val = 500; +uint16_t CCR3_Val = 250; +uint16_t CCR4_Val = 125; +uint16_t PrescalerValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + /* --------------------------------------------------------------- + TIM2 Configuration: Output Compare Inactive Mode: + In this example TIM2 input clock (TIM2CLK) is set to 2 * APB1 clock (PCLK1), + since APB1 prescaler is different from 1. + TIM2CLK = 2 * PCLK1 + PCLK1 = HCLK / 4 + => TIM2CLK = HCLK / 2 = SystemCoreClock /2 + + To get TIM2 counter clock at 1 KHz, the prescaler is computed as follows: + Prescaler = (TIM2CLK / TIM2 counter clock) - 1 + Prescaler = ((SystemCoreClock /2) /1 KHz) - 1 + + Generate 4 signals with 4 different delays: + TIM2_CH1 delay = CCR1_Val/TIM2 counter clock = 1000 ms + TIM2_CH2 delay = CCR2_Val/TIM2 counter clock = 500 ms + TIM2_CH3 delay = CCR3_Val/TIM2 counter clock = 250 ms + TIM2_CH4 delay = CCR4_Val/TIM2 counter clock = 125 ms + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + + --------------------------------------------------------------- */ + /* Compute the prescaler value */ + PrescalerValue = (uint16_t) ((SystemCoreClock / 2) / 1000) - 1; + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 65535; + TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure); + + /* Output Compare Active Mode configuration: Channel1 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Inactive; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR1_Val; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + + TIM_OC1Init(TIM2, &TIM_OCInitStructure); + + TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Disable); + + /* Output Compare Active Mode configuration: Channel2 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR2_Val; + + TIM_OC2Init(TIM2, &TIM_OCInitStructure); + + TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Disable); + + /* Output Compare Active Mode configuration: Channel3 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR3_Val; + + TIM_OC3Init(TIM2, &TIM_OCInitStructure); + + TIM_OC3PreloadConfig(TIM2, TIM_OCPreload_Disable); + + /* Output Compare Active Mode configuration: Channel4 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR4_Val; + + TIM_OC4Init(TIM2, &TIM_OCInitStructure); + + TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Disable); + + TIM_ARRPreloadConfig(TIM2, ENABLE); + + /* Turn on LED1, LED2, LED3 and LED4 */ + STM_EVAL_LEDOn(LED1); + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + + /* TIM IT enable */ + TIM_ITConfig(TIM2, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4, ENABLE); + + /* TIM2 enable counter */ + TIM_Cmd(TIM2, ENABLE); + + while (1) + {} +} + +/** + * @brief Configure the TIM Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + /* TIM2 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); + + /* GPIOA clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + + /* GPIOC Configuration: TIM2 CH1 (PA0), TIM2 CH2 (PA1), TIM2 CH2 (PA2) and TIM2 CH4 (PA3) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Connect TIM Channels to AF1 */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource0, GPIO_AF_TIM2); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_TIM2); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_TIM2); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_TIM2); + + /* Initialize Leds mounted on STM324xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Enable the TIM2 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/readme.txt new file mode 100644 index 000000000..1a785e473 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/readme.txt @@ -0,0 +1,97 @@ +/** + @page TIM_OCInactive TIM_OCInactive + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/OCInactive/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM OCInactive example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the TIM peripheral in Output Compare Inactive +mode with the corresponding Interrupt requests for each channel. + +The TIM2CLK frequency is set to SystemCoreClock / 2 (Hz), and the objective is +to get TIM2 counter clock at 1 KHz so the Prescaler is computed as following: + - Prescaler = (TIM2CLK / TIM2 counter clock) - 1 +SystemCoreClock is set to 120 MHz for STM32F2xx devices + +The TIM2 CCR1 register value is equal to 1000: +TIM2_CC1 delay = CCR1_Val/TIM2 counter clock = 1000 ms +so the PA.00 is reset after a delay equal to 1000 ms. + +The TIM2 CCR2 register value is equal to 500: +TIM2_CC2 delay = CCR2_Val/TIM2 counter clock = 500 ms +so the PA.01 is reset after a delay equal to 500 ms. + +The TIM2 CCR3 register value is equal to 250: +TIM2_CC3 delay = CCR3_Val/TIM2 counter clock = 250 ms +so the PA.02 is reset after a delay equal to 250 ms. + +The TIM2 CCR4 register value is equal to 125: +TIM2_CC4 delay = CCR4_Val/TIM2 counter clock = 125 ms +so the PA.03 is reset after a delay equal to 125 ms. + +While the counter is lower than the Output compare registers values, which +determines the Output delay, the PG.06, PG.08, PI.09 and PC.07 pin are turned on. + +When the counter value reaches the Output compare registers values, the Output +Compare interrupts are generated and, in the handler routine, these pins are turned off. + +@par Directory contents + + - TIM/OCInactive/stm32f2xx_conf.h Library Configuration file + - TIM/OCInactive/stm32f2xx_it.c Interrupt handlers + - TIM/OCInactive/stm32f2xx_it.h Interrupt handlers header file + - TIM/OCInactive/main.c Main program + - TIM/OCInactive/system_stm32f2xx.c STM32F2xx system clock configuration file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins and connect them an oscilloscope to monitor the different + waveforms. + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/stm32f2xx_conf.h new file mode 100644 index 000000000..cf2073f19 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file TIM/OCInactive/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/stm32f2xx_it.c new file mode 100644 index 000000000..0bbc0fa67 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/stm32f2xx_it.c @@ -0,0 +1,211 @@ +/** + ****************************************************************************** + * @file TIM/OCInactive/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_OCInactive + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles TIM2 global interrupt request. + * @param None + * @retval None + */ +void TIM2_IRQHandler(void) +{ + if (TIM_GetITStatus(TIM2, TIM_IT_CC1) != RESET) + { + /* Clear TIM2 Capture Compare1 interrupt pending bit*/ + TIM_ClearITPendingBit(TIM2, TIM_IT_CC1); + + /* LED1 turn-off after 1000 ms */ + STM_EVAL_LEDOff(LED1); + } + else if (TIM_GetITStatus(TIM2, TIM_IT_CC2) != RESET) + { + /* Clear TIM2 Capture Compare2 interrupt pending bit*/ + TIM_ClearITPendingBit(TIM2, TIM_IT_CC2); + + /* LED2 turn-off after 500 ms */ + STM_EVAL_LEDOff(LED2); + } + else if (TIM_GetITStatus(TIM2, TIM_IT_CC3) != RESET) + { + /* Clear TIM2 Capture Compare3 interrupt pending bit*/ + TIM_ClearITPendingBit(TIM2, TIM_IT_CC3); + + /* LED3 turn-off after 250 ms */ + STM_EVAL_LEDOff(LED3); + } + else + { + /* Clear TIM2 Capture Compare4 interrupt pending bit*/ + TIM_ClearITPendingBit(TIM2, TIM_IT_CC4); + + /* LED4 turn-off after 125 ms */ + STM_EVAL_LEDOff(LED4); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/stm32f2xx_it.h new file mode 100644 index 000000000..9a929ec4a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file TIM/OCInactive/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TIM2_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCInactive/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/main.c new file mode 100644 index 000000000..d9bf1f6b0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/main.c @@ -0,0 +1,227 @@ +/** + ****************************************************************************** + * @file TIM/OCToggle/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_OCToggle + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +__IO uint16_t CCR1_Val = 40961; +__IO uint16_t CCR2_Val = 20480; +__IO uint16_t CCR3_Val = 10240; +__IO uint16_t CCR4_Val = 5120; +uint16_t PrescalerValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + /* --------------------------------------------------------------------------- + TIM3 Configuration: Output Compare Toggle Mode: + + In this example TIM3 input clock (TIM3CLK) is set to 2 * APB1 clock (PCLK1), + since APB1 prescaler is different from 1. + TIM3CLK = 2 * PCLK1 + PCLK1 = HCLK / 4 + => TIM3CLK = HCLK / 2 = SystemCoreClock /2 + + To get TIM3 counter clock at 15 MHz, the prescaler is computed as follows: + Prescaler = (TIM3CLK / TIM3 counter clock) - 1 + Prescaler = ((SystemCoreClock /2) /15 MHz) - 1 + + CC1 update rate = TIM3 counter clock / CCR1_Val = 366.2 Hz + ==> So the TIM3 Channel 1 generates a periodic signal with a + frequency equal to 183.1 Hz. + + CC2 update rate = TIM3 counter clock / CCR2_Val = 732.4 Hz + ==> So the TIM3 Channel 2 generates a periodic signal with a + frequency equal to 366.3 Hz. + + CC3 update rate = TIM3 counter clock / CCR3_Val = 1464.8 Hz + ==> So the TIM3 Channel 3 generates a periodic signal with a + frequency equal to 732.4 Hz. + + CC4 update rate = TIM3 counter clock / CCR4_Val = 2929.6 Hz + ==> So the TIM3 Channel 4 generates a periodic signal with a + frequency equal to 1464.8 Hz. + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + --------------------------------------------------------------------------- */ + + /* Compute the prescaler value */ + PrescalerValue = (uint16_t) ((SystemCoreClock / 2) / 15000000) - 1; + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 65535; + TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); + + /* Output Compare Toggle Mode configuration: Channel1 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR1_Val; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; + TIM_OC1Init(TIM3, &TIM_OCInitStructure); + + TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Disable); + + /* Output Compare Toggle Mode configuration: Channel2 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR2_Val; + + TIM_OC2Init(TIM3, &TIM_OCInitStructure); + + TIM_OC2PreloadConfig(TIM3, TIM_OCPreload_Disable); + + /* Output Compare Toggle Mode configuration: Channel3 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR3_Val; + + TIM_OC3Init(TIM3, &TIM_OCInitStructure); + + TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Disable); + + /* Output Compare Toggle Mode configuration: Channel4 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR4_Val; + + TIM_OC4Init(TIM3, &TIM_OCInitStructure); + + TIM_OC4PreloadConfig(TIM3, TIM_OCPreload_Disable); + + /* TIM enable counter */ + TIM_Cmd(TIM3, ENABLE); + + /* TIM IT enable */ + TIM_ITConfig(TIM3, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4, ENABLE); + + while (1) + {} +} + +/** + * @brief Configure the TIM3 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* TIM3 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); + + /* GPIOC clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); + + /* GPIOC Configuration: TIM3 CH1 (PC6), TIM3 CH2 (PC7), TIM3 CH2 (PC8) and TIM3 CH4 (PC9) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Connect TIM Channels to AF2 */ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource6, GPIO_AF_TIM3); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource7, GPIO_AF_TIM3); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_TIM3); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_TIM3); + + /* Enable the TIM3 global Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/readme.txt new file mode 100644 index 000000000..36c91c225 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/readme.txt @@ -0,0 +1,94 @@ +/** + @page TIM_OCToggle TIM_OCToggle + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/OCToggle/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM OCToggle example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the TIM3 peripheral to generate four different +signals with four different frequencies. + +The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), and we want to get TIM3 +counter clock at 15 MHz so the Prescaler is computed as following: + - Prescaler = (TIM3CLK / TIM3 counter clock) - 1 +SystemCoreClock is set to 120 MHz for STM32F2xx devices + +The TIM3 CCR1 register value is equal to 40961: +CC1 update rate = TIM3 counter clock / CCR1_Val = 366.2 Hz, +so the TIM3 Channel 1 generates a periodic signal with a frequency equal to 183.1 Hz. + +The TIM3 CCR2 register is equal to 20480: +CC2 update rate = TIM3 counter clock / CCR2_Val = 732.4 Hz +so the TIM3 channel 2 generates a periodic signal with a frequency equal to 366.3 Hz. + +The TIM3 CCR3 register is equal to 10240: +CC3 update rate = TIM3 counter clock / CCR3_Val = 1464.8 Hz +so the TIM3 channel 3 generates a periodic signal with a frequency equal to 732.4 Hz. + +The TIM3 CCR4 register is equal to 5120: +CC4 update rate = TIM3 counter clock / CCR4_Val = 2929.6 Hz +so the TIM3 channel 4 generates a periodic signal with a frequency equal to 1464.8 Hz. + + +@par Directory contents + + - TIM/OCToggle/stm32f2xx_conf.h Library Configuration file + - TIM/OCToggle/stm32f2xx_it.c Interrupt handlers + - TIM/OCToggle/stm32f2xx_it.h Interrupt handlers header file + - TIM/OCToggle/main.c Main program + - TIM/OCToggle/system_stm32f2xx.c STM32F2xx system clock configuration file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the TIM3 pins to an oscilloscope to monitor the different waveforms: + - PC.06 (TIM3_CH1) + - PC.07 (TIM3_CH2) + - PC.08 (TIM3_CH3) + - PC.09 (TIM3_CH4) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/stm32f2xx_conf.h new file mode 100644 index 000000000..9ba014462 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file TIM/OCToggle/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/stm32f2xx_it.c new file mode 100644 index 000000000..48c31a640 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/stm32f2xx_it.c @@ -0,0 +1,215 @@ +/** + ****************************************************************************** + * @file TIM/OCToggle/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_OCToggle + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint16_t capture = 0; +extern __IO uint16_t CCR1_Val; +extern __IO uint16_t CCR2_Val; +extern __IO uint16_t CCR3_Val; +extern __IO uint16_t CCR4_Val; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles TIM3 global interrupt request. + * @param None + * @retval None + */ +void TIM3_IRQHandler(void) +{ + /* TIM3_CH1 toggling with frequency = 183.1 Hz */ + if (TIM_GetITStatus(TIM3, TIM_IT_CC1) != RESET) + { + TIM_ClearITPendingBit(TIM3, TIM_IT_CC1 ); + capture = TIM_GetCapture1(TIM3); + TIM_SetCompare1(TIM3, capture + CCR1_Val ); + } + + /* TIM3_CH2 toggling with frequency = 366.2 Hz */ + if (TIM_GetITStatus(TIM3, TIM_IT_CC2) != RESET) + { + TIM_ClearITPendingBit(TIM3, TIM_IT_CC2); + capture = TIM_GetCapture2(TIM3); + TIM_SetCompare2(TIM3, capture + CCR2_Val); + } + + /* TIM3_CH3 toggling with frequency = 732.4 Hz */ + if (TIM_GetITStatus(TIM3, TIM_IT_CC3) != RESET) + { + TIM_ClearITPendingBit(TIM3, TIM_IT_CC3); + capture = TIM_GetCapture3(TIM3); + TIM_SetCompare3(TIM3, capture + CCR3_Val); + } + + /* TIM3_CH4 toggling with frequency = 1464.8 Hz */ + if (TIM_GetITStatus(TIM3, TIM_IT_CC4) != RESET) + { + TIM_ClearITPendingBit(TIM3, TIM_IT_CC4); + capture = TIM_GetCapture4(TIM3); + TIM_SetCompare4(TIM3, capture + CCR4_Val); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/stm32f2xx_it.h new file mode 100644 index 000000000..541c4b106 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file TIM/OCToggle/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TIM3_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OCToggle/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/main.c new file mode 100644 index 000000000..a407aeb65 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/main.c @@ -0,0 +1,211 @@ +/** + ****************************************************************************** + * @file TIM/OnePulse/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_OnePulse + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_ICInitTypeDef TIM_ICInitStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +uint16_t PrescalerValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + /* -------------------------------------------------------------------------- + TIM4 configuration: One Pulse mode + The external signal is connected to TIM4_CH2 pin (PB.07), + The Rising edge is used as active edge, + The One Pulse signal is output on TIM4_CH1 pin (PB.06) + The TIM_Pulse defines the delay value + The (TIM_Period - TIM_Pulse) defines the One Pulse value. + + TIM4 input clock (TIM4CLK) is set to 2 * APB1 clock (PCLK1), + since APB1 prescaler is different from 1. + TIM4CLK = 2 * PCLK1 + PCLK1 = HCLK / 4 + => TIM4CLK = HCLK / 2 = SystemCoreClock /2 + + TIM2CLK = SystemCoreClock/2, we want to get TIM2 counter clock at 30 MHz: + Prescaler = (TIM2CLK / TIM2 counter clock) - 1 + Prescaler = ((SystemCoreClock /2) /30 MHz) - 1 + + The Autoreload value is 65535 (TIM4->ARR), so the maximum frequency value + to trigger the TIM4 input is 30000000/65535 = 458 Hz. + + The TIM_Pulse defines the delay value, the delay value is fixed + to 546.1 us: + delay = CCR1/TIM4 counter clock = 546.1 us. + The (TIM_Period - TIM_Pulse) defines the One Pulse value, + the pulse value is fixed to 1.638 ms: + One Pulse value = (TIM_Period - TIM_Pulse) / TIM4 counter clock = 1.638 ms. + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + + --------------------------------------------------------------------------- */ + + /* Compute the prescaler value */ + PrescalerValue = (uint16_t) ((SystemCoreClock / 2) / 30000000) - 1; + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 65535; + TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); + + /* TIM4 PWM2 Mode configuration: Channel1 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 16383; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + + TIM_OC1Init(TIM4, &TIM_OCInitStructure); + + /* TIM4 configuration in Input Capture Mode */ + + TIM_ICStructInit(&TIM_ICInitStructure); + + TIM_ICInitStructure.TIM_Channel = TIM_Channel_2; + TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStructure.TIM_ICFilter = 0; + + TIM_ICInit(TIM4, &TIM_ICInitStructure); + + /* One Pulse Mode selection */ + TIM_SelectOnePulseMode(TIM4, TIM_OPMode_Single); + + /* Input Trigger selection */ + TIM_SelectInputTrigger(TIM4, TIM_TS_TI2FP2); + + /* Slave Mode selection: Trigger Mode */ + TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Trigger); + + while (1) + {} +} + +/** + * @brief Configure the TIM4 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* TIM4 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); + + /* GPIOB clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); + + /* TIM4_CH1 pin (PB.06) configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* TIM4_CH2 pin (PB.07) configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Connect TIM pins to AF2 */ + GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_TIM4); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_TIM4); + +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/readme.txt new file mode 100644 index 000000000..afbfc9e40 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/readme.txt @@ -0,0 +1,88 @@ +/** + @page TIM_OnePulse TIM One Pulse example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/OnePulse/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM One Pulse example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to use the TIM peripheral to generate a One pulse Mode +after a Rising edge of an external signal is received in Timer Input pin. + +TIM2CLK = SystemCoreClock/2, we want to get TIM2 counter clock at 30 MHz: + - Prescaler = (TIM2CLK / TIM2 counter clock) - 1 + +SystemCoreClock is set to 120 MHz. + +The Autoreload value is 65535 (TIM4->ARR), so the maximum frequency value to +trigger the TIM4 input is 30000000/65535 = 458 Hz. + +The TIM4 is configured as follows: +The One Pulse mode is used, the external signal is connected to TIM4 CH2 pin (PB.07), +the rising edge is used as active edge, the One Pulse signal is output +on TIM4_CH1 (PB.06). + +The TIM_Pulse defines the delay value, the delay value is fixed to: +delay = CCR1/TIM4 counter clock = 16383 / 30000000 = 546.1 us. +The (TIM_Period - TIM_Pulse) defines the One Pulse value, the pulse value is fixed to: +One Pulse value = (TIM_Period - TIM_Pulse)/TIM4 counter clock + = (65535 - 16383) / 30000000 = 1.638 ms. + +@par Directory contents + + - TIM/OnePulse/stm32f2xx_conf.h Library Configuration file + - TIM/OnePulse/stm32f2xx_it.c Interrupt handlers + - TIM/OnePulse/stm32f2xx_it.h Interrupt handlers header file + - TIM/OnePulse/main.c Main program + - TIM/OnePulse/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the external signal to the TIM4_CH2 pin (PB.07) + - Connect the TIM4_CH1 (PB.06) pin to an oscilloscope to monitor the waveform. + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/stm32f2xx_conf.h new file mode 100644 index 000000000..678f2c282 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file TIM/OnePulse/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/stm32f2xx_it.c new file mode 100644 index 000000000..e18963d29 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/stm32f2xx_it.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file TIM/OnePulse/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_OnePulse + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/stm32f2xx_it.h new file mode 100644 index 000000000..a508aaef5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/OnePulse/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/OnePulse/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/main.c new file mode 100644 index 000000000..afeffc9c4 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/main.c @@ -0,0 +1,170 @@ +/** + ****************************************************************************** + * @file TIM/PWM_Input/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_PWM_Input + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_ICInitTypeDef TIM_ICInitStructure; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + + /* --------------------------------------------------------------------------- + TIM4 configuration: PWM Input mode + + In this example TIM4 input clock (TIM4CLK) is set to 2 * APB1 clock (PCLK1), + since APB1 prescaler is different from 1. + TIM4CLK = 2 * PCLK1 + PCLK1 = HCLK / 4 + => TIM4CLK = HCLK / 2 = SystemCoreClock /2 + + External Signal Frequency = TIM4 counter clock / TIM4_CCR2 in Hz. + + External Signal DutyCycle = (TIM4_CCR1*100)/(TIM4_CCR2) in %. + + --------------------------------------------------------------------------- */ + + TIM_ICInitStructure.TIM_Channel = TIM_Channel_2; + TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStructure.TIM_ICFilter = 0x0; + + TIM_PWMIConfig(TIM4, &TIM_ICInitStructure); + + /* Select the TIM4 Input Trigger: TI2FP2 */ + TIM_SelectInputTrigger(TIM4, TIM_TS_TI2FP2); + + /* Select the slave Mode: Reset Mode */ + TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Reset); + TIM_SelectMasterSlaveMode(TIM4,TIM_MasterSlaveMode_Enable); + + /* TIM enable counter */ + TIM_Cmd(TIM4, ENABLE); + + /* Enable the CC2 Interrupt Request */ + TIM_ITConfig(TIM4, TIM_IT_CC2, ENABLE); + + while (1); +} + +/** + * @brief Configure the TIM4 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* TIM4 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); + + /* GPIOB clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); + + /* TIM4 chennel2 configuration : PB.07 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Connect TIM pin to AF2 */ + GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_TIM4); + + /* Enable the TIM4 global Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/readme.txt new file mode 100644 index 000000000..d892ef0bc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/readme.txt @@ -0,0 +1,85 @@ +/** + @page TIM_PWM_Input TIM_PWM_Input + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/PWM_Input/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM PWM_Input example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to use the TIM peripheral to measure the frequency and +duty cycle of an external signal. + +The TIMxCLK frequency is set to SystemCoreClock/4 (Hz), the Prescaler is 0 so the +counter clock is SystemCoreClock/2 (Hz). +SystemCoreClock is set to 120 MHz fro STM32F2xx Devices RevA, RevZ and RevB. + +TIM4 is configured in PWM Input Mode: the external signal is connected to +TIM4 Channel2 used as input pin. +To measure the frequency and the duty cycle we use the TIM4 CC2 interrupt request, +so In the TIM4_IRQHandler routine, the frequency and the duty cycle of the external +signal are computed. +The "Frequency" variable contains the external signal frequency: +TIM4 counter clock = SystemCoreClock / 2, +Frequency = TIM4 counter clock / TIM4_CCR2 in Hz, +The "DutyCycle" variable contains the external signal duty cycle: +DutyCycle = (TIM4_CCR1*100)/(TIM4_CCR2) in %. + +The minimum frequency value to measure is 915 Hz (TIM4 counter clock / CCR MAX). + +@par Directory contents + + - TIM/PWM_Input/stm32f2xx_conf.h Library Configuration file + - TIM/PWM_Input/stm32f2xx_it.c Interrupt handlers + - TIM/PWM_Input/stm32f2xx_it.h Interrupt handlers header file + - TIM/PWM_Input/main.c Main program + - TIM/PWM_Input/system_stm32f2xx.c STM32F2xx system clock configuration file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the external signal to measure to the TIM4 CH2 pin (PB.07). + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/stm32f2xx_conf.h new file mode 100644 index 000000000..e860271dd --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file TIM/PWM_Input/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/stm32f2xx_it.c new file mode 100644 index 000000000..7d299b169 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/stm32f2xx_it.c @@ -0,0 +1,202 @@ +/** + ****************************************************************************** + * @file TIM/PWM_Input/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_PWM_Input + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint16_t IC2Value = 0; +__IO uint16_t DutyCycle = 0; +__IO uint32_t Frequency = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles TIM4 global interrupt request. + * @param None + * @retval None + */ +void TIM4_IRQHandler(void) +{ + RCC_ClocksTypeDef RCC_Clocks; + RCC_GetClocksFreq(&RCC_Clocks); + + /* Clear TIM4 Capture compare interrupt pending bit */ + TIM_ClearITPendingBit(TIM4, TIM_IT_CC2); + + /* Get the Input Capture value */ + IC2Value = TIM_GetCapture2(TIM4); + + if (IC2Value != 0) + { + /* Duty cycle computation */ + DutyCycle = (TIM_GetCapture1(TIM4) * 100) / IC2Value; + + /* Frequency computation + TIM4 counter clock = (RCC_Clocks.HCLK_Frequency)/2 */ + + Frequency = (RCC_Clocks.HCLK_Frequency)/2 / IC2Value; + } + else + { + DutyCycle = 0; + Frequency = 0; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/stm32f2xx_it.h new file mode 100644 index 000000000..2382ff054 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file TIM/PWM_Input/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TIM4_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Input/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/main.c new file mode 100644 index 000000000..cc8bac0ec --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/main.c @@ -0,0 +1,214 @@ +/** + ****************************************************************************** + * @file TIM/PWM_Output/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_PWM_Output + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +uint16_t CCR1_Val = 333; +uint16_t CCR2_Val = 249; +uint16_t CCR3_Val = 166; +uint16_t CCR4_Val = 83; +uint16_t PrescalerValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + /* ----------------------------------------------------------------------- + TIM3 Configuration: generate 4 PWM signals with 4 different duty cycles. + + In this example TIM3 input clock (TIM3CLK) is set to 2 * APB1 clock (PCLK1), + since APB1 prescaler is different from 1. + TIM3CLK = 2 * PCLK1 + PCLK1 = HCLK / 4 + => TIM3CLK = HCLK / 2 = SystemCoreClock /2 + + To get TIM3 counter clock at 20 MHz, the prescaler is computed as follows: + Prescaler = (TIM3CLK / TIM3 counter clock) - 1 + Prescaler = ((SystemCoreClock /2) /20 MHz) - 1 + + To get TIM3 output clock at 30 KHz, the period (ARR)) is computed as follows: + ARR = (TIM3 counter clock / TIM3 output clock) - 1 + = 665 + + TIM3 Channel1 duty cycle = (TIM3_CCR1/ TIM3_ARR)* 100 = 50% + TIM3 Channel2 duty cycle = (TIM3_CCR2/ TIM3_ARR)* 100 = 37.5% + TIM3 Channel3 duty cycle = (TIM3_CCR3/ TIM3_ARR)* 100 = 25% + TIM3 Channel4 duty cycle = (TIM3_CCR4/ TIM3_ARR)* 100 = 12.5% + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + ----------------------------------------------------------------------- */ + + + /* Compute the prescaler value */ + PrescalerValue = (uint16_t) ((SystemCoreClock /2) / 20000000) - 1; + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 665; + TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); + + /* PWM1 Mode configuration: Channel1 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR1_Val; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + + TIM_OC1Init(TIM3, &TIM_OCInitStructure); + + TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Enable); + + /* PWM1 Mode configuration: Channel2 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR2_Val; + + TIM_OC2Init(TIM3, &TIM_OCInitStructure); + + TIM_OC2PreloadConfig(TIM3, TIM_OCPreload_Enable); + + /* PWM1 Mode configuration: Channel3 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR3_Val; + + TIM_OC3Init(TIM3, &TIM_OCInitStructure); + + TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Enable); + + /* PWM1 Mode configuration: Channel4 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR4_Val; + + TIM_OC4Init(TIM3, &TIM_OCInitStructure); + + TIM_OC4PreloadConfig(TIM3, TIM_OCPreload_Enable); + + TIM_ARRPreloadConfig(TIM3, ENABLE); + + /* TIM3 enable counter */ + TIM_Cmd(TIM3, ENABLE); + + while (1) + {} +} + +/** + * @brief Configure the TIM3 Ouput Channels. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* TIM3 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); + + /* GPIOC clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); + + /* GPIOC Configuration: TIM3 CH1 (PC6), TIM3 CH2 (PC7), TIM3 CH3 (PC8) and TIM3 CH4 (PC9) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Connect TIM3 pins to AF2 */ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource6, GPIO_AF_TIM3); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource7, GPIO_AF_TIM3); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_TIM3); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_TIM3); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/readme.txt new file mode 100644 index 000000000..826c1e2d6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/readme.txt @@ -0,0 +1,100 @@ +/** + @page TIM_PWM_Output TIM_PWM_Output + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/PWM_Output/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM PWM_Output example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the TIM peripheral in PWM (Pulse Width Modulation) +mode. + +The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), to get TIM3 counter +clock at 20 MHz the Prescaler is computed as following: + - Prescaler = (TIM3CLK / TIM3 counter clock) - 1 + +SystemCoreClock is set to 120 MHz for STM32F2xx Devices RevA, RevZ and RevB. + +The TIM3 is running at 30 KHz: TIM3 Frequency = TIM3 counter clock/(ARR + 1) + = 20 MHz / 666 = 30 KHz +The TIM3 CCR1 register value is equal to 500, so the TIM3 Channel 1 generates a +PWM signal with a frequency equal to 30 KHz and a duty cycle equal to 50%: +TIM3 Channel1 duty cycle = (TIM3_CCR1/ TIM3_ARR + 1)* 100 = 50% + +The TIM3 CCR2 register value is equal to 375, so the TIM3 Channel 2 generates a +PWM signal with a frequency equal to 30 KHz and a duty cycle equal to 37.5%: +TIM3 Channel2 duty cycle = (TIM3_CCR2/ TIM3_ARR + 1)* 100 = 37.5% + +The TIM3 CCR3 register value is equal to 250, so the TIM3 Channel 3 generates a +PWM signal with a frequency equal to 30 KHz and a duty cycle equal to 25%: +TIM3 Channel3 duty cycle = (TIM3_CCR3/ TIM3_ARR + 1)* 100 = 25% + +The TIM3 CCR4 register value is equal to 125, so the TIM3 Channel 4 generates a +PWM signal with a frequency equal to 30 KHz and a duty cycle equal to 12.5%: +TIM3 Channel4 duty cycle = (TIM3_CCR4/ TIM3_ARR + 1)* 100 = 12.5% + +The PWM waveform can be displayed using an oscilloscope. + + +@par Directory contents + + - TIM/PWM_Output/stm32f2xx_conf.h Library Configuration file + - TIM/PWM_Output/stm32f2xx_it.c Interrupt handlers + - TIM/PWM_Output/stm32f2xx_it.h Interrupt handlers header file + - TIM/PWM_Output/main.c Main program + - TIM/PWM_Output/system_stm32f2xx.c STM32F2xx system clock configuration file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the following pins to an oscilloscope to monitor the different + waveforms: + - PC.06: (TIM3_CH1) + - PC.07: (TIM3_CH2) + - PC.08: (TIM3_CH3) + - PC.09: (TIM3_CH4) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/stm32f2xx_conf.h new file mode 100644 index 000000000..a154cfc4d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file TIM/PWM_Output/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/stm32f2xx_it.c new file mode 100644 index 000000000..df5dad833 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/stm32f2xx_it.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file TIM/PWM_Output/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_PWM_Output + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/stm32f2xx_it.h new file mode 100644 index 000000000..e5cc3b009 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/PWM_Output/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/PWM_Output/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/main.c new file mode 100644 index 000000000..5a8c1feec --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/main.c @@ -0,0 +1,232 @@ +/** + ****************************************************************************** + * @file TIM/Parallel_Synchro/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_Parallel_Synchro + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + /* --------------------------------------------------------------------------- + Timers synchronisation in parallel mode + 1/TIM2 is configured as Master Timer: + - PWM Mode is used + - The TIM2 Update event is used as Trigger Output + 2/TIM3 and TIM4 are slaves for TIM2, + - PWM Mode is used + - The ITR1(TIM2) is used as input trigger for both slaves + - Gated mode is used, so starts and stops of slaves counters + are controlled by the Master trigger output signal(update event). + + TIM2 input clock (TIM2CLK) is set to 2 * APB1 clock (PCLK1), + since APB1 prescaler is different from 1. + TIM2CLK = 2 * PCLK1 + PCLK1 = HCLK / 4 + => TIM2CLK = HCLK / 2 = SystemCoreClock /2 + + To get Master Timer TIM2 output clock at 234.375 KHz running at and the + duty cycle is equal to 25% : + + The period (TIM2_ARR) is computed as follows: + ARR = (TIM2 counter clock / TIM2 output clock) - 1 + = 255 + + The dutu cycle (TIM2_CCR1) is computed as follows: + CCR1 = ((TIM2_ARR + 1) * 25)/100 + = 64 + + The TIM3 is running: + - At (TIM2 frequency)/ (TIM3 period + 1) = 23.437 KHz and a duty cycle + equal to TIM3_CCR1/(TIM3_ARR + 1) = 30% + + The TIM4 is running: + - At (TIM2 frequency)/ (TIM4 period + 1) = 46.875 KHz and a duty cycle + equal to TIM4_CCR1/(TIM4_ARR + 1) = 60% + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + + ----------------------------------------------------------------------------*/ + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 255; + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure); + + TIM_TimeBaseStructure.TIM_Period = 9; + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); + + TIM_TimeBaseStructure.TIM_Period = 4; + TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); + + /* Master Configuration in PWM1 Mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 64; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + + TIM_OC1Init(TIM2, &TIM_OCInitStructure); + + /* Select the Master Slave Mode */ + TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Enable); + + /* Master Mode selection */ + TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update); + + /* Slaves Configuration: PWM1 Mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 3; + + TIM_OC1Init(TIM3, &TIM_OCInitStructure); + + TIM_OC1Init(TIM4, &TIM_OCInitStructure); + + /* Slave Mode selection: TIM3 */ + TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated); + TIM_SelectInputTrigger(TIM3, TIM_TS_ITR1); + + /* Slave Mode selection: TIM4 */ + TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated); + TIM_SelectInputTrigger(TIM4, TIM_TS_ITR1); + + /* TIM enable counter */ + TIM_Cmd(TIM3, ENABLE); + TIM_Cmd(TIM2, ENABLE); + TIM_Cmd(TIM4, ENABLE); + + while (1) + {} +} + +/** + * @brief Configure the TIM Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* TIM2, TIM3 and TIM4 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 | + RCC_APB1Periph_TIM4, ENABLE); + + /* GPIOA, GPIOB and GPIOC clocks enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC, ENABLE); + + /* GPIOC Configuration: PC6(TIM3 CH1) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* GPIOA Configuration: PA0(TIM2 CH1) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* GPIOB Configuration: PB6(TIM4 CH1) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Connect TIM pins to AF2 */ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource6, GPIO_AF_TIM3); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource0, GPIO_AF_TIM2); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_TIM4); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/readme.txt new file mode 100644 index 000000000..a2a38296a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/readme.txt @@ -0,0 +1,97 @@ +/** + @page TIM_Parallel_Synchro TIM Parallel Synchro example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/Parallel_Synchro/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM Parallel Synchro example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to synchronize TIM peripherals in parallel mode. +In this example three timers are used: + +Timers synchronisation in parallel mode: + +1/TIM2 is configured as Master Timer: + - PWM Mode is used + - The TIM2 Update event is used as Trigger Output + +2/TIM3 and TIM4 are slaves for TIM2, + - PWM Mode is used + - The ITR1(TIM2) is used as input trigger for both slaves + - Gated mode is used, so starts and stops of slaves counters are controlled + by the Master trigger output signal(update event). + +The TIM2 counter clock is 60 MHz. + + The Master Timer TIM2 is running at TIM2 frequency: + TIM2 frequency = TIM2 counter clock/ (TIM2 period + 1) = 234.375 KHz + and the duty cycle is equal to TIM2_CCR1/(TIM2_ARR + 1) = 25%. + + The TIM3 is running at: + (TIM2 frequency)/ (TIM3 period + 1) = 23.437 KHz and a duty cycle equal to + TIM3_CCR1/(TIM3_ARR + 1) = 30% + + The TIM4 is running at: + (TIM2 frequency)/ (TIM4 period + 1) = 46.875 KHz and a duty cycle equal to + TIM4_CCR1/(TIM4_ARR + 1) = 60% + +@par Directory contents + + - TIM/Parallel_Synchro/stm32f2xx_conf.h Library Configuration file + - TIM/Parallel_Synchro/stm32f2xx_it.c Interrupt handlers + - TIM/Parallel_Synchro/stm32f2xx_it.h Interrupt handlers header file + - TIM/Parallel_Synchro/main.c Main program + - TIM/Parallel_Synchro/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the pins to an oscilloscope to monitor the different waveforms: + - TIM2 CH1 (PA.00) + - TIM3 CH1 (PC.06) + - TIM4 CH1 (PB.06) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f2xx_conf.h new file mode 100644 index 000000000..6a05ee181 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file TIM/Parallel_Synchro/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f2xx_it.c new file mode 100644 index 000000000..a5fe2e65d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f2xx_it.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file TIM/Parallel_Synchro/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_Parallel_Synchro + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f2xx_it.h new file mode 100644 index 000000000..d8df9a003 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/Parallel_Synchro/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c new file mode 100644 index 000000000..4bd417e84 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c @@ -0,0 +1,181 @@ +/** + ****************************************************************************** + * @file TIM/TIM10_PWMOutput/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM10_PWMOutput + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +uint16_t CCR1_Val = 333; +uint16_t PrescalerValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + /* --------------------------------------------------------------------------- + TIM10 Configuration: generate 1 PWM signal: + + In this example TIM10 input clock (TIM10CLK) is set to 2 * APB2 clock (PCLK2), + since APB2 prescaler is different from 1. + TIM10CLK = 2 * PCLK2 + PCLK2 = HCLK / 2 + => TIM10CLK = HCLK = SystemCoreClock + + To get TIM10 counter clock at 20 MHz, the prescaler is computed as follows: + Prescaler = (TIM10CLK / TIM10 counter clock) - 1 + Prescaler = (SystemCoreClock /20 MHz) - 1 + + To get TIM10 output clock at 30 KHz, the period (TIM10_ARR) is computed as follows: + ARR = (TIM10 counter clock / TIM10 output clock) - 1 + = 665 + + TIM10 Channel1 duty cycle = (TIM10_CCR1/ TIM10_ARR)* 100 = 50% + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + --------------------------------------------------------------------------- */ + + + /* Compute the prescaler value */ + PrescalerValue = (uint16_t) (SystemCoreClock / 20000000) - 1; + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 665; + TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM10, &TIM_TimeBaseStructure); + + /* PWM1 Mode configuration: Channel1 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR1_Val; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + + TIM_OC1Init(TIM10, &TIM_OCInitStructure); + + TIM_OC1PreloadConfig(TIM10, TIM_OCPreload_Enable); + + TIM_ARRPreloadConfig(TIM10, ENABLE); + + /* TIM10 enable counter */ + TIM_Cmd(TIM10, ENABLE); + + while (1) + {} +} + +/** + * @brief Configure the TIM10 Ouput Channels. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* TIM10 clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM10, ENABLE); + + /* GPIOF clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOF, ENABLE); + + /* GPIOF Configuration: TIM10 CH1 (PF6) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 ; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOF, &GPIO_InitStructure); + + /* Connect TIM pins to AF3 */ + GPIO_PinAFConfig(GPIOF, GPIO_PinSource6, GPIO_AF_TIM10); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/readme.txt new file mode 100644 index 000000000..f16d5fb88 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/readme.txt @@ -0,0 +1,84 @@ +/** + @page TIM10_PWMOutput TIM10_PWMOutput + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/TIM10_PWMOutput/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM PWM_Output example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the TIM peripheral in PWM (Pulse Width Modulation) +mode. + +The TIM10CLK frequency is set to SystemCoreClock(Hz), to get TIM10 counter +clock at 20 MHz the Prescaler is computed as following: + - Prescaler = (TIM10CLK / TIM10 counter clock) - 1 + +SystemCoreClock is set to 120 MHz for STM32F2xx Devices RevA, RevZ and RevB. + +The TIM10 is running at 30 KHz: TIM10 Frequency = TIM10 counter clock/(ARR + 1) + = 20 MHz / 666 = 30 KHz + +The TIM10 CCR1 register value is equal to 500, so the TIM10 Channel 1 generates a +PWM signal with a frequency equal to 30 KHz and a duty cycle equal to 50%: + +TIM10 Channel1 duty cycle = (TIM10_CCR1/ TIM10_ARR + 1)* 100 = 50% + +The PWM waveform can be displayed using an oscilloscope. + +@par Directory contents + + - TIM/TIM10_PWMOutput/stm32f2xx_conf.h Library Configuration file + - TIM/TIM10_PWMOutput/stm32f2xx_it.c Interrupt handlers + - TIM/TIM10_PWMOutput/stm32f2xx_it.h Interrupt handlers header file + - TIM/TIM10_PWMOutput/main.c Main program + - TIM/TIM10_PWMOutput/system_stm32f2xx.c STM32F2xx system clock configuration file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the following pin to an oscilloscope PF.06: (TIM10_CH1) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f2xx_conf.h new file mode 100644 index 000000000..db5accedc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file TIM/TIM10_PWMOutput/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f2xx_it.c new file mode 100644 index 000000000..f9746bf1e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f2xx_it.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file TIM/TIM10_PWMOutput/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM10_PWMOutput + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f2xx_it.h new file mode 100644 index 000000000..3d286137e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/TIM10_PWMOutput/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/main.c new file mode 100644 index 000000000..5cf97ff63 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/main.c @@ -0,0 +1,271 @@ +/** + ****************************************************************************** + * @file TIM/TIM1_Synchro/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_TIM1_Synchro + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +TIM_BDTRInitTypeDef TIM_BDTRInitStructure; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM1 Configuration */ + TIM_Config(); + + /* --------------------------------------------------------------------------- + TIM1 and Timers(TIM3 and TIM4) synchronisation in parallel mode. + 1/TIM1 is configured as Master Timer: + - PWM Mode is used + - The TIM1 Update event is used as Trigger Output + + 2/TIM3 and TIM4 are slaves for TIM1, + - PWM Mode is used + - The ITR0(TIM1) is used as input trigger for both slaves + - Gated mode is used, so starts and stops of slaves counters + are controlled by the Master trigger output signal(update event). + + In this example TIM1 input clock (TIM1CLK) is set to 2 * APB2 clock (PCLK2), + since APB2 prescaler is different from 1. + TIM1CLK = 2 * PCLK2 + PCLK2 = HCLK / 2 + => TIM1CLK = HCLK = SystemCoreClock + + The TIM1 counter clock is equal to SystemCoreClock = 120 Mhz. + + The Master Timer TIM1 is running at: + TIM1 frequency = TIM1 counter clock / (TIM1_Period + 1) = 468.750 KHz + TIM1_Period = (TIM1 counter clock / TIM1 frequency) - 1 = 255 + and the duty cycle is equal to: TIM1_CCR1/(TIM1_ARR + 1) = 50% + + The TIM3 is running at: + (TIM1 frequency)/ ((TIM3 period +1)* (Repetition_Counter+1)) = 31.250 KHz and + a duty cycle equal to TIM3_CCR1/(TIM3_ARR + 1) = 33.3% + + The TIM4 is running at: + (TIM1 frequency)/ ((TIM4 period +1)* (Repetition_Counter+1)) = 46.875 KHz and + a duty cycle equal to TIM4_CCR1/(TIM4_ARR + 1) = 50% + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + --------------------------------------------------------------------------- */ + + + /* TIM3 Peripheral Configuration ----------------------------------------*/ + /* TIM3 Slave Configuration: PWM1 Mode */ + TIM_TimeBaseStructure.TIM_Period = 2; + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); + + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 1; + + TIM_OC1Init(TIM3, &TIM_OCInitStructure); + + /* Slave Mode selection: TIM3 */ + TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated); + TIM_SelectInputTrigger(TIM3, TIM_TS_ITR0); + + /* TIM4 Peripheral Configuration ----------------------------------------*/ + /* TIM4 Slave Configuration: PWM1 Mode */ + TIM_TimeBaseStructure.TIM_Period = 1; + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); + + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 1; + + TIM_OC1Init(TIM4, &TIM_OCInitStructure); + + /* Slave Mode selection: TIM4 */ + TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated); + TIM_SelectInputTrigger(TIM4, TIM_TS_ITR0); + + /* TIM1 Peripheral Configuration ----------------------------------------*/ + /* Time Base configuration */ + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseStructure.TIM_Period = 255; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_RepetitionCounter = 4; + + TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); + + /* Channel 1 Configuration in PWM mode */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; + TIM_OCInitStructure.TIM_Pulse = 127; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; + TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low; + TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set; + TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset; + + TIM_OC1Init(TIM1, &TIM_OCInitStructure); + + /* Automatic Output enable, Break, dead time and lock configuration*/ + TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable; + TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable; + TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_1; + TIM_BDTRInitStructure.TIM_DeadTime = 5; + TIM_BDTRInitStructure.TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High; + TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; + + TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure); + + /* Master Mode selection */ + TIM_SelectOutputTrigger(TIM1, TIM_TRGOSource_Update); + + /* Select the Master Slave Mode */ + TIM_SelectMasterSlaveMode(TIM1, TIM_MasterSlaveMode_Enable); + + /* TIM1 counter enable */ + TIM_Cmd(TIM1, ENABLE); + + /* TIM enable counter */ + TIM_Cmd(TIM3, ENABLE); + TIM_Cmd(TIM4, ENABLE); + + /* Main Output Enable */ + TIM_CtrlPWMOutputs(TIM1, ENABLE); + + while (1) + {} +} + +/** + * @brief Configures TIM1, TIM3 and TIM4 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* GPIOA, GPIOB and GPIOC clocks enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC, ENABLE); + + /* TIM1 clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); + + /* TIM3 and TIM4 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4, ENABLE); + + /* GPIOA Configuration: TIM1 Channel1 as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* GPIOC Configuration: TIM3 Channel1 as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* GPIOB Configuration: TIM4 Channel1 as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Connect TIM pins to AF1 */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_TIM1); + + /* Connect TIM pins to AF2 */ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource6, GPIO_AF_TIM3); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_TIM4); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/readme.txt new file mode 100644 index 000000000..8adbcb0f0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/readme.txt @@ -0,0 +1,97 @@ +/** + @page TIM_TIM1_Synchro TIM1 Synchro example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/TIM1_Synchro/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM TIM1 Synchro example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to synchronize TIM1 and Timers (TIM3 and TIM4) in parallel mode. + +Timers synchronisation in parallel mode: + +1/ TIM1 is configured as Master Timer: + - PWM Mode is used + - The TIM1 Update event is used as Trigger Output + +2/ TIM3 and TIM4 are slaves for TIM1, + - PWM Mode is used + - The ITR0(TIM1) is used as input trigger for both slaves + - Gated mode is used, so starts and stops of slaves counters + are controlled by the Master trigger output signal(update event). + +The TIM1 counter clock is 120 MHz. + + The Master Timer TIM1 is running at: + TIM1 frequency = TIM1 counter clock / (TIM1_Period + 1) = 468.750 KHz + and the duty cycle is equal to: TIM1_CCR1/(TIM1_ARR + 1) = 50% + + The TIM3 is running at: + (TIM1 frequency)/ ((TIM3 period +1)* (Repetition_Counter+1)) = 31.250 KHz and + a duty cycle equal to TIM3_CCR1/(TIM3_ARR + 1) = 33.3% + + The TIM4 is running at: + (TIM1 frequency)/ ((TIM4 period +1)* (Repetition_Counter+1)) = 46.875 KHz and + a duty cycle equal to TIM4_CCR1/(TIM4_ARR + 1) = 50% + + +@par Directory contents + + - TIM/TIM1_Synchro/stm32f2xx_conf.h Library Configuration file + - TIM/TIM1_Synchro/stm32f2xx_it.c Interrupt handlers + - TIM/TIM1_Synchro/stm32f2xx_it.h Interrupt handlers header file + - TIM/TIM1_Synchro/main.c Main program + - TIM/TIM1_Synchro/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the following pins to an oscilloscope to monitor the different waveforms: + - TIM1 CH1 (PA.08) + - TIM3 CH1 (PC.06) + - TIM4 CH1 (PB.06) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f2xx_conf.h new file mode 100644 index 000000000..02f870fd2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file TIM/TIM1_Synchro/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f2xx_it.c new file mode 100644 index 000000000..83a95f055 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f2xx_it.c @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file TIM/TIM1_Synchro/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_TIM1_Synchro + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f2xx_it.h new file mode 100644 index 000000000..5566b84c2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file TIM/TIM1_Synchro/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c new file mode 100644 index 000000000..700d41fee --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c @@ -0,0 +1,200 @@ +/** + ****************************************************************************** + * @file TIM/TIM9_OCToggle/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_TIM9_OCToggle + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +__IO uint16_t CCR1_Val = 40961; +__IO uint16_t CCR2_Val = 20480; +uint16_t PrescalerValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + /* --------------------------------------------------------------------------- + TIM9 Configuration: Output Compare Toggle Mode: + + In this example TIM9 input clock (TIM9CLK) is set to 2 * APB2 clock (PCLK2), + since APB2 prescaler is different from 1. + TIM9CLK = 2 * PCLK2 + PCLK2 = HCLK / 2 + => TIM9CLK = HCLK = SystemCoreClock + + To get TIM9 counter clock at 15 MHz, the prescaler is computed as follows: + Prescaler = (TIM9CLK / TIM9 counter clock) - 1 + Prescaler = (SystemCoreClock /15 MHz) - 1 + + CC1 update rate = TIM9 counter clock / CCR1_Val = 366.2 Hz + ==> So the TIM9 Channel 1 generates a periodic signal with + a frequency equal to 183.1 Hz + + CC2 update rate = TIM9 counter clock / CCR2_Val = 732.4 Hz + ==> So the TIM9 channel 2 generates a periodic signal with + a frequency equal to 366.3 Hz + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + --------------------------------------------------------------------------- */ + + + /* Compute the prescaler value */ + PrescalerValue = (uint16_t) (SystemCoreClock / 15000000) - 1; + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 65535; + TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM9, &TIM_TimeBaseStructure); + + /* Output Compare Toggle Mode configuration: Channel1 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR1_Val; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; + TIM_OC1Init(TIM9, &TIM_OCInitStructure); + + TIM_OC1PreloadConfig(TIM9, TIM_OCPreload_Disable); + + /* Output Compare Toggle Mode configuration: Channel2 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR2_Val; + + TIM_OC2Init(TIM9, &TIM_OCInitStructure); + + TIM_OC2PreloadConfig(TIM9, TIM_OCPreload_Disable); + + /* TIM enable counter */ + TIM_Cmd(TIM9, ENABLE); + + /* TIM IT enable */ + TIM_ITConfig(TIM9, TIM_IT_CC1 | TIM_IT_CC2, ENABLE); + + while (1) + {} +} + +/** + * @brief Configure the TIM9 Pins. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* TIM9 clock enable */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, ENABLE); + + /* GPIOA clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA , ENABLE); + + /* GPIOA Configuration: TIM9 CH1 (PA2) and TIM9 CH2 (PA3) */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Connect TIM pins to AF3 */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_TIM9); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_TIM9); + + /* Enable the TIM9 global Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TIM1_BRK_TIM9_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/readme.txt new file mode 100644 index 000000000..656f2e214 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/readme.txt @@ -0,0 +1,84 @@ +/** + @page TIM_TIM9_OCToggle TIM_TIM9_OCToggle + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file TIM/TIM9_OCToggle/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM TIM9_OCToggle example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the TIM9 peripheral to generate four different +signals with Two different frequencies. + +The TIM9CLK frequency is set to SystemCoreClock (Hz), and we want to get TIM9 +counter clock at 15 MHz so the Prescaler is computed as following: + - Prescaler = (TIM9CLK / TIM9 counter clock) - 1 + +SystemCoreClock is set to 120 MHz for STM32F2xx devices + +The TIM9 CCR1 register value is equal to 40961: +CC1 update rate = TIM9 counter clock / CCR1_Val = 366.2 Hz, +so the TIM9 Channel 1 generates a periodic signal with a frequency equal to 183.1 Hz. + +The TIM9 CCR2 register is equal to 20480: +CC2 update rate = TIM9 counter clock / CCR2_Val = 732.4 Hz +so the TIM9 channel 2 generates a periodic signal with a frequency equal to 366.3 Hz. + +@par Directory contents + + - TIM/TIM9_OCToggle/stm32f2xx_conf.h Library Configuration file + - TIM/TIM9_OCToggle/stm32f2xx_it.c Interrupt handlers + - TIM/TIM9_OCToggle/stm32f2xx_it.h Interrupt handlers header file + - TIM/TIM9_OCToggle/main.c Main program + - TIM/TIM9_OCToggle/system_stm32f2xx.c STM32F2xx system clock configuration file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect the TIM9 pins to an oscilloscope to monitor the different waveforms: + - PA.02 (TIM9_CH1) + - PA.03 (TIM9_CH2) + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f2xx_conf.h new file mode 100644 index 000000000..1e097ea25 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file TIM/TIM9_TIM9_OCToggle/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f2xx_it.c new file mode 100644 index 000000000..0d15f1569 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f2xx_it.c @@ -0,0 +1,198 @@ +/** + ****************************************************************************** + * @file TIM/TIM9_OCToggle/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_TIM9_OCToggle + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint16_t capture = 0; +extern __IO uint16_t CCR1_Val; +extern __IO uint16_t CCR2_Val; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles TIM9 global interrupt request. + * @param None + * @retval None + */ +void TIM1_BRK_TIM9_IRQHandler(void) +{ + /* TIM9_CH1 toggling with frequency = 183.1 Hz */ + if (TIM_GetITStatus(TIM9, TIM_IT_CC1) != RESET) + { + TIM_ClearITPendingBit(TIM9, TIM_IT_CC1); + capture = TIM_GetCapture1(TIM9); + TIM_SetCompare1(TIM9, capture + CCR1_Val); + } + + /* TIM9_CH2 toggling with frequency = 366.2 Hz */ + if (TIM_GetITStatus(TIM9, TIM_IT_CC2) != RESET) + { + TIM_ClearITPendingBit(TIM9, TIM_IT_CC2); + capture = TIM_GetCapture2(TIM9); + TIM_SetCompare2(TIM9, capture + CCR2_Val); + } + +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f2xx_it.h new file mode 100644 index 000000000..4518febc4 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file TIM/TIM9_OCToggle/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TIM1_BRK_TIM9_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/main.c new file mode 100644 index 000000000..ad3c67a9d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/main.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file TIM/TimeBase/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_TimeBase + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +TIM_OCInitTypeDef TIM_OCInitStructure; +__IO uint16_t CCR1_Val = 40961; +__IO uint16_t CCR2_Val = 27309; +__IO uint16_t CCR3_Val = 13654; +__IO uint16_t CCR4_Val = 6826; +uint16_t PrescalerValue = 0; + +/* Private function prototypes -----------------------------------------------*/ +void TIM_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* TIM Configuration */ + TIM_Config(); + + /* ----------------------------------------------------------------------- + TIM3 Configuration: Output Compare Timing Mode: + + In this example TIM3 input clock (TIM3CLK) is set to 2 * APB1 clock (PCLK1), + since APB1 prescaler is different from 1. + TIM3CLK = 2 * PCLK1 + PCLK1 = HCLK / 4 + => TIM3CLK = HCLK / 2 = SystemCoreClock /2 + + To get TIM3 counter clock at 6 MHz, the prescaler is computed as follows: + Prescaler = (TIM3CLK / TIM3 counter clock) - 1 + Prescaler = ((SystemCoreClock /2) /6 MHz) - 1 + + CC1 update rate = TIM3 counter clock / CCR1_Val = 146.48 Hz + ==> Toggling frequency = 73.24 Hz + + C2 update rate = TIM3 counter clock / CCR2_Val = 219.7 Hz + ==> Toggling frequency = 109.8 Hz + + CC3 update rate = TIM3 counter clock / CCR3_Val = 439.4 Hz + ==> Toggling frequency = 219.7 Hz + + CC4 update rate = TIM3 counter clock / CCR4_Val = 878.9 Hz + ==> Toggling frequency = 439.4 Hz + + Note: + SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f2xx.c file. + Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() + function to update SystemCoreClock variable value. Otherwise, any configuration + based on this variable will be incorrect. + ----------------------------------------------------------------------- */ + + + /* Compute the prescaler value */ + PrescalerValue = (uint16_t) ((SystemCoreClock / 2) / 6000000) - 1; + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 65535; + TIM_TimeBaseStructure.TIM_Prescaler = 0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); + + /* Prescaler configuration */ + TIM_PrescalerConfig(TIM3, PrescalerValue, TIM_PSCReloadMode_Immediate); + + /* Output Compare Timing Mode configuration: Channel1 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR1_Val; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + + TIM_OC1Init(TIM3, &TIM_OCInitStructure); + + TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Disable); + + /* Output Compare Timing Mode configuration: Channel2 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR2_Val; + + TIM_OC2Init(TIM3, &TIM_OCInitStructure); + + TIM_OC2PreloadConfig(TIM3, TIM_OCPreload_Disable); + + /* Output Compare Timing Mode configuration: Channel3 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR3_Val; + + TIM_OC3Init(TIM3, &TIM_OCInitStructure); + + TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Disable); + + /* Output Compare Timing Mode configuration: Channel4 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = CCR4_Val; + + TIM_OC4Init(TIM3, &TIM_OCInitStructure); + + TIM_OC4PreloadConfig(TIM3, TIM_OCPreload_Disable); + + /* TIM Interrupts enable */ + TIM_ITConfig(TIM3, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4, ENABLE); + + /* TIM3 enable counter */ + TIM_Cmd(TIM3, ENABLE); + + while (1); +} + +/** + * @brief Configure the TIM IRQ Handler. + * @param None + * @retval None + */ +void TIM_Config(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + /* TIM3 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); + + /* Enable the TIM3 gloabal Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Initialize Leds mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Turn on LED1, LED2, LED3 and LED4 */ + STM_EVAL_LEDOn(LED1); + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/readme.txt new file mode 100644 index 000000000..e5d1a0564 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/readme.txt @@ -0,0 +1,103 @@ +/** + @page TIM_TimeBase TIM_TimeBase + + @verbatim + ****************************************************************************** + * @file TIM/TimeBase/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the TIM Time Base example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to configure the TIM peripheral in Output Compare Timing +mode with the corresponding Interrupt requests for each channel in order to generate +4 different time bases. + +The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), to get TIM3 counter +clock at 6 MHz so the Prescaler is computed as following: + - Prescaler = (TIM3CLK / TIM3 counter clock) - 1 + +SystemCoreClock is set to 120MHz for STM32F2xx Devices RevA, RevZ and RevB. + +The TIM3 CC1 register value is equal to 40961, +CC1 update rate = TIM3 counter clock / CCR1_Val = 146.48 Hz, +so the TIM3 Channel 1 generates an interrupt each 6.8ms + +The TIM3 CC2 register is equal to 27309, +CC2 update rate = TIM3 counter clock / CCR2_Val = 219.7 Hz +so the TIM3 Channel 2 generates an interrupt each 4.55ms + +The TIM3 CC3 register is equal to 13654, +CC3 update rate = TIM3 counter clock / CCR3_Val = 439.4Hz +so the TIM3 Channel 3 generates an interrupt each 2.27ms + +The TIM3 CC4 register is equal to 6826, +CC4 update rate = TIM3 counter clock / CCR4_Val = 878.9 Hz +so the TIM3 Channel 4 generates an interrupt each 1.13ms. + +When the counter value reaches the Output compare registers values, the Output +Compare interrupts are generated and, in the handler routine, 4 pins(PG.06, PG.08, +PI.09 and PC.07) are toggled with the following frequencies: + +- PG.06: 73.24Hz (CC1) +- PG.08: 109.8Hz (CC2) +- PI.09: 219.7Hz (CC3) +- PC.07: 439.4Hz (CC4) + +@par Directory contents + + - TIM/TimeBase/stm32f2xx_conf.h Library Configuration file + - TIM/TimeBase/stm32f2xx_it.c Interrupt handlers + - TIM/TimeBase/stm32f2xx_it.h Interrupt handlers header file + - TIM/TimeBase/main.c Main program + - TIM/TimeBase/system_stm32f2xx.c STM32F2xx system clock configuration file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins and connect them on an oscilloscope to show the different + Time Base signals. + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/stm32f2xx_conf.h new file mode 100644 index 000000000..ec5011024 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/stm32f2xx_conf.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file TIM/TimeBase/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/stm32f2xx_it.c new file mode 100644 index 000000000..c0646471e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/stm32f2xx_it.c @@ -0,0 +1,221 @@ +/** + ****************************************************************************** + * @file TIM/TimeBase/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup TIM_TimeBase + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint16_t capture = 0; +extern __IO uint16_t CCR1_Val; +extern __IO uint16_t CCR2_Val; +extern __IO uint16_t CCR3_Val; +extern __IO uint16_t CCR4_Val; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + {} +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles TIM3 global interrupt request. + * @param None + * @retval None + */ +void TIM3_IRQHandler(void) +{ + if (TIM_GetITStatus(TIM3, TIM_IT_CC1) != RESET) + { + TIM_ClearITPendingBit(TIM3, TIM_IT_CC1); + + /* LED1 toggling with frequency = 73.24 Hz */ + STM_EVAL_LEDToggle(LED1); + capture = TIM_GetCapture1(TIM3); + TIM_SetCompare1(TIM3, capture + CCR1_Val); + } + else if (TIM_GetITStatus(TIM3, TIM_IT_CC2) != RESET) + { + TIM_ClearITPendingBit(TIM3, TIM_IT_CC2); + + /* LED2 toggling with frequency = 109.8 Hz */ + STM_EVAL_LEDToggle(LED2); + capture = TIM_GetCapture2(TIM3); + TIM_SetCompare2(TIM3, capture + CCR2_Val); + } + else if (TIM_GetITStatus(TIM3, TIM_IT_CC3) != RESET) + { + TIM_ClearITPendingBit(TIM3, TIM_IT_CC3); + + /* LED3 toggling with frequency = 219.7 Hz */ + STM_EVAL_LEDToggle(LED3); + capture = TIM_GetCapture3(TIM3); + TIM_SetCompare3(TIM3, capture + CCR3_Val); + } + else + { + TIM_ClearITPendingBit(TIM3, TIM_IT_CC4); + + /* LED4 toggling with frequency = 439.4 Hz */ + STM_EVAL_LEDToggle(LED4); + capture = TIM_GetCapture4(TIM3); + TIM_SetCompare4(TIM3, capture + CCR4_Val); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/stm32f2xx_it.h new file mode 100644 index 000000000..e2d7afb5d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file TIM/TimeBase/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void TIM2_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/TIM/TimeBase/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c new file mode 100644 index 000000000..d0dc8edb9 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file USART/HyperTerminal_Interrupt/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup USART_HyperTerminal_Interrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +USART_InitTypeDef USART_InitStructure; +extern uint8_t NbrOfDataToTransfer; +extern uint8_t NbrOfDataToRead; +extern __IO uint8_t TxCounter; +extern __IO uint16_t RxCounter; +/* Private function prototypes -----------------------------------------------*/ +void NVIC_Config(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* NVIC configuration */ + NVIC_Config(); + +/* USARTx configuration ------------------------------------------------------*/ + /* USARTx configured as follow: + - BaudRate = 9600 baud + - Word Length = 8 Bits + - Two Stop Bit + - Odd parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitStructure.USART_BaudRate = 9600; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_2; + USART_InitStructure.USART_Parity = USART_Parity_Odd; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit(COM1, &USART_InitStructure); + + /* Enable the EVAL_COM1 Transmit interrupt: this interrupt is generated when the + EVAL_COM1 transmit data register is empty */ + USART_ITConfig(EVAL_COM1, USART_IT_TXE, ENABLE); + + /* Wait until EVAL_COM1 send the TxBuffer */ + while(TxCounter < NbrOfDataToTransfer) + {} + + /* The software must wait until TC=1. The TC flag remains cleared during all data + transfers and it is set by hardware at the last frame’s end of transmission*/ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) + {} + + /* Enable the EVAL_COM1 Receive interrupt: this interrupt is generated when the + EVAL_COM1 receive data register is not empty */ + USART_ITConfig(EVAL_COM1, USART_IT_RXNE, ENABLE); + + /* Wait until EVAL_COM1 receive the RxBuffer */ + while(RxCounter < NbrOfDataToRead) + {} + + while (1) + { + } +} + +/** + * @brief Configures the nested vectored interrupt controller. + * @param None + * @retval None + */ +void NVIC_Config(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + /* Enable the USARTx Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = EVAL_COM1_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/readme.txt new file mode 100644 index 000000000..b6ff0866a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/readme.txt @@ -0,0 +1,98 @@ +/** + @page USART_HyperTerminal_Interrupt USART Hyperterminal interrupt Example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file USART/HyperTerminal_Interrupt/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the USART Hyperterminal interrupt Example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a description of how to use the EVAL_COM1 Transmit and Receive +interrupts to communicate with the hyperterminal. + + +First, the EVAL_COM1 sends the TxBuffer to the hyperterminal and still waiting for +a string from the hyperterminal that you must enter. +The string that you have entered is stored in the RxBuffer array. The receive +buffer have a RxBufferSize bytes as maximum (the reception is stopped when this +maximum receive value is reached). + +The EVAL_COM1 is configured as follow: + - BaudRate = 9600 baud + - Word Length = 8 Bits (7 data bit + 1 parity bit) + - Two Stop Bit + - Odd parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + +@note When the parity is enabled, the computed parity is inserted at the MSB +position of the transmitted data. + + +@par Directory contents + + - USART/HyperTerminal_Interrupt/stm32f2xx_conf.h Library Configuration file + - USART/HyperTerminal_Interrupt/stm32f2xx_it.h Interrupt handlers header file + - USART/HyperTerminal_Interrupt/stm32f2xx_it.c Interrupt handlers source file + - USART/HyperTerminal_Interrupt/main.c Main program + - USART/HyperTerminal_Interrupt/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port if you want to display data on the HyperTerminal. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 7 Bits + - Two Stop Bit + - Odd parity + - BaudRate = 9600 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f2xx_conf.h new file mode 100644 index 000000000..c6055bf20 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file USART/HyperTerminal_Interrupt/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f2xx_it.c new file mode 100644 index 000000000..f6bff6db5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f2xx_it.c @@ -0,0 +1,225 @@ +/** + ****************************************************************************** + * @file USART/HyperTerminal_Interrupt/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup USART_HyperTerminal_Interrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define USARTx_IRQHANDLER USART3_IRQHandler + +#define TXBUFFERSIZE (countof(TxBuffer) - 1) +#define RXBUFFERSIZE 0x20 + +/* Private macro -------------------------------------------------------------*/ +#define countof(a) (sizeof(a) / sizeof(*(a))) + +/* Private variables ---------------------------------------------------------*/ +uint8_t TxBuffer[] = "\n\rUSART Hyperterminal Interrupts Example: USART-Hyperterminal\ + communication using Interrupt\n\r"; +uint8_t RxBuffer[RXBUFFERSIZE]; +uint8_t NbrOfDataToTransfer = TXBUFFERSIZE; +uint8_t NbrOfDataToRead = RXBUFFERSIZE; +__IO uint8_t TxCounter = 0; +__IO uint16_t RxCounter = 0; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles USARTx global interrupt request. + * @param None + * @retval None + */ +void USARTx_IRQHANDLER(void) +{ + if(USART_GetITStatus(EVAL_COM1, USART_IT_RXNE) != RESET) + { + /* Read one byte from the receive data register */ + RxBuffer[RxCounter++] = (USART_ReceiveData(EVAL_COM1) & 0x7F); + + if(RxCounter == NbrOfDataToRead) + { + /* Disable the EVAL_COM1 Receive interrupt */ + USART_ITConfig(EVAL_COM1, USART_IT_RXNE, DISABLE); + } + } + + if(USART_GetITStatus(EVAL_COM1, USART_IT_TXE) != RESET) + { + /* Write one byte to the transmit data register */ + USART_SendData(EVAL_COM1, TxBuffer[TxCounter++]); + + if(TxCounter == NbrOfDataToTransfer) + { + /* Disable the EVAL_COM1 Transmit interrupt */ + USART_ITConfig(EVAL_COM1, USART_IT_TXE, DISABLE); + } + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f2xx_it.h new file mode 100644 index 000000000..61a1d047d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file USART/HyperTerminal_Interrupt/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void USARTx_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/main.c new file mode 100644 index 000000000..da09eea31 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/main.c @@ -0,0 +1,373 @@ +/** + ****************************************************************************** + * @file USART/Smartcard/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup USART_SmartCard + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#include "smartcard.h" +#include "stm322xg_eval.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Directories & Files ID */ +const uint8_t MasterRoot[2] = {0x3F, 0x00}; +const uint8_t GSMDir[2] = {0x7F, 0x20}; +const uint8_t ICCID[2] = {0x2F, 0xE2}; +const uint8_t IMSI[2] = {0x6F, 0x07}; +const uint8_t CHV1[8] = {'0', '0', '0', '0', '0', '0', '0', '0'}; + +/* APDU Transport Structures */ +SC_ADPU_Commands SC_ADPU; +SC_ADPU_Responce SC_Responce; +__IO uint32_t TimingDelay = 0; +static __IO ErrorStatus HSEStartUpStatus = SUCCESS; +__IO uint32_t CardInserted = 0; +uint32_t CHV1Status = 0, i = 0; +__IO uint8_t ICCID_Content[10] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; +__IO uint8_t IMSI_Content[9] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +/* Private function prototypes -----------------------------------------------*/ +static void Delay(uint32_t nCount); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + SC_State SCState = SC_POWER_OFF; + + /* Setup SysTick Timer for 1 msec interrupts */ + SysTick_Config(SystemCoreClock / 1000); + + /* Initialize LEDs available on STM322xG-EVAL board *************************/ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Configure Smartcard Interface GPIO pins */ + SC_IOConfig(); + +/*-------------------------------- Idle task ---------------------------------*/ + while(1) + { + /* Loop while no Smartcard is detected */ + while(CardInserted == 0) + { + } + + /* Start SC Demo ---------------------------------------------------------*/ + + /* Wait A2R --------------------------------------------------------------*/ + SCState = SC_POWER_ON; + + SC_ADPU.Header.CLA = 0x00; + SC_ADPU.Header.INS = SC_GET_A2R; + SC_ADPU.Header.P1 = 0x00; + SC_ADPU.Header.P2 = 0x00; + SC_ADPU.Body.LC = 0x00; + + while(SCState != SC_ACTIVE_ON_T0) + { + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + } + + /* Apply the Procedure Type Selection (PTS) */ + SC_PTSConfig(); + + /* Inserts delay(400ms) for Smartcard clock resynchronisation */ + Delay(400); + + /* Select MF -------------------------------------------------------------*/ + SC_ADPU.Header.CLA = SC_CLA_GSM11; + SC_ADPU.Header.INS = SC_SELECT_FILE; + SC_ADPU.Header.P1 = 0x00; + SC_ADPU.Header.P2 = 0x00; + SC_ADPU.Body.LC = 0x02; + + for(i = 0; i < SC_ADPU.Body.LC; i++) + { + SC_ADPU.Body.Data[i] = MasterRoot[i]; + } + while(i < LC_MAX) + { + SC_ADPU.Body.Data[i++] = 0; + } + SC_ADPU.Body.LE = 0; + + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + + /* Get Response on MF ----------------------------------------------------*/ + if(SC_Responce.SW1 == SC_DF_SELECTED) + { + SC_ADPU.Header.CLA = SC_CLA_GSM11; + SC_ADPU.Header.INS = SC_GET_RESPONCE; + SC_ADPU.Header.P1 = 0x00; + SC_ADPU.Header.P2 = 0x00; + SC_ADPU.Body.LC = 0x00; + SC_ADPU.Body.LE = SC_Responce.SW2; + + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + } + + /* Select ICCID ----------------------------------------------------------*/ + if(((SC_Responce.SW1 << 8) | (SC_Responce.SW2)) == SC_OP_TERMINATED) + { + /* Check if the CHV1 is enabled */ + if((SC_Responce.Data[13] & 0x80) == 0x00) + { + CHV1Status = 0x01; + } + /* Send APDU Command for ICCID selection */ + SC_ADPU.Header.CLA = SC_CLA_GSM11; + SC_ADPU.Header.INS = SC_SELECT_FILE; + SC_ADPU.Header.P1 = 0x00; + SC_ADPU.Header.P2 = 0x00; + SC_ADPU.Body.LC = 0x02; + + for(i = 0; i < SC_ADPU.Body.LC; i++) + { + SC_ADPU.Body.Data[i] = ICCID[i]; + } + while(i < LC_MAX) + { + SC_ADPU.Body.Data[i++] = 0; + } + SC_ADPU.Body.LE = 0; + + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + } + + /* Read Binary in ICCID --------------------------------------------------*/ + if(SC_Responce.SW1 == SC_EF_SELECTED) + { + SC_ADPU.Header.CLA = SC_CLA_GSM11; + SC_ADPU.Header.INS = SC_READ_BINARY; + SC_ADPU.Header.P1 = 0x00; + SC_ADPU.Header.P2 = 0x00; + SC_ADPU.Body.LC = 0x00; + + SC_ADPU.Body.LE = 10; + + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + } + + /* Select GSMDir ---------------------------------------------------------*/ + if(((SC_Responce.SW1 << 8) | (SC_Responce.SW2)) == SC_OP_TERMINATED) + { + /* Copy the ICCID File content into ICCID_Content buffer */ + for(i = 0; i < SC_ADPU.Body.LE; i++) + { + ICCID_Content[i] = SC_Responce.Data[i]; + } + /* Send APDU Command for GSMDir selection */ + SC_ADPU.Header.CLA = SC_CLA_GSM11; + SC_ADPU.Header.INS = SC_SELECT_FILE; + SC_ADPU.Header.P1 = 0x00; + SC_ADPU.Header.P2 = 0x00; + SC_ADPU.Body.LC = 0x02; + + for(i = 0; i < SC_ADPU.Body.LC; i++) + { + SC_ADPU.Body.Data[i] = GSMDir[i]; + } + while(i < LC_MAX) + { + SC_ADPU.Body.Data[i++] = 0; + } + SC_ADPU.Body.LE = 0; + + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + } + + /* Select IMSI -----------------------------------------------------------*/ + if(SC_Responce.SW1 == SC_DF_SELECTED) + { + SC_ADPU.Header.CLA = SC_CLA_GSM11; + SC_ADPU.Header.INS = SC_SELECT_FILE; + SC_ADPU.Header.P1 = 0x00; + SC_ADPU.Header.P2 = 0x00; + SC_ADPU.Body.LC = 0x02; + + for(i = 0; i < SC_ADPU.Body.LC; i++) + { + SC_ADPU.Body.Data[i] = IMSI[i]; + } + while(i < LC_MAX) + { + SC_ADPU.Body.Data[i++] = 0; + } + SC_ADPU.Body.LE = 0; + + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + } + + /* Get Response on IMSI File ---------------------------------------------*/ + if(SC_Responce.SW1 == SC_EF_SELECTED) + { + SC_ADPU.Header.CLA = SC_CLA_GSM11; + SC_ADPU.Header.INS = SC_GET_RESPONCE; + SC_ADPU.Header.P1 = 0x00; + SC_ADPU.Header.P2 = 0x00; + SC_ADPU.Body.LC = 0x00; + SC_ADPU.Body.LE = SC_Responce.SW2; + + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + } + + /* Read Binary in IMSI ---------------------------------------------------*/ + if(CHV1Status == 0x00) + { + if(((SC_Responce.SW1 << 8) | (SC_Responce.SW2)) == SC_OP_TERMINATED) + { + /* Enable CHV1 (PIN1) ------------------------------------------------*/ + SC_ADPU.Header.CLA = SC_CLA_GSM11; + SC_ADPU.Header.INS = SC_ENABLE; + SC_ADPU.Header.P1 = 0x00; + SC_ADPU.Header.P2 = 0x01; + SC_ADPU.Body.LC = 0x08; + + for(i = 0; i < SC_ADPU.Body.LC; i++) + { + SC_ADPU.Body.Data[i] = CHV1[i]; + } + while(i < LC_MAX) + { + SC_ADPU.Body.Data[i++] = 0; + } + SC_ADPU.Body.LE = 0; + + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + } + } + else + { + if(((SC_Responce.SW1 << 8) | (SC_Responce.SW2)) == SC_OP_TERMINATED) + { + /* Verify CHV1 (PIN1) ------------------------------------------------*/ + SC_ADPU.Header.CLA = SC_CLA_GSM11; + SC_ADPU.Header.INS = SC_VERIFY; + SC_ADPU.Header.P1 = 0x00; + SC_ADPU.Header.P2 = 0x01; + SC_ADPU.Body.LC = 0x08; + + for(i = 0; i < SC_ADPU.Body.LC; i++) + { + SC_ADPU.Body.Data[i] = CHV1[i]; + } + while(i < LC_MAX) + { + SC_ADPU.Body.Data[i++] = 0; + } + SC_ADPU.Body.LE = 0; + + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + } + } + /* Read Binary in IMSI ---------------------------------------------------*/ + if(((SC_Responce.SW1 << 8) | (SC_Responce.SW2)) == SC_OP_TERMINATED) + { + SC_ADPU.Header.CLA = SC_CLA_GSM11; + SC_ADPU.Header.INS = SC_READ_BINARY; + SC_ADPU.Header.P1 = 0x00; + SC_ADPU.Header.P2 = 0x00; + SC_ADPU.Body.LC = 0x00; + + SC_ADPU.Body.LE = 9; + + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + } + if(((SC_Responce.SW1 << 8) | (SC_Responce.SW2)) == SC_OP_TERMINATED) + { + /* Copy the IMSI File content into IMSI_Content buffer */ + for(i = 0; i < SC_ADPU.Body.LE; i++) + { + IMSI_Content[i] = SC_Responce.Data[i]; + } + } + /* Disable the Smartcard interface */ + SCState = SC_POWER_OFF; + SC_Handler(&SCState, &SC_ADPU, &SC_Responce); + CardInserted = 0; + } +} + +/** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length (time base 10 ms). + * @retval None + */ +static void Delay(uint32_t nCount) +{ + TimingDelay = nCount; + + while(TimingDelay != 0) + { + } +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number where + * the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/platform_config.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/platform_config.h new file mode 100644 index 000000000..4593d2616 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/platform_config.h @@ -0,0 +1,92 @@ +/** + ****************************************************************************** + * @file USART/Smartcard/platform_config.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Evaluation board specific configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PLATFORM_CONFIG_H +#define __PLATFORM_CONFIG_H + +/* Includes ------------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line corresponding to the STMicroelectronics evaluation board + used to run the example */ +#if !defined (USE_STM322xG_EVAL) + //#define USE_STM322xG_EVAL +#endif + +/* Define the STM32F2xx hardware depending on the used evaluation board */ +#ifdef USE_STM322xG_EVAL + #define SC_USART USART6 + #define SC_USART_CLK RCC_APB2Periph_USART6 + #define SC_USART_APBPERIPHCLOCK RCC_APB2PeriphClockCmd + #define SC_USART_IRQn USART6_IRQn + #define SC_USART_IRQHandler USART6_IRQHandler + + #define SC_USART_TX_PIN GPIO_Pin_6 + #define SC_USART_TX_GPIO_PORT GPIOC + #define SC_USART_TX_GPIO_CLK RCC_AHB1Periph_GPIOC + #define SC_USART_TX_SOURCE GPIO_PinSource6 + #define SC_USART_TX_AF GPIO_AF_USART6 + + #define SC_USART_CK_PIN GPIO_Pin_7 + #define SC_USART_CK_GPIO_PORT GPIOG + #define SC_USART_CK_GPIO_CLK RCC_AHB1Periph_GPIOG + #define SC_USART_CK_SOURCE GPIO_PinSource7 + #define SC_USART_CK_AF GPIO_AF_USART6 + + + /* Smartcard Inteface GPIO pins */ + #define SC_3_5V_PIN GPIO_Pin_15 + #define SC_3_5V_GPIO_PORT GPIOH + #define SC_3_5V_GPIO_CLK RCC_AHB1Periph_GPIOH + + #define SC_RESET_PIN GPIO_Pin_7 + #define SC_RESET_GPIO_PORT GPIOF + #define SC_RESET_GPIO_CLK RCC_AHB1Periph_GPIOF + + #define SC_CMDVCC_PIN GPIO_Pin_12 + #define SC_CMDVCC_GPIO_PORT GPIOG + #define SC_CMDVCC_GPIO_CLK RCC_AHB1Periph_GPIOG + + #define SC_OFF_PIN GPIO_Pin_6 + #define SC_OFF_GPIO_PORT GPIOF + #define SC_OFF_GPIO_CLK RCC_AHB1Periph_GPIOF + #define SC_OFF_EXTI_LINE EXTI_Line6 + #define SC_OFF_EXTI_PORT_SOURCE EXTI_PortSourceGPIOF + #define SC_OFF_EXTI_PIN_SOURCE EXTI_PinSource6 + #define SC_OFF_EXTI_IRQn EXTI9_5_IRQn + #define SC_OFF_EXTI_IRQHandler EXTI9_5_IRQHandler + +#endif /* USE_STM322xG_EVAL */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __PLATFORM_CONFIG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/readme.txt new file mode 100644 index 000000000..b6e2c2b5b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/readme.txt @@ -0,0 +1,85 @@ +/** + @page USART_Smartcard USART Smart Card example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file USART/SmartCard/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the USART Smart Card example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example describes a firmware Smartcard Interface based on the STM32F2xx USART +peripheral. The main purpose of this firmware example is to provide resources +facilitating the development of an application using the USART peripheral in +smartcard mode. + +The firmware interface is composed of library source files developed in order to +support ISO7816-3/4 specification, an application example is also provided. + +This example is based on the AN2598 "Smartcard interface with the STM32F101xx +and STM32F103xx" application note. For more details, please refer to AN2598 +available on www.st.com + + +@par Directory contents + + - USART/SmartCard/platform_config.h Evaluation board specific configuration file + - USART/SmartCard/stm32f2xx_conf.h Library Configuration file + - USART/SmartCard/stm32f2xx_it.h Interrupt handlers header file + - USART/SmartCard/smartcard.h Smart card Header file + - USART/SmartCard/stm32f2xx_it.c Interrupt handlers + - USART/SmartCard/smartcard.c Smart Card firmware functions + - USART/SmartCard/main.c Main program + - USART/SmartCard/system_stm32f2xx.c STM32F2xx system source file + + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + - Make sure that JP21 is closed. + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Add the "smartcard.c" file to the project source list + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/smartcard.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/smartcard.c new file mode 100644 index 000000000..8d66610cb --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/smartcard.c @@ -0,0 +1,858 @@ +/** + ****************************************************************************** + * @file USART/Smartcard/smartcard.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file provides all the Smartcard firmware functions. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup USART_SmartCard + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#include "smartcard.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Global variables definition and initialization ----------------------------*/ +SC_ATR SC_A2R; +uint8_t SC_ATR_Table[40]; +static __IO uint8_t SCData = 0; +static uint32_t F_Table[16] = {0, 372, 558, 744, 1116, 1488, 1860, 0, + 0, 512, 768, 1024, 1536, 2048, 0, 0}; +static uint32_t D_Table[8] = {0, 1, 2, 4, 8, 16, 0, 0}; + +/* Private function prototypes -----------------------------------------------*/ +/* Transport Layer -----------------------------------------------------------*/ +/*--------------APDU-----------*/ +static void SC_SendData(SC_ADPU_Commands *SC_ADPU, SC_ADPU_Responce *SC_ResponceStatus); + +/*------------ ATR ------------*/ +static void SC_AnswerReq(SC_State *SCState, uint8_t *card, uint8_t length); /* Ask ATR */ +static uint8_t SC_decode_Answer2reset(uint8_t *card); /* Decode ATR */ + +/* Physical Port Layer -------------------------------------------------------*/ +static void SC_Init(void); +static void SC_DeInit(void); +static void SC_VoltageConfig(uint32_t SC_Voltage); +static uint8_t SC_Detect(void); +static ErrorStatus USART_ByteReceive(uint8_t *Data, uint32_t TimeOut); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Handles all Smartcard states and serves to send and receive all + * communication data between Smartcard and reader. + * @param SCState: pointer to an SC_State enumeration that will contain the + * Smartcard state. + * @param SC_ADPU: pointer to an SC_ADPU_Commands structure that will be initialized. + * @param SC_Response: pointer to a SC_ADPU_Responce structure which will be initialized. + * @retval None + */ +void SC_Handler(SC_State *SCState, SC_ADPU_Commands *SC_ADPU, SC_ADPU_Responce *SC_Response) +{ + uint32_t i = 0; + + switch(*SCState) + { + case SC_POWER_ON: + if (SC_ADPU->Header.INS == SC_GET_A2R) + { + /* Smartcard intialization ------------------------------------------*/ + SC_Init(); + + /* Reset Data from SC buffer -----------------------------------------*/ + for (i = 0; i < 40; i++) + { + SC_ATR_Table[i] = 0; + } + + /* Reset SC_A2R Structure --------------------------------------------*/ + SC_A2R.TS = 0; + SC_A2R.T0 = 0; + for (i = 0; i < SETUP_LENGTH; i++) + { + SC_A2R.T[i] = 0; + } + for (i = 0; i < HIST_LENGTH; i++) + { + SC_A2R.H[i] = 0; + } + SC_A2R.Tlength = 0; + SC_A2R.Hlength = 0; + + /* Next State --------------------------------------------------------*/ + *SCState = SC_RESET_LOW; + } + break; + + case SC_RESET_LOW: + if(SC_ADPU->Header.INS == SC_GET_A2R) + { + /* If card is detected then Power ON, Card Reset and wait for an answer) */ + if (SC_Detect()) + { + while(((*SCState) != SC_POWER_OFF) && ((*SCState) != SC_ACTIVE)) + { + SC_AnswerReq(SCState, &SC_ATR_Table[0], 40); /* Check for answer to reset */ + } + } + else + { + (*SCState) = SC_POWER_OFF; + } + } + break; + + case SC_ACTIVE: + if (SC_ADPU->Header.INS == SC_GET_A2R) + { + if(SC_decode_Answer2reset(&SC_ATR_Table[0]) == T0_PROTOCOL) + { + (*SCState) = SC_ACTIVE_ON_T0; + } + else + { + (*SCState) = SC_POWER_OFF; + } + } + break; + + case SC_ACTIVE_ON_T0: + SC_SendData(SC_ADPU, SC_Response); + break; + + case SC_POWER_OFF: + SC_DeInit(); /* Disable Smartcard interface */ + break; + + default: (*SCState) = SC_POWER_OFF; + } +} + +/** + * @brief Enables or disables the power to the Smartcard. + * @param NewState: new state of the Smartcard power supply. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SC_PowerCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + GPIO_ResetBits(SC_CMDVCC_GPIO_PORT, SC_CMDVCC_PIN); + } + else + { + GPIO_SetBits(SC_CMDVCC_GPIO_PORT, SC_CMDVCC_PIN); + } +} + +/** + * @brief Sets or clears the Smartcard reset pin. + * @param ResetState: this parameter specifies the state of the Smartcard + * reset pin. BitVal must be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin. + * @arg Bit_SET: to set the port pin. + * @retval None + */ +void SC_Reset(BitAction ResetState) +{ + GPIO_WriteBit(SC_RESET_GPIO_PORT, SC_RESET_PIN, ResetState); +} + +/** + * @brief Resends the byte that failed to be received (by the Smartcard) correctly. + * @param None + * @retval None + */ +void SC_ParityErrorHandler(void) +{ + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } +} + +/** + * @brief Configures the IO speed (BaudRate) communication. + * @param None + * @retval None + */ +void SC_PTSConfig(void) +{ + RCC_ClocksTypeDef RCC_ClocksStatus; + uint32_t workingbaudrate = 0, apbclock = 0; + uint8_t locData = 0, PTSConfirmStatus = 1; + USART_InitTypeDef USART_InitStructure; + USART_ClockInitTypeDef USART_ClockInitStructure; + +/* Reconfigure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + apbclock /= ((SC_USART->GTPR & (uint16_t)0x00FF) * 2); + + /* Enable the DMA Receive (Set DMAR bit only) to enable interrupt generation + in case of a framing error FE */ + USART_DMACmd(SC_USART, USART_DMAReq_Rx, ENABLE); + + if((SC_A2R.T0 & (uint8_t)0x10) == 0x10) + { + if(SC_A2R.T[0] != 0x11) + { + /* Send PTSS */ + SCData = 0xFF; + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } + + /* Send PTS0 */ + SCData = 0x10; + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } + + /* Send PTS1 */ + SCData = SC_A2R.T[0]; + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } + + /* Send PCK */ + SCData = (uint8_t)0xFF^(uint8_t)0x10^(uint8_t)SC_A2R.T[0]; + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } + + /* Disable the DMA Receive (Reset DMAR bit only) */ + USART_DMACmd(SC_USART, USART_DMAReq_Rx, DISABLE); + + if((USART_ByteReceive(&locData, SC_RECEIVE_TIMEOUT)) == SUCCESS) + { + if(locData != 0xFF) + { + PTSConfirmStatus = 0x00; + } + } + if((USART_ByteReceive(&locData, SC_RECEIVE_TIMEOUT)) == SUCCESS) + { + if(locData != 0x10) + { + PTSConfirmStatus = 0x00; + } + } + if((USART_ByteReceive(&locData, SC_RECEIVE_TIMEOUT)) == SUCCESS) + { + if(locData != SC_A2R.T[0]) + { + PTSConfirmStatus = 0x00; + } + } + if((USART_ByteReceive(&locData, SC_RECEIVE_TIMEOUT)) == SUCCESS) + { + if(locData != ((uint8_t)0xFF^(uint8_t)0x10^(uint8_t)SC_A2R.T[0])) + { + PTSConfirmStatus = 0x00; + } + } + else + { + PTSConfirmStatus = 0x00; + } + /* PTS Confirm */ + if(PTSConfirmStatus == 0x01) + { + workingbaudrate = apbclock * D_Table[(SC_A2R.T[0] & (uint8_t)0x0F)]; + workingbaudrate /= F_Table[((SC_A2R.T[0] >> 4) & (uint8_t)0x0F)]; + + USART_ClockInitStructure.USART_Clock = USART_Clock_Enable; + USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low; + USART_ClockInitStructure.USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStructure.USART_LastBit = USART_LastBit_Enable; + USART_ClockInit(SC_USART, &USART_ClockInitStructure); + + USART_InitStructure.USART_BaudRate = workingbaudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_9b; + USART_InitStructure.USART_StopBits = USART_StopBits_1_5; + USART_InitStructure.USART_Parity = USART_Parity_Even; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_Init(SC_USART, &USART_InitStructure); + } + } + } +} + +/** + * @brief Manages the Smartcard transport layer: send APDU commands and receives + * the APDU responce. + * @param SC_ADPU: pointer to a SC_ADPU_Commands structure which will be initialized. + * @param SC_Response: pointer to a SC_ADPU_Responce structure which will be initialized. + * @retval None + */ +static void SC_SendData(SC_ADPU_Commands *SC_ADPU, SC_ADPU_Responce *SC_ResponceStatus) +{ + uint32_t i = 0; + uint8_t locData = 0; + + /* Reset responce buffer ---------------------------------------------------*/ + for(i = 0; i < LC_MAX; i++) + { + SC_ResponceStatus->Data[i] = 0; + } + + SC_ResponceStatus->SW1 = 0; + SC_ResponceStatus->SW2 = 0; + + /* Enable the DMA Receive (Set DMAR bit only) to enable interrupt generation + in case of a framing error FE */ + USART_DMACmd(SC_USART, USART_DMAReq_Rx, ENABLE); + + /* Send header -------------------------------------------------------------*/ + SCData = SC_ADPU->Header.CLA; + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } + + SCData = SC_ADPU->Header.INS; + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } + + SCData = SC_ADPU->Header.P1; + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } + + SCData = SC_ADPU->Header.P2; + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } + + /* Send body length to/from SC ---------------------------------------------*/ + if(SC_ADPU->Body.LC) + { + SCData = SC_ADPU->Body.LC; + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } + } + else if(SC_ADPU->Body.LE) + { + SCData = SC_ADPU->Body.LE; + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } + } + /* Flush the SC_USART DR */ + (void)USART_ReceiveData(SC_USART); + + /* -------------------------------------------------------- + Wait Procedure byte from card: + 1 - ACK + 2 - NULL + 3 - SW1; SW2 + -------------------------------------------------------- */ + + if((USART_ByteReceive(&locData, SC_RECEIVE_TIMEOUT)) == SUCCESS) + { + if(((locData & (uint8_t)0xF0) == 0x60) || ((locData & (uint8_t)0xF0) == 0x90)) + { + /* SW1 received */ + SC_ResponceStatus->SW1 = locData; + + if((USART_ByteReceive(&locData, SC_RECEIVE_TIMEOUT)) == SUCCESS) + { + /* SW2 received */ + SC_ResponceStatus->SW2 = locData; + } + } + else if (((locData & (uint8_t)0xFE) == (((uint8_t)~(SC_ADPU->Header.INS)) & \ + (uint8_t)0xFE))||((locData & (uint8_t)0xFE) == (SC_ADPU->Header.INS & (uint8_t)0xFE))) + { + SC_ResponceStatus->Data[0] = locData;/* ACK received */ + } + } + + /* If no status bytes received ---------------------------------------------*/ + if(SC_ResponceStatus->SW1 == 0x00) + { + /* Send body data to SC--------------------------------------------------*/ + if (SC_ADPU->Body.LC) + { + for(i = 0; i < SC_ADPU->Body.LC; i++) + { + SCData = SC_ADPU->Body.Data[i]; + + USART_SendData(SC_USART, SCData); + while(USART_GetFlagStatus(SC_USART, USART_FLAG_TC) == RESET) + { + } + } + /* Flush the SC_USART DR */ + (void)USART_ReceiveData(SC_USART); + /* Disable the DMA Receive (Reset DMAR bit only) */ + USART_DMACmd(SC_USART, USART_DMAReq_Rx, DISABLE); + } + + /* Or receive body data from SC ------------------------------------------*/ + else if (SC_ADPU->Body.LE) + { + for(i = 0; i < SC_ADPU->Body.LE; i++) + { + if(USART_ByteReceive(&locData, SC_RECEIVE_TIMEOUT) == SUCCESS) + { + SC_ResponceStatus->Data[i] = locData; + } + } + } + /* Wait SW1 --------------------------------------------------------------*/ + i = 0; + while(i < 10) + { + if(USART_ByteReceive(&locData, SC_RECEIVE_TIMEOUT) == SUCCESS) + { + SC_ResponceStatus->SW1 = locData; + i = 11; + } + else + { + i++; + } + } + /* Wait SW2 ------------------------------------------------------------*/ + i = 0; + while(i < 10) + { + if(USART_ByteReceive(&locData, SC_RECEIVE_TIMEOUT) == SUCCESS) + { + SC_ResponceStatus->SW2 = locData; + i = 11; + } + else + { + i++; + } + } + } +} + +/** + * @brief Requests the reset answer from card. + * @param SCState: pointer to an SC_State enumeration that will contain the Smartcard state. + * @param card: pointer to a buffer which will contain the card ATR. + * @param length: maximum ATR length + * @retval None + */ +static void SC_AnswerReq(SC_State *SCState, uint8_t *card, uint8_t length) +{ + uint8_t Data = 0; + uint32_t i = 0; + + switch(*SCState) + { + case SC_RESET_LOW: + /* Check responce with reset low ---------------------------------------*/ + for (i = 0; i < length; i++) + { + if((USART_ByteReceive(&Data, SC_RECEIVE_TIMEOUT)) == SUCCESS) + { + card[i] = Data; + } + } + if(card[0]) + { + (*SCState) = SC_ACTIVE; + SC_Reset(Bit_SET); + } + else + { + (*SCState) = SC_RESET_HIGH; + } + break; + + case SC_RESET_HIGH: + /* Check responce with reset high --------------------------------------*/ + SC_Reset(Bit_SET); /* Reset High */ + + while(length--) + { + if((USART_ByteReceive(&Data, SC_RECEIVE_TIMEOUT)) == SUCCESS) + { + *card++ = Data; /* Receive data for timeout = SC_RECEIVE_TIMEOUT */ + } + } + if(card[0]) + { + (*SCState) = SC_ACTIVE; + } + else + { + (*SCState) = SC_POWER_OFF; + } + break; + + case SC_ACTIVE: + break; + + case SC_POWER_OFF: + /* Close Connection if no answer received ------------------------------*/ + SC_Reset(Bit_SET); /* Reset high - a bit is used as level shifter from 3.3 to 5 V */ + SC_PowerCmd(DISABLE); + break; + + default: + (*SCState) = SC_RESET_LOW; + } +} + +/** + * @brief Decodes the Answer to reset received from card. + * @param card: pointer to the buffer containing the card ATR. + * @retval None + */ +static uint8_t SC_decode_Answer2reset(uint8_t *card) +{ + uint32_t i = 0, flag = 0, buf = 0, protocol = 0; + + SC_A2R.TS = card[0]; /* Initial character */ + SC_A2R.T0 = card[1]; /* Format character */ + + SC_A2R.Hlength = SC_A2R.T0 & (uint8_t)0x0F; + + if ((SC_A2R.T0 & (uint8_t)0x80) == 0x80) + { + flag = 1; + } + + for (i = 0; i < 4; i++) + { + SC_A2R.Tlength = SC_A2R.Tlength + (((SC_A2R.T0 & (uint8_t)0xF0) >> (4 + i)) & (uint8_t)0x1); + } + + for (i = 0; i < SC_A2R.Tlength; i++) + { + SC_A2R.T[i] = card[i + 2]; + } + + protocol = SC_A2R.T[SC_A2R.Tlength - 1] & (uint8_t)0x0F; + + while (flag) + { + if ((SC_A2R.T[SC_A2R.Tlength - 1] & (uint8_t)0x80) == 0x80) + { + flag = 1; + } + else + { + flag = 0; + } + + buf = SC_A2R.Tlength; + SC_A2R.Tlength = 0; + + for (i = 0; i < 4; i++) + { + SC_A2R.Tlength = SC_A2R.Tlength + (((SC_A2R.T[buf - 1] & (uint8_t)0xF0) >> (4 + i)) & (uint8_t)0x1); + } + + for (i = 0;i < SC_A2R.Tlength; i++) + { + SC_A2R.T[buf + i] = card[i + 2 + buf]; + } + SC_A2R.Tlength += (uint8_t)buf; + } + + for (i = 0; i < SC_A2R.Hlength; i++) + { + SC_A2R.H[i] = card[i + 2 + SC_A2R.Tlength]; + } + + return (uint8_t)protocol; +} + +/** + * @brief Initializes all peripheral used for Smartcard interface. + * @param None + * @retval None + */ +static void SC_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + USART_ClockInitTypeDef USART_ClockInitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* Enable GPIO clocks */ + RCC_AHB1PeriphClockCmd(SC_USART_TX_GPIO_CLK | SC_USART_CK_GPIO_CLK, ENABLE); + + /* Enable SC_USART clock */ + SC_USART_APBPERIPHCLOCK(SC_USART_CLK, ENABLE); + + /* Connect PXx to SC_USART_TX */ + GPIO_PinAFConfig(SC_USART_TX_GPIO_PORT, SC_USART_TX_SOURCE, SC_USART_TX_AF); + + /* Connect PXx to SC_USART_CK */ + GPIO_PinAFConfig(SC_USART_CK_GPIO_PORT, SC_USART_CK_SOURCE, SC_USART_CK_AF); + + /* Configure USART Tx and Rx as alternate function push-pull */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_InitStructure.GPIO_Pin = SC_USART_CK_PIN; + GPIO_Init(SC_USART_CK_GPIO_PORT, &GPIO_InitStructure); + + /* Configure USART Tx pin as alternate function open-drain */ + GPIO_InitStructure.GPIO_Pin = SC_USART_TX_PIN; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_Init(SC_USART_TX_GPIO_PORT, &GPIO_InitStructure); + + /* Enable SC_USART IRQ */ + NVIC_InitStructure.NVIC_IRQChannel = SC_USART_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + +/* SC_USART configuration ----------------------------------------------------*/ + /* SC_USART configured as follow: + - Word Length = 9 Bits + - 1.5 Stop Bit + - Even parity + - BaudRate = 8064 baud + - Hardware flow control disabled (RTS and CTS signals) + - Tx and Rx enabled + - USART Clock enabled + */ + + /* USART Clock set to 6 MHz (PCLK2 (60 MHz) / 10) */ + USART_SetPrescaler(SC_USART, 0x05); + + /* USART Guard Time set to 16 Bit */ + USART_SetGuardTime(SC_USART, 16); + + USART_ClockInitStructure.USART_Clock = USART_Clock_Enable; + USART_ClockInitStructure.USART_CPOL = USART_CPOL_Low; + USART_ClockInitStructure.USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStructure.USART_LastBit = USART_LastBit_Enable; + USART_ClockInit(SC_USART, &USART_ClockInitStructure); + + + USART_InitStructure.USART_BaudRate = 16129; + USART_InitStructure.USART_WordLength = USART_WordLength_9b; + USART_InitStructure.USART_StopBits = USART_StopBits_1_5; + USART_InitStructure.USART_Parity = USART_Parity_Even; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_Init(SC_USART, &USART_InitStructure); + + /* Enable the SC_USART Parity Error Interrupt */ + USART_ITConfig(SC_USART, USART_IT_PE, ENABLE); + + /* Enable the SC_USART Framing Error Interrupt */ + USART_ITConfig(SC_USART, USART_IT_ERR, ENABLE); + + /* Enable SC_USART */ + USART_Cmd(SC_USART, ENABLE); + + /* Enable the NACK Transmission */ + USART_SmartCardNACKCmd(SC_USART, ENABLE); + + /* Enable the Smartcard Interface */ + USART_SmartCardCmd(SC_USART, ENABLE); + + /* Set RSTIN HIGH */ + SC_Reset(Bit_SET); +} + +/** + * @brief Deinitializes all ressources used by the Smartcard interface. + * @param None + * @retval None + */ +static void SC_DeInit(void) +{ + /* Disable CMDVCC */ + SC_PowerCmd(DISABLE); + + /* Deinitializes the SC_USART */ + USART_DeInit(SC_USART); + + /* Disable SC_USART clock */ + SC_USART_APBPERIPHCLOCK(SC_USART_CLK, DISABLE); +} + +/** + * @brief Configures the card power voltage. + * @param SC_Voltage: specifies the card power voltage. + * This parameter can be one of the following values: + * @arg SC_VOLTAGE_5V: 5V cards. + * @arg SC_VOLTAGE_3V: 3V cards. + * @retval None + */ +static void SC_VoltageConfig(uint32_t SC_Voltage) +{ + if(SC_Voltage == SC_VOLTAGE_5V) + { + /* Select Smartcard 5V */ + GPIO_SetBits(SC_3_5V_GPIO_PORT, SC_3_5V_PIN); + } + else + { + /* Select Smartcard 3V */ + GPIO_ResetBits(SC_3_5V_GPIO_PORT, SC_3_5V_PIN); + } +} + +/** + * @brief Configures GPIO hardware resources used for Samrtcard. + * @param None + * @retval None + */ +void SC_IOConfig(void) +{ + EXTI_InitTypeDef EXTI_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + /* Enable GPIO clock */ + RCC_AHB1PeriphClockCmd(SC_OFF_GPIO_CLK | SC_CMDVCC_GPIO_CLK | + SC_3_5V_GPIO_CLK | SC_RESET_GPIO_CLK, ENABLE); + + /* Enable SYSCFG clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + /* Configure Smartcard CMDVCC pin */ + GPIO_InitStructure.GPIO_Pin = SC_CMDVCC_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_Init(SC_CMDVCC_GPIO_PORT, &GPIO_InitStructure); + + /* Configure Smartcard Reset pin */ + GPIO_InitStructure.GPIO_Pin = SC_RESET_PIN; + GPIO_Init(SC_RESET_GPIO_PORT, &GPIO_InitStructure); + + /* Configure Smartcard 3/5V pin */ + GPIO_InitStructure.GPIO_Pin = SC_3_5V_PIN; + GPIO_Init(SC_3_5V_GPIO_PORT, &GPIO_InitStructure); + + /* Select 5V */ + SC_VoltageConfig(SC_VOLTAGE_5V); + + /* Disable CMDVCC */ + SC_PowerCmd(DISABLE); + + /* Set RSTIN HIGH */ + SC_Reset(Bit_SET); + + /* Configure Smartcard OFF pin */ + GPIO_InitStructure.GPIO_Pin = SC_OFF_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(SC_OFF_GPIO_PORT, &GPIO_InitStructure); + + /* Configure EXTI line connected to Smartcard OFF Pin */ + SYSCFG_EXTILineConfig(SC_OFF_EXTI_PORT_SOURCE, SC_OFF_EXTI_PIN_SOURCE); + + EXTI_ClearITPendingBit(SC_OFF_EXTI_LINE); + + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_Line = SC_OFF_EXTI_LINE; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Clear the SC_OFF_EXTI_IRQn Pending Bit */ + NVIC_ClearPendingIRQ(SC_OFF_EXTI_IRQn); + NVIC_InitStructure.NVIC_IRQChannel = SC_OFF_EXTI_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +/** + * @brief Detects whether the Smartcard is present or not. + * @param None. + * @retval 0 - Smartcard inserted + * 1 - Smartcard not inserted + */ +static uint8_t SC_Detect(void) +{ + return GPIO_ReadInputDataBit(SC_OFF_GPIO_PORT, SC_OFF_PIN); +} + +/** + * @brief Receives a new data while the time out not elapsed. + * @param None + * @retval An ErrorStatus enumuration value: + * - SUCCESS: New data has been received + * - ERROR: time out was elapsed and no further data is received + */ +static ErrorStatus USART_ByteReceive(uint8_t *Data, uint32_t TimeOut) +{ + uint32_t Counter = 0; + + while((USART_GetFlagStatus(SC_USART, USART_FLAG_RXNE) == RESET) && (Counter != TimeOut)) + { + Counter++; + } + + if(Counter != TimeOut) + { + *Data = (uint8_t)USART_ReceiveData(SC_USART); + return SUCCESS; + } + else + { + return ERROR; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/smartcard.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/smartcard.h new file mode 100644 index 000000000..936e1ef7d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/smartcard.h @@ -0,0 +1,156 @@ +/** + ****************************************************************************** + * @file USART/Smartcard/smartcard.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains all the functions prototypes for the Smartcard + * firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SMARTCARD_H +#define __SMARTCARD_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "platform_config.h" + +/* Exported constants --------------------------------------------------------*/ +#define T0_PROTOCOL 0x00 /* T0 protocol */ +#define DIRECT 0x3B /* Direct bit convention */ +#define INDIRECT 0x3F /* Indirect bit convention */ +#define SETUP_LENGTH 20 +#define HIST_LENGTH 20 +#define LC_MAX 20 +#define SC_RECEIVE_TIMEOUT 0x8000 /* Direction to reader */ + +/* SC Tree Structure ----------------------------------------------------------- + MasterFile + ________|___________ + | | | + System UserData Note +------------------------------------------------------------------------------*/ + +/* SC ADPU Command: Operation Code -------------------------------------------*/ +#define SC_CLA_GSM11 0xA0 + +/*------------------------ Data Area Management Commands ---------------------*/ +#define SC_SELECT_FILE 0xA4 +#define SC_GET_RESPONCE 0xC0 +#define SC_STATUS 0xF2 +#define SC_UPDATE_BINARY 0xD6 +#define SC_READ_BINARY 0xB0 +#define SC_WRITE_BINARY 0xD0 +#define SC_UPDATE_RECORD 0xDC +#define SC_READ_RECORD 0xB2 + +/*-------------------------- Administrative Commands -------------------------*/ +#define SC_CREATE_FILE 0xE0 + +/*-------------------------- Safety Management Commands ----------------------*/ +#define SC_VERIFY 0x20 +#define SC_CHANGE 0x24 +#define SC_DISABLE 0x26 +#define SC_ENABLE 0x28 +#define SC_UNBLOCK 0x2C +#define SC_EXTERNAL_AUTH 0x82 +#define SC_GET_CHALLENGE 0x84 + +/*-------------------------- Answer to reset Commands ------------------------*/ +#define SC_GET_A2R 0x00 + +/* SC STATUS: Status Code ----------------------------------------------------*/ +#define SC_EF_SELECTED 0x9F +#define SC_DF_SELECTED 0x9F +#define SC_OP_TERMINATED 0x9000 + +/* Smartcard Voltage */ +#define SC_VOLTAGE_5V 0 +#define SC_VOLTAGE_3V 1 + +/* Exported types ------------------------------------------------------------*/ +typedef enum +{ + SC_POWER_ON = 0x00, + SC_RESET_LOW = 0x01, + SC_RESET_HIGH = 0x02, + SC_ACTIVE = 0x03, + SC_ACTIVE_ON_T0 = 0x04, + SC_POWER_OFF = 0x05 +} SC_State; + +/* ATR structure - Answer To Reset -------------------------------------------*/ +typedef struct +{ + uint8_t TS; /* Bit Convention */ + uint8_t T0; /* High nibble = Number of setup byte; low nibble = Number of historical byte */ + uint8_t T[SETUP_LENGTH]; /* Setup array */ + uint8_t H[HIST_LENGTH]; /* Historical array */ + uint8_t Tlength; /* Setup array dimension */ + uint8_t Hlength; /* Historical array dimension */ +} SC_ATR; + +/* ADPU-Header command structure ---------------------------------------------*/ +typedef struct +{ + uint8_t CLA; /* Command class */ + uint8_t INS; /* Operation code */ + uint8_t P1; /* Selection Mode */ + uint8_t P2; /* Selection Option */ +} SC_Header; + +/* ADPU-Body command structure -----------------------------------------------*/ +typedef struct +{ + uint8_t LC; /* Data field length */ + uint8_t Data[LC_MAX]; /* Command parameters */ + uint8_t LE; /* Expected length of data to be returned */ +} SC_Body; + +/* ADPU Command structure ----------------------------------------------------*/ +typedef struct +{ + SC_Header Header; + SC_Body Body; +} SC_ADPU_Commands; + +/* SC response structure -----------------------------------------------------*/ +typedef struct +{ + uint8_t Data[LC_MAX]; /* Data returned from the card */ + uint8_t SW1; /* Command Processing status */ + uint8_t SW2; /* Command Processing qualification */ +} SC_ADPU_Responce; + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* APPLICATION LAYER ---------------------------------------------------------*/ +void SC_Handler(SC_State *SCState, SC_ADPU_Commands *SC_ADPU, SC_ADPU_Responce *SC_Response); +void SC_PowerCmd(FunctionalState NewState); +void SC_Reset(BitAction ResetState); +void SC_IOConfig(void); +void SC_ParityErrorHandler(void); +void SC_PTSConfig(void); + +#endif /* __SMARTCARD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/stm32f2xx_conf.h new file mode 100644 index 000000000..2197a4327 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file USART/Smartcard/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/stm32f2xx_it.c new file mode 100644 index 000000000..d7b589fb9 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/stm32f2xx_it.c @@ -0,0 +1,260 @@ +/** + ****************************************************************************** + * @file USART/Smartcard/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "smartcard.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup USART_SmartCard + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern __IO uint32_t CardInserted; +extern __IO uint32_t TimingDelay; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + /* Decrement the TimingDelay variable */ + if (TimingDelay != 0x00) + { + TimingDelay--; + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles SC_USART global interrupt request. + * @param None + * @retval None + */ +void SC_USART_IRQHandler(void) +{ + /* If a Frame error is signaled by the card */ + if(USART_GetITStatus(SC_USART, USART_IT_FE) != RESET) + { + USART_ReceiveData(SC_USART); + + /* Resend the byte that failed to be received (by the Smartcard) correctly */ + SC_ParityErrorHandler(); + } + + /* If the SC_USART detects a parity error */ + if(USART_GetITStatus(SC_USART, USART_IT_PE) != RESET) + { + /* Enable SC_USART RXNE Interrupt (until receiving the corrupted byte) */ + USART_ITConfig(SC_USART, USART_IT_RXNE, ENABLE); + /* Flush the SC_USART DR register */ + USART_ReceiveData(SC_USART); + } + + if(USART_GetITStatus(SC_USART, USART_IT_RXNE) != RESET) + { + /* Disable SC_USART RXNE Interrupt */ + USART_ITConfig(SC_USART, USART_IT_RXNE, DISABLE); + USART_ReceiveData(SC_USART); + } + + /* If a Overrun error is signaled by the card */ + if(USART_GetITStatus(SC_USART, USART_IT_ORE) != RESET) + { + USART_ReceiveData(SC_USART); + } + /* If a Noise error is signaled by the card */ + if(USART_GetITStatus(SC_USART, USART_IT_NE) != RESET) + { + USART_ReceiveData(SC_USART); + } +} + +/** + * @brief This function handles the smartcard detection interrupt request. + * @param None + * @retval None + */ +void SC_OFF_EXTI_IRQHandler(void) +{ + if(EXTI_GetITStatus(SC_OFF_EXTI_LINE) != RESET) + { + /* Clear EXTI Line Pending Bit */ + EXTI_ClearITPendingBit(SC_OFF_EXTI_LINE); + + /* Toggle LED1..4 */ + STM_EVAL_LEDToggle(LED1); + STM_EVAL_LEDToggle(LED2); + STM_EVAL_LEDToggle(LED3); + STM_EVAL_LEDToggle(LED4); + + /* Smartcard detected */ + CardInserted = 1; + + /* Enable CMDVCC */ + SC_PowerCmd(ENABLE); + + /* Reset the card */ + SC_Reset(Bit_RESET); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/stm32f2xx_it.h new file mode 100644 index 000000000..f405f4568 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/stm32f2xx_it.h @@ -0,0 +1,54 @@ +/** + ****************************************************************************** + * @file USART/Smartcard/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void SC_USART_IRQHandler(void); +void SC_OFF_EXTI_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/SmartCard/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/main.c new file mode 100644 index 000000000..e4051b43a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/main.c @@ -0,0 +1,145 @@ +/** + ****************************************************************************** + * @file USART/USART_Printf/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup USART_Printf + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +USART_InitTypeDef USART_InitStructure; + +/* Private function prototypes -----------------------------------------------*/ + +#ifdef __GNUC__ + /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* USARTx configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + STM_EVAL_COMInit(COM1, &USART_InitStructure); + + /* Output a message on Hyperterminal using printf function */ + printf("\n\rUSART Printf Example: retarget the C library printf function to the USART\n\r"); + + while (1) + { + } +} + +/** + * @brief Retargets the C library printf function to the USART. + * @param None + * @retval None + */ +PUTCHAR_PROTOTYPE +{ + /* Place your implementation of fputc here */ + /* e.g. write a character to the USART */ + USART_SendData(EVAL_COM1, (uint8_t) ch); + + /* Loop until the end of transmission */ + while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET) + {} + + return ch; +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/readme.txt new file mode 100644 index 000000000..7cf79a9c0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/readme.txt @@ -0,0 +1,88 @@ +/** + @page USART_Printf USART_Printf + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file USART/USART_Printf/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the USART Printf Example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to retarget the C library printf function to the USART. +This implementation output the printf message on the Hyperterminal using USART3. + +The USARTx is configured as follow: + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + + +@par Directory contents + + - USART/USART_Printf/system_stm32f2xx.c STM32F2xx system clock configuration file + - USART/USART_Printf/stm32f2xx_conf.h Library Configuration file + - USART/USART_Printf/stm32f2xx_it.h Interrupt handlers header file + - USART/USART_Printf/stm32f2xx_it.c Interrupt handlers + - USART/USART_Printf/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Connect a null-modem female/female RS232 cable between the DB9 connector + CN16 (USART3) and PC serial port if you want to display data on the HyperTerminal. + @note Make sure that jumper JP22 is in position 1-2 + + - Hyperterminal configuration: + - Word Length = 8 Bits + - One Stop Bit + - No parity + - BaudRate = 115200 baud + - flow control: None + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/stm32f2xx_conf.h new file mode 100644 index 000000000..9097b311b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file USART/USART_Printf/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/stm32f2xx_it.c new file mode 100644 index 000000000..fd3f900da --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/stm32f2xx_it.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file USART/USART_Printf/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup USART_Printf + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/stm32f2xx_it.h new file mode 100644 index 000000000..820b45141 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file USART/USART_Printf/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_Printf/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/main.c new file mode 100644 index 000000000..0e762a7cf --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/main.c @@ -0,0 +1,586 @@ +/** + ****************************************************************************** + * @file USART/USART_TwoBoards/DataExchangeDMA/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples +* @{ +*/ + +/** @addtogroup USART_DataExchangeDMA +* @{ +*/ + +/* Private typedef -----------------------------------------------------------*/ +DMA_InitTypeDef DMA_InitStructure; + +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint8_t TxBuffer[] = "USART DMA Example: Communication between two USART using DMA"; +uint8_t CmdBuffer [2] = {0x00, 0x00}; /* {Command, Number of byte to receive or to transmit} */ +__IO uint32_t TimeOut = 0x0; + +#ifdef USART_TRANSMITTER_MODE + JOYState_TypeDef PressedButton = JOY_NONE; + JOYState_TypeDef ReleasedButton = JOY_NONE; +#endif /* USART_TRANSMITTER_MODE */ + +#ifdef USART_RECEIVER_MODE +uint8_t RxBuffer [RXBUFFERSIZE]; +#endif /* USART_RECEIVER_MODE */ + + +/* Private function prototypes -----------------------------------------------*/ +static void TimeOut_UserCallback(void); +static void USART_Config(void); +static void SysTickConfig(void); +static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength); + +#ifdef USART_RECEIVER_MODE +static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength); +#endif /* USART_RECEIVER_MODE */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* USART configuration -----------------------------------------------------*/ + USART_Config(); + + /* SysTick configuration ---------------------------------------------------*/ + SysTickConfig(); + + /* LEDs configuration ------------------------------------------------------*/ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* IO Expanderconfiguration ------------------------------------------------*/ +#ifdef USART_TRANSMITTER_MODE + TimeOut = USER_TIMEOUT; + while ((IOE_Config() != IOE_OK) && (TimeOut != 0)) + { + } + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } +#endif /* USART_TRANSMITTER_MODE */ + + while (1) + { +/******************************************************************************/ +/* USART in Transmitter Mode */ +/******************************************************************************/ +#ifdef USART_TRANSMITTER_MODE + + /* Clear Buffers */ + Fill_Buffer(CmdBuffer, 2); + + DMA_DeInit(USARTx_TX_DMA_STREAM); + DMA_InitStructure.DMA_Channel = USARTx_TX_DMA_CHANNEL; + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + + /****************** USART will Transmit Specific Command ******************/ + /* Prepare the DMA to transfer the transaction command (2bytes) from the + memory to the USART */ + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)CmdBuffer; + DMA_InitStructure.DMA_BufferSize = (uint16_t)2; + DMA_Init(USARTx_TX_DMA_STREAM, &DMA_InitStructure); + + /* Prepare Command to be transmitted */ + /* Waiting joystick pressed */ + PressedButton = JOY_NONE; + while (PressedButton == JOY_NONE) + { + PressedButton = IOE_JoyStickGetState(); + } + + /* Waiting joystick released */ + ReleasedButton = IOE_JoyStickGetState(); + while ((PressedButton == ReleasedButton) && (ReleasedButton != JOY_NONE)) + { + ReleasedButton = IOE_JoyStickGetState(); + } + + + if(PressedButton != JOY_NONE) + { + /* For each joystick state correspond a command to be sent through USART */ + switch (PressedButton) + { + /* JOY_RIGHT button pressed */ + case JOY_RIGHT: + CmdBuffer[0] = CMD_RIGHT; + CmdBuffer[1] = CMD_RIGHT_SIZE; + break; + /* JOY_LEFT button pressed */ + case JOY_LEFT: + CmdBuffer[0] = CMD_LEFT; + CmdBuffer[1] = CMD_LEFT_SIZE; + break; + /* JOY_UP button pressed */ + case JOY_UP: + CmdBuffer[0] = CMD_UP; + CmdBuffer[1] = CMD_UP_SIZE; + break; + /* JOY_DOWN button pressed */ + case JOY_DOWN: + CmdBuffer[0] = CMD_DOWN; + CmdBuffer[1] = CMD_DOWN_SIZE; + break; + /* JOY_SEL button pressed */ + case JOY_SEL: + CmdBuffer[0] = CMD_SEL; + CmdBuffer[1] = CMD_SEL_SIZE; + break; + default: + break; + } + + /* Enable the USART DMA requests */ + USART_DMACmd(USARTx, USART_DMAReq_Tx, ENABLE); + + /* Clear the TC bit in the SR register by writing 0 to it */ + USART_ClearFlag(USARTx, USART_FLAG_TC); + + /* Enable the DMA TX Stream, USART will start sending the command code (2bytes) */ + DMA_Cmd(USARTx_TX_DMA_STREAM, ENABLE); + + /* Wait the USART DMA Tx transfer complete or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetFlagStatus(USARTx_TX_DMA_STREAM, USARTx_TX_DMA_FLAG_TCIF) == RESET)&&(TimeOut != 0)) + { + } + + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* The software must wait until TC=1. The TC flag remains cleared during all data + transfers and it is set by hardware at the last frame’s end of transmission*/ + TimeOut = USER_TIMEOUT; + while ((USART_GetFlagStatus(USARTx, USART_FLAG_TC) == RESET)&&(TimeOut != 0)) + { + } + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Clear DMA Streams flags */ + DMA_ClearFlag(USARTx_TX_DMA_STREAM, USARTx_TX_DMA_FLAG_HTIF | USARTx_TX_DMA_FLAG_TCIF); + + /* Disable the DMA Streams */ + DMA_Cmd(USARTx_TX_DMA_STREAM, DISABLE); + + /* Disable the USART Tx DMA request */ + USART_DMACmd(USARTx, USART_DMAReq_Tx, DISABLE); + + /******************* USART will Transmit Data Buffer ********************/ + /* Prepare the DMA to transfer the transaction data (length defined by + CmdBuffer[1] variable) from the memory to the USART */ + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)TxBuffer; + DMA_InitStructure.DMA_BufferSize = (uint16_t)CmdBuffer[1]; + DMA_Init(USARTx_TX_DMA_STREAM, &DMA_InitStructure); + + /* Enable the USART Tx DMA request */ + USART_DMACmd(USARTx, USART_DMAReq_Tx, ENABLE); + + /* Clear the TC bit in the SR register by writing 0 to it */ + USART_ClearFlag(USARTx, USART_FLAG_TC); + + /* Enable DMA USART Tx Stream */ + DMA_Cmd(USARTx_TX_DMA_STREAM, ENABLE); + + /* Wait the USART DMA Tx transfer complete or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetFlagStatus(USARTx_TX_DMA_STREAM, USARTx_TX_DMA_FLAG_TCIF) == RESET)&&(TimeOut != 0)) + { + } + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* The software must wait until TC=1, The TC flag remains cleared during all data + transfers and it is set by hardware at the last frame’s end of transmission */ + TimeOut = USER_TIMEOUT; + while ((USART_GetFlagStatus(USARTx, USART_FLAG_TC) == RESET)&&(TimeOut != 0)) + { + } + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Clear all DMA Streams flags */ + DMA_ClearFlag(USARTx_TX_DMA_STREAM, USARTx_TX_DMA_FLAG_HTIF | USARTx_TX_DMA_FLAG_TCIF); + + /* Disable the DMA Stream */ + DMA_Cmd(USARTx_TX_DMA_STREAM, DISABLE); + + /* Disable the USART Tx DMA request */ + USART_DMACmd(USARTx, USART_DMAReq_Tx, DISABLE); + } + +#endif /* USART_TRANSMITTER_MODE */ + +/******************************************************************************/ +/* USART in Receiver Mode */ +/******************************************************************************/ +#ifdef USART_RECEIVER_MODE + /* Clear Buffers */ + Fill_Buffer(RxBuffer, TXBUFFERSIZE); + Fill_Buffer(CmdBuffer, 2); + + DMA_DeInit(USARTx_RX_DMA_STREAM); + DMA_InitStructure.DMA_Channel = USARTx_RX_DMA_CHANNEL; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + /****************** USART will Receive Specific Command *******************/ + /* Configure the DMA to receive 2 bytes (transaction command), in case of USART receiver */ + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)CmdBuffer; + DMA_InitStructure.DMA_BufferSize = (uint16_t)2; + DMA_Init(USARTx_RX_DMA_STREAM, &DMA_InitStructure); + + /* Enable the USART Rx DMA request */ + USART_DMACmd(USARTx, USART_DMAReq_Rx, ENABLE); + /* Enable the DMA RX Stream */ + DMA_Cmd(USARTx_RX_DMA_STREAM, ENABLE); + + /* Wait the USART DMA Rx transfer complete (to receive the transaction command) */ + while (DMA_GetFlagStatus(USARTx_RX_DMA_STREAM, USARTx_RX_DMA_FLAG_TCIF) == RESET) + { + } + + /* Clear all DMA Streams flags */ + DMA_ClearFlag(USARTx_RX_DMA_STREAM, USARTx_RX_DMA_FLAG_HTIF | USARTx_RX_DMA_FLAG_TCIF); + + /* Disable the DMA Rx Stream */ + DMA_Cmd(USARTx_RX_DMA_STREAM, DISABLE); + + /* Disable the USART Rx DMA requests */ + USART_DMACmd(USARTx, USART_DMAReq_Rx, DISABLE); + + /************* USART will receive the the transaction data ****************/ + /* Transaction data (length defined by CmdBuffer[1] variable) */ + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)RxBuffer; + DMA_InitStructure.DMA_BufferSize = (uint16_t)CmdBuffer[1]; + DMA_Init(USARTx_RX_DMA_STREAM, &DMA_InitStructure); + + /* Enable the USART Rx DMA requests */ + USART_DMACmd(USARTx, USART_DMAReq_Rx , ENABLE); + + /* Enable the DMA Stream */ + DMA_Cmd(USARTx_RX_DMA_STREAM, ENABLE); + + /* Wait the USART DMA Rx transfer complete or time out */ + TimeOut = USER_TIMEOUT; + while ((DMA_GetFlagStatus(USARTx_RX_DMA_STREAM, USARTx_RX_DMA_FLAG_TCIF) == RESET)&&(TimeOut != 0)) + { + } + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Clear all DMA Streams flags */ + DMA_ClearFlag(USARTx_RX_DMA_STREAM, USARTx_RX_DMA_FLAG_HTIF | USARTx_RX_DMA_FLAG_TCIF); + + /* Disable the DMA Stream */ + DMA_Cmd(USARTx_RX_DMA_STREAM, DISABLE); + + /* Disable the USART Rx DMA requests */ + USART_DMACmd(USARTx, USART_DMAReq_Rx, DISABLE); + + switch (CmdBuffer[1]) + { + /* CMD_RIGHT command received */ + case CMD_RIGHT_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_RIGHT_SIZE) != FAILED) + { + /* Turn ON LED2 and LED3 */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + /* Turn OFF LED4 */ + STM_EVAL_LEDOff(LED4); + } + break; + /* CMD_LEFT command received */ + case CMD_LEFT_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_LEFT_SIZE) != FAILED) + { + /* Turn ON LED4 */ + STM_EVAL_LEDOn(LED4); + /* Turn OFF LED2 and LED3 */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + } + break; + /* CMD_UP command received */ + case CMD_UP_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_UP_SIZE) != FAILED) + { + /* Turn ON LED2 */ + STM_EVAL_LEDOn(LED2); + /* Turn OFF LED3 and LED4 */ + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + } + break; + /* CMD_DOWN command received */ + case CMD_DOWN_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_DOWN_SIZE) != FAILED) + { + /* Turn ON LED3 */ + STM_EVAL_LEDOn(LED3); + /* Turn OFF LED2 and LED4 */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED4); + } + break; + /* CMD_SEL command received */ + case CMD_SEL_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_SEL_SIZE) != FAILED) + { + /* Turn ON all LED2, LED3 and LED4 */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + } + break; + default: + break; + } +#endif /* USART_RECEIVER_MODE */ + } +} + +/** + * @brief Basic management of the timeout situation. + * @param None. + * @retval None. + */ +static void TimeOut_UserCallback(void) +{ + /* User can add his own implementation to manage TimeOut Communication failure */ + /* Block communication and all processes */ + while (1) + { + } +} + +/** + * @brief Configures the USART Peripheral. + * @param None + * @retval None + */ +static void USART_Config(void) +{ + USART_InitTypeDef USART_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Peripheral Clock Enable -------------------------------------------------*/ + /* Enable GPIO clock */ + RCC_AHB1PeriphClockCmd(USARTx_TX_GPIO_CLK | USARTx_RX_GPIO_CLK, ENABLE); + + /* Enable USART clock */ + USARTx_CLK_INIT(USARTx_CLK, ENABLE); + + /* Enable the DMA clock */ + RCC_AHB1PeriphClockCmd(USARTx_DMAx_CLK, ENABLE); + + /* USARTx GPIO configuration -----------------------------------------------*/ + /* Connect USART pins to AF7 */ + GPIO_PinAFConfig(USARTx_TX_GPIO_PORT, USARTx_TX_SOURCE, USARTx_TX_AF); + GPIO_PinAFConfig(USARTx_RX_GPIO_PORT, USARTx_RX_SOURCE, USARTx_RX_AF); + + /* Configure USART Tx and Rx as alternate function push-pull */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + + GPIO_InitStructure.GPIO_Pin = USARTx_TX_PIN; + GPIO_Init(USARTx_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = USARTx_RX_PIN; + GPIO_Init(USARTx_RX_GPIO_PORT, &GPIO_InitStructure); + + /* USARTx configuration ----------------------------------------------------*/ + /* Enable the USART OverSampling by 8 */ + USART_OverSampling8Cmd(USARTx, ENABLE); + + /* USARTx configured as follow: + - BaudRate = 3750000 baud + - Maximum BaudRate that can be achieved when using the Oversampling by 8 + is: (USART APB Clock / 8) + Example: + - (USART3 APB1 Clock / 8) = (30 MHz / 8) = 3750000 baud + - (USART1 APB2 Clock / 8) = (60 MHz / 8) = 7500000 baud + - Maximum BaudRate that can be achieved when using the Oversampling by 16 + is: (USART APB Clock / 16) + Example: (USART3 APB1 Clock / 16) = (30 MHz / 16) = 1875000 baud + Example: (USART1 APB2 Clock / 16) = (60 MHz / 16) = 3750000 baud + - Word Length = 8 Bits + - one Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitStructure.USART_BaudRate = 3750000; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + /* When using Parity the word length must be configured to 9 bits */ + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(USARTx, &USART_InitStructure); + + /* Configure DMA controller to manage USART TX and RX DMA request ----------*/ + DMA_InitStructure.DMA_PeripheralBaseAddr = USARTx_DR_ADDRESS; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + /* Here only the unchanged parameters of the DMA initialization structure are + configured. During the program operation, the DMA will be configured with + different parameters according to the operation phase */ + + /* Enable USART */ + USART_Cmd(USARTx, ENABLE); +} + +/** + * @brief Configures the SysTick Base time to 10 ms. + * @param None + * @retval None + */ +static void SysTickConfig(void) +{ + /* Set SysTick Timer for 10ms interrupts */ + if (SysTick_Config(SystemCoreClock / 100)) + { + /* Capture error */ + while (1); + } + /* Configure the SysTick handler priority */ + NVIC_SetPriority(SysTick_IRQn, 0x0); +} + +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer1 identical to pBuffer2 + * FAILED: pBuffer1 differs from pBuffer2 + */ +#ifdef USART_RECEIVER_MODE +static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} +#endif /* USART_RECEIVER_MODE */ + +/** + * @brief Fills buffer. + * @param pBuffer: pointer on the Buffer to fill + * @param BufferLength: size of the buffer to fill + * @retval None + */ +static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength) +{ + uint16_t index = 0; + + /* Put in global buffer same values */ + for (index = 0; index < BufferLength; index++ ) + { + pBuffer[index] = 0x00; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + {} +} +#endif + +/** +* @} +*/ + +/** +* @} +*/ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/main.h new file mode 100644 index 000000000..84715ef48 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/main.h @@ -0,0 +1,137 @@ +/** + ****************************************************************************** + * @file USART/USART_TwoBoards/DataExchangeDMA/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stm322xg_eval_ioe.h" + +/* Exported typedef ----------------------------------------------------------*/ +#define countof(a) (sizeof(a) / sizeof(*(a))) +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Exported define -----------------------------------------------------------*/ + +/* Uncomment the line below if you will use the USART peripheral as Transmitter */ +#define USART_TRANSMITTER_MODE +/* Uncomment the line below if you will use the USART peripheral as Receiver */ +/* #define USART_RECEIVER_MODE */ + +/* USER_TIMEOUT value for waiting loops. This timeout is just guarantee that the + application will not remain stuck if the USART communication is corrupted. + You may modify this timeout value depending on CPU frequency and application + conditions (interrupts routines, number of data to transfer, baudrate, CPU + frequency...). */ +#define USER_TIMEOUT ((uint32_t)0x64) /* Waiting 1s */ + +/* Definition for USARTx resources ********************************************/ +#define USARTx USART3 +#define USARTx_CLK RCC_APB1Periph_USART3 +#define USARTx_CLK_INIT RCC_APB1PeriphClockCmd +#define USARTx_IRQn USART3_IRQn +#define USARTx_IRQHandler USART3_IRQHandler + +#define USARTx_TX_PIN GPIO_Pin_10 +#define USARTx_TX_GPIO_PORT GPIOC +#define USARTx_TX_GPIO_CLK RCC_AHB1Periph_GPIOC +#define USARTx_TX_SOURCE GPIO_PinSource10 +#define USARTx_TX_AF GPIO_AF_USART3 + +#define USARTx_RX_PIN GPIO_Pin_11 +#define USARTx_RX_GPIO_PORT GPIOC +#define USARTx_RX_GPIO_CLK RCC_AHB1Periph_GPIOC +#define USARTx_RX_SOURCE GPIO_PinSource11 +#define USARTx_RX_AF GPIO_AF_USART3 + +/* Definition for DMAx resources **********************************************/ +#define USARTx_DR_ADDRESS ((uint32_t)USART3 + 0x04) + +#define USARTx_DMA DMA1 +#define USARTx_DMAx_CLK RCC_AHB1Periph_DMA1 + +#define USARTx_TX_DMA_CHANNEL DMA_Channel_4 +#define USARTx_TX_DMA_STREAM DMA1_Stream3 +#define USARTx_TX_DMA_FLAG_FEIF DMA_FLAG_FEIF3 +#define USARTx_TX_DMA_FLAG_DMEIF DMA_FLAG_DMEIF3 +#define USARTx_TX_DMA_FLAG_TEIF DMA_FLAG_TEIF3 +#define USARTx_TX_DMA_FLAG_HTIF DMA_FLAG_HTIF3 +#define USARTx_TX_DMA_FLAG_TCIF DMA_FLAG_TCIF3 + +#define USARTx_RX_DMA_CHANNEL DMA_Channel_4 +#define USARTx_RX_DMA_STREAM DMA1_Stream1 +#define USARTx_RX_DMA_FLAG_FEIF DMA_FLAG_FEIF1 +#define USARTx_RX_DMA_FLAG_DMEIF DMA_FLAG_DMEIF1 +#define USARTx_RX_DMA_FLAG_TEIF DMA_FLAG_TEIF1 +#define USARTx_RX_DMA_FLAG_HTIF DMA_FLAG_HTIF1 +#define USARTx_RX_DMA_FLAG_TCIF DMA_FLAG_TCIF1 + +#define USARTx_DMA_TX_IRQn DMA1_Stream3_IRQn +#define USARTx_DMA_RX_IRQn DMA1_Stream1_IRQn +#define USARTx_DMA_TX_IRQHandler DMA1_Stream3_IRQHandler +#define USARTx_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler + +/* Misc definition ************************************************************/ +/* Transmit buffer size */ +#define TXBUFFERSIZE (countof(TxBuffer) - 1) +/* Receive buffer size */ +#define RXBUFFERSIZE TXBUFFERSIZE + +/* Commands list */ +#define CMD_RIGHT 0x55 +#define CMD_LEFT 0xAA +#define CMD_UP 0x33 +#define CMD_DOWN 0xCC +#define CMD_SEL 0xFF +#define CMD_ACK 0x66 + +/* Number of data bytes for each command */ +#define CMD_RIGHT_SIZE 0x01 +#define CMD_LEFT_SIZE 0x05 +#define CMD_UP_SIZE 0x14 +#define CMD_DOWN_SIZE 0x1E +#define CMD_SEL_SIZE TXBUFFERSIZE + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/readme.txt new file mode 100644 index 000000000..0481efbf2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/readme.txt @@ -0,0 +1,151 @@ +/** + @page USART_DataExchangeDMA USART Communication Boards Data Exchange using DMA example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file USART/USART_TwoBoards/DataExchangeDMA/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the USART Communication Boards Data Exchange using + * DMA example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a small application in which joystick buttons are used +to trigger USART communications using DMA and though using USART firmware library. + +- Hardware Description + +To use this example, you need to load it on two STM32 boards (let's call them +BoardA and BoardB) then connect these two boards through USART lines and GND. +In the firmware example uncomment the dedicated line in the main.h file to use +the USART peripheral as STM32 Transmitter or as STM32 Receiver device. + +@verbatim +*------------------------------------------------------------------------------* +| BoardA BoardB | +| ____________________ ____________________ | +| | | | | | +| | | | | | +| | __________ | | __________ | | +| | | USART |____|TX_____________RX|____| USART | | | +| | | Device1 |____|RX_____________TX|____| Device2 | | | +| | |____TX____| | | |____RX____| | | +| | | | | | +| | O LD1 | | O LD1 | | +| | O LD2 Joystick | | O LD2 Joystick | | +| | O LD3 _ | | O LD3 _ | | +| | O LD4 |_| | | O LD4 |_| | | +| | | | | | +| | GND O--|-----------------|--O GND | | +| |____________________| |____________________| | +| | +| | +*------------------------------------------------------------------------------* +@endverbatim + +@note +- The connection between the pins should use a common Ground. + +- Software Description + +On Transmitter Board, at each joystick buttons press: +- The USART Transmitter Board sends the specific command to the USART Receiver Board + the command contains the transaction code (CMD_RIGHT, CMD_LEFT, CMD_UP, CMD_DOWN + or CMD_SEL) followed by the number of data to be transmitted (CMD_RIGHT_SIZE, + CMD_LEFT_SIZE, CMD_UP_SIZE, CMD_DOWN_SIZE or CMD_SEL_SIZE). + +- The USART Receiver Board receives the specific command (2 bytes received : 1 byte :code + and 1 byte : number of data). + +- The USART Transmitter Board sends the number of bytes (already defined in the specific + command)from TxBuffer to the USART Receiver Board. + +- The USART Receiver Board compares the number of bytes received with the defined ones into + his TxBuffer. + + Received data correctness is signaled by LED lightening and though as follow: + - Joystick RIGHT and data correctly received ==> LD2, LD3 ON and LD4 OFF + - Joystick LEFT and data correctly received ==> LD4 ON, LD2 and LD3 are OFF + - Joystick UP and data correctly received ==> LD2 ON, LD3 and LD4 are OFF + - Joystick DOWN and data correctly received ==> LD3 ON, LD2 and LD4 are OFF + - Joystick SEL and data correctly received ==> LD2, LD3 and LD4 are ON + +In both boards, the data transfers is managed using the USART Tx/Rx channels DMA requests. + +The SysTick is configured to generate interrupt each 10ms. A dedicated counter +inside the SysTick ISR is used to toggle the LD1 each 100ms indicating that the +firmware is running. +These operations can be repeated infinitely. + +A defined communication timeout is insuring that the application will not remain +stuck if the USART communication is corrupted. +You can adjust this timeout through the USER_TIMEOUT define inside main.h file +depending on CPU frequency and application conditions (interrupts routines, +number of data to transfer, baudrate, CPU frequency...). +When a given operation is not finished within the defined timeout, a callback is +made to the function "TimeOut_UserCallback()", this function is used to manage +timeout communication failure. In this example, this callback implements a simple +infinite loop, but user can add his own implementation to manage timeout failure. + + +@par Directory contents + + - USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_conf.h Library Configuration file + - USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_it.c Interrupt handlers + - USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_it.h Interrupt handlers header file + - USART/USART_TwoBoards/DataExchangeDMA/main.c Main program + - USART/USART_TwoBoards/DataExchangeDMA/main.h Main program header file + - USART/USART_TwoBoards/DataExchangeDMA/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool. + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + - Use the Joystick buttons + - Connect BoardA USART3 TX pin (PC.10) to BoardB USART3 RX pin (PC.11) + - Connect BoardA USART3 RX pin (PC.11) to BoardB USART3 TX pin (PC.10) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_conf.h new file mode 100644 index 000000000..bc18f6b33 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_it.c new file mode 100644 index 000000000..0e1f37647 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_it.c @@ -0,0 +1,192 @@ +/** + ****************************************************************************** + * @file USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup USART_DataExchangeDMA + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint8_t Counter = 0x00; +extern __IO uint32_t TimeOut; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + /* Decrement the timeout value */ + if (TimeOut != 0x0) + { + TimeOut--; + } + + if (Counter < 10) + { + Counter++; + } + else + { + Counter = 0x00; + STM_EVAL_LEDToggle(LED1); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx_md.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_it.h new file mode 100644 index 000000000..0669db7ae --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file USART/USART_TwoBoards/DataExchangeDMA/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeDMA/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/main.c new file mode 100644 index 000000000..62ab40c81 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/main.c @@ -0,0 +1,529 @@ +/** + ****************************************************************************** + * @file USART/USART_TwoBoards/DataExchangeInterrupt/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup USART_DataExchangeInterrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +uint8_t TxBuffer[] = "USART Interrupt Example: Communication between two USART using Interrupt"; +uint8_t RxBuffer [RXBUFFERSIZE]; +__IO uint8_t RxIndex = 0x00; +__IO uint8_t TxIndex = 0x00; + +__IO JOYState_TypeDef PressedButton = JOY_NONE; +__IO uint8_t UsartMode = USART_MODE_TRANSMITTER; +__IO uint8_t UsartTransactionType = USART_TRANSACTIONTYPE_CMD; + +uint8_t CmdBuffer [0x02] = {0x00, 0x00}; /* {Transaction Command, +Number of byte to receive or to transmit} */ +uint8_t AckBuffer [0x02] = {0x00, 0x00}; /* {Transaction Command, ACK command} */ + +__IO uint32_t TimeOut = 0x00; +/* Private function prototypes -----------------------------------------------*/ +static void USART_Config(void); +static void SysTickConfig(void); +static void TimeOut_UserCallback(void); +static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength); +static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength); +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* USART configuration -----------------------------------------------------*/ + USART_Config(); + + /* SysTick configuration ---------------------------------------------------*/ + SysTickConfig(); + + /* Initialize LEDs mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Configure the IO Expander mounted on STM322xG-EVAL board */ + TimeOut = USER_TIMEOUT; + while ((IOE_Config() != IOE_OK) && (TimeOut != 0x00)) + {} + + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Enable the USARTx Receive interrupt: this interrupt is generated when the + USARTx receive data register is not empty */ + USART_ITConfig(USARTx, USART_IT_RXNE, ENABLE); + + while (1) + { + TxIndex = 0x00; + RxIndex = 0x00; + UsartTransactionType = USART_TRANSACTIONTYPE_CMD; + UsartMode = USART_MODE_RECEIVER; + + Fill_Buffer(CmdBuffer, 0x02); + Fill_Buffer(AckBuffer, 0x02); + + /* Clear the RxBuffer */ + Fill_Buffer(RxBuffer, TXBUFFERSIZE); + + PressedButton = IOE_JoyStickGetState(); + + /* Waiting Joystick is pressed or transaction command is received */ + while ((PressedButton == JOY_NONE) && (CmdBuffer[0x00] == 0x00)) + { + PressedButton = IOE_JoyStickGetState(); + } + + /* + If the Joystick is pressed go to transmitter mode, otherwise (the transaction + command is received) go to receiver mode + */ + +/******************************************************************************/ +/* USART in Mode Transmitter */ +/******************************************************************************/ + if ((PressedButton != JOY_NONE) && (CmdBuffer[0x00] == 0x00)) + { + UsartMode = USART_MODE_TRANSMITTER; + switch (PressedButton) + { + /* JOY_RIGHT button pressed */ + case JOY_RIGHT: + CmdBuffer[0x00] = CMD_RIGHT; + CmdBuffer[0x01] = CMD_RIGHT_SIZE; + break; + /* JOY_LEFT button pressed */ + case JOY_LEFT: + CmdBuffer[0x00] = CMD_LEFT; + CmdBuffer[0x01] = CMD_LEFT_SIZE; + break; + /* JOY_UP button pressed */ + case JOY_UP: + CmdBuffer[0x00] = CMD_UP; + CmdBuffer[0x01] = CMD_UP_SIZE; + break; + /* JOY_DOWN button pressed */ + case JOY_DOWN: + CmdBuffer[0x00] = CMD_DOWN; + CmdBuffer[0x01] = CMD_DOWN_SIZE; + break; + /* JOY_SEL button pressed */ + case JOY_SEL: + CmdBuffer[0x00] = CMD_SEL; + CmdBuffer[0x01] = CMD_SEL_SIZE; + break; + default: + break; + } + + if (CmdBuffer[0x00]!= 0x00) + { + /* Enable the USARTx transmit data register empty interrupt */ + USART_ITConfig(USARTx, USART_IT_TXE, ENABLE); + + /* Wait until USART sends the command or time out */ + TimeOut = USER_TIMEOUT; + while ((TxIndex < 0x02)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* The software must wait until TC=1. The TC flag remains cleared during all data + transfers and it is set by hardware at the last frame’s end of transmission*/ + TimeOut = USER_TIMEOUT; + while ((USART_GetFlagStatus(USARTx, USART_FLAG_TC) == RESET)&&(TimeOut != 0x00)) + { + } + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* Wait until USART receives the Ack command or time out*/ + TimeOut = USER_TIMEOUT; + while ((RxIndex < 0x02)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + /* USART sends the data */ + UsartTransactionType = USART_TRANSACTIONTYPE_DATA; + TxIndex = 0x00; + RxIndex = 0x00; + + /* Enable the USARTx transmit data register empty interrupt */ + USART_ITConfig(USARTx, USART_IT_TXE, ENABLE); + + /* Wait until end of data transfer */ + TimeOut = USER_TIMEOUT; + while ((TxIndex < GetVar_NbrOfData())&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* The software must wait until TC=1. The TC flag remains cleared during all data + transfers and it is set by hardware at the last frame’s end of transmission*/ + TimeOut = USER_TIMEOUT; + while ((USART_GetFlagStatus(USARTx, USART_FLAG_TC) == RESET)&&(TimeOut != 0x00)) + { + } + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + } + CmdBuffer[0x00] = 0x00; + } + +/******************************************************************************/ +/* USART in Receiver Mode */ +/******************************************************************************/ + if (CmdBuffer[0x00] != 0x00) + { + /* Wait until USART receives the command or time out */ + TimeOut = USER_TIMEOUT; + while ((RxIndex < 0x02)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + UsartMode = USART_MODE_RECEIVER; + + /* Enable the USARTx transmit data register empty interrupt */ + USART_ITConfig(USARTx, USART_IT_TXE, ENABLE); + + /* Wait until USART sends the ACK command or time out*/ + TimeOut = USER_TIMEOUT; + while ((TxIndex < 0x02)&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* The software must wait until TC=1. The TC flag remains cleared during all data + transfers and it is set by hardware at the last frame’s end of transmission*/ + TimeOut = USER_TIMEOUT; + while ((USART_GetFlagStatus(USARTx, USART_FLAG_TC) == RESET)&&(TimeOut != 0x00)) + { + } + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + + /* USART receives the data */ + UsartTransactionType = USART_TRANSACTIONTYPE_DATA; + TxIndex = 0x00; + RxIndex = 0x00; + + /* Wait until end of data transfer or time out */ + TimeOut = USER_TIMEOUT; + while ((RxIndex < GetVar_NbrOfData())&&(TimeOut != 0x00)) + {} + if(TimeOut == 0) + { + TimeOut_UserCallback(); + } + switch (CmdBuffer[0x01]) + { + /* CMD_RIGHT command received */ + case CMD_RIGHT_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_RIGHT_SIZE) != FAILED) + { + /* Turn ON LED2 and LED3 */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + /* Turn OFF LED4 */ + STM_EVAL_LEDOff(LED4); + } + break; + /* CMD_LEFT command received */ + case CMD_LEFT_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_LEFT_SIZE) != FAILED) + { + /* Turn ON LED4 */ + STM_EVAL_LEDOn(LED4); + /* Turn OFF LED2 and LED3 */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED3); + } + break; + /* CMD_UP command received */ + case CMD_UP_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_UP_SIZE) != FAILED) + { + /* Turn ON LED2 */ + STM_EVAL_LEDOn(LED2); + /* Turn OFF LED3 and LED4 */ + STM_EVAL_LEDOff(LED3); + STM_EVAL_LEDOff(LED4); + } + break; + /* CMD_DOWN command received */ + case CMD_DOWN_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_DOWN_SIZE) != FAILED) + { + /* Turn ON LED3 */ + STM_EVAL_LEDOn(LED3); + /* Turn OFF LED2 and LED4 */ + STM_EVAL_LEDOff(LED2); + STM_EVAL_LEDOff(LED4); + } + break; + /* CMD_SEL command received */ + case CMD_SEL_SIZE: + if (Buffercmp(TxBuffer, RxBuffer, CMD_SEL_SIZE) != FAILED) + { + /* Turn ON all LED2, LED3 and LED4 */ + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + } + break; + default: + break; + } + CmdBuffer[0x00] = 0x00; + } + } +} + +/** + * @brief Basic management of the timeout situation. + * @param None. + * @retval None. + */ +static void TimeOut_UserCallback(void) +{ + /* User can add his own implementation to manage TimeOut Communication failure */ + /* Block communication and all processes */ + while (1) + { + } +} + +/** + * @brief Configures the USART Peripheral. + * @param None + * @retval None + */ +static void USART_Config(void) +{ + USART_InitTypeDef USART_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIO clock */ + RCC_AHB1PeriphClockCmd(USARTx_TX_GPIO_CLK | USARTx_RX_GPIO_CLK, ENABLE); + + /* Enable USART clock */ + USARTx_CLK_INIT(USARTx_CLK, ENABLE); + + /* Connect USART pins to AF7 */ + GPIO_PinAFConfig(USARTx_TX_GPIO_PORT, USARTx_TX_SOURCE, USARTx_TX_AF); + GPIO_PinAFConfig(USARTx_RX_GPIO_PORT, USARTx_RX_SOURCE, USARTx_RX_AF); + + /* Configure USART Tx and Rx as alternate function push-pull */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_InitStructure.GPIO_Pin = USARTx_TX_PIN; + GPIO_Init(USARTx_TX_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = USARTx_RX_PIN; + GPIO_Init(USARTx_RX_GPIO_PORT, &GPIO_InitStructure); + + /* Enable the USART OverSampling by 8 */ + USART_OverSampling8Cmd(USARTx, ENABLE); + + /* USARTx configuration ----------------------------------------------------*/ + /* USARTx configured as follow: + - BaudRate = 3750000 baud + - Maximum BaudRate that can be achieved when using the Oversampling by 8 + is: (USART APB Clock / 8) + Example: + - (USART3 APB1 Clock / 8) = (30 MHz / 8) = 3750000 baud + - (USART1 APB2 Clock / 8) = (60 MHz / 8) = 7500000 baud + - Maximum BaudRate that can be achieved when using the Oversampling by 16 + is: (USART APB Clock / 16) + Example: (USART3 APB1 Clock / 16) = (30 MHz / 16) = 1875000 baud + Example: (USART1 APB2 Clock / 16) = (60 MHz / 16) = 3750000 baud + - Word Length = 8 Bits + - one Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + USART_InitStructure.USART_BaudRate = 3750000; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(USARTx, &USART_InitStructure); + + /* NVIC configuration */ + /* Configure the Priority Group to 2 bits */ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + + /* Enable the USARTx Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = USARTx_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Enable USART */ + USART_Cmd(USARTx, ENABLE); +} + +/** + * @brief Configures the SysTick Base time to 10 ms. + * @param None + * @retval None + */ +static void SysTickConfig(void) +{ + /* Setup SysTick Timer for 10ms interrupts */ + if (SysTick_Config(SystemCoreClock / 100)) + { + /* Capture error */ + while (1); + } + /* Configure the SysTick handler priority */ + NVIC_SetPriority(SysTick_IRQn, 0x0); +} + +/** + * @brief Compares two buffers. + * @param pBuffer1, pBuffer2: buffers to be compared. + * @param BufferLength: buffer's length + * @retval PASSED: pBuffer1 identical to pBuffer2 + * FAILED: pBuffer1 differs from pBuffer2 + */ +static TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength) +{ + while (BufferLength--) + { + if (*pBuffer1 != *pBuffer2) + { + return FAILED; + } + pBuffer1++; + pBuffer2++; + } + + return PASSED; +} +/** + * @brief Returns NbrOfData value. + * @param None + * @retval Tx Buffer Size (NbrOfDataToTransfer). + */ +uint8_t GetVar_NbrOfData(void) +{ + return CmdBuffer[0x01]; +} +/** + * @brief Fills buffer. + * @param pBuffer: pointer on the Buffer to fill + * @param BufferLength: size of the buffer to fill + * @retval None + */ +static void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLength) +{ + uint16_t index = 0; + + /* Put in global buffer same values */ + for (index = 0; index < BufferLength; index++ ) + { + pBuffer[index] = 0x00; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + {} +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/main.h new file mode 100644 index 000000000..5f6bcbe4f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/main.h @@ -0,0 +1,116 @@ +/** + ****************************************************************************** + * @file USART/USART_TwoBoards/DataExchangeInterrupt/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stm322xg_eval_ioe.h" + +/* Exported typedef -----------------------------------------------------------*/ +#define countof(a) (sizeof(a) / sizeof(*(a))) +typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus; + +/* Exported define ------------------------------------------------------------*/ + +/* USER_TIMEOUT value for waiting loops. This timeout is just guarantee that the + application will not remain stuck if the USART communication is corrupted. + You may modify this timeout value depending on CPU frequency and application + conditions (interrupts routines, number of data to transfer, baudrate, frequence + CPU...). */ +#define USER_TIMEOUT ((uint32_t)0x64) /* Waiting 1s */ + +/* USART Mode Selected */ +#define USART_MODE_TRANSMITTER 0x00 +#define USART_MODE_RECEIVER 0x01 + +/* USART Transaction Type */ +#define USART_TRANSACTIONTYPE_CMD 0x00 +#define USART_TRANSACTIONTYPE_DATA 0x01 + + +/* Definition for USARTx resources ********************************************/ +#define USARTx USART3 +#define USARTx_CLK RCC_APB1Periph_USART3 +#define USARTx_CLK_INIT RCC_APB1PeriphClockCmd +#define USARTx_IRQn USART3_IRQn +#define USARTx_IRQHandler USART3_IRQHandler + +#define USARTx_TX_PIN GPIO_Pin_10 +#define USARTx_TX_GPIO_PORT GPIOC +#define USARTx_TX_GPIO_CLK RCC_AHB1Periph_GPIOC +#define USARTx_TX_SOURCE GPIO_PinSource10 +#define USARTx_TX_AF GPIO_AF_USART3 + +#define USARTx_RX_PIN GPIO_Pin_11 +#define USARTx_RX_GPIO_PORT GPIOC +#define USARTx_RX_GPIO_CLK RCC_AHB1Periph_GPIOC +#define USARTx_RX_SOURCE GPIO_PinSource11 +#define USARTx_RX_AF GPIO_AF_USART3 + + +/* Misc definition ************************************************************/ +/* Transmit buffer size */ +#define TXBUFFERSIZE (countof(TxBuffer) - 1) +/* Receive buffer size */ +#define RXBUFFERSIZE TXBUFFERSIZE + +/* Commands list */ +#define CMD_RIGHT 0x55 +#define CMD_LEFT 0xAA +#define CMD_UP 0x33 +#define CMD_DOWN 0xCC +#define CMD_SEL 0xFF + +#define CMD_ACK 0x66 + +/* Number of data bytes for each command */ +#define CMD_RIGHT_SIZE 0x01 +#define CMD_LEFT_SIZE 0x05 +#define CMD_UP_SIZE 0x14 +#define CMD_DOWN_SIZE 0x1E +#define CMD_SEL_SIZE TXBUFFERSIZE + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +uint8_t GetVar_NbrOfData(void); +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/readme.txt new file mode 100644 index 000000000..45b92e0ed --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/readme.txt @@ -0,0 +1,152 @@ +/** + @page USART_DataExchangeInterrupt USART Communication Boards Data Exchange using Interrupt example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file USART/USART_TwoBoards/DataExchangeInterrupt/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the USART Communication Boards Interrupt Data Exchange + * using Interrupt example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example provides a small application in which joystick buttons are used +to trigger USART communication using interrupts and though using USART firmware +library. + +- Hardware Description + +To use this example, you need to load it on two STM32 boards (let's call them +BoardA and BoardB) then connect these two boards through UART lines and GND. + +@verbatim +*------------------------------------------------------------------------------* +| BoardA BoardB | +| ____________________ ____________________ | +| | | | | | +| | | | | | +| | __________ | | __________ | | +| | | UART |____|TX_____________RX|____| UART | | | +| | | Device1 |____|RX_____________TX|____| Device2 | | | +| | |__________| | | |__________| | | +| | | | | | +| | O LD1 | | O LD1 | | +| | O LD2 Joystick | | O LD2 Joystick | | +| | O LD3 _ | | O LD3 _ | | +| | O LD4 |_| | | O LD4 |_| | | +| | | | | | +| | GND O--|-----------------|--O GND | | +| |____________________| |____________________| | +| | +| | +*------------------------------------------------------------------------------* +@endverbatim + +@note +- The connection between the pins should use a common Ground. + +- Software Description + +On BoardA, at each joystick buttons press: +- The USART BoardA sends the specific command to the USART BoardB (the command + contains the transaction code (CMD_RIGHT, CMD_LEFT, CMD_UP, CMD_DOWN or CMD_SEL) + followed by the number of data to be transmitted (CMD_RIGHT_SIZE, CMD_LEFT_SIZE, + CMD_UP_SIZE, CMD_DOWN_SIZE or CMD_SEL_SIZE) + +- The USART BoardB receives the command and sends the CMD_ACK command to the USART BoardA + +- The USART BoardA receives the CMD_ACK command and sends the number of bytes + from TxBuffer to the USART BoardB. + +- The USART BoardB compares the number of bytes received with the defined ones into + his TxBuffer. + + Received data correctness is signaled by LED lightening and though as follow: + - Joystick RIGHT and data correctly received ==> LD2, LD3 ON and LD4 OFF + - Joystick LEFT and data correctly received ==> LD4 ON, LD2 and LD3 are OFF + - Joystick UP and data correctly received ==> LD2 ON, LD3 and LD4 are OFF + - Joystick DOWN and data correctly received ==> LD3 ON, LD2 and LD4 are OFF + - Joystick SEL and data correctly received ==> LD2, LD3 and LD4 are ON + +The steps described above can be also initiated and ensured by BoardB. + +In both boards(BoardA or BoardB), the data transfers is managed using USARTx_IRQHandler +in stm32f2xx_it.c file. + +The SysTick is configured to generate interrupt each 10ms. A dedicated counter +inside the SysTick ISR is used to toggle the LD1 each 100ms indicating that the +firmware is running. +These operations can be repeated infinitely. + +A defined communication timeout is insuring that the application will not remain +stuck if the USART communication is corrupted. +You can adjust this timeout through the USER_TIMEOUT define inside main.h file +depending on CPU frequency and application conditions (interrupts routines, +number of data to transfer, baudrate, CPU frequency...). +When a given operation is not finished within the defined timeout, a callback is +made to the function "TimeOut_UserCallback()", this function is used to manage +timeout communication failure. In this example, this callback implements a simple +infinite loop, but user can add his own implementation to manage timeout failure. + + +@par Directory contents + + - USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h Library Configuration file + - USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c Interrupt handlers + - USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h Interrupt handlers header file + - USART/USART_TwoBoards/DataExchangeInterrupt/main.c Main program + - USART/USART_TwoBoards/DataExchangeInterrupt/main.h Main program header file + - USART/USART_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c STM32F2xx system source file + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board. + + - STM322xG-EVAL Set-up + - Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09 + and PC.07 pins + - Use the Joystick buttons + - Connect BoardA USART3 TX pin (PC.10) to BoardB USART3 RX pin (PC.11) + - Connect BoardA USART3 RX pin (PC.11) to BoardB USART3 TX pin (PC.10) + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h new file mode 100644 index 000000000..59cbd1702 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c new file mode 100644 index 000000000..40831cf61 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c @@ -0,0 +1,272 @@ +/** + ****************************************************************************** + * @file USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup USART_DataExchangeInterrupt + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern uint8_t TxBuffer[]; +extern uint8_t RxBuffer[]; +extern uint8_t CmdBuffer[]; +extern uint8_t AckBuffer[]; +extern __IO uint8_t RxIndex; +extern __IO uint8_t TxIndex; + +extern __IO uint8_t UsartTransactionType; +extern __IO uint8_t UsartMode; + +__IO uint8_t Counter = 0x00; +extern __IO uint32_t TimeOut; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + /* Decrement the timeout value */ + if (TimeOut != 0x0) + { + TimeOut--; + } + + if (Counter < 10) + { + Counter++; + } + else + { + Counter = 0x00; + STM_EVAL_LEDToggle(LED1); + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/******************************************************************************/ +/** +* @brief This function handles USRAT interrupt request. +* @param None +* @retval None +*/ +void USARTx_IRQHandler(void) +{ + /* USART in mode Tramitter -------------------------------------------------*/ + if (USART_GetITStatus(USARTx, USART_IT_TXE) == SET) + { /* When Joystick Pressed send the command then send the data */ + if (UsartMode == USART_MODE_TRANSMITTER) + { /* Send the command */ + if (UsartTransactionType == USART_TRANSACTIONTYPE_CMD) + { + USART_SendData(USARTx, CmdBuffer[TxIndex++]); + if (TxIndex == 0x02) + { + /* Disable the USARTx transmit data register empty interrupt */ + USART_ITConfig(USARTx, USART_IT_TXE, DISABLE); + } + } + /* Send the data */ + else + { + USART_SendData(USARTx, TxBuffer[TxIndex++]); + if (TxIndex == GetVar_NbrOfData()) + { + /* Disable the USARTx transmit data register empty interrupt */ + USART_ITConfig(USARTx, USART_IT_TXE, DISABLE); + } + } + } + /*If Data Received send the ACK*/ + else + { + USART_SendData(USARTx, AckBuffer[TxIndex++]); + if (TxIndex == 0x02) + { + /* Disable the USARTx transmit data register empty interrupt */ + USART_ITConfig(USARTx, USART_IT_TXE, DISABLE); + } + } + } + + /* USART in mode Receiver --------------------------------------------------*/ + if (USART_GetITStatus(USARTx, USART_IT_RXNE) == SET) + { + if (UsartMode == USART_MODE_TRANSMITTER) + { + AckBuffer[RxIndex++] = USART_ReceiveData(USARTx); + } + else + { + /* Receive the command */ + if (UsartTransactionType == USART_TRANSACTIONTYPE_CMD) + { + CmdBuffer[RxIndex++] = USART_ReceiveData(USARTx); + } + /* Receive the USART data */ + else + { + RxBuffer[RxIndex++] = USART_ReceiveData(USARTx); + } + } + } +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h new file mode 100644 index 000000000..621dd0ad4 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file USART/USART_TwoBoards/DataExchangeInterrupt/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void USARTx_IRQHandler(void); + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/USART/USART_TwoBoards/DataExchangeInterrupt/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/main.c new file mode 100644 index 000000000..81d14fc0e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/main.c @@ -0,0 +1,164 @@ +/** + ****************************************************************************** + * @file WWDG/WWDG_Example/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup WWDG_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +__IO uint32_t TimingDelay = 0; + +/* Private function prototypes -----------------------------------------------*/ +void Delay(__IO uint32_t nTime); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* Initialize LEDs and Key Button mounted on STM322xG-EVAL board */ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI); + + /* Check if the system has resumed from WWDG reset */ + if (RCC_GetFlagStatus(RCC_FLAG_WWDGRST) != RESET) + { + /* WWDGRST flag set */ + /* Turn on LED1 */ + STM_EVAL_LEDOn(LED1); + + /* Clear reset flags */ + RCC_ClearFlag(); + } + else + { + /* WWDGRST flag is not set */ + /* Turn off LED1 */ + STM_EVAL_LEDOff(LED1); + } + + /* Setup SysTick Timer for 1 msec interrupts */ + if (SysTick_Config(SystemCoreClock / 1000)) + { + /* Capture error */ + while (1); + } + + /* WWDG configuration */ + /* Enable WWDG clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE); + + /* WWDG clock counter = (PCLK1 (30MHz)/4096)/8 = 915 Hz (~1092 us) */ + WWDG_SetPrescaler(WWDG_Prescaler_8); + + /* Set Window value to 80; WWDG counter should be refreshed only when the counter + is below 80 (and greater than 64) otherwise a reset will be generated */ + WWDG_SetWindowValue(80); + + /* Enable WWDG and set counter value to 127, WWDG timeout = ~1092 us * 64 = 69.9 ms + In this case the refresh window is: ~1092 * (127-80) = 51.3 ms < refresh window < ~1092 * 64 = 69.9ms + */ + WWDG_Enable(127); + + while (1) + { + /* Toggle LED2 */ + STM_EVAL_LEDToggle(LED2); + + /* Insert 53 ms delay */ + Delay(53); + + /* Update WWDG counter */ + WWDG_SetCounter(127); + } +} + +/** + * @brief Inserts a delay time. + * @param nTime: specifies the delay time length, in milliseconds. + * @retval None + */ +void Delay(__IO uint32_t nTime) +{ + TimingDelay = nTime; + + while(TimingDelay != 0); +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/readme.txt new file mode 100644 index 000000000..48f0589e6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/readme.txt @@ -0,0 +1,94 @@ +/** + @page WWDG_Example WWDG_Example + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file WWDG/WWDG_Example/readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Description of the WWDG Example. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +@par Example Description + +This example shows how to update at regular period the WWDG counter and how to +simulate a software fault generating an MCU WWDG reset on expiry of a programmed +time period. + +The WWDG timeout is set to 69.9 ms and the refresh window is set to 80. +The WWDG counter is refreshed each 50ms in the main program infinite loop to +prevent a WWDG reset. +LED2 is also toggled each 53 ms indicating that the program is running. + +An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt +on the rising edge of the signal. + +The EXTI Line is used to simulate a software failure: once the EXTI Line event +occurs, by pressing the Key push-button, the corresponding interrupt is served. +In the ISR, a write to invalid address generates a Hardfault exception containing +an infinite loop and preventing to return to main program (the WWDG counter is +not refreshed). +As a result, when the WWDG counter falls to 63, the WWDG reset occurs. +If the WWDG reset is generated, after the system resumes from reset, LED1 turns on. + +If the EXTI Line event does not occur, the WWDG counter is indefinitely refreshed +in the main program infinite loop, and there is no WWDG reset. + + +@par Directory contents + + - WWDG_Example/system_stm32f2xx.c STM32F2xx system clock configuration file + - WWDG_Example/stm32f2xx_conf.h Library Configuration file + - WWDG_Example/stm32f2xx_it.c Interrupt handlers + - WWDG_Example/stm32f2xx_it.h Header for stm32f2xx_it.c + - WWDG_Example/main.c Main program + +@note The "system_stm32f2xx.c" is generated by an automatic clock configuration + tool and can be easily customized to your own configuration. + To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" + provided with the AN3362 package available on ST Microcontrollers + + +@par Hardware and Software environment + + - This example runs on STM32F2xx Devices. + + - This example has been tested with STM322xG-EVAL RevB and can be easily tailored + to any other development board + + + - STM322xG-EVAL Set-up + - Use LD1 and LD2 leds connected respectively to PG.06 and PG.08 pins + - Use the KEY push button connected to PG.15 pin (EXTI Line15). + + +@par How to use it ? + +In order to make the program work, you must do the following : + - Copy all source files from this example folder to the template folder under + Project\STM32F2xx_StdPeriph_Template + - Open your preferred toolchain + - Rebuild all files and load your image into target memory + - Run the example + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/stm32f2xx_conf.h new file mode 100644 index 000000000..9ec369e5a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file WWDG/WWDG_Example/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/stm32f2xx_it.c new file mode 100644 index 000000000..988d47d98 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/stm32f2xx_it.c @@ -0,0 +1,197 @@ +/** + ****************************************************************************** + * @file WWDG/WWDG_Example/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "stm322xg_eval.h" + +/** @addtogroup STM32F2xx_StdPeriph_Examples + * @{ + */ + +/** @addtogroup WWDG_Example + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +extern __IO uint32_t TimingDelay; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + TimingDelay--; +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @brief This function handles External line 15 to 10 interrupt request. + * @param None + * @retval None + */ +void EXTI15_10_IRQHandler(void) +{ + if (EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET) + { + /* Clear the Key Button EXTI Line Pending Bit */ + EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); + + /* As the following address is invalid (not mapped), a Hardfault exception + will be generated with an infinite loop and when the WWDG counter falls to 63 + the WWDG reset occurs */ + *(__IO uint32_t *) 0xA0001000 = 0xFF; + } +} + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/stm32f2xx_it.h new file mode 100644 index 000000000..6bf5116e8 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file WWDG/WWDG_Example/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Examples/WWDG/WWDG_Example/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/Project.ewd b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/Project.ewd new file mode 100644 index 000000000..dcaffc6b8 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/Project.ewd @@ -0,0 +1,884 @@ + + + + 2 + + STM322xG_EVAL + + ARM + + 1 + + C-SPY + 2 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + JLINK_ID + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 0 + 1 + 1 + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/Project.ewp b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/Project.ewp new file mode 100644 index 000000000..fe9345700 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/Project.ewp @@ -0,0 +1,1039 @@ + + + + 2 + + STM322xG_EVAL + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + CMSIS + + $PROJ_DIR$\..\system_stm32f2xx.c + + + + EWARM + + $PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F2xx\Source\Templates\iar\startup_stm32f2xx.s + + + + STM32_EVAL + + $PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM322xG_EVAL\stm322xg_eval.c + + + $PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM322xG_EVAL\stm322xg_eval_fsmc_sram.c + + + $PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM322xG_EVAL\stm322xg_eval_ioe.c + + + $PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM322xG_EVAL\stm322xg_eval_lcd.c + + + + STM32F2xx_StdPeriph_Driver + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c + + + $PROJ_DIR$\..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c + + + + User + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\stm32f2xx_it.c + + + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/Project.eww b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/Project.eww new file mode 100644 index 000000000..b71bdbfb2 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/Project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\Project.ewp + + + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/readme.txt new file mode 100644 index 000000000..b5dac7472 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/readme.txt @@ -0,0 +1,64 @@ +/** + @page ewarm EWARM Project Template for STM32F2xx devices + + @verbatim + ******************* (C) COPYRIGHT 2012 STMicroelectronics ******************** + * @file readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This sub-directory contains all the user-modifiable files needed to + * create a new project linked with the STM32F2xx Standard Peripherals + * Library and working with IAR Embedded Workbench for ARM (EWARM) + * software toolchain. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + + @par Directory contents + + - project .ewd/.eww/.ewp: A pre-configured project file with the provided library + structure that produces an executable image with IAR + Embedded Workbench. + + - stm32f2xx_flash.icf : This file is the IAR Linker configuration file used to + place program code (readonly) in internal FLASH and data + (readwrite, Stack and Heap)in internal SRAM. + You can customize this file to your need. + + - stm32f2xx_flash_extsram.icf: This file is the IAR Linker configuration file + used to place program code (readonly) in internal + FLASH and data (readwrite, Stack and Heap)in + external SRAM. You can customize this file to your need. + + - stm32f2xx_ram.icf: This file is the IAR Linker configuration file used to + place program code (readonly) and data (readwrite, Stack + and Heap)in internal SRAM. + You can customize this file to your need. + + @par How to use it ? + + - Open the Project.eww workspace. + - Rebuild all files: Project->Rebuild all + - Load project image: Project->Download and Debug + - Run program: Debug->Go(F5) + + @note The needed define symbols for this config are already declared in the + preprocessor section: USE_STM322xG_EVAL, STM32F2XX, USE_STDPERIPH_DRIVER + + + *

© COPYRIGHT STMicroelectronics

+ */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/stm32f2xx_flash.icf b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/stm32f2xx_flash.icf new file mode 100644 index 000000000..4f4f7bf4a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/stm32f2xx_flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20020000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/stm32f2xx_flash_extsram.icf b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/stm32f2xx_flash_extsram.icf new file mode 100644 index 000000000..e09a45a03 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/stm32f2xx_flash_extsram.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x64000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x640FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; /* EXTSRAM_region */ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/stm32f2xx_sram.icf b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/stm32f2xx_sram.icf new file mode 100644 index 000000000..df159b539 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/EWARM/stm32f2xx_sram.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20010000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/MDK-ARM/Project.uvopt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/MDK-ARM/Project.uvopt new file mode 100644 index 000000000..8b72f3ab6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/MDK-ARM/Project.uvopt @@ -0,0 +1,800 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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stm32f2xx_syscfg.c + + + 3 + 35 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c + stm32f2xx_tim.c + + + 3 + 36 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c + stm32f2xx_usart.c + + + 3 + 37 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c + stm32f2xx_wwdg.c + + + + + CMSIS + 1 + 0 + 0 + + 4 + 38 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\system_stm32f2xx.c + system_stm32f2xx.c + + + + + MDK-ARM + 1 + 0 + 0 + + 5 + 39 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\Libraries\CMSIS\Device\ST\STM32F2xx\Source\Templates\arm\startup_stm32f2xx.s + startup_stm32f2xx.s + + + + + 1 + 0 + + 100 + 0 + + + ..\main.c + 0 + 108 + 118 + + + + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/MDK-ARM/Project.uvproj b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/MDK-ARM/Project.uvproj new file mode 100644 index 000000000..801a1151d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/MDK-ARM/Project.uvproj @@ -0,0 +1,610 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + STM322xG_EVAL + 0x4 + ARM-ADS + + + STM32F207IG + STMicroelectronics + IRAM(0x20000000-0x2001FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M3") + + "STARTUP\ST\STM32F2xx\startup_stm32f2xx.s" ("STM32F2xx Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000) + 5124 + stm32f2xx.h + + + + + + + + + + SFD\ST\STM32F2xx\STM32F2xx.sfr + 0 + + + + ST\STM32F2xx\ + ST\STM32F2xx\ + + 0 + 0 + 0 + 0 + 1 + + .\STM322xG_EVAL\ + STM322xG_EVAL + 1 + 0 + 0 + 1 + 1 + .\STM322xG_EVAL\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DARMSTM.DLL + -pSTM32F207IG + SARMCM3.DLL + -MPU + TARMSTM.DLL + -pSTM32F207IG + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 1 + + + + + + + + + + + + + + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + BIN\UL2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + + + USE_STM322xG_EVAL, STM32F2XX, USE_STDPERIPH_DRIVER + + ..\;..\..\..\Libraries\CMSIS\Device\ST\STM32F2xx\Include;..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM322xG_EVAL + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + User + + + main.c + 1 + ..\main.c + + + stm32f2xx_it.c + 1 + ..\stm32f2xx_it.c + + + + + STM32_EVAL + + + stm322xg_eval_fsmc_sram.c + 1 + ..\..\..\Utilities\STM32_EVAL\STM322xG_EVAL\stm322xg_eval_fsmc_sram.c + + + stm322xg_eval_ioe.c + 1 + ..\..\..\Utilities\STM32_EVAL\STM322xG_EVAL\stm322xg_eval_ioe.c + + + stm322xg_eval_lcd.c + 1 + ..\..\..\Utilities\STM32_EVAL\STM322xG_EVAL\stm322xg_eval_lcd.c + + + stm322xg_eval.c + 1 + ..\..\..\Utilities\STM32_EVAL\STM322xG_EVAL\stm322xg_eval.c + + + + + STM32F2xx_StdPeriph_Driver + + + misc.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c + + + stm32f2xx_adc.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c + + + stm32f2xx_can.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c + + + stm32f2xx_crc.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c + + + stm32f2xx_cryp.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c + + + stm32f2xx_cryp_aes.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c + + + stm32f2xx_cryp_des.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c + + + stm32f2xx_cryp_tdes.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c + + + stm32f2xx_dac.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c + + + stm32f2xx_dbgmcu.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c + + + stm32f2xx_dcmi.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c + + + stm32f2xx_dma.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c + + + stm32f2xx_exti.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c + + + stm32f2xx_flash.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c + + + stm32f2xx_fsmc.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c + + + stm32f2xx_gpio.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c + + + stm32f2xx_hash.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c + + + stm32f2xx_hash_md5.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c + + + stm32f2xx_hash_sha1.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c + + + stm32f2xx_i2c.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c + + + stm32f2xx_iwdg.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c + + + stm32f2xx_pwr.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c + + + stm32f2xx_rcc.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c + + + stm32f2xx_rng.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c + + + stm32f2xx_rtc.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c + + + stm32f2xx_sdio.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c + + + stm32f2xx_spi.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c + + + stm32f2xx_syscfg.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c + + + stm32f2xx_tim.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c + + + stm32f2xx_usart.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c + + + stm32f2xx_wwdg.c + 1 + ..\..\..\Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c + + + + + CMSIS + + + system_stm32f2xx.c + 1 + ..\system_stm32f2xx.c + + + + + MDK-ARM + + + startup_stm32f2xx.s + 2 + ..\..\..\Libraries\CMSIS\Device\ST\STM32F2xx\Source\Templates\arm\startup_stm32f2xx.s + + + + + + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/MDK-ARM/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/MDK-ARM/readme.txt new file mode 100644 index 000000000..c233650ec --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/MDK-ARM/readme.txt @@ -0,0 +1,53 @@ +/** + @page mdkarm MDK-ARM Project Template for STM32F2xx devices + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This sub-directory contains all the user-modifiable files needed to + * create a new project linked with the STM32F2xx Standard Peripherals + * Library and working with RealView Microcontroller Development Kit + * (MDK-ARM) software toolchain. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + + @par Directory contents + + - Project.uvproj/.uvopt: A pre-configured project file with the provided library + structure that produces an executable image with MDK-ARM. + +@note Enabling "Options for Target — Output – Browser Information" is useful for + quick source files navigation but may slow the compilation time. + + + @par How to use it ? + + - Open the Project.uvproj project + - Rebuild all files: Project->Rebuild all target files + - Load project image: Debug->Start/Stop Debug Session + - Run program: Debug->Run (F5) + + @note The needed define symbols for this config are already declared in the + preprocessor section: USE_STM322xG_EVAL, STM32F2XX, USE_STDPERIPH_DRIVER + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/Project.rapp b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/Project.rapp new file mode 100644 index 000000000..56081ee8f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/Project.rapp @@ -0,0 +1,167 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + +
+ + +
+ + + + + \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/Project.rprj b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/Project.rprj new file mode 100644 index 000000000..7e5c81b0a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/Project.rprj @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/readme.txt new file mode 100644 index 000000000..683d8ee89 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/readme.txt @@ -0,0 +1,54 @@ +/** + @page ride RIDE Project Template for STM32F2xx devices + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This sub-directory contains all the user-modifiable files needed to + * create a new project linked with the STM32F2xx Standard Peripherals + * Library and working with RIDE7 software toolchain. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + + @par Directory contents + + - project .rprj/.rapp: A pre-configured project file with the provided library + structure that produces an executable image with RIDE7. + + - stm32f2xx_flash_extsram.ld: This file is the RAISONANCE linker script used to + place program code (readonly) in internal FLASH and + data (readwrite, Stack and Heap)in external SRAM. + You can customize this file to your need. + + @par How to use it ? + + - Open the Project.rprj project. + - Rebuild all files: Project->build project + - Load project image: Debug->start(ctrl+D) + - Run program: Debug->Run(ctrl+F9) + + @note The needed define symbols for this config are already declared in the + preprocessor section: USE_STM322xG_EVAL, STM32F2XX, USE_STDPERIPH_DRIVER + + + *

© COPYRIGHT STMicroelectronics

+ */ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/stm32f2xx_flash_extsram.ld b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/stm32f2xx_flash_extsram.ld new file mode 100644 index 000000000..b988d4460 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/RIDE/stm32f2xx_flash_extsram.ld @@ -0,0 +1,240 @@ +/* +Linker script for STM32F2xx_1024K_128K +*/ + +/* include the common STM32F2xx sub-script */ + +/* Common part of the linker scripts for STM32 devices*/ + + +/* default stack sizes. +These are used by the startup in order to allocate stacks for the different modes. +*/ + +__Stack_Size = 1024 ; + +PROVIDE ( _Stack_Size = __Stack_Size ) ; + +__Stack_Init = _estack - __Stack_Size ; + +/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/ +PROVIDE ( _Stack_Init = __Stack_Init ) ; + +/* +There will be a link error if there is not this amount of RAM free at the end. +*/ +_Minimum_Stack_Size = 0x100 ; + + +/* include the memory spaces definitions sub-script */ +/* +Linker subscript for STM32F2xx definitions with 1024K Flash and 1024K External SRAM */ + +/* Memory Spaces Definitions */ + +MEMORY +{ + RAM (xrw) : ORIGIN = 0x64000000, LENGTH = 1024K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K + FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0 + EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0 +} + +/* higher address of the user mode stack */ +_estack = 0x64100000; + + + +/* include the sections management sub-script for FLASH mode */ + +/* Sections Definitions */ + +SECTIONS +{ + /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */ + .flashtext : + { + . = ALIGN(4); + *(.flashtext) /* Startup code */ + . = ALIGN(4); + } >FLASH + + + /* the program code is stored in the .text section, which goes to Flash */ + .text : + { + . = ALIGN(4); + + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + + . = ALIGN(4); + _etext = .; + /* This is used by the startup in order to initialize the .data secion */ + _sidata = _etext; + } >FLASH + + + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + + + /* This is the uninitialized data section */ + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* This is the user stack section + This is just to check that there is enough RAM left for the User mode stack + It should generate an error if it's full. + */ + ._usrstack : + { + . = ALIGN(4); + _susrstack = . ; + + . = . + _Minimum_Stack_Size ; + + . = ALIGN(4); + _eusrstack = . ; + } >RAM + + + + /* this is the FLASH Bank1 */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + .b1text : + { + *(.b1text) /* remaining code */ + *(.b1rodata) /* read-only data (constants) */ + *(.b1rodata*) + } >FLASHB1 + + /* this is the EXTMEM */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + + /* EXTMEM Bank0 */ + .eb0text : + { + *(.eb0text) /* remaining code */ + *(.eb0rodata) /* read-only data (constants) */ + *(.eb0rodata*) + } >EXTMEMB0 + + /* EXTMEM Bank1 */ + .eb1text : + { + *(.eb1text) /* remaining code */ + *(.eb1rodata) /* read-only data (constants) */ + *(.eb1rodata*) + } >EXTMEMB1 + + /* EXTMEM Bank2 */ + .eb2text : + { + *(.eb2text) /* remaining code */ + *(.eb2rodata) /* read-only data (constants) */ + *(.eb2rodata*) + } >EXTMEMB2 + + /* EXTMEM Bank0 */ + .eb3text : + { + *(.eb3text) /* remaining code */ + *(.eb3rodata) /* read-only data (constants) */ + *(.eb3rodata*) + } >EXTMEMB3 + + + + /* after that it's only debugging information. */ + + /* remove the debugging information from the standard libraries */ + DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/Release_Notes.html b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/Release_Notes.html new file mode 100644 index 000000000..d2682e0d3 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/Release_Notes.html @@ -0,0 +1,136 @@ + + + + + + +Release Notes for STM32F2xx Standard Peripherals Library Template + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
Back to Release page
+

Release +Notes for STM32F2xx Standard Peripherals Library Template

+

Copyright 2012 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F2xx Standard Peripherals Library +Template +update History
    2. +
  2. License
    3. +
+ + +

STM32F2xx Standard +Peripherals Library Template update History

V1.1.0 / 13-April-2012

Main +Changes

+
  • All source files: license disclaimer text update and add link to the License file on ST Internet.
  • Update +template projects to use the latest version of the supported toolchains +(for more details refer to the Library's main release notes)
  • Update template projects to be in line with changes made on latest version of the STM32F2xx CMSIS V1.1.0 and STM322xG-EVAL drivers V5.0.0
    • Changes to be in line with STM32F2xx CMSIS V1.1.0: the update are due to modification on the folder organization (to be in line with CMSIS standard V2.1)
      • In the project complier preprocessor, update STM32F2xx CMSIS include folder path to "Libraries\CMSIS\Device\ST\STM32F2xx\Include" instead of "Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx"
      • In the project files, remove core_cm3.c file
      • In the project files, update path of startup_stm32f2xx.s file to "Libraries\CMSIS\Device\ST\STM32F2xx\Source\Templates\'compiler'" instead of "Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\startup\'compiler'"
    • Changes to be in line with STM322xG-EVAL drivers V5.0.0: the update are due to modification on the EVAL drivers architecture and folder organization (for more details refer to STM322xG-EVAL drivers release notes)
      • In the project files, remove stm32_eval.c\.h files
      • In the project files, add the EVAL board driver source file "stm322xg_eval.c" instead of "stm32_eval.c"
      • main.c: include the EVAL board driver header file #include "stm322xg_eval.h" instead of #include "stm32_eval.h"

V1.0.0 / 18-April-2011

Main +Changes

+
  • First official release for STM32F2xx devices
+ +
    + +
+

License

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License. + +
+
+

For + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/.cproject b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/.cproject new file mode 100644 index 000000000..1f46f867c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/.cproject @@ -0,0 +1,235 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TASKING VX-toolset for ARM Cortex: control program v4.2r1 Build 118 + TASKING VX-toolset for ARM Cortex: assembler v4.2r1 Build 141 + TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.2r1 Build 135 + TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.2r1 Build 652 + TASKING program builder v4.2r1 Build 063 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/.project b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/.project new file mode 100644 index 000000000..dfae19462 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/.project @@ -0,0 +1,232 @@ + + + STM322xG-EVAL + + + + + + com.tasking.arm.TskManagedBuilder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + com.tasking.arm.target + + + + CMSIS + 2 + WORKSPACE_LOC/.metadata/Link + + + STM32F2xx_StdPeriph_Driver + 2 + WORKSPACE_LOC/.metadata/Link + + + STM32_EVAL + 2 + WORKSPACE_LOC/.metadata/Link + + + User + 2 + WORKSPACE_LOC/.metadata/Link + + + CMSIS/system_stm32f2xx.c + 1 + PARENT-2-PROJECT_LOC/system_stm32f2xx.c + + + STM32F2xx_StdPeriph_Driver/misc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_adc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_can.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_crc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_cryp.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_cryp_aes.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_cryp_des.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_des.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_cryp_tdes.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_tdes.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_dac.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dac.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_dbgmcu.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_dcmi.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_dma.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_exti.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_flash.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_fsmc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_gpio.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_hash.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_hash_md5.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_hash_sha1.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_sha1.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_i2c.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_i2c.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_iwdg.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_pwr.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_rcc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_rng.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_rtc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_sdio.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_spi.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_syscfg.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_tim.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_usart.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c + + + STM32F2xx_StdPeriph_Driver/stm32f2xx_wwdg.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c + + + STM32_EVAL/stm322xg_eval.c + 1 + PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval.c + + + STM32_EVAL/stm322xg_eval_fsmc_sram.c + 1 + PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_sram.c + + + STM32_EVAL/stm322xg_eval_ioe.c + 1 + PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_ioe.c + + + STM32_EVAL/stm322xg_eval_lcd.c + 1 + PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_lcd.c + + + User/main.c + 1 + PARENT-2-PROJECT_LOC/main.c + + + User/stm32f2xx_it.c + 1 + PARENT-2-PROJECT_LOC/stm32f2xx_it.c + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/STM322xG-EVAL.board.launch b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/STM322xG-EVAL.board.launch new file mode 100644 index 000000000..ace9b6343 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/STM322xG-EVAL.board.launch @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/TASKING/stm32f2xx.lsl b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/TASKING/stm32f2xx.lsl new file mode 100644 index 000000000..0e4a7f354 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/STM322xG-EVAL/TASKING/stm32f2xx.lsl @@ -0,0 +1,221 @@ +//////////////////////////////////////////////////////////////////////////// +// +// File : stm32f2xx.lsl +// +// Version : @(#)stm32f2xx.lsl 1.1 10/11/03 +// +// Description : LSL file for the STMicroelectronics STM32F2xx +// +// Copyright 2010 Altium BV +// +// Macros specific to control this LSL file +// +// __MEMORY Define this macro to suppress definition of on-chip +// memory. Must be defined when you want to define on-chip +// in your project's LSL file. +// __FLASH_SIZE Specifies the size of flash memory to be allocated +// __SRAM_SIZE Specifies the size of the SRAM memory to be allocated +// __NO_DEFAULT_AUTO_VECTORS +// When enabled the interrup vector table will not be +// generated +// __COPY_VECTOR_TABLE Define this macro to enable copying the vector table +// at startup from ROM to RAM +// __VECTOR_TABLE_RAM_COPY +// Define this macro to enable copying the vector table +// at startup from ROM to RAM. It is also required to +// define the macro __VECTOR_TABLE_RAM_SPACE +// __VECTOR_TABLE_RAM_SPACE +// Define size of the RAM space for the vector table when +// it is copied from ROM to RAM +// __VECTOR_TABLE_ROM_ADDR +// Specify the vector table address in ROM +// __VECTOR_TABLE_RAM_ADDR +// Specify the vector table address in RAM when the the +// it is copied from ROM to RAM (__COPY_VECTOR_TABLE) +// +// See arm_arch.lsl for more available macros. +// +// Notes: +// In the STM32F2xx, 3 different boot modes can be selected +// - User Flash memory is selected as boot space +// - SystemMemory is selected as boot space +// - Embedded SRAM is selected as boot space +// +// This aliases the physical memory associated with each boot mode to Block +// 000 (0x00000000 boot memory). Even when aliased in the boot memory space, +// the related memory (Flash memory or SRAM) is still accessible at its +// original memory space. +// +//////////////////////////////////////////////////////////////////////////// + +#ifndef __NO_DEFAULT_AUTO_VECTORS +// Suppress the vectors as defined arm_arch.lsl, because we define our +// own vectors for CMIS +#define __CMSIS_VECTORS 1 +#define __NO_DEFAULT_AUTO_VECTORS 1 +#define __NR_OF_VECTORS 97 +#endif + +#ifndef __VECTOR_TABLE_ROM_ADDR +# define __VECTOR_TABLE_ROM_ADDR 0x08000000 +#endif + +#ifndef __VECTOR_TABLE_RAM_ADDR +# define __VECTOR_TABLE_RAM_ADDR 0x00000000 +#endif + + +#ifndef __STACK +# define __STACK 4k +#endif + +#ifndef __HEAP +# define __HEAP 2k +#endif + +#include + +// +// If no memory is defined yet use the following memory settings +// +#ifndef __MEMORY + +// Specify default size for Flash and SRAM +#ifndef __FLASH_SIZE +# define __FLASH_SIZE 1024k +#endif +#ifndef __SRAM_SIZE +# define __SRAM_SIZE 128k +#endif + +memory STM32F2xx_Flash +{ + mau = 8; + type = rom; + size = __FLASH_SIZE; + map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus); +} + +memory STM32F2xx_SRAM +{ + mau = 8; + type = ram; + size = __SRAM_SIZE; + map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus); +} + +#endif /* __MEMORY */ + + +// +// Define the vector table for CMSIS +// +#ifdef __CMSIS_VECTORS +section_setup ::linear +{ + // vector table with handler addresses + vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR, + template = ".text.handler_address", + template_symbol = "_lc_vector_handler", + vector_prefix = "_vector_", + fill = loop, + no_inline + ) + { + vector ( id = 0, fill = "_lc_ub_stack" ); // Top of Stack + vector ( id = 1, fill = "_START" ); // Reset Handler + vector ( id = 2, optional, fill = "NMI_Handler" ); // NMI Handler + vector ( id = 3, optional, fill = "HardFault_Handler" ); // Hard Fault Handler + vector ( id = 4, optional, fill = "MemManage_Handler" ); // MPU Fault Handler + vector ( id = 5, optional, fill = "BusFault_Handler" ); // Bus Fault Handler + vector ( id = 6, optional, fill = "UsageFault_Handler" ); // Usage Fault Handler + vector ( id = 11, optional, fill = "SVC_Handler" ); // SVCall Handler + vector ( id = 12, optional, fill = "DebugMon_Handler" ); // Debug Monitor Handler + vector ( id = 14, optional, fill = "PendSV_Handler" ); // PendSV Handler + vector ( id = 15, optional, fill = "SysTick_Handler" ); // SysTick Handler + + // External Interrupts : + vector ( id = 16, optional, fill = "WWDG_IRQHandler" ); // Window Watchdog + vector ( id = 17, optional, fill = "PVD_IRQHandler" ); // PVD through EXTI Line detect + vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" ); // Tamper amd TimeStanp through EXTI + vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" ); // RTC Wakeup through the EXTI line + vector ( id = 20, optional, fill = "FLASH_IRQHandler" ); // Flash global interrupt + vector ( id = 21, optional, fill = "RCC_IRQHandler" ); // RCC global interrupt + vector ( id = 22, optional, fill = "EXTI0_IRQHandler" ); // EXTI Line 0 interrupt + vector ( id = 23, optional, fill = "EXTI1_IRQHandler" ); // EXTI Line 1 interrupt + vector ( id = 24, optional, fill = "EXTI2_IRQHandler" ); // EXTI Line 2 interrupt + vector ( id = 25, optional, fill = "EXTI3_IRQHandler" ); // EXTI Line 3 interrupt + vector ( id = 26, optional, fill = "EXTI4_IRQHandler" ); // EXTI Line 4 interrupt + vector ( id = 27, optional, fill = "DMA1_Stream0_IRQHandler" ); // DMA1 Stream 0 interrupt + vector ( id = 28, optional, fill = "DMA1_Stream1_IRQHandler" ); // DMA1 Stream 1 interrupt + vector ( id = 29, optional, fill = "DMA1_Stream2_IRQHandler" ); // DMA1 Stream 2 interrupt + vector ( id = 30, optional, fill = "DMA1_Stream3_IRQHandler" ); // DMA1 Stream 3 interrupt + vector ( id = 31, optional, fill = "DMA1_Stream4_IRQHandler" ); // DMA1 Stream 4 interrupt + vector ( id = 32, optional, fill = "DMA1_Stream5_IRQHandler" ); // DMA1 Stream 5 interrupt + vector ( id = 33, optional, fill = "DMA1_Stream6_IRQHandler" ); // DMA1 Stream 6 interrupt + vector ( id = 34, optional, fill = "ADC_IRQHandler" ); // ADC_IRQHandler interrupts + vector ( id = 35, optional, fill = "CAN1_TX_IRQHandler" ); // CAN1 TX interrupts + vector ( id = 36, optional, fill = "CAN1_RX0_IRQHandler" ); // CAN1 RX0 interrupts + vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" ); // CAN1 RX1 interrupt + vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" ); // CAN1 SCE interrupt + vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" ); // EXTI Line 9..5 interrupts + vector ( id = 40, optional, fill = "TIM1_BRK_TIM9_IRQHandler" ); // TIM1 Break irq and TIM9 global interrupt + vector ( id = 41, optional, fill = "TIM1_UP_TIM10_IRQHandler" ); // TIM1 Update irq and TIM10 global interrupt + vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM11_IRQHandler" ); // TIM1 Trigger and Commutation irqs and TIM10 global irq + vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" ); // TIM1 Capture Compare + vector ( id = 44, optional, fill = "TIM2_IRQHandler" ); // TIM2 global interrupt + vector ( id = 45, optional, fill = "TIM3_IRQHandler" ); // TIM3 global interrupt + vector ( id = 46, optional, fill = "TIM4_IRQHandler" ); // TIM4 global interrupt + vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" ); // I2C1 Event + vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" ); // I2C1 Error + vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" ); // I2C2 Event + vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" ); // I2C2 Error + vector ( id = 51, optional, fill = "SPI1_IRQHandler" ); // SPI1 global interrupt + vector ( id = 52, optional, fill = "SPI2_IRQHandler" ); // SPI2 global interrupt + vector ( id = 53, optional, fill = "USART1_IRQHandler" ); // USART1 global interrupt + vector ( id = 54, optional, fill = "USART2_IRQHandler" ); // USART2 global interrupt + vector ( id = 55, optional, fill = "USART3_IRQHandler" ); // USART3 global interrupt + vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" ); // EXTI Line 15..10 interrupts + vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" ); // RTC Alarm through EXTI Line + vector ( id = 58, optional, fill = "OTG_FS_WKUP_IRQHandler" ); // USB On-The-Go FS Wakeup throught EXTI + vector ( id = 59, optional, fill = "TIM8_BRK_TIM12_IRQHandler" ); // TIM8 Break irq and TIM12 global irq + vector ( id = 60, optional, fill = "TIM8_UP_TIM13_IRQHandler" ); // TIM8 Update irq and TIM13 global irq + vector ( id = 61, optional, fill = "TIM8_TRG_COM_TIM14_IRQHandler" ); // TIM8 trigger and Comm. irqs and TIM14 global irq + vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" ); // TIM8 Capture Compare irq + vector ( id = 63, optional, fill = "DMA1_Stream7_IRQHandler" ); // DMA1 Stream7 global interrupt + vector ( id = 64, optional, fill = "FSMC_IRQHandler" ); // FSMC global interrupt + vector ( id = 65, optional, fill = "SDIO_IRQHandler" ); // SDIO global interrupt + vector ( id = 66, optional, fill = "TIM5_IRQHandler" ); // TIM5 global interrupt + vector ( id = 67, optional, fill = "SPI3_IRQHandler" ); // SPI3 global interrupt + vector ( id = 68, optional, fill = "UART4_IRQHandler" ); // UART4 global interrupt + vector ( id = 69, optional, fill = "UART5_IRQHandler" ); // UART5 global interrupt + vector ( id = 70, optional, fill = "TIM6_DAC_IRQHandler" ); // TIM6 glbl irq, DAC1 and DAC2 underrun err irqs + vector ( id = 71, optional, fill = "TIM7_IRQHandler" ); // TIM7 global interrupt + vector ( id = 72, optional, fill = "DMA2_Stream0_IRQHandler" ); // DMA2 Stream0 global interrupt + vector ( id = 73, optional, fill = "DMA2_Stream1_IRQHandler" ); // DMA2 Stream1 global interrupt + vector ( id = 74, optional, fill = "DMA2_Stream2_IRQHandler" ); // DMA2 Stream2 global interrupt + vector ( id = 75, optional, fill = "DMA2_Stream3_IRQHandler" ); // DMA2 Stream3 global interrupt + vector ( id = 76, optional, fill = "DMA2_Stream4_IRQHandler" ); // DMA2 Stream4 global interrupt + vector ( id = 77, optional, fill = "ETH_IRQHandler" ); // Ethernet global interrupt + vector ( id = 78, optional, fill = "ETH_WKUP_IRQHandler" ); // Ethernet Wakeup through EXTI line irq + vector ( id = 79, optional, fill = "CAN2_TX_IRQHandler" ); // CAN2 TX interrupts + vector ( id = 80, optional, fill = "CAN2_RX0_IRQHandler" ); // CAN2 RX0 interrupts + vector ( id = 81, optional, fill = "CAN2_RX1_IRQHandler" ); // CAN2 RX1 interrupt + vector ( id = 82, optional, fill = "CAN2_SCE_IRQHandler" ); // CAN2 SCE interrupt + vector ( id = 83, optional, fill = "OTG_FS_IRQHandler" ); // USB On The Go FS global interrupt + vector ( id = 84, optional, fill = "DMA2_Stream5_IRQHandler" ); // DMA2 Stream5 global interrupt + vector ( id = 85, optional, fill = "DMA2_Stream6_IRQHandler" ); // DMA2 Stream6 global interrupt + vector ( id = 86, optional, fill = "DMA2_Stream7_IRQHandler" ); // DMA2 Stream7 global interrupt + vector ( id = 87, optional, fill = "USART6_IRQHandler" ); // USART6 global interrupt + vector ( id = 88, optional, fill = "I2C3_EV_IRQHandler" ); // I2C3 event interrupt + vector ( id = 89, optional, fill = "I2C3_ER_IRQHandler" ); // I2C3 error interrupt + vector ( id = 90, optional, fill = "OTG_HS_EP1_OUT_IRQHandler" ); // USB On The Go HS End Point 1 OUT global irq + vector ( id = 91, optional, fill = "OTG_HS_EP1_IN_IRQHandler" ); // USB On The Go HS End Point 1 In global irq + vector ( id = 92, optional, fill = "OTG_HS_WKUP_IRQHandler" ); // USB On The Go HS Wakeup through EXTI irq + vector ( id = 93, optional, fill = "OTG_HS_IRQHandler" ); // USB On The Go HS global interrupt + vector ( id = 94, optional, fill = "DCMI_IRQHandler" ); // DCMI global interrupt + vector ( id = 95, optional, fill = "CRYP_IRQHandler" ); // CRYP crypto global interrupt + vector ( id = 96, optional, fill = "HASH_RNG_IRQHandler" ); // Hash and Rng global interrupt + } +} +#endif /* __CMSIS_VECTORS */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/readme.txt new file mode 100644 index 000000000..f0c3d5c7a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TASKING/readme.txt @@ -0,0 +1,61 @@ +/** + @page tasking TASKING Project Template for STM32F2xx devices + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This sub-directory contains all the user-modifiable files needed to + * create a new project linked with the STM32F2xx Standard Peripherals + * Library and working with TASKING VX-toolset for ARM Cortex-M. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + + @par Directory contents + + - .cproject/.project: A pre-configured project file with the provided library + structure that produces an executable image with TASKING. + +- TASKING : This folder contains + + - stm32f2xx.lsl : This file is TASKING linker script that contains the + STM32F2xx vector table and used to place program code (readonly) + in internal FLASH and data (readwrite, Stack and Heap)in + internal SRAM. + You can customize this file to your need. + + + @par How to use it ? + + - Open TASKING toolchain. + - Click on File->Import, select General->'Existing Projects into Workspace' + and then click "Next". + - Browse to TASKING workspace directory and select the project: + - STM322xG-EVAL: to configure the project for STM32F2xx devices. + - Rebuild all project files: Select the project in the "Project explorer" + window then click on Project->build project menu. + - Run program: Select the project in the "Project explorer" window then click + Run->Debug (F11) + + @note The needed define symbols for this config are already declared in the + preprocessor section: USE_STM322xG_EVAL, STM32F2XX, USE_STDPERIPH_DRIVER + + + *

© COPYRIGHT STMicroelectronics

+ */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/.cproject b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/.cproject new file mode 100644 index 000000000..d6e8081fa --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/.cproject @@ -0,0 +1,441 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/.project b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/.project new file mode 100644 index 000000000..d1c88377e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/.project @@ -0,0 +1,295 @@ + + + STM322xG_EVAL + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?children? + ?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\|| + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/STM322xG_EVAL/Debug} + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + CMSIS + 2 + PARENT-4-PROJECT_LOC/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/.metadata/Link + + + STM322xG_EVAL + 2 + virtual:/virtual + + + StdPeriph_Driver + 2 + PARENT-4-PROJECT_LOC/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/.metadata/Link + + + TrueSTUDIO + 2 + PARENT-4-PROJECT_LOC/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/.metadata/Link + + + User + 2 + PARENT-4-PROJECT_LOC/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/.metadata/Link + + + CMSIS/system_stm32f2xx.c + 1 + PARENT-2-PROJECT_LOC/system_stm32f2xx.c + + + STM322xG_EVAL/stm322xg_eval.c + 1 + PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval.c + + + STM322xG_EVAL/stm322xg_eval_fsmc_sram.c + 1 + PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_sram.c + + + STM322xG_EVAL/stm322xg_eval_ioe.c + 1 + PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_ioe.c + + + STM322xG_EVAL/stm322xg_eval_lcd.c + 1 + PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_lcd.c + + + StdPeriph_Driver/STM32F2xx_adc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_adc.c + + + StdPeriph_Driver/STM32F2xx_can.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_can.c + + + StdPeriph_Driver/STM32F2xx_crc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_crc.c + + + StdPeriph_Driver/STM32F2xx_dac.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_dac.c + + + StdPeriph_Driver/STM32F2xx_dbgmcu.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_dbgmcu.c + + + StdPeriph_Driver/STM32F2xx_dma.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_dma.c + + + StdPeriph_Driver/STM32F2xx_exti.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_exti.c + + + StdPeriph_Driver/STM32F2xx_flash.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_flash.c + + + StdPeriph_Driver/STM32F2xx_fsmc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_fsmc.c + + + StdPeriph_Driver/STM32F2xx_gpio.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_gpio.c + + + StdPeriph_Driver/STM32F2xx_i2c.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_i2c.c + + + StdPeriph_Driver/STM32F2xx_iwdg.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_iwdg.c + + + StdPeriph_Driver/STM32F2xx_pwr.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_pwr.c + + + StdPeriph_Driver/STM32F2xx_rcc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_rcc.c + + + StdPeriph_Driver/STM32F2xx_rtc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_rtc.c + + + StdPeriph_Driver/STM32F2xx_sdio.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_sdio.c + + + StdPeriph_Driver/STM32F2xx_spi.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_spi.c + + + StdPeriph_Driver/STM32F2xx_tim.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_tim.c + + + StdPeriph_Driver/STM32F2xx_usart.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_usart.c + + + StdPeriph_Driver/STM32F2xx_wwdg.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/STM32F2xx_wwdg.c + + + StdPeriph_Driver/misc.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c + + + StdPeriph_Driver/stm32f2xx_cryp.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c + + + StdPeriph_Driver/stm32f2xx_cryp_aes.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c + + + StdPeriph_Driver/stm32f2xx_cryp_des.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_des.c + + + StdPeriph_Driver/stm32f2xx_cryp_tdes.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_tdes.c + + + StdPeriph_Driver/stm32f2xx_dcmi.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c + + + StdPeriph_Driver/stm32f2xx_hash.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c + + + StdPeriph_Driver/stm32f2xx_hash_md5.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c + + + StdPeriph_Driver/stm32f2xx_hash_sha1.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_sha1.c + + + StdPeriph_Driver/stm32f2xx_rng.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c + + + StdPeriph_Driver/stm32f2xx_syscfg.c + 1 + PARENT-4-PROJECT_LOC/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c + + + TrueSTUDIO/startup_stm32f2xx.s + 1 + PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/TrueSTUDIO/startup_stm32f2xx.s + + + User/STM32F2xx_it.c + 1 + PARENT-4-PROJECT_LOC/Project/STM32F2xx_StdPeriph_Template/STM32F2xx_it.c + + + User/main.c + 1 + PARENT-4-PROJECT_LOC/Project/STM32F2xx_StdPeriph_Template/main.c + + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs new file mode 100644 index 000000000..b0b3d39dd --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs @@ -0,0 +1,12 @@ +#Thu Nov 17 16:06:11 GMT+01:00 2011 +BOARD=STM322xG-EVAL +CODE_LOCATION=FLASH +ENDIAN=Little-endian +MCU=STM32F207IG +MCU_VENDOR=STMicroelectronics +MODEL=Lite +PROBE=ST-LINK +PROJECT_FORMAT_VERSION=2 +TARGET=STMicroelectronics\u00AE STM32\u2122 +VERSION=2.2.0 +eclipse.preferences.version=1 diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/stm32_flash.ld b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/stm32_flash.ld new file mode 100644 index 000000000..9e297a396 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/STM322xG_EVAL/stm32_flash.ld @@ -0,0 +1,171 @@ +/* +***************************************************************************** +** +** File : stm32_flash.ld +** +** Abstract : Linker script for STM32F207IG Device with +** 1MByte FLASH, 128KByte SRAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the Atollic TrueSTUDIO(R) toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of 128K SRAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x200; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/note.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/note.txt new file mode 100644 index 000000000..851faae5c --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/note.txt @@ -0,0 +1,66 @@ +/** + @page note Note for TrueSTUDIO + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** + * @file note.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the needed step to use "printf" with TrueSTUDIO + * toolchain. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + +The C runtime library include many functions, including some that typically +handle I/O. The I/O related runtime functions include printf(), fopen(), fclose(), +and many others. + +It is common to redirect the I/O from these functions to the actual embedded +platform, such as redirecting printf() output to an LCD display or a serial cable, +or to redirect file operations like fopen() and fclose() to some Flash file +system middleware. + +The free Lite version of TrueSTUDIO do not support I/O redirection, and instead +have do-nothing stubs compiled into the C runtime library. + +To support printf() redirection in the professional version, you should do the following: + - Open TrueSTUDIO professional and load your project. + - In the Project explorer, Right click on the project and select New->Other... + - Expand System calls + - Select Minimal System Calls Implementation and click next. + - Click on Finish and verify that "syscalls.c" is added to your project. + - Add the following code in the _write() function in "syscalls.c". + + @code + /*****************************************/ + int Index; + + for (Index = 0; Index < len; Index++) + { + __io_putchar( *ptr++ ); + } + + return len; + /*****************************************/ + @endcode + + - Finally, Rebuild your project. + + + *

© COPYRIGHT STMicroelectronics

+ */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/readme.txt b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/readme.txt new file mode 100644 index 000000000..8aa6a7ef6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/readme.txt @@ -0,0 +1,64 @@ +/** + @page truestudio TrueSTUDIO Project Template for STM32F2xx devices + + @verbatim + ******************** (C) COPYRIGHT 2012 STMicroelectronics ******************* + * @file readme.txt + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This sub-directory contains all the user-modifiable files needed to + * create a new project linked with the STM32F2xx Standard Peripherals + * Library and working with TrueSTUDIO software toolchain. + ****************************************************************************** + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + @endverbatim + + @par Directory contents + + - .cproject/.project: A pre-configured project file with the provided library + structure that produces an executable image with TrueSTUDIO. + + - stm32_flash.ld: This file is the TrueSTUDIO linker script used to + place program code (readonly) in internal FLASH and + data (readwrite, Stack and Heap)in internal SRAM. + You can customize this file to your need. + + - stm32f2xx_flash_extsram.ld: This file is the TrueSTUDIO linker script used to + place program code (readonly) in internal FLASH and + data (readwrite, Stack and Heap)in external SRAM. + You can customize this file to your need. + + @par How to use it ? + + - Open the TrueSTUDIO toolchain. + - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace + directory. + - Click on File->Import, select General->'Existing Projects into Workspace' + and then click "Next". + - Browse to the TrueSTUDIO workspace directory and select the project: + - STM322xG_EVAL: to configure the project for STM32F2xx devices. + - Rebuild all project files: Select the project in the "Project explorer" + window then click on Project->build project menu. + - Run program: Select the project in the "Project explorer" window then click + Run->Debug (F11) + + @note The needed define symbols for this config are already declared in the + preprocessor section: USE_STM322xG_EVAL, STM32F2XX, USE_STDPERIPH_DRIVER + + + *

© COPYRIGHT STMicroelectronics

+ */ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/stm32f2xx_flash_extsram.ld b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/stm32f2xx_flash_extsram.ld new file mode 100644 index 000000000..636f721c1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/TrueSTUDIO/stm32f2xx_flash_extsram.ld @@ -0,0 +1,171 @@ +/* +***************************************************************************** +** +** File : stm32_flash.ld +** +** Abstract : Linker script for STM32F207IG Device with +** 1MByte FLASH, 128KByte SRAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the Atollic TrueSTUDIO(R) toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x64100000; /* end of 1M SRAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x200; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1M + RAM (xrw) : ORIGIN = 0x64000000, LENGTH = 1M + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/main.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/main.c new file mode 100644 index 000000000..44b8bfc38 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/main.c @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file Project/STM32F2xx_StdPeriph_Template/main.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/** @addtogroup Template_Project + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define MESSAGE1 " STM32F2xx " +#define MESSAGE2 " Device running on " +#define MESSAGE3 " STM322xG-EVAL " + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static __IO uint32_t TimingDelay; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + RCC_ClocksTypeDef RCC_Clocks; + + /*!< At this stage the microcontroller clock setting is already configured, + this is done through SystemInit() function which is called from startup + file (startup_stm32f2xx.s) before to branch to application main. + To reconfigure the default setting of SystemInit() function, refer to + system_stm32f2xx.c file + */ + + /* SysTick end of count event each 10ms */ + RCC_GetClocksFreq(&RCC_Clocks); + SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); + + /* Initialize LEDs and LCD available on STM322xG-EVAL board *****************/ + STM_EVAL_LEDInit(LED1); + STM_EVAL_LEDInit(LED2); + STM_EVAL_LEDInit(LED3); + STM_EVAL_LEDInit(LED4); + + /* Initialize the LCD */ + STM322xG_LCD_Init(); + + /* Display message on STM322xG-EVAL LCD *************************************/ + /* Clear the LCD */ + LCD_Clear(White); + + /* Set the LCD Back Color */ + LCD_SetBackColor(Blue); + /* Set the LCD Text Color */ + LCD_SetTextColor(White); + LCD_DisplayStringLine(LINE(0), (uint8_t *)MESSAGE1); + LCD_DisplayStringLine(LINE(1), (uint8_t *)MESSAGE2); + LCD_DisplayStringLine(LINE(2), (uint8_t *)MESSAGE3); + + /* Turn on LEDs available on STM322xG-EVAL **********************************/ + STM_EVAL_LEDOn(LED1); + STM_EVAL_LEDOn(LED2); + STM_EVAL_LEDOn(LED3); + STM_EVAL_LEDOn(LED4); + + /* Add your application code here + */ + + /* Infinite loop */ + while (1) + { + /* Toggle LD4 */ + STM_EVAL_LEDToggle(LED4); + + /* Insert 50 ms delay */ + Delay(5); + + /* Toggle LD2 */ + STM_EVAL_LEDToggle(LED2); + + /* Insert 50 ms delay */ + Delay(5); + } +} + +/** + * @brief Inserts a delay time. + * @param nTime: specifies the delay time length, in 10 ms. + * @retval None + */ +void Delay(__IO uint32_t nTime) +{ + TimingDelay = nTime; + + while(TimingDelay != 0); +} + +/** + * @brief Decrements the TimingDelay variable. + * @param None + * @retval None + */ +void TimingDelay_Decrement(void) +{ + if (TimingDelay != 0x00) + { + TimingDelay--; + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/main.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/main.h new file mode 100644 index 000000000..0438a1aaa --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/main.h @@ -0,0 +1,47 @@ +/** + ****************************************************************************** + * @file Project/STM32F2xx_StdPeriph_Template/main.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Header for main.c module + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm322xg_eval.h" +#include "stm322xg_eval_lcd.h" +#include + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TimingDelay_Decrement(void); +void Delay(__IO uint32_t nTime); + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/stm32f2xx_conf.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/stm32f2xx_conf.h new file mode 100644 index 000000000..837d2a778 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/stm32f2xx_conf.h @@ -0,0 +1,94 @@ +/** + ****************************************************************************** + * @file Project/STM32F2xx_StdPeriph_Template/stm32f2xx_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_CONF_H +#define __STM32F2xx_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +#include "stm32f2xx_adc.h" +#include "stm32f2xx_can.h" +#include "stm32f2xx_crc.h" +#include "stm32f2xx_cryp.h" +#include "stm32f2xx_dac.h" +#include "stm32f2xx_dbgmcu.h" +#include "stm32f2xx_dcmi.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_exti.h" +#include "stm32f2xx_flash.h" +#include "stm32f2xx_fsmc.h" +#include "stm32f2xx_hash.h" +#include "stm32f2xx_gpio.h" +#include "stm32f2xx_i2c.h" +#include "stm32f2xx_iwdg.h" +#include "stm32f2xx_pwr.h" +#include "stm32f2xx_rcc.h" +#include "stm32f2xx_rng.h" +#include "stm32f2xx_rtc.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_spi.h" +#include "stm32f2xx_syscfg.h" +#include "stm32f2xx_tim.h" +#include "stm32f2xx_usart.h" +#include "stm32f2xx_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* If an external clock source is used, then the value of the following define + should be set to the value of the external clock source, else, if no external + clock is used, keep this define commented */ +/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F2xx_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.c new file mode 100644 index 000000000..e34dd794a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.c @@ -0,0 +1,168 @@ +/** + ****************************************************************************** + * @file Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx_it.h" +#include "main.h" + +/** @addtogroup Template_Project + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + TimingDelay_Decrement(); +} + +/******************************************************************************/ +/* STM32F2xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f2xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.h new file mode 100644 index 000000000..ab94b737a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file Project/STM32F2xx_StdPeriph_Template/stm32f2xx_it.h + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2xx_IT_H +#define __STM32F2xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/system_stm32f2xx.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/system_stm32f2xx.c new file mode 100644 index 000000000..482a20d13 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Project/STM32F2xx_StdPeriph_Template/system_stm32f2xx.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.1.0 + * @date 13-April-2012 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Release_Notes.html b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Release_Notes.html new file mode 100644 index 000000000..93880a9e0 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Release_Notes.html @@ -0,0 +1,570 @@ + + + + + +Release Notes for STM32F2xx Standard Peripherals Library + + + + + +
+


+

+
+ + + + + + +
+ + + + + + +
+

Release +Notes for STM32F2xx Standard Peripherals Library

+

Copyright 2012 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F2xx Standard Peripheral +Library update History
    2. +
  2. License
    3. +
+

STM32F2xx Standard +Peripherals Library update History

V1.1.0 / 13-April-2012

Main +Changes

+
  • All source files: license disclaimer text update and add link to the License file on ST Internet.
  • STM32F2xx HAL and BSP components update (for more details refer to each component's release notes):
    • CMSIS drivers: update directory structure to be compliant with CMSIS V2.1, full API compatibility maintained vs. V1.0.0
    • Standard Peripherals Drivers: miscellaneous bug fix and enhancement
    • STM322xG_EVAL board drivers: update drivers architecture and folder organization, full API compatibility maintained vs. V4.6.2 (and V4.6.1)
  • Template projects: 
    • Update to be in line with changes made on latest version of the STM32F2xx CMSIS and STM322xG_EVAL drivers
    • Update to use the latest version of the supported toolchains
  • All +examples: 
    • Update to be in line with latest version of STM322xG_EVAL board drivers
    • Miscellaneous bug fix and enhancement
    • +For more details refer to the example's release notes

+

Contents

+

Development Toolchains and Compilers

+
  • IAR Embedded Workbench for ARM (EWARM) toolchain V6.30.7 + J-Link
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V4.23 + ULINK
  • Raisonance IDE RIDE7 (RIDE) toolchain (RIDE7 IDE:7.36, RKitARM for RIDE7:1.38) + Rlink Pro
  • Atollic TrueSTUDIO toolchain V3.0.0 + ST-LINK
  • TASKING VX-toolset for ARM Cortex-M V4.2r1 + ST-LINK

V1.0.0 / 18-April-2011

Main +Changes

+
  • First official release for STM32F2xx devices

+

Contents

+

Development Toolchains and Compilers

+
  • IAR Embedded Workbench for ARM (EWARM) toolchain V6.10.5
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V4.20
  • Raisonance IDE RIDE7 (RIDE) toolchain (RIDE7 IDE:7.30.10, RKitARM for RIDE7:1.31.10)
  • Atollic TrueSTUDIO STM32 (TrueSTUDIO) toolchain V2.0.1
  • TASKING VX-toolset for ARM Cortex-M V3.2r1

 + +

License

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License. + +
+
+
+

For + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32
+

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/Release_Notes.html b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/Release_Notes.html new file mode 100644 index 000000000..95520c402 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/Release_Notes.html @@ -0,0 +1,264 @@ + + + + + + + + + + + + + + + + Release Notes for STM32 Evaluation Board Common Drivers + + + + + + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
+

Back to Release page

+
+

Release +Notes for STM32 Evaluation Board Common Drivers

+

Copyright +2012 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32 Evaluation Board Common Drivers +update History
    2. +
  2. License
    3. +
+ + +

STM32 Evaluation Board Common Drivers update History

V5.0.2 / 05-March-2012

+

Main +Changes

+ +
  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V5.0.1 / 28-December-2011

Main +Changes

+
  • All source files: update disclaimer to add reference to the new license agreement

V5.0.0 / 30-September-2011

+

Main +Changes

+ +
  • Update STM32 Evaluation Board Drivers architecture and folder organization, full API compatibility maintained vs. V4.6.2
    • All the HW drivers required for each board are provided within this board folder. The concerned drivers are:
      • stm32_eval_i2c_ee.c\.h: I2C M24CXX EEPROM memory driver
      • stm32_eval_i2c_tsensor.c\.h: I2C LM75 temperature sensor driver
      • stm32_eval_spi_flash.c\.h: SPI M25Pxxx FLASH memory driver
      • stm32_eval_sdio_sd.c\.h: SDIO SD Card memory driver
      • stm32_eval_spi_sd.c\.h: SPI SD Card memory driver 
      • These drivers were moved from \Common to \STM32XXX_EVAL folder(s)
    • \Common folder contains only drivers for the fonts and log module used by the LCD driver
    • stm32_eval.c\.h files removed, as consequence you need to perform the following update on your project configuration  (based on EVAL drivers V4.6.2):
      • In the project files, add your EVAL board driver source file (ex. "stm3210c_eval.c") instead of "stm32_eval.c"
      • Include your EVAL board driver header file (ex. #include "stm3210c_eval.h") instead of #include "stm32_eval.h"
      • If +you are using the EVAL board's LCD, you need to add the include of +the LCD header file (ex: #include "stm3210c_eval_lcd.h")
        • If +you are using the LCD log module, after copying it to the application +folder you have to edit it and update the name of the LCD header file. For more details, refer to the lcd_log_conf_template.h driver description.

V4.6.2 / 22-July-2011

+

Main +Changes

+ +
  • STM3210C_EVAL
    • stm3210c_eval_lcd.c: update to support new LCD AM240320D5TOQW01H (controller ILI9325)
  • STM322xG-EVAL
    • stm322xg_eval.h: fix value of the SDIO clock divider (SDIO_TRANSFER_CLK_DIV constant) to 2 instead of 0
    • stm322xg_eval_lcd.c: increase FSMC AddressSetupTime value from 1 to 3 to be compliant with some LCD access timing
    • stm322xg_eval_audio_codec.c: update Codec_CtrlInterface_Init() and Codec_GPIO_Init() functions to not reconfigure the I2C peripheral if it's already enabled and configured (to +avoid configuring the I2C twice when using both Audio codec and IO +Expander drivers in the same application).

V4.6.1 / 18-April-2011

+

Main +Changes

+ +
  • Update some STM322xG_EVAL drivers (no change on the API) to fix warnings with TASKING C compiler.
  • Change the Release Notes name to STM32 Evaluation Board Drivers
  • stm322xg_eval.c
    • SD_LowLevel_Init(): change SDIO pins speed configuration to "GPIO_Speed_25MHz"

V4.6.0 / 11-March-2011

+

Main +Changes

+ +
  • Official version supporting STM322xG_EVAL evaluation board RevB (for STM32F2xx devices).
  • Common
    • Add +new LCD log utility drivers: The LCD Log module allows to automatically +set a header and footer on any application using the LCD display and +allows to dump user, debug and error messages by using the following +macros: LCD_ErrLog(),    LCD_UsrLog() and LCD_DbgLog().
Note: the STM322xG_EVAL board RevA was wrongly named STM3220F_EVAL

V4.5.0 / 07-March-2011

+

Main +Changes

+ +
  • stm32_eval_sdio_sd.c\.h: driver improvement
    • SD Clock increased to 24MHz to improve the data transfer performance.
    • Add +new functions to check the SDIO peripheral and SD Card status at any +time: SD_WaitReadOperation(), SD_WaitWriteOperation(). The +software sequence is little bit changed but without any impact on +driver API. For more details, refer to the stm32_eval_sdio_sd.c +driver description.
    • Add +new structure containing the SD Status register parameters. This +structure is called by the +         + SD_SendSDStatus() function.
    • Transfers mode updated
      • Read/Write Block using Polling and DMA modes
      • Read/Write Multi Blocks using DMA mode only
      • Interrupt mode removed
    • Data transfer functions are managing only fixed Block size (512-byte) 
  • STM32100B-EVAL
    • stm32100b_eval_cec.c: fix some strict ANSI-C errors
  • STM32100E-EVAL
    • stm32100e_eval_cec.c: fix some strict ANSI-C errors
+

V4.4.0 / 31-December-2010

+

Main +Changes

+ +
  • Add new directory for STM32L152-EVAL board containing the following files:
    • stm32l152_eval.h/.c, stm32l152_eval_lcd.h/.c, stm32l152_eval_glass_lcd.h/.c, stm32l152_eval_i2c_ee.h/.c
  • Add support for the STM32100E-EVAL Rev B: SPI FLASH CS pin "sFLASH_CS_PIN" changed from PB.02 to PE.06.
  • stm32100e_eval_lcd.h/.c: Add support for "LCD_ILI9325" LCD controller.
  • stm32100e_eval_fsmc_onenand.h/.c driver updated to correct asynchronous and synchronous read operations procedures.
    +
+ +

4.3.0 +- 10/15/2010

+
  1. General
+ +
  • I2C EEPROM, Temperature Sensor and IOE Expander drivers updated to use the DMA for read/write transfer and add more robustness
  • SD Card (SDIO) driver updated to add more robustness
  • SPI Flash and SD Card (SPI) drivers: SPI MISO pin configuration changed to Input Floating 
+ + + +
  1. Utilities
+ + + + + +
  • Add new directory for STM32100E-EVAL board containing the following files:
    • stm32100e_eval.h/.c, +stm32100e_eval_lcd.h/.c, stm32100e_eval_cec.h/.c, +stm32100e_eval_fsmc_onenand.h/.c, stm32100e_eval_fsmc_sram.h/.c, +stm32100e_eval_ioe.h/.c
      +
  • Common
    • stm32_eval_sdio_sd.c: +Update the DMA End of Transfer Check loop inside the SD_ReadBlock(), +SD_WriteBlock(), SD_ReadMultiBlocks() and SD_Write MultiBlocks().
    • stm32_eval_i2c_ee.c/.h
      +
      • Enhanced sEE_WaitEepromStandbyState() function for more robustness.
      • Enhanced Read and Write operations to manage I2C limitations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
      • Add +critical sections user callbacks allowing to disable then enable +interrupts when I2C operation require to be not interrupted.
    • stm32_eval_i2c_tsensor.c/.h
      +
      • Enhanced I2C communication functions by using DMA for registers Read and Write operations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
  • STM32100B_EVAL
    • stm32100b_eval.h: Add LM75 DMA defines.
    • stm32100b_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
  • STM3210B_EVAL
    • stm3210b_eval.h: Add LM75 DMA defines.
    • stm3210b_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
  • STM3210C_EVAL
    • stm3210c_eval.h: Add EEPROM driver Timeout define.
    • stm3210c_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
    • stm3210c_eval_i2c_ioe.c
      • Enhanced I2C communication functions by using DMA for registers Read and Write operations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
      • change IOE_I2C_SPEED from "400000" to "300000".
  • STM3210E_EVAL
    • stm3210e_eval.c: change "void SD_WaitForDMAEndOfTransfer(void)" to "uint32_t SD_DMAEndOfTransferStatus(void)".
    • stm3210e_eval.h: Add LM75 DMA defines.
    • stm3210e_eval_fsmc_nand.h: remove "NAND_CMD_AREA_TRUE1" define.
    • stm3210e_eval_fsmc_nand.c: Update FSMC timing in NAND_Init() function to be aligned with AN2784 application note.
    • stm3210e_eval_fsmc_nor.c
      • NOR_Init() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure 
    • stm3210e_eval_fsmc_sram.c
      +
      • Update FSMC timing in SRAM_Init() function to be aligned with AN2784 application note.
        +
      • SRAM_Init() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure 
    • stm3210e_eval_lcd.c
      • LCD_FSMCConfig() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure 
+ + +

4.2.0 +- 04/16/2010

+
  1. General
+ +
  • I2C EEPROM driver +update to use the DMA to +perform data transfer to/from EEPROM memory.
+ +
  1. Utilities
+
  • STM32_EVAL
+
    • stm32_eval_i2c_ee.c: +updated to use the DMA to perform data transfer to/from +EEPROM memory. For more details, refer to the description provided +within this file.
    • stm3210c_eval.c: add low level +functions to configure the DMA (needed for I2C EEPROM driver)
      +
    • stm3210c_eval_ioe.c: add a delay +in IOE_TS_GetState() function to wait till the end of ADC +conversion
    • stm3210e_eval_fsmc_nor.c: add PD6 pin configuration in +NOR_Init() function
    • stm3210b_eval_lcd.c: remove the +second ";" from "static void PutPixel(int16_t x, int16_t y);;" 
+

4.1.0 +- 03/01/2010

+
  1. General
+
  • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices.
  • Add support for the +STMicroelectronics STM32100B-EVAL evaluation board.
+
  1. Utilities
+
  • STM32_EVAL
+
  • Add new directory +"Common" containing a common drivers for all STM32 evaluation boards: +fonts.h/.c, stm32_eval_i2c_ee.h/.c, stm32_eval_spi_flash.h/.c, + stm32_eval_i2c_tsensor.h/.c, + stm32_eval_spi_sd.h/.c +and stm32_eval_sdio_sd.h/.c
  • Add new driver for the +STM32100B-EVAL managing Leds, push button and COM ports.
  • New HDMI CEC High level +driver.
    +
  • For all LCD drivers new fonts has +been added.
  • New FSMC memories +drivers for STM3210E-EVAL board: stm3210e_eval_fsmc_sram.h/.c, stm3210e_eval_fsmc_nor.h/.c +and stm3210e_eval_fsmc_nand.h/.c.

License

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License. + +
+
+

For +complete documentation on STM32 Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ + \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/fonts.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/fonts.c new file mode 100644 index 000000000..66b6e4dc6 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/fonts.c @@ -0,0 +1,1003 @@ +/** + ****************************************************************************** + * @file fonts.c + * @author MCD Application Team + * @version V5.0.2 + * @date 05-March-2012 + * @brief This file provides text fonts for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "fonts.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file includes the Fonts driver of STM32xx-EVAL boards. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Variables + * @{ + */ +const uint16_t ASCII16x24_Table [] = { +/** + * @brief Space ' ' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '!' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '"' + */ + 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '#' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60, + 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318, + 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000, +/** + * @brief '$' + */ + 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C, + 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C, + 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '%' + */ + 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611, + 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460, + 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000, +/** + * @brief '&' + */ + 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0, + 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06, + 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '(' + */ + 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060, + 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000, +/** + * @brief ')' + */ + 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000, +/** + * @brief '*' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '+' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ',' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, +/** + * @brief '-' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '.' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '/' + */ + 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300, + 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0, + 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '0' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C, + 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '1' + */ + 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '2' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '3' + */ + 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600, + 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '4' + */ + 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60, + 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00, + 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '5' + */ + 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC, + 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '6' + */ + 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC, + 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '7' + */ + 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380, + 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '8' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638, + 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38, + 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '9' + */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C, + 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C, + 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ':' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ';' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000, +/** + * @brief '<' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0, + 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '=' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '>' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0, + 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '?' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00, + 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '@' + */ + 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411, + 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004, + 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'A' + */ + 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60, + 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C, + 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'B' + */ + 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C, + 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C, + 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'C' + */ + 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006, + 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C, + 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'D' + */ + 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006, + 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06, + 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'E' + */ + 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'F' + */ + 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'G' + */ + 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003, + 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C, + 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'H' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'I' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'J' + */ + 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738, + 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'K' + */ + 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6, + 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'L' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'M' + */ + 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836, + 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6, + 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'N' + */ + 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC, + 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C, + 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'O' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'P' + */ + 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Q' + */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C, + 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'R' + */ + 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806, + 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'S' + */ + 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C, + 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C, + 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'T' + */ + 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'U' + */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'V' + */ + 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C, + 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'W' + */ + 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366, + 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C, + 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'X' + */ + 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0, + 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C, + 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Y' + */ + 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660, + 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'Z' + */ + 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600, + 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006, + 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '[' + */ + 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '\' + */ + 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0, + 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ']' + */ + 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000, +/** + * @brief '^' + */ + 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630, + 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '_' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief ''' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'a' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8, + 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C, + 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'b' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'c' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0, + 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30, + 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'd' + */ + 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'e' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30, + 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'f' + */ + 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'g' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8, + 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18, + 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000, +/** + * @brief 'h' + */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'i' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'j' + */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000, +/** + * @brief 'k' + */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C, + 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C, + 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'l' + */ + 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'm' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF, + 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, + 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'n' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'o' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30, + 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'p' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000, +/** + * @brief 'q' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000, +/** + * @brief 'r' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0, + 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 's' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0, + 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 't' + */ + 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'u' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818, + 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38, + 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'v' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18, + 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'w' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1, + 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C, + 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'x' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38, + 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30, + 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief 'y' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830, + 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380, + 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000, +/** + * @brief 'z' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, +/** + * @brief '{' + */ + 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000, +/** + * @brief '|' + */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, +/** + * @brief '}' + */ + 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000, +/** + * @brief '~' + */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}; + +const uint16_t ASCII12x12_Table [] = { + 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x2000,0x0000,0x0000, + 0x0000,0x5000,0x5000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0900,0x0900,0x1200,0x7f00,0x1200,0x7f00,0x1200,0x2400,0x2400,0x0000,0x0000, + 0x1000,0x3800,0x5400,0x5000,0x5000,0x3800,0x1400,0x5400,0x5400,0x3800,0x1000,0x0000, + 0x0000,0x3080,0x4900,0x4900,0x4a00,0x32c0,0x0520,0x0920,0x0920,0x10c0,0x0000,0x0000, + 0x0000,0x0c00,0x1200,0x1200,0x1400,0x1800,0x2500,0x2300,0x2300,0x1d80,0x0000,0x0000, + 0x0000,0x4000,0x4000,0x4000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0800,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000, + 0x0000,0x4000,0x2000,0x2000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x2000,0x2000, + 0x0000,0x2000,0x7000,0x2000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x0800,0x0800,0x7f00,0x0800,0x0800,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000, + 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000, + 0x0000,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x4000,0x0000,0x0000, + 0x0000,0x1000,0x2800,0x4400,0x4400,0x4400,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000, + 0x0000,0x1000,0x3000,0x5000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x0000,0x0000, + 0x0000,0x3000,0x4800,0x4400,0x0400,0x0800,0x1000,0x2000,0x4000,0x7c00,0x0000,0x0000, + 0x0000,0x3000,0x4800,0x0400,0x0800,0x1000,0x0800,0x4400,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x0800,0x1800,0x1800,0x2800,0x2800,0x4800,0x7c00,0x0800,0x0800,0x0000,0x0000, + 0x0000,0x3c00,0x2000,0x4000,0x7000,0x4800,0x0400,0x4400,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x1800,0x2400,0x4000,0x5000,0x6800,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000, + 0x0000,0x7c00,0x0400,0x0800,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x0000,0x0000, + 0x0000,0x1000,0x2800,0x4400,0x2800,0x1000,0x2800,0x4400,0x2800,0x1000,0x0000,0x0000, + 0x0000,0x1000,0x2800,0x4400,0x4400,0x2c00,0x1400,0x0400,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000, + 0x0000,0x0000,0x0400,0x0800,0x3000,0x4000,0x3000,0x0800,0x0400,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x7c00,0x0000,0x0000,0x7c00,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x4000,0x2000,0x1800,0x0400,0x1800,0x2000,0x4000,0x0000,0x0000,0x0000, + 0x0000,0x3800,0x6400,0x4400,0x0400,0x0800,0x1000,0x1000,0x0000,0x1000,0x0000,0x0000, + 0x0000,0x0f80,0x1040,0x2ea0,0x51a0,0x5120,0x5120,0x5120,0x5320,0x4dc0,0x2020,0x1040, + 0x0000,0x0800,0x1400,0x1400,0x1400,0x2200,0x3e00,0x2200,0x4100,0x4100,0x0000,0x0000, + 0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x0000,0x0000, + 0x0000,0x0e00,0x1100,0x2100,0x2000,0x2000,0x2000,0x2100,0x1100,0x0e00,0x0000,0x0000, + 0x0000,0x3c00,0x2200,0x2100,0x2100,0x2100,0x2100,0x2100,0x2200,0x3c00,0x0000,0x0000, + 0x0000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000, + 0x0000,0x3e00,0x2000,0x2000,0x2000,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000, + 0x0000,0x0e00,0x1100,0x2100,0x2000,0x2700,0x2100,0x2100,0x1100,0x0e00,0x0000,0x0000, + 0x0000,0x2100,0x2100,0x2100,0x2100,0x3f00,0x2100,0x2100,0x2100,0x2100,0x0000,0x0000, + 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000, + 0x0000,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x4800,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x2200,0x2400,0x2800,0x2800,0x3800,0x2800,0x2400,0x2400,0x2200,0x0000,0x0000, + 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000, + 0x0000,0x2080,0x3180,0x3180,0x3180,0x2a80,0x2a80,0x2a80,0x2a80,0x2480,0x0000,0x0000, + 0x0000,0x2100,0x3100,0x3100,0x2900,0x2900,0x2500,0x2300,0x2300,0x2100,0x0000,0x0000, + 0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000, + 0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000, + 0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1600,0x0d00,0x0100,0x0000, + 0x0000,0x3e00,0x2100,0x2100,0x2100,0x3e00,0x2400,0x2200,0x2100,0x2080,0x0000,0x0000, + 0x0000,0x1c00,0x2200,0x2200,0x2000,0x1c00,0x0200,0x2200,0x2200,0x1c00,0x0000,0x0000, + 0x0000,0x3e00,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000, + 0x0000,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000, + 0x0000,0x4100,0x4100,0x2200,0x2200,0x2200,0x1400,0x1400,0x1400,0x0800,0x0000,0x0000, + 0x0000,0x4440,0x4a40,0x2a40,0x2a80,0x2a80,0x2a80,0x2a80,0x2a80,0x1100,0x0000,0x0000, + 0x0000,0x4100,0x2200,0x1400,0x1400,0x0800,0x1400,0x1400,0x2200,0x4100,0x0000,0x0000, + 0x0000,0x4100,0x2200,0x2200,0x1400,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000, + 0x0000,0x7e00,0x0200,0x0400,0x0800,0x1000,0x1000,0x2000,0x4000,0x7e00,0x0000,0x0000, + 0x0000,0x3000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000, + 0x0000,0x4000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,0x0000,0x0000, + 0x0000,0x6000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000, + 0x0000,0x1000,0x2800,0x2800,0x2800,0x4400,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7e00, + 0x4000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3800,0x4400,0x0400,0x3c00,0x4400,0x4400,0x3c00,0x0000,0x0000, + 0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x4000,0x4000,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x0400,0x0400,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x7c00,0x4000,0x4400,0x3800,0x0000,0x0000, + 0x0000,0x6000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x4400, + 0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000, + 0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, + 0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000, + 0x0000,0x4000,0x4000,0x4800,0x5000,0x6000,0x5000,0x5000,0x4800,0x4800,0x0000,0x0000, + 0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x5200,0x6d00,0x4900,0x4900,0x4900,0x4900,0x4900,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x4400,0x4400,0x4400,0x3800,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x4000,0x4000, + 0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x0400, + 0x0000,0x0000,0x0000,0x5000,0x6000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x3000,0x0800,0x4800,0x3000,0x0000,0x0000, + 0x0000,0x4000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x6000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x4400,0x4400,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x2800,0x1000,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x4900,0x4900,0x5500,0x5500,0x5500,0x5500,0x2200,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x4400,0x2800,0x2800,0x1000,0x2800,0x2800,0x4400,0x0000,0x0000, + 0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x1000,0x1000,0x1000,0x1000, + 0x0000,0x0000,0x0000,0x7800,0x0800,0x1000,0x2000,0x2000,0x4000,0x7800,0x0000,0x0000, + 0x0000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000, + 0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000, + 0x0000,0x4000,0x2000,0x2000,0x2000,0x2000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000, + 0x0000,0x0000,0x0000,0x0000,0x7400,0x5800,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000, + 0x0000,0x0000,0x7000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x7000,0x0000,0x0000}; + +const uint16_t ASCII8x12_Table [] = { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x10,0x00, + 0x00,0x00,0x00,0x28,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x14,0x14,0x3e,0x14,0x28,0x7c,0x28,0x28,0x00, + 0x00,0x00,0x10,0x38,0x54,0x50,0x38,0x14,0x14,0x54,0x38,0x10, + 0x00,0x00,0x00,0x44,0xa8,0xa8,0x50,0x14,0x1a,0x2a,0x24,0x00, + 0x00,0x00,0x00,0x20,0x50,0x50,0x20,0xe8,0x98,0x98,0x60,0x00, + 0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x40,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80, + 0x00,0x00,0x00,0x80,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40, + 0x00,0x00,0x00,0x40,0xe0,0x40,0xa0,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x20,0x20,0xf8,0x20,0x20,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00, + 0x00,0x00,0x00,0x20,0x20,0x20,0x40,0x40,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x90,0x90,0x60,0x00, + 0x00,0x00,0x00,0x20,0x60,0xa0,0x20,0x20,0x20,0x20,0x20,0x00, + 0x00,0x00,0x00,0x60,0x90,0x10,0x10,0x20,0x40,0x80,0xf0,0x00, + 0x00,0x00,0x00,0x60,0x90,0x10,0x60,0x10,0x10,0x90,0x60,0x00, + 0x00,0x00,0x00,0x10,0x30,0x50,0x50,0x90,0xf8,0x10,0x10,0x00, + 0x00,0x00,0x00,0x70,0x40,0x80,0xe0,0x10,0x10,0x90,0x60,0x00, + 0x00,0x00,0x00,0x60,0x90,0x80,0xa0,0xd0,0x90,0x90,0x60,0x00, + 0x00,0x00,0x00,0xf0,0x10,0x20,0x20,0x20,0x40,0x40,0x40,0x00, + 0x00,0x00,0x00,0x60,0x90,0x90,0x60,0x90,0x90,0x90,0x60,0x00, + 0x00,0x00,0x00,0x60,0x90,0x90,0xb0,0x50,0x10,0x90,0x60,0x00, + 0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x00, + 0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x40, + 0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x80,0x60,0x10,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x00,0xf0,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x10,0x60,0x80,0x00,0x00, + 0x00,0x00,0x00,0x60,0x90,0x10,0x20,0x40,0x40,0x00,0x40,0x00, + 0x00,0x00,0x00,0x1c,0x22,0x5b,0xa5,0xa5,0xa5,0xa5,0x9e,0x41, + 0x00,0x00,0x00,0x20,0x50,0x50,0x50,0x50,0x70,0x88,0x88,0x00, + 0x00,0x00,0x00,0xf0,0x88,0x88,0xf0,0x88,0x88,0x88,0xf0,0x00, + 0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x80,0x84,0x44,0x38,0x00, + 0x00,0x00,0x00,0xe0,0x90,0x88,0x88,0x88,0x88,0x90,0xe0,0x00, + 0x00,0x00,0x00,0xf8,0x80,0x80,0xf8,0x80,0x80,0x80,0xf8,0x00, + 0x00,0x00,0x00,0x78,0x40,0x40,0x70,0x40,0x40,0x40,0x40,0x00, + 0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x9c,0x84,0x44,0x38,0x00, + 0x00,0x00,0x00,0x88,0x88,0x88,0xf8,0x88,0x88,0x88,0x88,0x00, + 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x90,0x90,0x60,0x00, + 0x00,0x00,0x00,0x88,0x90,0xa0,0xe0,0xa0,0x90,0x90,0x88,0x00, + 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0xf0,0x00, + 0x00,0x00,0x00,0x82,0xc6,0xc6,0xaa,0xaa,0xaa,0xaa,0x92,0x00, + 0x00,0x00,0x00,0x84,0xc4,0xa4,0xa4,0x94,0x94,0x8c,0x84,0x00, + 0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x48,0x30,0x00, + 0x00,0x00,0x00,0xf0,0x88,0x88,0x88,0xf0,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x58,0x34,0x04, + 0x00,0x00,0x00,0x78,0x44,0x44,0x78,0x50,0x48,0x44,0x42,0x00, + 0x00,0x00,0x00,0x70,0x88,0x80,0x70,0x08,0x88,0x88,0x70,0x00, + 0x00,0x00,0x00,0xf8,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00, + 0x00,0x00,0x00,0x84,0x84,0x84,0x84,0x84,0x84,0x48,0x30,0x00, + 0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x50,0x50,0x20,0x00, + 0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0x44,0x00, + 0x00,0x00,0x00,0x84,0x48,0x48,0x30,0x30,0x48,0x48,0x84,0x00, + 0x00,0x00,0x00,0x88,0x50,0x50,0x20,0x20,0x20,0x20,0x20,0x00, + 0x00,0x00,0x00,0xf8,0x08,0x10,0x20,0x20,0x40,0x80,0xf8,0x00, + 0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80, + 0x00,0x00,0x00,0x80,0x80,0x40,0x40,0x40,0x40,0x20,0x20,0x00, + 0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40, + 0x00,0x00,0x00,0x40,0xa0,0xa0,0xa0,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8, + 0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x70,0x90,0x90,0x70,0x00, + 0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x00, + 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x80,0x80,0x90,0x60,0x00, + 0x00,0x00,0x00,0x10,0x10,0x50,0xb0,0x90,0x90,0xb0,0x50,0x00, + 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0xf0,0x80,0x90,0x60,0x00, + 0x00,0x00,0x00,0xc0,0x80,0xc0,0x80,0x80,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10, + 0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00, + 0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80, + 0x00,0x00,0x00,0x80,0x80,0x90,0xa0,0xc0,0xa0,0x90,0x90,0x00, + 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x00,0x00,0xa6,0xda,0x92,0x92,0x92,0x92,0x00, + 0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00, + 0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x60,0x00, + 0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x80, + 0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10, + 0x00,0x00,0x00,0x00,0x00,0xa0,0xc0,0x80,0x80,0x80,0x80,0x00, + 0x00,0x00,0x00,0x00,0x00,0xe0,0x90,0x40,0x20,0x90,0x60,0x00, + 0x00,0x00,0x00,0x80,0x80,0xc0,0x80,0x80,0x80,0x80,0xc0,0x00, + 0x00,0x00,0x00,0x00,0x00,0x90,0x90,0x90,0x90,0xb0,0x50,0x00, + 0x00,0x00,0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x20,0x00, + 0x00,0x00,0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0x44,0x00, + 0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x20,0x20,0x50,0x88,0x00, + 0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x50,0x50,0x20,0x20,0x20, + 0x00,0x00,0x00,0x00,0x00,0xf0,0x10,0x20,0x40,0x80,0xf0,0x00, + 0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x80, + 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80, + 0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x20,0x40,0x40,0x40,0x40, + 0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0xb0,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0xe0,0xa0,0xa0,0xa0,0xa0,0xa0,0xe0,0x00}; + +const uint16_t ASCII8x8_Table [] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, + 0xa0, 0xa0, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x24, 0x24, 0xfe, 0x48, 0xfc, 0x48, 0x48, + 0x38, 0x54, 0x50, 0x38, 0x14, 0x14, 0x54, 0x38, + 0x44, 0xa8, 0xa8, 0x50, 0x14, 0x1a, 0x2a, 0x24, + 0x10, 0x28, 0x28, 0x10, 0x74, 0x4c, 0x4c, 0x30, + 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08, + 0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, + 0x00, 0x00, 0x24, 0x18, 0x3c, 0x18, 0x24, 0x00, + 0x00, 0x00, 0x10, 0x10, 0x7c, 0x10, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, + 0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x20, + 0x18, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x18, + 0x08, 0x18, 0x28, 0x08, 0x08, 0x08, 0x08, 0x08, + 0x38, 0x44, 0x00, 0x04, 0x08, 0x10, 0x20, 0x7c, + 0x18, 0x24, 0x04, 0x18, 0x04, 0x04, 0x24, 0x18, + 0x04, 0x0c, 0x14, 0x24, 0x44, 0x7e, 0x04, 0x04, + 0x3c, 0x20, 0x20, 0x38, 0x04, 0x04, 0x24, 0x18, + 0x18, 0x24, 0x20, 0x38, 0x24, 0x24, 0x24, 0x18, + 0x3c, 0x04, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10, + 0x18, 0x24, 0x24, 0x18, 0x24, 0x24, 0x24, 0x18, + 0x18, 0x24, 0x24, 0x24, 0x1c, 0x04, 0x24, 0x18, + 0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00, + 0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x10, 0x00, + 0x00, 0x00, 0x04, 0x18, 0x20, 0x18, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x3c, 0x00, 0x3c, 0x00, 0x00, + 0x00, 0x00, 0x20, 0x18, 0x04, 0x18, 0x20, 0x00, + 0x18, 0x24, 0x04, 0x08, 0x10, 0x10, 0x00, 0x10, + 0x3c, 0x42, 0x99, 0xa5, 0xa5, 0x9d, 0x42, 0x38, + 0x38, 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44, + 0x78, 0x44, 0x44, 0x78, 0x44, 0x44, 0x44, 0x78, + 0x1c, 0x22, 0x42, 0x40, 0x40, 0x42, 0x22, 0x1c, + 0x70, 0x48, 0x44, 0x44, 0x44, 0x44, 0x48, 0x70, + 0x7c, 0x40, 0x40, 0x7c, 0x40, 0x40, 0x40, 0x7c, + 0x3c, 0x20, 0x20, 0x38, 0x20, 0x20, 0x20, 0x20, + 0x1c, 0x22, 0x42, 0x40, 0x4e, 0x42, 0x22, 0x1c, + 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44, 0x44, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x04, 0x04, 0x04, 0x04, 0x04, 0x24, 0x24, 0x18, + 0x44, 0x48, 0x50, 0x70, 0x50, 0x48, 0x48, 0x44, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c, + 0x82, 0xc6, 0xc6, 0xaa, 0xaa, 0xaa, 0xaa, 0x92, + 0x42, 0x62, 0x52, 0x52, 0x4a, 0x4a, 0x46, 0x42, + 0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18, + 0x78, 0x44, 0x44, 0x44, 0x78, 0x40, 0x40, 0x40, + 0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x2c, 0x1a, + 0x78, 0x44, 0x44, 0x78, 0x50, 0x48, 0x44, 0x42, + 0x38, 0x44, 0x40, 0x38, 0x04, 0x44, 0x44, 0x38, + 0x7c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18, + 0x44, 0x44, 0x28, 0x28, 0x28, 0x28, 0x28, 0x10, + 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x44, + 0x42, 0x24, 0x24, 0x18, 0x18, 0x24, 0x24, 0x42, + 0x44, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x7c, 0x04, 0x08, 0x10, 0x10, 0x20, 0x40, 0x7c, + 0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1c, + 0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, + 0x1c, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x1c, + 0x10, 0x28, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x18, 0x04, 0x1c, 0x24, 0x24, 0x1c, + 0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x34, 0x28, + 0x00, 0x00, 0x18, 0x24, 0x20, 0x20, 0x24, 0x18, + 0x04, 0x04, 0x14, 0x2c, 0x24, 0x24, 0x2c, 0x14, + 0x00, 0x00, 0x18, 0x24, 0x3c, 0x20, 0x24, 0x18, + 0x00, 0x18, 0x10, 0x10, 0x18, 0x10, 0x10, 0x10, + 0x00, 0x18, 0x24, 0x24, 0x18, 0x04, 0x24, 0x18, + 0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24, + 0x10, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x08, 0x00, 0x08, 0x08, 0x08, 0x08, 0x28, 0x10, + 0x20, 0x20, 0x24, 0x28, 0x30, 0x28, 0x24, 0x24, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x00, 0x00, 0xa6, 0xda, 0x92, 0x92, 0x92, 0x92, + 0x00, 0x00, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24, + 0x00, 0x00, 0x18, 0x24, 0x24, 0x24, 0x24, 0x18, + 0x00, 0x28, 0x34, 0x24, 0x38, 0x20, 0x20, 0x20, + 0x00, 0x14, 0x2c, 0x24, 0x1c, 0x04, 0x04, 0x04, + 0x00, 0x00, 0x2c, 0x30, 0x20, 0x20, 0x20, 0x20, + 0x00, 0x00, 0x18, 0x24, 0x10, 0x08, 0x24, 0x18, + 0x00, 0x10, 0x38, 0x10, 0x10, 0x10, 0x10, 0x18, + 0x00, 0x00, 0x24, 0x24, 0x24, 0x24, 0x2c, 0x14, + 0x00, 0x00, 0x44, 0x44, 0x28, 0x28, 0x28, 0x10, + 0x00, 0x00, 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0x44, + 0x00, 0x00, 0x44, 0x28, 0x10, 0x10, 0x28, 0x44, + 0x00, 0x28, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10, + 0x00, 0x00, 0x3c, 0x04, 0x08, 0x10, 0x20, 0x3c, + 0x00, 0x08, 0x10, 0x10, 0x20, 0x10, 0x10, 0x08, + 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, + 0x00, 0x10, 0x08, 0x08, 0x04, 0x08, 0x08, 0x10, + 0x00, 0x00, 0x00, 0x60, 0x92, 0x0c, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + +sFONT Font16x24 = { + ASCII16x24_Table, + 16, /* Width */ + 24, /* Height */ +}; + +sFONT Font12x12 = { + ASCII12x12_Table, + 12, /* Width */ + 12, /* Height */ +}; + +sFONT Font8x12 = { + ASCII8x12_Table, + 8, /* Width */ + 12, /* Height */ +}; + + +sFONT Font8x8 = { + ASCII8x8_Table, + 8, /* Width */ + 8, /* Height */ +}; + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/fonts.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/fonts.h new file mode 100644 index 000000000..6d9f7d2ee --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/fonts.h @@ -0,0 +1,124 @@ +/** + ****************************************************************************** + * @file fonts.h + * @author MCD Application Team + * @version V5.0.2 + * @date 05-March-2012 + * @brief Header for fonts.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FONTS_H +#define __FONTS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @{ + */ + +/** @defgroup FONTS_Exported_Types + * @{ + */ +typedef struct _tFont +{ + const uint16_t *table; + uint16_t Width; + uint16_t Height; + +} sFONT; + +extern sFONT Font16x24; +extern sFONT Font12x12; +extern sFONT Font8x12; +extern sFONT Font8x8; + +/** + * @} + */ + +/** @defgroup FONTS_Exported_Constants + * @{ + */ +#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height)) + +/** + * @} + */ + +/** @defgroup FONTS_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup FONTS_Exported_Functions + * @{ + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FONTS_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/lcd_log.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/lcd_log.c new file mode 100644 index 000000000..f171e0545 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/lcd_log.c @@ -0,0 +1,528 @@ +/** + ****************************************************************************** + * @file lcd_log.c + * @author MCD Application Team + * @version V5.0.2 + * @date 05-March-2012 + * @brief This file provides all the LCD Log firmware functions. + * + * The LCD Log module allows to automatically set a header and footer + * on any application using the LCD display and allows to dump user, + * debug and error messages by using the following macros: LCD_ErrLog(), + * LCD_UsrLog() and LCD_DbgLog(). + * + * It supports also the scroll feature by embedding an internal software + * cache for display. This feature allows to dump message sequentially + * on the display even if the number of displayed lines is bigger than + * the total number of line allowed by the display. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lcd_log.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL +* @{ +*/ + +/** @addtogroup Common + * @{ + */ + +/** @defgroup LCD_LOG +* @brief LCD Log LCD_Application module +* @{ +*/ + +/** @defgroup LCD_LOG_Private_Types +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup LCD_LOG_Private_Defines +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup LCD_LOG_Private_Macros +* @{ +*/ +/** +* @} +*/ + + +/** @defgroup LCD_LOG_Private_Variables +* @{ +*/ + +LCD_LOG_line LCD_CacheBuffer [LCD_CACHE_DEPTH]; +uint16_t LCD_LineColor; +uint16_t LCD_CacheBuffer_xptr; +uint16_t LCD_CacheBuffer_yptr_top; +uint16_t LCD_CacheBuffer_yptr_bottom; + +uint16_t LCD_CacheBuffer_yptr_top_bak; +uint16_t LCD_CacheBuffer_yptr_bottom_bak; + +FunctionalState LCD_CacheBuffer_yptr_invert; +FunctionalState LCD_ScrollActive; +FunctionalState LCD_Lock; +FunctionalState LCD_Scrolled; +uint16_t LCD_ScrollBackStep; + +/** +* @} +*/ + + +/** @defgroup LCD_LOG_Private_FunctionPrototypes +* @{ +*/ +static void LCD_LOG_UpdateDisplay (void); +/** +* @} +*/ + + +/** @defgroup LCD_LOG_Private_Functions +* @{ +*/ + + +/** +* @brief Init the LCD Log module +* @param None +* @retval None +*/ + +void LCD_LOG_Init ( void) +{ + /* Deinit LCD cache */ + LCD_LOG_DeInit(); + /* Clear the LCD */ + LCD_Clear(Black); +} + +/** +* @brief DeInitializes the LCD Log module. +* @param None +* @retval None +*/ +void LCD_LOG_DeInit(void) +{ + LCD_LineColor = LCD_LOG_DEFAULT_COLOR; + LCD_CacheBuffer_xptr = 0; + LCD_CacheBuffer_yptr_top = 0; + LCD_CacheBuffer_yptr_bottom = 0; + + LCD_CacheBuffer_yptr_top_bak = 0; + LCD_CacheBuffer_yptr_bottom_bak = 0; + + LCD_CacheBuffer_yptr_invert= ENABLE; + LCD_ScrollActive = DISABLE; + LCD_Lock = DISABLE; + LCD_Scrolled = DISABLE; + LCD_ScrollBackStep = 0; +} + +/** +* @brief Display the application header (title) on the LCD screen +* @param Title : pointer to the string to be displayed +* @retval None +*/ +void LCD_LOG_SetHeader (uint8_t *Title) +{ + sFONT *cFont; + uint32_t size = 0 , idx; + uint8_t *ptr = Title; + uint8_t tmp[27]; + + /* center the header */ + while (*ptr++) size ++ ; + + /* truncate extra text */ + if(size > 26) + { + size = 26; + } + + for (idx = 0 ; idx < 27 ; idx ++) + { + tmp[idx] = ' '; + } + + for (idx = 0 ; idx < size ; idx ++) + { + tmp[idx + (27 - size)/2] = Title[idx]; + } + + /* Clear the LCD */ + LCD_Clear(Black); + + /* Set the LCD Font */ + LCD_SetFont (&Font12x12); + + cFont = LCD_GetFont(); + /* Set the LCD Text Color */ + LCD_SetTextColor(White); + LCD_SetBackColor(Blue); + LCD_ClearLine(0); + LCD_DisplayStringLine(cFont->Height, tmp); + LCD_ClearLine(2 * cFont->Height); + + LCD_SetBackColor(Black); + LCD_SetFont (&Font8x12); +} + +/** +* @brief Display the application footer (status) on the LCD screen +* @param Status : pointer to the string to be displayed +* @retval None +*/ +void LCD_LOG_SetFooter(uint8_t *Status) +{ + sFONT *cFont; + uint8_t tmp[40], i; + LCD_SetBackColor(Blue); + cFont = LCD_GetFont(); + + for (i= 0; i< (320/cFont->Width)-1 ; i++) + { + tmp[i] = ' '; + } + + tmp[(320/cFont->Width)-1] = 0; + LCD_DisplayStringLine(LCD_PIXEL_HEIGHT - cFont->Height, tmp); + LCD_DisplayStringLine(LCD_PIXEL_HEIGHT - cFont->Height, Status); + LCD_SetBackColor(Black); +} + +/** +* @brief Clear the Text Zone +* @param None +* @retval None +*/ +void LCD_LOG_ClearTextZone(void) +{ + uint8_t i=0; + sFONT *cFont = LCD_GetFont(); + + for (i= 0 ; i < YWINDOW_SIZE; i++) + { + LCD_ClearLine((i + YWINDOW_MIN) * cFont->Height); + } + + LCD_LOG_DeInit(); +} + +/** +* @brief Redirect the printf to the lcd +* @param c: character to be displayed +* @param f: output file pointer +* @retval None +*/ +PUTCHAR_PROTOTYPE +{ + + sFONT *cFont = LCD_GetFont(); + uint32_t idx; + + if(LCD_Lock == DISABLE) + { + if((LCD_ScrollActive == ENABLE)||(LCD_ScrollActive == ENABLE)) + { + LCD_CacheBuffer_yptr_bottom = LCD_CacheBuffer_yptr_bottom_bak; + LCD_CacheBuffer_yptr_top = LCD_CacheBuffer_yptr_top_bak; + LCD_ScrollActive = DISABLE; + LCD_Scrolled = DISABLE; + LCD_ScrollBackStep = 0; + + } + + if(( LCD_CacheBuffer_xptr < LCD_PIXEL_WIDTH /cFont->Width ) && ( ch != '\n')) + { + LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].line[LCD_CacheBuffer_xptr++] = (uint16_t)ch; + } + else + { + if(LCD_CacheBuffer_yptr_top >= LCD_CacheBuffer_yptr_bottom) + { + + if(LCD_CacheBuffer_yptr_invert == DISABLE) + { + LCD_CacheBuffer_yptr_top++; + + if(LCD_CacheBuffer_yptr_top == LCD_CACHE_DEPTH) + { + LCD_CacheBuffer_yptr_top = 0; + } + } + else + { + LCD_CacheBuffer_yptr_invert= DISABLE; + } + } + + for(idx = LCD_CacheBuffer_xptr ; idx < LCD_PIXEL_WIDTH /cFont->Width; idx++) + { + LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].line[LCD_CacheBuffer_xptr++] = ' '; + } + LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].color = LCD_LineColor; + + LCD_CacheBuffer_xptr = 0; + + LCD_LOG_UpdateDisplay (); + + LCD_CacheBuffer_yptr_bottom ++; + + if (LCD_CacheBuffer_yptr_bottom == LCD_CACHE_DEPTH) + { + LCD_CacheBuffer_yptr_bottom = 0; + LCD_CacheBuffer_yptr_top = 1; + LCD_CacheBuffer_yptr_invert = ENABLE; + } + + if( ch != '\n') + { + LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].line[LCD_CacheBuffer_xptr++] = (uint16_t)ch; + } + + } + } + return ch; +} + +/** +* @brief Update the text area display +* @param None +* @retval None +*/ +static void LCD_LOG_UpdateDisplay (void) +{ + uint8_t cnt = 0 ; + uint16_t length = 0 ; + uint16_t ptr = 0, index = 0; + + sFONT *cFont = LCD_GetFont(); + + if((LCD_CacheBuffer_yptr_bottom < (YWINDOW_SIZE -1)) && + (LCD_CacheBuffer_yptr_bottom >= LCD_CacheBuffer_yptr_top)) + { + LCD_SetTextColor(LCD_CacheBuffer[cnt + LCD_CacheBuffer_yptr_bottom].color); + LCD_DisplayStringLine ((YWINDOW_MIN + LCD_CacheBuffer_yptr_bottom) * cFont->Height, + (uint8_t *)(LCD_CacheBuffer[cnt + LCD_CacheBuffer_yptr_bottom].line)); + } + else + { + + if(LCD_CacheBuffer_yptr_bottom < LCD_CacheBuffer_yptr_top) + { + /* Virtual length for rolling */ + length = LCD_CACHE_DEPTH + LCD_CacheBuffer_yptr_bottom ; + } + else + { + length = LCD_CacheBuffer_yptr_bottom; + } + + ptr = length - YWINDOW_SIZE + 1; + + for (cnt = 0 ; cnt < YWINDOW_SIZE ; cnt ++) + { + + index = (cnt + ptr )% LCD_CACHE_DEPTH ; + + LCD_SetTextColor(LCD_CacheBuffer[index].color); + LCD_DisplayStringLine ((cnt + YWINDOW_MIN) * cFont->Height, + (uint8_t *)(LCD_CacheBuffer[index].line)); + + } + } + +} + +#ifdef LCD_SCROLL_ENABLED +/** +* @brief Display previous text frame +* @param None +* @retval Status +*/ +ErrorStatus LCD_LOG_ScrollBack (void) +{ + + if(LCD_ScrollActive == DISABLE) + { + + LCD_CacheBuffer_yptr_bottom_bak = LCD_CacheBuffer_yptr_bottom; + LCD_CacheBuffer_yptr_top_bak = LCD_CacheBuffer_yptr_top; + + + if(LCD_CacheBuffer_yptr_bottom > LCD_CacheBuffer_yptr_top) + { + + if ((LCD_CacheBuffer_yptr_bottom - LCD_CacheBuffer_yptr_top) <= YWINDOW_SIZE) + { + LCD_Lock = DISABLE; + return ERROR; + } + } + LCD_ScrollActive = ENABLE; + + if((LCD_CacheBuffer_yptr_bottom > LCD_CacheBuffer_yptr_top)&& + (LCD_Scrolled == DISABLE )) + { + LCD_CacheBuffer_yptr_bottom--; + LCD_Scrolled = ENABLE; + } + + } + + if(LCD_ScrollActive == ENABLE) + { + LCD_Lock = ENABLE; + + if(LCD_CacheBuffer_yptr_bottom > LCD_CacheBuffer_yptr_top) + { + + if((LCD_CacheBuffer_yptr_bottom - LCD_CacheBuffer_yptr_top) < YWINDOW_SIZE ) + { + LCD_Lock = DISABLE; + return ERROR; + } + + LCD_CacheBuffer_yptr_bottom --; + } + else if(LCD_CacheBuffer_yptr_bottom <= LCD_CacheBuffer_yptr_top) + { + + if((LCD_CACHE_DEPTH - LCD_CacheBuffer_yptr_top + LCD_CacheBuffer_yptr_bottom) < YWINDOW_SIZE) + { + LCD_Lock = DISABLE; + return ERROR; + } + LCD_CacheBuffer_yptr_bottom --; + + if(LCD_CacheBuffer_yptr_bottom == 0xFFFF) + { + LCD_CacheBuffer_yptr_bottom = LCD_CACHE_DEPTH - 2; + } + } + LCD_ScrollBackStep++; + LCD_LOG_UpdateDisplay(); + LCD_Lock = DISABLE; + } + return SUCCESS; +} + +/** +* @brief Display next text frame +* @param None +* @retval Status +*/ +ErrorStatus LCD_LOG_ScrollForward (void) +{ + + if(LCD_ScrollBackStep != 0) + { + if(LCD_ScrollActive == DISABLE) + { + + LCD_CacheBuffer_yptr_bottom_bak = LCD_CacheBuffer_yptr_bottom; + LCD_CacheBuffer_yptr_top_bak = LCD_CacheBuffer_yptr_top; + + if(LCD_CacheBuffer_yptr_bottom > LCD_CacheBuffer_yptr_top) + { + + if ((LCD_CacheBuffer_yptr_bottom - LCD_CacheBuffer_yptr_top) <= YWINDOW_SIZE) + { + LCD_Lock = DISABLE; + return ERROR; + } + } + LCD_ScrollActive = ENABLE; + + if((LCD_CacheBuffer_yptr_bottom > LCD_CacheBuffer_yptr_top)&& + (LCD_Scrolled == DISABLE )) + { + LCD_CacheBuffer_yptr_bottom--; + LCD_Scrolled = ENABLE; + } + + } + + if(LCD_ScrollActive == ENABLE) + { + LCD_Lock = ENABLE; + LCD_ScrollBackStep--; + + if(++LCD_CacheBuffer_yptr_bottom == LCD_CACHE_DEPTH) + { + LCD_CacheBuffer_yptr_bottom = 0; + } + + LCD_LOG_UpdateDisplay(); + LCD_Lock = DISABLE; + + } + return SUCCESS; + } + else // LCD_ScrollBackStep == 0 + { + LCD_Lock = DISABLE; + return ERROR; + } +} +#endif /* LCD_SCROLL_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/lcd_log.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/lcd_log.h new file mode 100644 index 000000000..4fe101b26 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/lcd_log.h @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file lcd_log.h + * @author MCD Application Team + * @version V5.0.2 + * @date 05-March-2012 + * @brief header for the lcd_log.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LCD_LOG_H__ +#define __LCD_LOG_H__ + +/* Includes ------------------------------------------------------------------*/ + +#include "lcd_log_conf.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup LCD_LOG + * @{ + */ + +/** @defgroup LCD_LOG + * @brief + * @{ + */ + + +/** @defgroup LCD_LOG_Exported_Defines + * @{ + */ +#ifdef __GNUC__ +/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf + set to 'Yes') calls __io_putchar() */ +#define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else +#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif /* __GNUC__ */ + +/** These value can be changed by user */ + +#ifdef LCD_SCROLL_ENABLED + #define LCD_CACHE_DEPTH (YWINDOW_SIZE + CACHE_SIZE) +#else + #define LCD_CACHE_DEPTH YWINDOW_SIZE +#endif +/** + * @} + */ + +/** @defgroup LCD_LOG_Exported_Types + * @{ + */ +typedef struct _LCD_LOG_line +{ + uint8_t line[XWINDOW_MAX]; + uint16_t color; + +}LCD_LOG_line; + +/** + * @} + */ + +/** @defgroup LCD_LOG_Exported_Macros + * @{ + */ +#define LCD_ErrLog(...) LCD_LineColor = Red;\ + printf("ERROR: ") ;\ + printf(__VA_ARGS__);\ + LCD_LineColor = LCD_LOG_DEFAULT_COLOR + +#define LCD_UsrLog(...) LCD_LineColor = LCD_LOG_DEFAULT_COLOR;\ + printf(__VA_ARGS__);\ + + +#define LCD_DbgLog(...) LCD_LineColor = Cyan;\ + printf(__VA_ARGS__);\ + LCD_LineColor = LCD_LOG_DEFAULT_COLOR +/** + * @} + */ + +/** @defgroup LCD_LOG_Exported_Variables + * @{ + */ +extern uint16_t LCD_LineColor; +/** + * @} + */ + +/** @defgroup LCD_LOG_Exported_FunctionsPrototype + * @{ + */ +void LCD_LOG_Init(void); +void LCD_LOG_DeInit(void); +void LCD_LOG_SetHeader(uint8_t *Title); +void LCD_LOG_SetFooter(uint8_t *Status); +void LCD_LOG_ClearTextZone(void); +#ifdef LCD_SCROLL_ENABLED + ErrorStatus LCD_LOG_ScrollBack(void); + ErrorStatus LCD_LOG_ScrollForward(void); +#endif +/** + * @} + */ + + +#endif /* __LCD_LOG_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/lcd_log_conf_template.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/lcd_log_conf_template.h new file mode 100644 index 000000000..6e8f7e333 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/lcd_log_conf_template.h @@ -0,0 +1,113 @@ +/** + ****************************************************************************** + * @file lcd_log_conf_template.h + * @author MCD Application Team + * @version V5.0.2 + * @date 05-March-2012 + * @brief lcd_log configuration template file. + * This file should be copied to the application folder and modified + * as follows: + * - Rename it to 'lcd_log_conf.h'. + * - Update the name of the LCD header file depending on the EVAL board + * you are using (see line32 below). + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LCD_LOG_CONF_H__ +#define __LCD_LOG_CONF_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32xxx_eval_lcd.h" /* replace 'stm32xxx' with your EVAL board name, ex: stm3210c_eval_lcd.h */ +#include + +/** @addtogroup LCD_LOG + * @{ + */ + +/** @defgroup LCD_LOG + * @brief This file is the + * @{ + */ + + +/** @defgroup LCD_LOG_CONF_Exported_Defines + * @{ + */ +/* Comment the line below to disable the scroll back and forward features */ +#define LCD_SCROLL_ENABLED + +/* Define the LCD default text color */ +#define LCD_LOG_DEFAULT_COLOR LCD_COLOR_WHITE + +/* Define the display window settings */ +#define YWINDOW_MIN 3 +#define YWINDOW_SIZE 12 +#define XWINDOW_MAX 50 + +/* Define the cache depth */ +#define CACHE_SIZE 50 + +/** @defgroup LCD_LOG_CONF_Exported_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup LCD_LOG_Exported_Macros + * @{ + */ + + +/** + * @} + */ + +/** @defgroup LCD_LOG_CONF_Exported_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup LCD_LOG_CONF_Exported_FunctionsPrototype + * @{ + */ + +/** + * @} + */ + + +#endif /* __LCD_LOG_H__ */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/stm32_eval_legacy.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/stm32_eval_legacy.h new file mode 100644 index 000000000..0a50858c5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/Common/stm32_eval_legacy.h @@ -0,0 +1,208 @@ +/** + ****************************************************************************** + * @file stm32_eval_legacy.h + * @author MCD Application Team + * @version V5.0.2 + * @date 05-March-2012 + * @brief This file contains defines legacy for STM32 EVAL drivers. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_EVAL_LEGACY_H +#define __STM32_EVAL_LEGACY_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* STM322xG_EVAL Defines Legacy */ +#ifdef USE_STM3220F_EVAL + #define USE_STM322xG_EVAL +#endif +#define STM3220F_LCD_Init STM322xG_LCD_Init + +/* Button Defines Legacy */ +#define Button_WAKEUP BUTTON_WAKEUP +#define Button_TAMPER BUTTON_TAMPER +#define Button_KEY BUTTON_KEY +#define Button_RIGHT BUTTON_RIGHT +#define Button_LEFT BUTTON_LEFT +#define Button_UP BUTTON_UP +#define Button_DOWN BUTTON_DOWN +#define Button_SEL BUTTON_SEL +#define Mode_GPIO BUTTON_MODE_GPIO +#define Mode_EXTI BUTTON_MODE_EXTI +#define Button_Mode_TypeDef ButtonMode_TypeDef +#define JOY_CENTER JOY_SEL +#define JOY_State_TypeDef JOYState_TypeDef + +/* LCD Defines Legacy */ +#define LCD_RSNWR_GPIO_CLK LCD_NWR_GPIO_CLK +#define LCD_SPI_GPIO_PORT LCD_SPI_SCK_GPIO_PORT +#define LCD_SPI_GPIO_CLK LCD_SPI_SCK_GPIO_CLK +#define R0 LCD_REG_0 +#define R1 LCD_REG_1 +#define R2 LCD_REG_2 +#define R3 LCD_REG_3 +#define R4 LCD_REG_4 +#define R5 LCD_REG_5 +#define R6 LCD_REG_6 +#define R7 LCD_REG_7 +#define R8 LCD_REG_8 +#define R9 LCD_REG_9 +#define R10 LCD_REG_10 +#define R12 LCD_REG_12 +#define R13 LCD_REG_13 +#define R14 LCD_REG_14 +#define R15 LCD_REG_15 +#define R16 LCD_REG_16 +#define R17 LCD_REG_17 +#define R18 LCD_REG_18 +#define R19 LCD_REG_19 +#define R20 LCD_REG_20 +#define R21 LCD_REG_21 +#define R22 LCD_REG_22 +#define R23 LCD_REG_23 +#define R24 LCD_REG_24 +#define R25 LCD_REG_25 +#define R26 LCD_REG_26 +#define R27 LCD_REG_27 +#define R28 LCD_REG_28 +#define R29 LCD_REG_29 +#define R30 LCD_REG_30 +#define R31 LCD_REG_31 +#define R32 LCD_REG_32 +#define R33 LCD_REG_33 +#define R34 LCD_REG_34 +#define R36 LCD_REG_36 +#define R37 LCD_REG_37 +#define R40 LCD_REG_40 +#define R41 LCD_REG_41 +#define R43 LCD_REG_43 +#define R45 LCD_REG_45 +#define R48 LCD_REG_48 +#define R49 LCD_REG_49 +#define R50 LCD_REG_50 +#define R51 LCD_REG_51 +#define R52 LCD_REG_52 +#define R53 LCD_REG_53 +#define R54 LCD_REG_54 +#define R55 LCD_REG_55 +#define R56 LCD_REG_56 +#define R57 LCD_REG_57 +#define R59 LCD_REG_59 +#define R60 LCD_REG_60 +#define R61 LCD_REG_61 +#define R62 LCD_REG_62 +#define R63 LCD_REG_63 +#define R64 LCD_REG_64 +#define R65 LCD_REG_65 +#define R66 LCD_REG_66 +#define R67 LCD_REG_67 +#define R68 LCD_REG_68 +#define R69 LCD_REG_69 +#define R70 LCD_REG_70 +#define R71 LCD_REG_71 +#define R72 LCD_REG_72 +#define R73 LCD_REG_73 +#define R74 LCD_REG_74 +#define R75 LCD_REG_75 +#define R76 LCD_REG_76 +#define R77 LCD_REG_77 +#define R78 LCD_REG_78 +#define R79 LCD_REG_79 +#define R80 LCD_REG_80 +#define R81 LCD_REG_81 +#define R82 LCD_REG_82 +#define R83 LCD_REG_83 +#define R96 LCD_REG_96 +#define R97 LCD_REG_97 +#define R106 LCD_REG_106 +#define R118 LCD_REG_118 +#define R128 LCD_REG_128 +#define R129 LCD_REG_129 +#define R130 LCD_REG_130 +#define R131 LCD_REG_131 +#define R132 LCD_REG_132 +#define R133 LCD_REG_133 +#define R134 LCD_REG_134 +#define R135 LCD_REG_135 +#define R136 LCD_REG_136 +#define R137 LCD_REG_137 +#define R139 LCD_REG_139 +#define R140 LCD_REG_140 +#define R141 LCD_REG_141 +#define R143 LCD_REG_143 +#define R144 LCD_REG_144 +#define R145 LCD_REG_145 +#define R146 LCD_REG_146 +#define R147 LCD_REG_147 +#define R148 LCD_REG_148 +#define R149 LCD_REG_149 +#define R150 LCD_REG_150 +#define R151 LCD_REG_151 +#define R152 LCD_REG_152 +#define R153 LCD_REG_153 +#define R154 LCD_REG_154 +#define R157 LCD_REG_157 +#define R192 LCD_REG_192 +#define R193 LCD_REG_193 +#define R227 LCD_REG_227 +#define R229 LCD_REG_229 +#define R231 LCD_REG_231 +#define R239 LCD_REG_239 +#define White LCD_COLOR_WHITE +#define Black LCD_COLOR_BLACK +#define Grey LCD_COLOR_GREY +#define Blue LCD_COLOR_BLUE +#define Blue2 LCD_COLOR_BLUE2 +#define Red LCD_COLOR_RED +#define Magenta LCD_COLOR_MAGENTA +#define Green LCD_COLOR_GREEN +#define Cyan LCD_COLOR_CYAN +#define Yellow LCD_COLOR_YELLOW +#define Line0 LCD_LINE_0 +#define Line1 LCD_LINE_1 +#define Line2 LCD_LINE_2 +#define Line3 LCD_LINE_3 +#define Line4 LCD_LINE_4 +#define Line5 LCD_LINE_5 +#define Line6 LCD_LINE_6 +#define Line7 LCD_LINE_7 +#define Line8 LCD_LINE_8 +#define Line9 LCD_LINE_9 +#define Horizontal LCD_DIR_HORIZONTAL +#define Vertical LCD_DIR_VERTICAL + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_EVAL_LEGACY_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/Release_Notes.html b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/Release_Notes.html new file mode 100644 index 000000000..606cb0238 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/Release_Notes.html @@ -0,0 +1,273 @@ + + + + + + + + + + + + + + + + Release Notes for STM322xG_EVAL Evaluation Board Drivers + + + + + + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
+

Back to Release page

+
+

Release +Notes for STM322xG_EVAL Evaluation Board Drivers

+

Copyright +2012 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM322xG_EVAL Evaluation Board Drivers +update History
    2. +
  2. License
    3. +
+ + +

STM322xG_EVAL Evaluation Board Drivers update History

V5.0.3 / 05-March-2012

+

Main +Changes

+ +
  • All source files: license disclaimer text update and add link to the License file on ST Internet.
  • stm322xg_eval_lcd.c
    • Enhance Gamma Curve settings for ILI9320 controller 
  • stm322xg_eval.c and stm322xg_eval_ioe.c
    • Swap +the order of I2C IOs and alternate function (AF) +configuration: AF configuration should be done before to configure the +IOs.
  • stm322xg_eval_sdio_sd.c
    • In SD_WaitWriteOperation() and SD_WaitReadOperation() functions: reset StopCondition flag after sending CMD12

V5.0.2 / 28-December-2011

Main +Changes

+
  • All source files: update disclaimer to add reference to the new license agreement
  • stm322xg_eval_lcd.c
    • Remove “static” from TextColor and BackColor variables declaration (need to be changed from other application modules) 
  • stm322xg_eval_ioe.h
    • Add +conditional compilation on the default DMA stream(s) used for I2C1 Tx +and Rx transfers, to allow user to change them from application level.

V5.0.1 / 14-November-2011

+

Main +Changes

+ +
  • stm322xg_eval_sdio_sd.h
    • SD_CardInfo structure, define CardCapacity variable as 64-bit long (instead of 32-bit)  to support SDHC memory cards with capacity greater than 4 GB.

V5.0.0 / 07-October-2011

+

Main +Changes

+ +
  • Update STM32 Evaluation Board Drivers architecture and folder organization, full API compatibility maintained vs. V4.6.2
    • All the HW drivers required for each board are provided within this board folder. The concerned drivers are:
      • stm32_eval_i2c_ee.c\.h: I2C M24Cxx EEPROM memory driver
      • stm32_eval_i2c_tsensor.c\.h: I2C LM75 temperature sensor driver
      • stm32_eval_spi_flash.c\.h: SPI M25Pxxx FLASH memory driver
      • stm32_eval_sdio_sd.c\.h: SDIO SD Card memory driver
      • stm32_eval_spi_sd.c\.h: SPI SD Card memory driver 
      • These drivers were moved from \Common to \STM32XXX_EVAL folder(s)
    • \Common folder contains only drivers for the fonts and log module used by the LCD driver
    • stm32_eval.c\.h files removed, as consequence you need to perform the following update on your project configuration  (based on EVAL drivers V4.6.2):
      • In the project files, add your EVAL board driver source file "stm322xg_eval.c" instead of "stm32_eval.c"
      • Include your EVAL board driver header file #include "stm322xg_eval.h" instead of #include "stm32_eval.h"
      • If +you are using the EVAL board's LCD, you need to add the include of +the LCD header file #include "stm322xg_eval_lcd.h"
        • If +you are using the LCD log module, after copying it to the application +folder you have to edit it and update the name of the LCD header file. For more details, refer to the lcd_log_conf_template.h driver description.
    • stm322xg_eval.h/.c
      • change value of “SDIO_TRANSFER_CLK_DIV” define from 2 to 0 to achieve SD max frequency at 24MHz.
      • Remove SD_DMAEndOfTransferStatus() function as now the DMA transfer is tracked using DMA End of transfer interrupt.
      • Add new define for the SDIO's DMA2 Stream (3 or 6): SD_SDIO_DMA_IRQn and SD_SDIO_DMA_IRQHANDLER.
    • stm322xg_eval_sdio_sd.h/.c
      • Add new function SD_ProcessDMAIRQ() to be called from the DMA end of transfer interrupt. 
      • Add some improvements by handling SDIO errors and adding timeout for different loops.
      • Refer to the driver header file's comments for more information on how to use the provided API.
    • stm322xg_eval_fsmc_sram.c
      • Add IOs config of missing FSMC address lines (FSMC_A21, FSMC_A22 and FSMC_A23).

V4.6.2 / 22-July-2011

+

Main +Changes

+ +
  • STM3210C_EVAL
    • stm3210c_eval_lcd.c: update to support new LCD AM240320D5TOQW01H (controller ILI9325)
  • STM322xG-EVAL
    • stm322xg_eval.h: fix value of the SDIO clock divider (SDIO_TRANSFER_CLK_DIV constant) to 2 instead of 0
    • stm322xg_eval_lcd.c: increase FSMC AddressSetupTime value from 1 to 3 to be compliant with some LCD access timing
    • stm322xg_eval_audio_codec.c: update Codec_CtrlInterface_Init() and Codec_GPIO_Init() functions to not reconfigure the I2C peripheral if it's already enabled and configured (to +avoid configuring the I2C twice when using both Audio codec and IO +Expander drivers in the same application).

V4.6.1 / 18-April-2011

+

Main +Changes

+ +
  • Update some STM322xG_EVAL drivers (no change on the API) to fix warnings with TASKING C compiler.
  • Change the Release Notes name to STM32 Evaluation Board Drivers
  • stm322xg_eval.c
    • SD_LowLevel_Init(): change SDIO pins speed configuration to "GPIO_Speed_25MHz"

V4.6.0 / 11-March-2011

+

Main +Changes

+ +
  • Official version supporting STM322xG_EVAL evaluation board RevB (for STM32F2xx devices).
  • Common
    • Add +new LCD log utility drivers: The LCD Log module allows to automatically +set a header and footer on any application using the LCD display and +allows to dump user, debug and error messages by using the following +macros: LCD_ErrLog(),    LCD_UsrLog() and LCD_DbgLog().
Note: the STM322xG_EVAL board RevA was wrongly named STM3220F_EVAL

V4.5.0 / 07-March-2011

+

Main +Changes

+ +
  • stm32_eval_sdio_sd.c\.h: driver improvement
    • SD Clock increased to 24MHz to improve the data transfer performance.
    • Add +new functions to check the SDIO peripheral and SD Card status at any +time: SD_WaitReadOperation(), SD_WaitWriteOperation(). The +software sequence is little bit changed but without any impact on +driver API. For more details, refer to the stm32_eval_sdio_sd.c +driver description.
    • Add +new structure containing the SD Status register parameters. This +structure is called by the +         + SD_SendSDStatus() function.
    • Transfers mode updated
      • Read/Write Block using Polling and DMA modes
      • Read/Write Multi Blocks using DMA mode only
      • Interrupt mode removed
    • Data transfer functions are managing only fixed Block size (512-byte) 
  • STM32100B-EVAL
    • stm32100b_eval_cec.c: fix some strict ANSI-C errors
  • STM32100E-EVAL
    • stm32100e_eval_cec.c: fix some strict ANSI-C errors
+

V4.4.0 / 31-December-2010

+

Main +Changes

+ +
  • Add new directory for STM32L152-EVAL board containing the following files:
    • stm32l152_eval.h/.c, stm32l152_eval_lcd.h/.c, stm32l152_eval_glass_lcd.h/.c, stm32l152_eval_i2c_ee.h/.c
  • Add support for the STM32100E-EVAL Rev B: SPI FLASH CS pin "sFLASH_CS_PIN" changed from PB.02 to PE.06.
  • stm32100e_eval_lcd.h/.c: Add support for "LCD_ILI9325" LCD controller.
  • stm32100e_eval_fsmc_onenand.h/.c driver updated to correct asynchronous and synchronous read operations procedures.
    +
+ +

4.3.0 +- 10/15/2010

+
  1. General
+ +
  • I2C EEPROM, Temperature Sensor and IOE Expander drivers updated to use the DMA for read/write transfer and add more robustness
  • SD Card (SDIO) driver updated to add more robustness
  • SPI Flash and SD Card (SPI) drivers: SPI MISO pin configuration changed to Input Floating 
+ + + +
  1. Utilities
+ + + + + +
  • Add new directory for STM32100E-EVAL board containing the following files:
    • stm32100e_eval.h/.c, +stm32100e_eval_lcd.h/.c, stm32100e_eval_cec.h/.c, +stm32100e_eval_fsmc_onenand.h/.c, stm32100e_eval_fsmc_sram.h/.c, +stm32100e_eval_ioe.h/.c
      +
  • Common
    • stm32_eval_sdio_sd.c: +Update the DMA End of Transfer Check loop inside the SD_ReadBlock(), +SD_WriteBlock(), SD_ReadMultiBlocks() and SD_Write MultiBlocks().
    • stm32_eval_i2c_ee.c/.h
      +
      • Enhanced sEE_WaitEepromStandbyState() function for more robustness.
      • Enhanced Read and Write operations to manage I2C limitations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
      • Add +critical sections user callbacks allowing to disable then enable +interrupts when I2C operation require to be not interrupted.
    • stm32_eval_i2c_tsensor.c/.h
      +
      • Enhanced I2C communication functions by using DMA for registers Read and Write operations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
  • STM32100B_EVAL
    • stm32100b_eval.h: Add LM75 DMA defines.
    • stm32100b_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
  • STM3210B_EVAL
    • stm3210b_eval.h: Add LM75 DMA defines.
    • stm3210b_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
  • STM3210C_EVAL
    • stm3210c_eval.h: Add EEPROM driver Timeout define.
    • stm3210c_eval_lcd.c: Change "SPI_FLASH" by "sFLASH" in LCD_DrawBMP() function.
    • stm3210c_eval_i2c_ioe.c
      • Enhanced I2C communication functions by using DMA for registers Read and Write operations.
      • Add Timeout management with user callback implementation which allows recovering from I2C bus errors.
      • change IOE_I2C_SPEED from "400000" to "300000".
  • STM3210E_EVAL
    • stm3210e_eval.c: change "void SD_WaitForDMAEndOfTransfer(void)" to "uint32_t SD_DMAEndOfTransferStatus(void)".
    • stm3210e_eval.h: Add LM75 DMA defines.
    • stm3210e_eval_fsmc_nand.h: remove "NAND_CMD_AREA_TRUE1" define.
    • stm3210e_eval_fsmc_nand.c: Update FSMC timing in NAND_Init() function to be aligned with AN2784 application note.
    • stm3210e_eval_fsmc_nor.c
      • NOR_Init() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure 
    • stm3210e_eval_fsmc_sram.c
      +
      • Update FSMC timing in SRAM_Init() function to be aligned with AN2784 application note.
        +
      • SRAM_Init() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure 
    • stm3210e_eval_lcd.c
      • LCD_FSMCConfig() function: add FSMC_AsynchronousWait field to FSMC_NORSRAMInitStructure 
+ + +

4.2.0 +- 04/16/2010

+
  1. General
+ +
  • I2C EEPROM driver +update to use the DMA to +perform data transfer to/from EEPROM memory.
+ +
  1. Utilities
+
  • STM32_EVAL
+
    • stm32_eval_i2c_ee.c: +updated to use the DMA to perform data transfer to/from +EEPROM memory. For more details, refer to the description provided +within this file.
    • stm3210c_eval.c: add low level +functions to configure the DMA (needed for I2C EEPROM driver)
      +
    • stm3210c_eval_ioe.c: add a delay +in IOE_TS_GetState() function to wait till the end of ADC +conversion
    • stm3210e_eval_fsmc_nor.c: add PD6 pin configuration in +NOR_Init() function
    • stm3210b_eval_lcd.c: remove the +second ";" from "static void PutPixel(int16_t x, int16_t y);;" 
+

4.1.0 +- 03/01/2010

+
  1. General
+
  • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices.
  • Add support for the +STMicroelectronics STM32100B-EVAL evaluation board.
+
  1. Utilities
+
  • STM32_EVAL
+
  • Add new directory +"Common" containing a common drivers for all STM32 evaluation boards: +fonts.h/.c, stm32_eval_i2c_ee.h/.c, stm32_eval_spi_flash.h/.c, + stm32_eval_i2c_tsensor.h/.c, + stm32_eval_spi_sd.h/.c +and stm32_eval_sdio_sd.h/.c
  • Add new driver for the +STM32100B-EVAL managing Leds, push button and COM ports.
  • New HDMI CEC High level +driver.
    +
  • For all LCD drivers new fonts has +been added.
  • New FSMC memories +drivers for STM3210E-EVAL board: stm3210e_eval_fsmc_sram.h/.c, stm3210e_eval_fsmc_nor.h/.c +and stm3210e_eval_fsmc_nand.h/.c.

License

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless +required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See +the License for the specific language governing permissions and +limitations under the License. + +
+
+

For +complete documentation on STM32 Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ + \ No newline at end of file diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval.c new file mode 100644 index 000000000..9b76f0a5b --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval.c @@ -0,0 +1,737 @@ +/** + ****************************************************************************** + * @file stm322xg_eval.c + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file provides + * - set of firmware functions to manage Leds, push-button and COM ports + * - low level initialization functions for SD card (on SDIO) and + * serial EEPROM (sEE) + * available on STM322xG-EVAL evaluation board(MB786) RevA and RevB + * from STMicroelectronics. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" +#include "stm32f2xx_sdio.h" +#include "stm32f2xx_dma.h" +#include "stm32f2xx_i2c.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @defgroup STM322xG_EVAL_LOW_LEVEL + * @brief This file provides firmware functions to manage Leds, push-buttons, + * COM ports, SD card on SDIO and serial EEPROM (sEE) available on + * STM322xG-EVAL evaluation board from STMicroelectronics. + * @{ + */ + +/** @defgroup STM322xG_EVAL_LOW_LEVEL_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_LOW_LEVEL_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_LOW_LEVEL_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_LOW_LEVEL_Private_Variables + * @{ + */ +GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT, + LED4_GPIO_PORT}; +const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, + LED4_PIN}; +const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK, + LED4_GPIO_CLK}; + +GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT, + KEY_BUTTON_GPIO_PORT}; + +const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN, + KEY_BUTTON_PIN}; + +const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK, + KEY_BUTTON_GPIO_CLK}; + +const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE, + TAMPER_BUTTON_EXTI_LINE, + KEY_BUTTON_EXTI_LINE}; + +const uint8_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE, + TAMPER_BUTTON_EXTI_PORT_SOURCE, + KEY_BUTTON_EXTI_PORT_SOURCE}; + +const uint8_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE, + TAMPER_BUTTON_EXTI_PIN_SOURCE, + KEY_BUTTON_EXTI_PIN_SOURCE}; +const uint8_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn, + KEY_BUTTON_EXTI_IRQn}; + +USART_TypeDef* COM_USART[COMn] = {EVAL_COM1}; + +GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT}; + +GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT}; + +const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK}; + +const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK}; + +const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK}; + +const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN}; + +const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN}; + +const uint8_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE}; + +const uint8_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE}; + +const uint8_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF}; + +const uint8_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF}; + +DMA_InitTypeDef sEEDMA_InitStructure; +NVIC_InitTypeDef NVIC_InitStructure; + +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_LOW_LEVEL_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_LOW_LEVEL_Private_Functions + * @{ + */ + +/** + * @brief Configures LED GPIO. + * @param Led: Specifies the Led to be configured. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @arg LED4 + * @retval None + */ +void STM_EVAL_LEDInit(Led_TypeDef Led) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable the GPIO_LED Clock */ + RCC_AHB1PeriphClockCmd(GPIO_CLK[Led], ENABLE); + + + /* Configure the GPIO_LED pin */ + GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led]; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure); +} + +/** + * @brief Turns selected LED On. + * @param Led: Specifies the Led to be set on. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @arg LED4 + * @retval None + */ +void STM_EVAL_LEDOn(Led_TypeDef Led) +{ + GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led]; +} + +/** + * @brief Turns selected LED Off. + * @param Led: Specifies the Led to be set off. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @arg LED4 + * @retval None + */ +void STM_EVAL_LEDOff(Led_TypeDef Led) +{ + GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led]; +} + +/** + * @brief Toggles the selected LED. + * @param Led: Specifies the Led to be toggled. + * This parameter can be one of following parameters: + * @arg LED1 + * @arg LED2 + * @arg LED3 + * @arg LED4 + * @retval None + */ +void STM_EVAL_LEDToggle(Led_TypeDef Led) +{ + GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led]; +} + +/** + * @brief Configures Button GPIO and EXTI Line. + * @param Button: Specifies the Button to be configured. + * This parameter can be one of following parameters: + * @arg BUTTON_WAKEUP: Wakeup Push Button + * @arg BUTTON_TAMPER: Tamper Push Button + * @arg BUTTON_KEY: Key Push Button + * @arg BUTTON_RIGHT: Joystick Right Push Button + * @arg BUTTON_LEFT: Joystick Left Push Button + * @arg BUTTON_UP: Joystick Up Push Button + * @arg BUTTON_DOWN: Joystick Down Push Button + * @arg BUTTON_SEL: Joystick Sel Push Button + * @param Button_Mode: Specifies Button mode. + * This parameter can be one of following parameters: + * @arg BUTTON_MODE_GPIO: Button will be used as simple IO + * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt + * generation capability + * @retval None + */ +void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode) +{ + GPIO_InitTypeDef GPIO_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + + /* Enable the BUTTON Clock */ + RCC_AHB1PeriphClockCmd(BUTTON_CLK[Button], ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + /* Configure Button pin as input */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button]; + GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure); + + + if (Button_Mode == BUTTON_MODE_EXTI) + { + /* Connect Button EXTI Line to Button GPIO Pin */ + SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]); + + /* Configure Button EXTI line */ + EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button]; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + + if(Button != BUTTON_WAKEUP) + { + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + } + else + { + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + } + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Enable and set Button EXTI Interrupt to the lowest priority */ + NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button]; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + + NVIC_Init(&NVIC_InitStructure); + } +} + +/** + * @brief Returns the selected Button state. + * @param Button: Specifies the Button to be checked. + * This parameter can be one of following parameters: + * @arg BUTTON_WAKEUP: Wakeup Push Button + * @arg BUTTON_TAMPER: Tamper Push Button + * @arg BUTTON_KEY: Key Push Button + * @arg BUTTON_RIGHT: Joystick Right Push Button + * @arg BUTTON_LEFT: Joystick Left Push Button + * @arg BUTTON_UP: Joystick Up Push Button + * @arg BUTTON_DOWN: Joystick Down Push Button + * @arg BUTTON_SEL: Joystick Sel Push Button + * @retval The Button GPIO pin value. + */ +uint32_t STM_EVAL_PBGetState(Button_TypeDef Button) +{ + return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]); +} + + +/** + * @brief Configures COM port. + * @param COM: Specifies the COM port to be configured. + * This parameter can be one of following parameters: + * @arg COM1 + * @arg COM2 + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that + * contains the configuration information for the specified USART peripheral. + * @retval None + */ +void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIO clock */ + RCC_AHB1PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE); + + if (COM == COM1) + { + /* Enable UART clock */ + RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE); + } + + /* Connect PXx to USARTx_Tx*/ + GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]); + + /* Connect PXx to USARTx_Rx*/ + GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]); + + /* Configure USART Tx as alternate function */ + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + + GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM]; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure); + + /* Configure USART Rx as alternate function */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM]; + GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure); + + /* USART configuration */ + USART_Init(COM_USART[COM], USART_InitStruct); + + /* Enable USART */ + USART_Cmd(COM_USART[COM], ENABLE); +} + +/** + * @brief DeInitializes the SDIO interface. + * @param None + * @retval None + */ +void SD_LowLevel_DeInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /*!< Disable SDIO Clock */ + SDIO_ClockCmd(DISABLE); + + /*!< Set Power State to OFF */ + SDIO_SetPowerState(SDIO_PowerState_OFF); + + /*!< DeInitializes the SDIO peripheral */ + SDIO_DeInit(); + + /* Disable the SDIO APB2 Clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, DISABLE); + + GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_MCO); + + /* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Configure PD.02 CMD line */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* Configure PC.12 pin: CLK pin */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_Init(GPIOC, &GPIO_InitStructure); +} + +/** + * @brief Initializes the SD Card and put it into StandBy State (Ready for + * data transfer). + * @param None + * @retval None + */ +void SD_LowLevel_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* GPIOC and GPIOD Periph clock enable */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | SD_DETECT_GPIO_CLK, ENABLE); + + GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_SDIO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_SDIO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_SDIO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_SDIO); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_SDIO); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_SDIO); + + /* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Configure PD.02 CMD line */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* Configure PC.12 pin: CLK pin */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */ + GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure); + + /* Enable the SDIO APB2 Clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE); + + /* Enable the DMA2 Clock */ + RCC_AHB1PeriphClockCmd(SD_SDIO_DMA_CLK, ENABLE); +} + +/** + * @brief Configures the DMA2 Channel4 for SDIO Tx request. + * @param BufferSRC: pointer to the source buffer + * @param BufferSize: buffer size + * @retval None + */ +void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize) +{ + DMA_InitTypeDef SDDMA_InitStructure; + + DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF); + + /* DMA2 Stream3 or Stream6 disable */ + DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE); + + /* DMA2 Stream3 or Stream6 Config */ + DMA_DeInit(SD_SDIO_DMA_STREAM); + + SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL; + SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS; + SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferSRC; + SDDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + SDDMA_InitStructure.DMA_BufferSize = 0; + SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4; + SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; + DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure); + DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE); + DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral); + + /* DMA2 Stream3 or Stream6 enable */ + DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE); + +} + +/** + * @brief Configures the DMA2 Channel4 for SDIO Rx request. + * @param BufferDST: pointer to the destination buffer + * @param BufferSize: buffer size + * @retval None + */ +void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize) +{ + DMA_InitTypeDef SDDMA_InitStructure; + + DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_FEIF | SD_SDIO_DMA_FLAG_DMEIF | SD_SDIO_DMA_FLAG_TEIF | SD_SDIO_DMA_FLAG_HTIF | SD_SDIO_DMA_FLAG_TCIF); + + /* DMA2 Stream3 or Stream6 disable */ + DMA_Cmd(SD_SDIO_DMA_STREAM, DISABLE); + + /* DMA2 Stream3 or Stream6 Config */ + DMA_DeInit(SD_SDIO_DMA_STREAM); + + SDDMA_InitStructure.DMA_Channel = SD_SDIO_DMA_CHANNEL; + SDDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS; + SDDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)BufferDST; + SDDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + SDDMA_InitStructure.DMA_BufferSize = 0; + SDDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + SDDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + SDDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word; + SDDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word; + SDDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + SDDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + SDDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + SDDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + SDDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC4; + SDDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_INC4; + DMA_Init(SD_SDIO_DMA_STREAM, &SDDMA_InitStructure); + DMA_ITConfig(SD_SDIO_DMA_STREAM, DMA_IT_TC, ENABLE); + DMA_FlowControllerConfig(SD_SDIO_DMA_STREAM, DMA_FlowCtrl_Peripheral); + + /* DMA2 Stream3 or Stream6 enable */ + DMA_Cmd(SD_SDIO_DMA_STREAM, ENABLE); +} + +/** + * @brief DeInitializes peripherals used by the I2C EEPROM driver. + * @param None + * @retval None + */ +void sEE_LowLevel_DeInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* sEE_I2C Peripheral Disable */ + I2C_Cmd(sEE_I2C, DISABLE); + + /* sEE_I2C DeInit */ + I2C_DeInit(sEE_I2C); + + /*!< sEE_I2C Periph clock disable */ + RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE); + + /*!< GPIO configuration */ + /*!< Configure sEE_I2C pins: SCL */ + GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); + + /*!< Configure sEE_I2C pins: SDA */ + GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN; + GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); + + /* Configure and enable I2C DMA TX Stream interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; + NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Configure and enable I2C DMA RX Stream interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; + NVIC_Init(&NVIC_InitStructure); + + /* Disable and Deinitialize the DMA Streams */ + DMA_Cmd(sEE_I2C_DMA_STREAM_TX, DISABLE); + DMA_Cmd(sEE_I2C_DMA_STREAM_RX, DISABLE); + DMA_DeInit(sEE_I2C_DMA_STREAM_TX); + DMA_DeInit(sEE_I2C_DMA_STREAM_RX); +} + +/** + * @brief Initializes peripherals used by the I2C EEPROM driver. + * @param None + * @retval None + */ +void sEE_LowLevel_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /*!< sEE_I2C Periph clock enable */ + RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE); + + /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */ + RCC_AHB1PeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE); + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + /* Reset sEE_I2C IP */ + RCC_APB1PeriphResetCmd(sEE_I2C_CLK, ENABLE); + + /* Release reset signal of sEE_I2C IP */ + RCC_APB1PeriphResetCmd(sEE_I2C_CLK, DISABLE); + + /*!< GPIO configuration */ + /* Connect PXx to I2C_SCL*/ + GPIO_PinAFConfig(sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_SOURCE, sEE_I2C_SCL_AF); + /* Connect PXx to I2C_SDA*/ + GPIO_PinAFConfig(sEE_I2C_SDA_GPIO_PORT, sEE_I2C_SDA_SOURCE, sEE_I2C_SDA_AF); + + /*!< Configure sEE_I2C pins: SCL */ + GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); + /*!< Configure sEE_I2C pins: SDA */ + GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN; + GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); + + + /* Configure and enable I2C DMA TX Channel interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + /* Configure and enable I2C DMA RX Channel interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO; + NVIC_Init(&NVIC_InitStructure); + + /*!< I2C DMA TX and RX channels configuration */ + /* Enable the DMA clock */ + RCC_AHB1PeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE); + + /* Clear any pending flag on Rx Stream */ + DMA_ClearFlag(sEE_I2C_DMA_STREAM_TX, sEE_TX_DMA_FLAG_FEIF | sEE_TX_DMA_FLAG_DMEIF | sEE_TX_DMA_FLAG_TEIF | \ + sEE_TX_DMA_FLAG_HTIF | sEE_TX_DMA_FLAG_TCIF); + /* Disable the EE I2C Tx DMA stream */ + DMA_Cmd(sEE_I2C_DMA_STREAM_TX, DISABLE); + /* Configure the DMA stream for the EE I2C peripheral TX direction */ + DMA_DeInit(sEE_I2C_DMA_STREAM_TX); + sEEDMA_InitStructure.DMA_Channel = sEE_I2C_DMA_CHANNEL; + sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address; + sEEDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; /* This parameter will be configured durig communication */; + sEEDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; /* This parameter will be configured durig communication */ + sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF; /* This parameter will be configured durig communication */ + sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + sEEDMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + sEEDMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + sEEDMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + sEEDMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(sEE_I2C_DMA_STREAM_TX, &sEEDMA_InitStructure); + + /* Clear any pending flag on Rx Stream */ + DMA_ClearFlag(sEE_I2C_DMA_STREAM_RX, sEE_RX_DMA_FLAG_FEIF | sEE_RX_DMA_FLAG_DMEIF | sEE_RX_DMA_FLAG_TEIF | \ + sEE_RX_DMA_FLAG_HTIF | sEE_RX_DMA_FLAG_TCIF); + /* Disable the EE I2C DMA Rx stream */ + DMA_Cmd(sEE_I2C_DMA_STREAM_RX, DISABLE); + /* Configure the DMA stream for the EE I2C peripheral RX direction */ + DMA_DeInit(sEE_I2C_DMA_STREAM_RX); + DMA_Init(sEE_I2C_DMA_STREAM_RX, &sEEDMA_InitStructure); + + /* Enable the DMA Channels Interrupts */ + DMA_ITConfig(sEE_I2C_DMA_STREAM_TX, DMA_IT_TC, ENABLE); + DMA_ITConfig(sEE_I2C_DMA_STREAM_RX, DMA_IT_TC, ENABLE); +} + +/** + * @brief Initializes DMA channel used by the I2C EEPROM driver. + * @param None + * @retval None + */ +void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction) +{ + /* Initialize the DMA with the new parameters */ + if (Direction == sEE_DIRECTION_TX) + { + /* Configure the DMA Tx Stream with the buffer address and the buffer size */ + sEEDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)pBuffer; + sEEDMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize; + DMA_Init(sEE_I2C_DMA_STREAM_TX, &sEEDMA_InitStructure); + } + else + { + /* Configure the DMA Rx Stream with the buffer address and the buffer size */ + sEEDMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)pBuffer; + sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize; + DMA_Init(sEE_I2C_DMA_STREAM_RX, &sEEDMA_InitStructure); + } +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval.h new file mode 100644 index 000000000..52e633317 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval.h @@ -0,0 +1,373 @@ +/** + ****************************************************************************** + * @file stm322xg_eval.h + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file contains definitions for STM322xG_EVAL's Leds, push-buttons + * and COM ports hardware resources. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM322xG_EVAL_H +#define __STM322xG_EVAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f2xx.h" +#include "stm32_eval_legacy.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_LOW_LEVEL + * @{ + */ + +/** @defgroup STM322xG_EVAL_LOW_LEVEL_Exported_Types + * @{ + */ +typedef enum +{ + LED1 = 0, + LED2 = 1, + LED3 = 2, + LED4 = 3 +} Led_TypeDef; + +typedef enum +{ + BUTTON_WAKEUP = 0, + BUTTON_TAMPER = 1, + BUTTON_KEY = 2, + BUTTON_RIGHT = 3, + BUTTON_LEFT = 4, + BUTTON_UP = 5, + BUTTON_DOWN = 6, + BUTTON_SEL = 7 +} Button_TypeDef; + +typedef enum +{ + BUTTON_MODE_GPIO = 0, + BUTTON_MODE_EXTI = 1 +} ButtonMode_TypeDef; + +typedef enum +{ + JOY_NONE = 0, + JOY_SEL = 1, + JOY_DOWN = 2, + JOY_LEFT = 3, + JOY_RIGHT = 4, + JOY_UP = 5 +} JOYState_TypeDef +; + +typedef enum +{ + COM1 = 0, + COM2 = 1 +} COM_TypeDef; +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_LOW_LEVEL_Exported_Constants + * @{ + */ + +/** + * @brief Define for STM322xG_EVAL board + */ +#if !defined (USE_STM322xG_EVAL) + #define USE_STM322xG_EVAL +#endif + +/** @addtogroup STM322xG_EVAL_LOW_LEVEL_LED + * @{ + */ +#define LEDn 4 + +#define LED1_PIN GPIO_Pin_6 +#define LED1_GPIO_PORT GPIOG +#define LED1_GPIO_CLK RCC_AHB1Periph_GPIOG + +#define LED2_PIN GPIO_Pin_8 +#define LED2_GPIO_PORT GPIOG +#define LED2_GPIO_CLK RCC_AHB1Periph_GPIOG + +#define LED3_PIN GPIO_Pin_9 +#define LED3_GPIO_PORT GPIOI +#define LED3_GPIO_CLK RCC_AHB1Periph_GPIOI + +#define LED4_PIN GPIO_Pin_7 +#define LED4_GPIO_PORT GPIOC +#define LED4_GPIO_CLK RCC_AHB1Periph_GPIOC + +/** + * @} + */ + +/** @addtogroup STM322xG_EVAL_LOW_LEVEL_BUTTON + * @{ + */ +#define BUTTONn 3 /*!< Joystick pins are connected to + an IO Expander (accessible through + I2C1 interface) */ + +/** + * @brief Wakeup push-button + */ +#define WAKEUP_BUTTON_PIN GPIO_Pin_0 +#define WAKEUP_BUTTON_GPIO_PORT GPIOA +#define WAKEUP_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA +#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0 +#define WAKEUP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA +#define WAKEUP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0 +#define WAKEUP_BUTTON_EXTI_IRQn EXTI0_IRQn + +/** + * @brief Tamper push-button + */ +#define TAMPER_BUTTON_PIN GPIO_Pin_13 +#define TAMPER_BUTTON_GPIO_PORT GPIOC +#define TAMPER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOC +#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13 +#define TAMPER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC +#define TAMPER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource13 +#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn + +/** + * @brief Key push-button + */ +#define KEY_BUTTON_PIN GPIO_Pin_15 +#define KEY_BUTTON_GPIO_PORT GPIOG +#define KEY_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOG +#define KEY_BUTTON_EXTI_LINE EXTI_Line15 +#define KEY_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOG +#define KEY_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource15 +#define KEY_BUTTON_EXTI_IRQn EXTI15_10_IRQn +/** + * @} + */ + +/** @addtogroup STM322xG_EVAL_LOW_LEVEL_COM + * @{ + */ +#define COMn 1 + +/** + * @brief Definition for COM port1, connected to USART3 + */ +#define EVAL_COM1 USART3 +#define EVAL_COM1_CLK RCC_APB1Periph_USART3 +#define EVAL_COM1_TX_PIN GPIO_Pin_10 +#define EVAL_COM1_TX_GPIO_PORT GPIOC +#define EVAL_COM1_TX_GPIO_CLK RCC_AHB1Periph_GPIOC +#define EVAL_COM1_TX_SOURCE GPIO_PinSource10 +#define EVAL_COM1_TX_AF GPIO_AF_USART3 +#define EVAL_COM1_RX_PIN GPIO_Pin_11 +#define EVAL_COM1_RX_GPIO_PORT GPIOC +#define EVAL_COM1_RX_GPIO_CLK RCC_AHB1Periph_GPIOC +#define EVAL_COM1_RX_SOURCE GPIO_PinSource11 +#define EVAL_COM1_RX_AF GPIO_AF_USART3 +#define EVAL_COM1_IRQn USART3_IRQn + +/** + * @} + */ + +/** @addtogroup STM322xG_EVAL_LOW_LEVEL_SD_FLASH + * @{ + */ +/** + * @brief SD FLASH SDIO Interface + */ +#define SD_DETECT_PIN GPIO_Pin_13 /* PH.13 */ +#define SD_DETECT_GPIO_PORT GPIOH /* GPIOH */ +#define SD_DETECT_GPIO_CLK RCC_AHB1Periph_GPIOH + +#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80) +/** + * @brief SDIO Intialization Frequency (400KHz max) + */ +#define SDIO_INIT_CLK_DIV ((uint8_t)0x76) +/** + * @brief SDIO Data Transfer Frequency (25MHz max) + */ +#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0) + +#define SD_SDIO_DMA DMA2 +#define SD_SDIO_DMA_CLK RCC_AHB1Periph_DMA2 + +#define SD_SDIO_DMA_STREAM3 3 +//#define SD_SDIO_DMA_STREAM6 6 + +#ifdef SD_SDIO_DMA_STREAM3 + #define SD_SDIO_DMA_STREAM DMA2_Stream3 + #define SD_SDIO_DMA_CHANNEL DMA_Channel_4 + #define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF3 + #define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF3 + #define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF3 + #define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF3 + #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF3 + #define SD_SDIO_DMA_IRQn DMA2_Stream3_IRQn + #define SD_SDIO_DMA_IRQHANDLER DMA2_Stream3_IRQHandler +#elif defined SD_SDIO_DMA_STREAM6 + #define SD_SDIO_DMA_STREAM DMA2_Stream6 + #define SD_SDIO_DMA_CHANNEL DMA_Channel_4 + #define SD_SDIO_DMA_FLAG_FEIF DMA_FLAG_FEIF6 + #define SD_SDIO_DMA_FLAG_DMEIF DMA_FLAG_DMEIF6 + #define SD_SDIO_DMA_FLAG_TEIF DMA_FLAG_TEIF6 + #define SD_SDIO_DMA_FLAG_HTIF DMA_FLAG_HTIF6 + #define SD_SDIO_DMA_FLAG_TCIF DMA_FLAG_TCIF6 + #define SD_SDIO_DMA_IRQn DMA2_Stream6_IRQn + #define SD_SDIO_DMA_IRQHANDLER DMA2_Stream6_IRQHandler +#endif /* SD_SDIO_DMA_STREAM3 */ + +/** + * @} + */ + +/** @addtogroup STM322xG_EVAL_LOW_LEVEL_I2C_EE + * @{ + */ +/** + * @brief I2C EEPROM Interface pins + */ +#define sEE_I2C I2C1 +#define sEE_I2C_CLK RCC_APB1Periph_I2C1 +#define sEE_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */ +#define sEE_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */ +#define sEE_I2C_SCL_GPIO_CLK RCC_AHB1Periph_GPIOB +#define sEE_I2C_SCL_SOURCE GPIO_PinSource6 +#define sEE_I2C_SCL_AF GPIO_AF_I2C1 +#define sEE_I2C_SDA_PIN GPIO_Pin_9 /* PB.09 */ +#define sEE_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */ +#define sEE_I2C_SDA_GPIO_CLK RCC_AHB1Periph_GPIOB +#define sEE_I2C_SDA_SOURCE GPIO_PinSource9 +#define sEE_I2C_SDA_AF GPIO_AF_I2C1 +#define sEE_M24C64_32 + +#define sEE_I2C_DMA DMA1 +#define sEE_I2C_DMA_CHANNEL DMA_Channel_1 +#define sEE_I2C_DMA_STREAM_TX DMA1_Stream6 +#define sEE_I2C_DMA_STREAM_RX DMA1_Stream0 +#define sEE_I2C_DMA_CLK RCC_AHB1Periph_DMA1 +#define sEE_I2C_DR_Address ((uint32_t)0x40005410) +#define sEE_USE_DMA + +#define sEE_I2C_DMA_TX_IRQn DMA1_Stream6_IRQn +#define sEE_I2C_DMA_RX_IRQn DMA1_Stream0_IRQn +#define sEE_I2C_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler +#define sEE_I2C_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define sEE_I2C_DMA_PREPRIO 0 +#define sEE_I2C_DMA_SUBPRIO 0 + +#define sEE_TX_DMA_FLAG_FEIF DMA_FLAG_FEIF6 +#define sEE_TX_DMA_FLAG_DMEIF DMA_FLAG_DMEIF6 +#define sEE_TX_DMA_FLAG_TEIF DMA_FLAG_TEIF6 +#define sEE_TX_DMA_FLAG_HTIF DMA_FLAG_HTIF6 +#define sEE_TX_DMA_FLAG_TCIF DMA_FLAG_TCIF6 +#define sEE_RX_DMA_FLAG_FEIF DMA_FLAG_FEIF0 +#define sEE_RX_DMA_FLAG_DMEIF DMA_FLAG_DMEIF0 +#define sEE_RX_DMA_FLAG_TEIF DMA_FLAG_TEIF0 +#define sEE_RX_DMA_FLAG_HTIF DMA_FLAG_HTIF0 +#define sEE_RX_DMA_FLAG_TCIF DMA_FLAG_TCIF0 + +#define sEE_DIRECTION_TX 0 +#define sEE_DIRECTION_RX 1 + +/* Time constant for the delay caclulation allowing to have a millisecond + incrementing counter. This value should be equal to (System Clock / 1000). + ie. if system clock = 120MHz then sEE_TIME_CONST should be 120. */ +#define sEE_TIME_CONST 120 +/** + * @} + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_LOW_LEVEL_Exported_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_LOW_LEVEL_Exported_Functions + * @{ + */ +void STM_EVAL_LEDInit(Led_TypeDef Led); +void STM_EVAL_LEDOn(Led_TypeDef Led); +void STM_EVAL_LEDOff(Led_TypeDef Led); +void STM_EVAL_LEDToggle(Led_TypeDef Led); +void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); +uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); +void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); +void SD_LowLevel_DeInit(void); +void SD_LowLevel_Init(void); +void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize); +void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize); +void sEE_LowLevel_DeInit(void); +void sEE_LowLevel_Init(void); +void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM322xG_EVAL_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_audio_codec.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_audio_codec.c new file mode 100644 index 000000000..7f6f2409d --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_audio_codec.c @@ -0,0 +1,1465 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_audio_codec.c + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file includes the low layer driver for CS43L22 Audio Codec + * available on STM322xG-EVAL evaluation board(MB786) RevA and RevB. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/*============================================================================================================================== + User NOTES +1. How To use this driver: +-------------------------- + - This driver supports STM32F2xx devices on STM322xG-EVAL (MB786 RevA) Evaluation boards. + + - Configure the options in file stm322xg_eval_audio_codec.h in the section CONFIGURATION. + Refer to the sections 2 and 3 to have more details on the possible configurations. + + - Call the function EVAL_AUDIO_Init( + OutputDevice: physical output mode (OUTPUT_DEVICE_SPEAKER, + OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_AUTO or + OUTPUT_DEVICE_BOTH) + Volume: initial volume to be set (0 is min (mute), 100 is max (100%) + AudioFreq: Audio frequency in Hz (8000, 16000, 22500, 32000 ...) + this parameter is relative to the audio file/stream type. + ) + This function configures all the hardware required for the audio application (codec, I2C, I2S, + GPIOs, DMA and interrupt if needed). This function returns 0 if configuration is OK. + if the returned value is different from 0 or the function is stuck then the communication with + the codec or the IOExpander has failed (try to un-plug the power or reset device in this case). + + OUTPUT_DEVICE_SPEAKER: only speaker will be set as output for the audio stream. + + OUTPUT_DEVICE_HEADPHONE: only headphones will be set as output for the audio stream. + + OUTPUT_DEVICE_AUTO: Selection of output device is made through external switch (implemented + into the audio jack on the evaluation board). When the Headphone is connected it is used + as output. When the headphone is disconnected from the audio jack, the output is + automatically switched to Speaker. + + OUTPUT_DEVICE_BOTH: both Speaker and Headphone are used as outputs for the audio stream + at the same time. + + - Call the function EVAL_AUDIO_Play( + pBuffer: pointer to the audio data file address + Size: size of the buffer to be sent in Bytes + ) + to start playing (for the first time) from the audio file/stream. + + - Call the function EVAL_AUDIO_PauseResume( + Cmd: AUDIO_PAUSE (or 0) to pause playing or AUDIO_RESUME (or + any value different from 0) to resume playing. + ) + Note. After calling EVAL_AUDIO_PauseResume() function for pause, only EVAL_AUDIO_PauseResume() should be called + for resume (it is not allowed to call EVAL_AUDIO_Play() in this case). + Note. This function should be called only when the audio file is played or paused (not stopped). + + - For each mode, you may need to implement the relative callback functions into your code. + The Callback functions are named EVAL_AUDIO_XXX_CallBack() and only their prototypes are declared in + the stm322xg_eval_audio_codec.h file. (refer to the example for more details on the callbacks implementations) + + - To Stop playing, to modify the volume level or to mute, use the functions + EVAL_AUDIO_Stop(), EVAL_AUDIO_VolumeCtl() and EVAL_AUDIO_Mute(). + + - The driver API and the callback functions are at the end of the stm322xg_eval_audio_codec.h file. + + + Driver architecture: + -------------------- + This driver is composed of three main layers: + o High Audio Layer: consists of the function API exported in the stm322xg_eval_audio_codec.h file + (EVAL_AUDIO_Init(), EVAL_AUDIO_Play() ...) + o Codec Control layer: consists of the functions API controlling the audio codec (CS43L22) and + included as local functions in file stm322xg_eval_audio_codec.c (Codec_Init(), Codec_Play() ...) + o Media Access Layer (MAL): which consists of functions allowing to access the media containing/ + providing the audio file/stream. These functions are also included as local functions into + the stm322xg_eval_audio_codec.c file (Audio_MAL_Init(), Audio_MAL_Play() ...) + Each set of functions (layer) may be implemented independently of the others and customized when + needed. + +2. Modes description: +--------------------- + + AUDIO_MAL_MODE_NORMAL : is suitable when the audio file is in a memory location. + + AUDIO_MAL_MODE_CIRCULAR: is suitable when the audio data are read either from a + memory location or from a device at real time (double buffer could be used). + +3. DMA interrupts description: +------------------------------ + + EVAL_AUDIO_IT_TC_ENABLE: Enable this define to use the DMA end of transfer interrupt. + then, a callback should be implemented by user to perform specific actions + when the DMA has finished the transfer. + + EVAL_AUDIO_IT_HT_ENABLE: Enable this define to use the DMA end of half transfer interrupt. + then, a callback should be implemented by user to perform specific actions + when the DMA has reached the half of the buffer transfer (generally, it is useful + to load the first half of buffer while DMA is loading from the second half). + + EVAL_AUDIO_IT_ER_ENABLE: Enable this define to manage the cases of error on DMA transfer. + +4. Known Limitations: +--------------------- + 1- When using the Speaker, if the audio file quality is not high enough, the speaker output + may produce high and uncomfortable noise level. To avoid this issue, to use speaker + output properly, try to increase audio file sampling rate (typically higher than 48KHz). + This operation will lead to larger file size. + 2- Communication with the audio codec (through I2C) may be corrupted if it is interrupted by some + user interrupt routines (in this case, interrupts could be disabled just before the start of + communication then re-enabled when it is over). Note that this communication is only done at + the configuration phase (EVAL_AUDIO_Init() or EVAL_AUDIO_Stop()) and when Volume control modification is + performed (EVAL_AUDIO_VolumeCtl() or EVAL_AUDIO_Mute()). When the audio data is played, no communication is + required with the audio codec. + 3- Parsing of audio file is not implemented (in order to determine audio file properties: Mono/Stereo, Data size, + File size, Audio Frequency, Audio Data header size ...). The configuration is fixed for the given audio file. + 4- Mono audio streaming is not supported (in order to play mono audio streams, each data should be sent twice + on the I2S or should be duplicated on the source buffer. Or convert the stream in stereo before playing). + 5- Supports only 16-bit audio data size. +===============================================================================================================================*/ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval_audio_codec.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_AUDIO_CODEC + * @brief This file includes the low layer driver for CS43L22 Audio Codec + * available on STM322xG-EVAL evaluation board(MB786) RevA and RevB. + * @{ + */ + +/** @defgroup STM322xG_EVAL_AUDIO_CODEC_Private_Types + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_AUDIO_CODEC_Private_Defines + * @{ + */ + +/* Mask for the bit EN of the I2S CFGR register */ +#define I2S_ENABLE_MASK 0x0400 + +/* Delay for the Codec to be correctly reset */ +#define CODEC_RESET_DELAY 0x4FFF + +/* Codec audio Standards */ +#ifdef I2S_STANDARD_PHILLIPS + #define CODEC_STANDARD 0x04 + #define I2S_STANDARD I2S_Standard_Phillips +#elif defined(I2S_STANDARD_MSB) + #define CODEC_STANDARD 0x00 + #define I2S_STANDARD I2S_Standard_MSB +#elif defined(I2S_STANDARD_LSB) + #define CODEC_STANDARD 0x08 + #define I2S_STANDARD I2S_Standard_LSB +#else + #error "Error: No audio communication standard selected !" +#endif /* I2S_STANDARD */ + +/* The 7 bits Codec address (sent through I2C interface) */ +#define CODEC_ADDRESS 0x94 /* b00100111 */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_AUDIO_CODEC_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_AUDIO_CODEC_Private_Variables + * @{ + */ +/* This structure is declared global because it is handled by two different functions */ +static DMA_InitTypeDef DMA_InitStructure; +DMA_InitTypeDef AUDIO_MAL_DMA_InitStructure; + +uint32_t AudioTotalSize = 0xFFFF; /* This variable holds the total size of the audio file */ +uint32_t AudioRemSize = 0xFFFF; /* This variable holds the remaining data in audio file */ +uint16_t *CurrentPos; /* This variable holds the current position of audio pointer */ + +__IO uint32_t CODECTimeout = CODEC_LONG_TIMEOUT; +__IO uint8_t OutputDev = 0; + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_AUDIO_CODEC_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_AUDIO_CODEC_Private_Functions + * @{ + */ + +/*----------------------------------- + Audio Codec functions + ------------------------------------------*/ +/* High Layer codec functions */ +static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq); +static uint32_t Codec_DeInit(void); +static uint32_t Codec_Play(void); +static uint32_t Codec_PauseResume(uint32_t Cmd); +static uint32_t Codec_Stop(uint32_t Cmd); +static uint32_t Codec_VolumeCtrl(uint8_t Volume); +static uint32_t Codec_Mute(uint32_t Cmd); +/* Low layer codec functions */ +static void Codec_CtrlInterface_Init(void); +static void Codec_CtrlInterface_DeInit(void); +static void Codec_AudioInterface_Init(uint32_t AudioFreq); +static void Codec_AudioInterface_DeInit(void); +static void Codec_Reset(void); +static uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue); +static uint32_t Codec_ReadRegister(uint8_t RegisterAddr); +static void Codec_GPIO_Init(void); +static void Codec_GPIO_DeInit(void); +static void Delay(__IO uint32_t nCount); +/*----------------------------------------------------------------------------*/ + +/*----------------------------------- + MAL (Media Access Layer) functions + ------------------------------------------*/ +/* Peripherals configuration functions */ +static void Audio_MAL_Init(void); +static void Audio_MAL_DeInit(void); +static void Audio_MAL_Play(uint32_t Addr, uint32_t Size); +static void Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr); +static void Audio_MAL_Stop(void); +/*----------------------------------------------------------------------------*/ + +/** + * @brief Configure the audio peripherals. + * @param OutputDevice: OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE, + * OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO . + * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max)) + * @param AudioFreq: Audio frequency used to play the audio stream. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq) +{ + /* Perform low layer Codec initialization */ + if (Codec_Init(OutputDevice, VOLUME_CONVERT(Volume), AudioFreq) != 0) + { + return 1; + } + else + { + /* I2S data transfer preparation: + Prepare the Media to be used for the audio transfer from memory to I2S peripheral */ + Audio_MAL_Init(); + + /* Return 0 when all operations are OK */ + return 0; + } +} + +/** + * @brief Deinitializes all the resources used by the codec (those initialized + * by EVAL_AUDIO_Init() function) EXCEPT the I2C resources since they are + * used by the IOExpander as well (and eventually other modules). + * @param None + * @retval 0 if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_DeInit(void) +{ + /* DeInitialize the Media layer */ + Audio_MAL_DeInit(); + + /* DeInitialize Codec */ + Codec_DeInit(); + + return 0; +} + +/** + * @brief Starts playing audio stream from a data buffer for a determined size. + * @param pBuffer: Pointer to the buffer + * @param Size: Number of audio data BYTES. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size) +{ + /* Set the total number of data to be played (count in half-word) */ + AudioTotalSize = Size/2; + + /* Call the audio Codec Play function */ + Codec_Play(); + + /* Update the Media layer and enable it for play */ + Audio_MAL_Play((uint32_t)pBuffer, (uint32_t)(DMA_MAX(AudioTotalSize / 2))); + + /* Update the remaining number of data to be played */ + AudioRemSize = (Size/2) - DMA_MAX(AudioTotalSize); + + /* Update the current audio pointer position */ + CurrentPos = pBuffer + DMA_MAX(AudioTotalSize); + + return 0; +} + +/** + * @brief This function Pauses or Resumes the audio file stream. In case + * of using DMA, the DMA Pause feature is used. In all cases the I2S + * peripheral is disabled. + * + * @WARNING When calling EVAL_AUDIO_PauseResume() function for pause, only + * this function should be called for resume (use of EVAL_AUDIO_Play() + * function for resume could lead to unexpected behavior). + * + * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different + * from 0) to resume. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd) +{ + /* Call the Audio Codec Pause/Resume function */ + if (Codec_PauseResume(Cmd) != 0) + { + return 1; + } + else + { + /* Call the Media layer pause/resume function */ + Audio_MAL_PauseResume(Cmd, 0); + + /* Return 0 if all operations are OK */ + return 0; + } +} + +/** + * @brief Stops audio playing and Power down the Audio Codec. + * @param Option: could be one of the following parameters + * - CODEC_PDWN_SW: for software power off (by writing registers). + * Then no need to reconfigure the Codec after power on. + * - CODEC_PDWN_HW: completely shut down the codec (physically). + * Then need to reconfigure the Codec after power on. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_Stop(uint32_t Option) +{ + /* Call Audio Codec Stop function */ + if (Codec_Stop(Option) != 0) + { + return 1; + } + else + { + /* Call Media layer Stop function */ + Audio_MAL_Stop(); + + /* Update the remaining data number */ + AudioRemSize = AudioTotalSize; + + /* Return 0 when all operations are correctly done */ + return 0; + } +} + +/** + * @brief Controls the current audio volume level. + * @param Volume: Volume level to be set in percentage from 0% to 100% (0 for + * Mute and 100 for Max volume level). + * @retval 0 if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume) +{ + /* Call the codec volume control function with converted volume value */ + return (Codec_VolumeCtrl(VOLUME_CONVERT(Volume))); +} + +/** + * @brief Enables or disables the MUTE mode by software + * @param Command: could be AUDIO_MUTE_ON to mute sound or AUDIO_MUTE_OFF to + * unmute the codec and restore previous volume level. + * @retval 0 if correct communication, else wrong communication + */ +uint32_t EVAL_AUDIO_Mute(uint32_t Cmd) +{ + /* Call the Codec Mute function */ + return (Codec_Mute(Cmd)); +} + +/** + * @brief This function handles main Media layer interrupt. + * @param None + * @retval 0 if correct communication, else wrong communication + */ +void Audio_MAL_IRQHandler(void) +{ +#ifndef AUDIO_MAL_MODE_NORMAL + uint16_t *pAddr = (uint16_t *)CurrentPos; + uint32_t Size = AudioRemSize; +#endif /* AUDIO_MAL_MODE_NORMAL */ + +#ifdef AUDIO_MAL_DMA_IT_TC_EN + /* Transfer complete interrupt */ + if (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC) != RESET) + { + #ifdef AUDIO_MAL_MODE_NORMAL + /* Check if the end of file has been reached */ + if (AudioRemSize > 0) + { + /* Wait the DMA Stream to be effectively disabled */ + while (DMA_GetCmdStatus(AUDIO_MAL_DMA_STREAM) != DISABLE) + {} + + /* Clear the Interrupt flag */ + DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC); + + /* Re-Configure the buffer address and size */ + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) CurrentPos; + DMA_InitStructure.DMA_BufferSize = (uint32_t) (DMA_MAX(AudioRemSize)); + + /* Configure the DMA Stream with the new parameters */ + DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure); + + /* Enable the I2S DMA Stream*/ + DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE); + + /* Update the current pointer position */ + CurrentPos += DMA_MAX(AudioRemSize); + + /* Update the remaining number of data to be played */ + AudioRemSize -= DMA_MAX(AudioRemSize); + } + else + { + /* Disable the I2S DMA Stream*/ + DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE); + + /* Clear the Interrupt flag */ + DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC); + + /* Manage the remaining file size and new address offset: This function + should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */ + EVAL_AUDIO_TransferComplete_CallBack((uint32_t)CurrentPos, 0); + } + + #elif defined(AUDIO_MAL_MODE_CIRCULAR) + /* Manage the remaining file size and new address offset: This function + should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */ + EVAL_AUDIO_TransferComplete_CallBack(pAddr, Size); + + /* Clear the Interrupt flag */ + DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC); + #endif /* AUDIO_MAL_MODE_NORMAL */ + } +#endif /* AUDIO_MAL_DMA_IT_TC_EN */ + +#ifdef AUDIO_MAL_DMA_IT_HT_EN + /* Half Transfer complete interrupt */ + if (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_HT) != RESET) + { + /* Manage the remaining file size and new address offset: This function + should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */ + EVAL_AUDIO_HalfTransfer_CallBack((uint32_t)pAddr, Size); + + /* Clear the Interrupt flag */ + DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_HT); + } +#endif /* AUDIO_MAL_DMA_IT_HT_EN */ + +#ifdef AUDIO_MAL_DMA_IT_TE_EN + /* FIFO Error interrupt */ + if ((DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TE) != RESET) || \ + (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_FE) != RESET) || \ + (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_DME) != RESET)) + + { + /* Manage the error generated on DMA FIFO: This function + should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */ + EVAL_AUDIO_Error_CallBack((uint32_t*)&pAddr); + + /* Clear the Interrupt flag */ + DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TE | AUDIO_MAL_DMA_FLAG_FE | \ + AUDIO_MAL_DMA_FLAG_DME); + } +#endif /* AUDIO_MAL_DMA_IT_TE_EN */ +} + +/*======================== + + CS43L22 Audio Codec Control Functions + ==============================*/ +/** + * @brief Initializes the audio codec and all related interfaces (control + * interface: I2C and audio interface: I2S) + * @param OutputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE, + * OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO . + * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max)) + * @param AudioFreq: Audio frequency used to play the audio stream. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq) +{ + uint32_t counter = 0; + + /* Configure the Codec related IOs */ + Codec_GPIO_Init(); + + /* Reset the Codec Registers */ + Codec_Reset(); + + /* Initialize the Control interface of the Audio Codec */ + Codec_CtrlInterface_Init(); + + /* Keep Codec powered OFF */ + counter += Codec_WriteRegister(0x02, 0x01); + + switch (OutputDevice) + { + case OUTPUT_DEVICE_SPEAKER: + counter += Codec_WriteRegister(0x04, 0xFA); /* SPK always ON & HP always OFF */ + OutputDev = 0xFA; + break; + + case OUTPUT_DEVICE_HEADPHONE: + counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */ + OutputDev = 0xAF; + break; + + case OUTPUT_DEVICE_BOTH: + counter += Codec_WriteRegister(0x04, 0xAA); /* SPK always ON & HP always ON */ + OutputDev = 0xAA; + break; + + case OUTPUT_DEVICE_AUTO: + counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */ + OutputDev = 0x05; + break; + + default: + counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */ + OutputDev = 0x05; + break; + } + + /* Clock configuration: Auto detection */ + counter += Codec_WriteRegister(0x05, 0x81); + + /* Set the Slave Mode and the audio Standard */ + counter += Codec_WriteRegister(0x06, CODEC_STANDARD); + + /* Set the Master volume */ + Codec_VolumeCtrl(Volume); + + /* If the Speaker is enabled, set the Mono mode and volume attenuation level */ + if (OutputDevice != OUTPUT_DEVICE_HEADPHONE) + { + /* Set the Speaker Mono mode */ + counter += Codec_WriteRegister(0x0F , 0x06); + + /* Set the Speaker attenuation level */ + counter += Codec_WriteRegister(0x24, 0x00); + counter += Codec_WriteRegister(0x25, 0x00); + } + + /* Power on the Codec */ + counter += Codec_WriteRegister(0x02, 0x9E); + + /* Additional configuration for the CODEC. These configurations are done to reduce + the time needed for the Codec to power off. If these configurations are removed, + then a long delay should be added between powering off the Codec and switching + off the I2S peripheral MCLK clock (which is the operating clock for Codec). + If this delay is not inserted, then the codec will not shut down properly and + it results in high noise after shut down. */ + + /* Disable the analog soft ramp */ + counter += Codec_WriteRegister(0x0A, 0x00); + /* Disable the digital soft ramp */ + counter += Codec_WriteRegister(0x0E, 0x04); + /* Disable the limiter attack level */ + counter += Codec_WriteRegister(0x27, 0x00); + /* Adjust Bass and Treble levels */ + counter += Codec_WriteRegister(0x1F, 0x0F); + /* Adjust PCM volume level */ + counter += Codec_WriteRegister(0x1A, 0x0A); + counter += Codec_WriteRegister(0x1B, 0x0A); + + /* Configure the I2S peripheral */ + Codec_AudioInterface_Init(AudioFreq); + + /* Return communication control value */ + return counter; +} + +/** + * @brief Restore the audio codec state to default state and free all used + * resources. + * @param None + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t Codec_DeInit(void) +{ + uint32_t counter = 0; + + /* Reset the Codec Registers */ + Codec_Reset(); + + /* Keep Codec powered OFF */ + counter += Codec_WriteRegister(0x02, 0x01); + + /* Deinitialize all use GPIOs */ + Codec_GPIO_DeInit(); + + /* Disable the Codec control interface */ + Codec_CtrlInterface_DeInit(); + + /* Deinitialize the Codec audio interface (I2S) */ + Codec_AudioInterface_DeInit(); + + /* Return communication control value */ + return counter; +} + +/** + * @brief Start the audio Codec play feature. + * @note For this codec no Play options are required. + * @param None + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t Codec_Play(void) +{ + /* + No actions required on Codec level for play command + */ + + /* Return communication control value */ + return 0; +} + +/** + * @brief Pauses and resumes playing on the audio codec. + * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different + * from 0) to resume. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t Codec_PauseResume(uint32_t Cmd) +{ + uint32_t counter = 0; + + /* Pause the audio file playing */ + if (Cmd == AUDIO_PAUSE) + { + /* Mute the output first */ + counter += Codec_Mute(AUDIO_MUTE_ON); + + /* Put the Codec in Power save mode */ + counter += Codec_WriteRegister(0x02, 0x01); + } + else /* AUDIO_RESUME */ + { + /* Unmute the output first */ + counter += Codec_Mute(AUDIO_MUTE_OFF); + + counter += Codec_WriteRegister(0x04, OutputDev); + + /* Exit the Power save mode */ + counter += Codec_WriteRegister(0x02, 0x9E); + } + + return counter; +} + +/** + * @brief Stops audio Codec playing. It powers down the codec. + * @param CodecPdwnMode: selects the power down mode. + * - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this + * mode the codec keeps the previous initialization + * (no need to re-Initialize the codec registers). + * - CODEC_PDWN_HW: Physically power down the codec. When resuming from this + * mode, the codec is set to default configuration + * (user should re-Initialize the codec in order to + * play again the audio stream). + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t Codec_Stop(uint32_t CodecPdwnMode) +{ + uint32_t counter = 0; + + /* Mute the output first */ + Codec_Mute(AUDIO_MUTE_ON); + + if (CodecPdwnMode == CODEC_PDWN_SW) + { + /* Power down the DAC and the speaker (PMDAC and PMSPK bits)*/ + counter += Codec_WriteRegister(0x02, 0x9F); + } + else /* CODEC_PDWN_HW */ + { + /* Power down the DAC components */ + counter += Codec_WriteRegister(0x02, 0x9F); + + /* Wait at least 100us */ + Delay(0xFFF); + + /* Reset The pin */ + IOE_WriteIOPin(AUDIO_RESET_PIN, BitReset); + } + + return counter; +} + +/** + * @brief Sets higher or lower the codec volume level. + * @param Volume: a byte value from 0 to 255 (refer to codec registers + * description for more details). + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t Codec_VolumeCtrl(uint8_t Volume) +{ + uint32_t counter = 0; + + if (Volume > 0xE6) + { + /* Set the Master volume */ + counter += Codec_WriteRegister(0x20, Volume - 0xE7); + counter += Codec_WriteRegister(0x21, Volume - 0xE7); + } + else + { + /* Set the Master volume */ + counter += Codec_WriteRegister(0x20, Volume + 0x19); + counter += Codec_WriteRegister(0x21, Volume + 0x19); + } + + return counter; +} + +/** + * @brief Enables or disables the mute feature on the audio codec. + * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the + * mute mode. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t Codec_Mute(uint32_t Cmd) +{ + uint32_t counter = 0; + + /* Set the Mute mode */ + if (Cmd == AUDIO_MUTE_ON) + { + counter += Codec_WriteRegister(0x04, 0xFF); + } + else /* AUDIO_MUTE_OFF Disable the Mute */ + { + counter += Codec_WriteRegister(0x04, OutputDev); + } + + return counter; +} + +/** + * @brief Resets the audio codec. It restores the default configuration of the + * codec (this function shall be called before initializing the codec). + * @note This function calls an external driver function: The IO Expander driver. + * @param None + * @retval None + */ +static void Codec_Reset(void) +{ + /* Configure the IO Expander (to use the Codec Reset pin mapped on the IOExpander) */ + IOE_Config(); + + /* Power Down the codec */ + IOE_WriteIOPin(AUDIO_RESET_PIN, BitReset); + + /* wait for a delay to insure registers erasing */ + Delay(CODEC_RESET_DELAY); + + /* Power on the codec */ + IOE_WriteIOPin(AUDIO_RESET_PIN, BitSet); +} + +/** + * @brief Switch dynamically (while audio file is played) the output target + * (speaker or headphone). + * @note This function modifies a global variable of the audio codec driver: OutputDev. + * @param Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER, + * OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO + * @retval 0 if correct communication, else wrong communication + */ +uint32_t Codec_SwitchOutput(uint8_t Output) +{ + uint8_t counter = 0; + + switch (Output) + { + case OUTPUT_DEVICE_SPEAKER: + counter += Codec_WriteRegister(0x04, 0xFA); /* SPK always ON & HP always OFF */ + OutputDev = 0xFA; + break; + + case OUTPUT_DEVICE_HEADPHONE: + counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */ + OutputDev = 0xAF; + break; + + case OUTPUT_DEVICE_BOTH: + counter += Codec_WriteRegister(0x04, 0xAA); /* SPK always ON & HP always ON */ + OutputDev = 0xAA; + break; + + case OUTPUT_DEVICE_AUTO: + counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */ + OutputDev = 0x05; + break; + + default: + counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */ + OutputDev = 0x05; + break; + } + + return counter; +} + +/** + * @brief Writes a Byte to a given register into the audio codec through the + control interface (I2C) + * @param RegisterAddr: The address (location) of the register to be written. + * @param RegisterValue: the Byte value to be written into destination register. + * @retval 0 if correct communication, else wrong communication + */ +static uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue) +{ + uint32_t result = 0; + + /*!< While the bus is busy */ + CODECTimeout = CODEC_LONG_TIMEOUT; + while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BUSY)) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /* Start the config sequence */ + I2C_GenerateSTART(CODEC_I2C, ENABLE); + + /* Test on EV5 and clear it */ + CODECTimeout = CODEC_FLAG_TIMEOUT; + while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT)) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /* Transmit the slave address and enable writing operation */ + I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Transmitter); + + /* Test on EV6 and clear it */ + CODECTimeout = CODEC_FLAG_TIMEOUT; + while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /* Transmit the first address for write operation */ + I2C_SendData(CODEC_I2C, RegisterAddr); + + /* Test on EV8 and clear it */ + CODECTimeout = CODEC_FLAG_TIMEOUT; + while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING)) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /* Prepare the register value to be sent */ + I2C_SendData(CODEC_I2C, RegisterValue); + + /*!< Wait till all data have been physically transferred on the bus */ + CODECTimeout = CODEC_LONG_TIMEOUT; + while(!I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BTF)) + { + if((CODECTimeout--) == 0) Codec_TIMEOUT_UserCallback(); + } + + /* End the configuration sequence */ + I2C_GenerateSTOP(CODEC_I2C, ENABLE); + +#ifdef VERIFY_WRITTENDATA + /* Verify that the data has been correctly written */ + result = (Codec_ReadRegister(RegisterAddr) == RegisterValue)? 0:1; +#endif /* VERIFY_WRITTENDATA */ + + /* Return the verifying value: 0 (Passed) or 1 (Failed) */ + return result; +} + +/** + * @brief Reads and returns the value of an audio codec register through the + * control interface (I2C). + * @param RegisterAddr: Address of the register to be read. + * @retval Value of the register to be read or dummy value if the communication + * fails. + */ +static uint32_t Codec_ReadRegister(uint8_t RegisterAddr) +{ + uint32_t result = 0; + + /*!< While the bus is busy */ + CODECTimeout = CODEC_LONG_TIMEOUT; + while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BUSY)) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /* Start the config sequence */ + I2C_GenerateSTART(CODEC_I2C, ENABLE); + + /* Test on EV5 and clear it */ + CODECTimeout = CODEC_FLAG_TIMEOUT; + while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT)) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /* Transmit the slave address and enable writing operation */ + I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Transmitter); + + /* Test on EV6 and clear it */ + CODECTimeout = CODEC_FLAG_TIMEOUT; + while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /* Transmit the register address to be read */ + I2C_SendData(CODEC_I2C, RegisterAddr); + + /* Test on EV8 and clear it */ + CODECTimeout = CODEC_FLAG_TIMEOUT; + while (I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BTF) == RESET) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /*!< Send STRAT condition a second time */ + I2C_GenerateSTART(CODEC_I2C, ENABLE); + + /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */ + CODECTimeout = CODEC_FLAG_TIMEOUT; + while(!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT)) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /*!< Send Codec address for read */ + I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Receiver); + + /* Wait on ADDR flag to be set (ADDR is still not cleared at this level */ + CODECTimeout = CODEC_FLAG_TIMEOUT; + while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_ADDR) == RESET) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /*!< Disable Acknowledgment */ + I2C_AcknowledgeConfig(CODEC_I2C, DISABLE); + + /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */ + (void)CODEC_I2C->SR2; + + /*!< Send STOP Condition */ + I2C_GenerateSTOP(CODEC_I2C, ENABLE); + + /* Wait for the byte to be received */ + CODECTimeout = CODEC_FLAG_TIMEOUT; + while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_RXNE) == RESET) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /*!< Read the byte received from the Codec */ + result = I2C_ReceiveData(CODEC_I2C); + + /* Wait to make sure that STOP flag has been cleared */ + CODECTimeout = CODEC_FLAG_TIMEOUT; + while(CODEC_I2C->CR1 & I2C_CR1_STOP) + { + if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); + } + + /*!< Re-Enable Acknowledgment to be ready for another reception */ + I2C_AcknowledgeConfig(CODEC_I2C, ENABLE); + + /* Clear AF flag for next communication */ + I2C_ClearFlag(CODEC_I2C, I2C_FLAG_AF); + + /* Return the byte read from Codec */ + return result; +} + +/** + * @brief Initializes the Audio Codec control interface (I2C). + * @param None + * @retval None + */ +static void Codec_CtrlInterface_Init(void) +{ + I2C_InitTypeDef I2C_InitStructure; + + /* Enable the CODEC_I2C peripheral clock */ + RCC_APB1PeriphClockCmd(CODEC_I2C_CLK, ENABLE); + + /* If the I2C peripheral is already enabled, don't reconfigure it */ + if ((CODEC_I2C->CR1 & I2C_CR1_PE) != 0) + { + /* CODEC_I2C peripheral configuration */ + I2C_DeInit(CODEC_I2C); + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStructure.I2C_OwnAddress1 = 0x33; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + + /* Enable the I2C peripheral */ + I2C_Cmd(CODEC_I2C, ENABLE); + + /* Initialize the I2C peripheral */ + I2C_Init(CODEC_I2C, &I2C_InitStructure); + } +} + +/** + * @brief Restore the Audio Codec control interface to its default state. + * This function doesn't de-initialize the I2C because the I2C peripheral + * may be used by other modules. + * @param None + * @retval None + */ +static void Codec_CtrlInterface_DeInit(void) +{ + /* Disable the I2C peripheral */ /* This step is not done here because + the I2C interface can be used by other modules */ + /* I2C_DeInit(CODEC_I2C); */ +} + +/** + * @brief Initializes the Audio Codec audio interface (I2S) + * @note This function assumes that the I2S input clock (through PLL_R in + * Devices RevA/Z and through dedicated PLLI2S_R in Devices RevB/Y) + * is already configured and ready to be used. + * @param AudioFreq: Audio frequency to be configured for the I2S peripheral. + * @retval None + */ +static void Codec_AudioInterface_Init(uint32_t AudioFreq) +{ + I2S_InitTypeDef I2S_InitStructure; + + /* Enable the CODEC_I2S peripheral clock */ + RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, ENABLE); + + /* CODEC_I2S peripheral configuration */ + SPI_I2S_DeInit(CODEC_I2S); + I2S_InitStructure.I2S_AudioFreq = AudioFreq; + I2S_InitStructure.I2S_Standard = I2S_STANDARD; + I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b; + I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low; + I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx; +#ifdef CODEC_MCLK_ENABLED + I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable; +#elif defined(CODEC_MCLK_DISABLED) + I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable; +#else + #error "No selection for the MCLK output has been defined !" +#endif /* CODEC_MCLK_ENABLED */ + + /* Initialize the I2S peripheral with the structure above */ + I2S_Init(CODEC_I2S, &I2S_InitStructure); + + /* The I2S peripheral will be enabled only in the EVAL_AUDIO_Play() function + or by user functions if DMA mode not enabled */ +} + +/** + * @brief Restores the Audio Codec audio interface to its default state. + * @param None + * @retval None + */ +static void Codec_AudioInterface_DeInit(void) +{ + /* Disable the CODEC_I2S peripheral (in case it hasn't already been disabled) */ + I2S_Cmd(CODEC_I2S, DISABLE); + + /* Deinitialize the CODEC_I2S peripheral */ + SPI_I2S_DeInit(CODEC_I2S); + + /* Disable the CODEC_I2S peripheral clock */ + RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, DISABLE); +} + +/** + * @brief Initializes IOs used by the Audio Codec (on the control and audio + * interfaces). + * @param None + * @retval None + */ +static void Codec_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable I2S and I2C GPIO clocks */ + RCC_AHB1PeriphClockCmd(CODEC_I2C_GPIO_CLOCK | CODEC_I2S_GPIO_CLOCK, ENABLE); + + /* CODEC_I2C SCL and SDA pins configuration -------------------------------------*/ + /* If the I2C peripheral is already enabled, don't reconfigure it */ + if ((CODEC_I2C->CR1 & I2C_CR1_PE) != 0) + { + GPIO_InitStructure.GPIO_Pin = CODEC_I2C_SCL_PIN | CODEC_I2C_SDA_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(CODEC_I2C_GPIO, &GPIO_InitStructure); + /* Connect pins to Periph */ + GPIO_PinAFConfig(CODEC_I2C_GPIO, CODEC_I2S_SCL_PINSRC, CODEC_I2C_GPIO_AF); + GPIO_PinAFConfig(CODEC_I2C_GPIO, CODEC_I2S_SDA_PINSRC, CODEC_I2C_GPIO_AF); + } + + /* CODEC_I2S pins configuration: WS, SCK and SD pins -----------------------------*/ + GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN | CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure); + /* Connect pins to I2S peripheral */ + GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_WS_PINSRC, CODEC_I2S_GPIO_AF); + GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, CODEC_I2S_GPIO_AF); + GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SD_PINSRC, CODEC_I2S_GPIO_AF); + + #ifdef CODEC_MCLK_ENABLED + /* CODEC_I2S pins configuration: MCK pin */ + GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure); + /* Connect pins to I2S peripheral */ + GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF); + #endif /* CODEC_MCLK_ENABLED */ +} + +/** + * @brief Restores the IOs used by the Audio Codec interface to their default state. + * @param None + * @retval None + */ +static void Codec_GPIO_DeInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Deinitialize all the GPIOs used by the driver (EXCEPT the I2C IOs since + they are used by the IOExpander as well) */ + GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN | CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure); + /* Disconnect pins from I2S peripheral */ + GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_WS_PIN, 0x00); + GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PIN, 0x00); + GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SD_PIN, 0x00); + +#ifdef CODEC_MCLK_ENABLED + /* CODEC_I2S pins deinitialization: MCK pin */ + GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN; + GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure); + /* Disconnect pins from I2S peripheral */ + GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF); +#endif /* CODEC_MCLK_ENABLED */ +} + +/** + * @brief Inserts a delay time (not accurate timing). + * @param nCount: specifies the delay time length. + * @retval None + */ +static void Delay( __IO uint32_t nCount) +{ + for (; nCount != 0; nCount--); +} + +#ifdef USE_DEFAULT_TIMEOUT_CALLBACK +/** + * @brief Basic management of the timeout situation. + * @param None + * @retval None + */ +uint32_t Codec_TIMEOUT_UserCallback(void) +{ + /* The following code allows I2C error recovery and return to normal communication + if the error source doesn’t still exist (ie. hardware issue..) */ + I2C_InitTypeDef I2C_InitStructure; + + /* LCD_ErrLog("> I2C Timeout error occurred\n"); */ + + I2C_GenerateSTOP(CODEC_I2C, ENABLE); + I2C_SoftwareResetCmd(CODEC_I2C, ENABLE); + I2C_SoftwareResetCmd(CODEC_I2C, DISABLE); + + /* CODEC_I2C peripheral configuration */ + I2C_DeInit(CODEC_I2C); + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStructure.I2C_OwnAddress1 = 0x33; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + /* Enable the I2C peripheral */ + I2C_Cmd(CODEC_I2C, ENABLE); + I2C_Init(CODEC_I2C, &I2C_InitStructure); + + /* At this stage the I2C error should be recovered and device can communicate + again (except if the error source still exist). + User can implement mechanism (ex. test on max trial number) to manage situation + when the I2C can't recover from current error. */ + + /* LCD_UsrLog("> I2C error recovered.\n"); */ + + return 0; +} +#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */ +/*======================== + + Audio MAL Interface Control Functions + + ==============================*/ + +/** + * @brief Initializes and prepares the Media to perform audio data transfer + * from Media to the I2S peripheral. + * @param None + * @retval None + */ +static void Audio_MAL_Init(void) +{ +#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN) + NVIC_InitTypeDef NVIC_InitStructure; +#endif + + /* Enable the DMA clock */ + RCC_AHB1PeriphClockCmd(AUDIO_MAL_DMA_CLOCK, ENABLE); + + /* Configure the DMA Stream */ + DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE); + DMA_DeInit(AUDIO_MAL_DMA_STREAM); + /* Set the parameters to be configured */ + DMA_InitStructure.DMA_Channel = AUDIO_MAL_DMA_CHANNEL; + DMA_InitStructure.DMA_PeripheralBaseAddr = CODEC_I2S_ADDRESS; + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; /* This field will be configured in play function */ + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE; /* This field will be configured in play function */ + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = AUDIO_MAL_DMA_PERIPH_DATA_SIZE; + DMA_InitStructure.DMA_MemoryDataSize = AUDIO_MAL_DMA_MEM_DATA_SIZE; +#ifdef AUDIO_MAL_MODE_NORMAL + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; +#elif defined(AUDIO_MAL_MODE_CIRCULAR) + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; +#else + #error "AUDIO_MAL_MODE_NORMAL or AUDIO_MAL_MODE_CIRCULAR should be selected !!" +#endif /* AUDIO_MAL_MODE_NORMAL */ + DMA_InitStructure.DMA_Priority = DMA_Priority_High; + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure); + + /* Enable the selected DMA interrupts (selected in "stm32_eval_audio_codec.h" defines) */ +#ifdef AUDIO_MAL_DMA_IT_TC_EN + DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TC, ENABLE); +#endif /* AUDIO_MAL_DMA_IT_TC_EN */ +#ifdef AUDIO_MAL_DMA_IT_HT_EN + DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_HT, ENABLE); +#endif /* AUDIO_MAL_DMA_IT_HT_EN */ +#ifdef AUDIO_MAL_DMA_IT_TE_EN + DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TE | DMA_IT_FE | DMA_IT_DME, ENABLE); +#endif /* AUDIO_MAL_DMA_IT_TE_EN */ + + /* Enable the I2S DMA request */ + SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE); + +#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN) + /* I2S DMA IRQ Channel configuration */ + NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +#endif +} + +/** + * @brief Restore default state of the used Media. + * @param None + * @retval None + */ +static void Audio_MAL_DeInit(void) +{ +#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN) + NVIC_InitTypeDef NVIC_InitStructure; + + /* Deinitialize the NVIC interrupt for the I2S DMA Stream */ + NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO; + NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; + NVIC_Init(&NVIC_InitStructure); +#endif + + /* Disable the DMA stream before the deinit */ + DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE); + + /* Dinitialize the DMA Stream */ + DMA_DeInit(AUDIO_MAL_DMA_STREAM); + + /* + The DMA clock is not disabled, since it can be used by other streams + */ +} + +/** + * @brief Starts playing audio stream from the audio Media. + * @param None + * @retval None + */ +static void Audio_MAL_Play(uint32_t Addr, uint32_t Size) +{ + /* Configure the buffer address and size */ + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)Addr; + DMA_InitStructure.DMA_BufferSize = (uint32_t)Size; + + /* Configure the DMA Stream with the new parameters */ + DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure); + + /* Enable the I2S DMA Stream*/ + DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE); + + /* If the I2S peripheral is still not enabled, enable it */ + if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0) + { + I2S_Cmd(CODEC_I2S, ENABLE); + } +} + +/** + * @brief Pauses or Resumes the audio stream playing from the Media. + * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different + * from 0) to resume. + * @param Addr: Address from/at which the audio stream should resume/pause. + * @retval None + */ +static void Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr) +{ + /* Pause the audio file playing */ + if (Cmd == AUDIO_PAUSE) + { + /* Disable the I2S DMA request */ + SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, DISABLE); + + /* Pause the I2S DMA Stream + Note. For the STM32F2xx devices, the DMA implements a pause feature, + by disabling the stream, all configuration is preserved and data + transfer is paused till the next enable of the stream.*/ + DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE); + } + else /* AUDIO_RESUME */ + { + /* Enable the I2S DMA request */ + SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE); + + /* Resume the I2S DMA Stream + Note. For the STM32F2xx devices, the DMA implements a pause feature, + by disabling the stream, all configuration is preserved and data + transfer is paused till the next enable of the stream.*/ + DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE); + + /* If the I2S peripheral is still not enabled, enable it */ + if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0) + { + I2S_Cmd(CODEC_I2S, ENABLE); + } + } +} + +/** + * @brief Stops audio stream playing on the used Media. + * @param None + * @retval None + */ +static void Audio_MAL_Stop(void) +{ + /* Stop the Transfer on the I2S side: Stop and disable the DMA stream */ + DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE); + + /* Clear all the DMA flags for the next transfer */ + DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC |AUDIO_MAL_DMA_FLAG_HT | \ + AUDIO_MAL_DMA_FLAG_FE | AUDIO_MAL_DMA_FLAG_TE); + + /* + The I2S DMA requests are not disabled here. + */ + + /* In all modes, disable the I2S peripheral */ + I2S_Cmd(CODEC_I2S, DISABLE); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_audio_codec.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_audio_codec.h new file mode 100644 index 000000000..b648678fa --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_audio_codec.h @@ -0,0 +1,278 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_audio_codec.h + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file contains all the functions prototypes for the + * stm322xg_eval_audio_codec.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM322xG_EVAL_AUDIOCODEC_H +#define __STM322xG_EVAL_AUDIOCODEC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" +#include "stm322xg_eval_ioe.h" /* IOExpander driver is included in order to allow + CS43L22 codec reset pin managment on the + evaluation board */ + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @defgroup STM322xG_EVAL_AUDIO_CODEC + * @{ + */ + + +/** @defgroup STM322xG_EVAL_AUDIO_CODEC_Exported_Types + * @{ + */ + +/** @defgroup STM322xG_EVAL_AUDIO_CODEC_Exported_Constants + * @{ + */ + +/*------------------------------------ + CONFIGURATION: Audio Codec Driver Configuration parameters + ----------------------------------------*/ +/* Audio Transfer mode (DMA, Interrupt or Polling) */ +#define AUDIO_MAL_MODE_NORMAL /* Uncomment this line to enable the audio + Transfer using DMA */ +/* #define AUDIO_MAL_MODE_CIRCULAR */ /* Uncomment this line to enable the audio + Transfer using DMA */ + +/* For the DMA modes select the interrupt that will be used */ +#define AUDIO_MAL_DMA_IT_TC_EN /* Uncomment this line to enable DMA Transfer Complete interrupt */ +/* #define AUDIO_MAL_DMA_IT_HT_EN */ /* Uncomment this line to enable DMA Half Transfer Complete interrupt */ +/* #define AUDIO_MAL_DMA_IT_TE_EN */ /* Uncomment this line to enable DMA Transfer Error interrupt */ + +/* Select the interrupt preemption priority and subpriority for the DMA interrupt */ +#define EVAL_AUDIO_IRQ_PREPRIO 0 /* Select the preemption priority level(0 is the highest) */ +#define EVAL_AUDIO_IRQ_SUBRIO 0 /* Select the sub-priority level (0 is the highest) */ + +/* Uncomment the following line to use the default Codec_TIMEOUT_UserCallback() + function implemented in stm322xg_eval_audio_codec.c file. + Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition + occurs during communication (waiting on an event that doesn't occur, bus + errors, busy devices ...). */ +/* #define USE_DEFAULT_TIMEOUT_CALLBACK */ +/*----------------------------------------------------------------------------*/ + +/*------------------------------------ + OPTIONAL Configuration defines parameters + ----------------------------------------*/ +/* I2C clock speed configuration (in Hz) + WARNING: + Make sure that this define is not already declared in other files (ie. + stm322xg_eval.h file). It can be used in parallel by other modules. */ +#ifndef I2C_SPEED + #define I2C_SPEED 100000 +#endif /* I2C_SPEED */ + +/* Uncomment defines below to select standard for audio communication between + Codec and I2S peripheral */ +#define I2S_STANDARD_PHILLIPS +/* #define I2S_STANDARD_MSB */ +/* #define I2S_STANDARD_LSB */ + +/* Uncomment the defines below to select if the Master clock mode should be + enabled or not */ +#define CODEC_MCLK_ENABLED +/* #deine CODEC_MCLK_DISABLED */ + +/* Uncomment this line to enable verifying data sent to codec after each write + operation */ +#define VERIFY_WRITTENDATA +/*----------------------------------------------------------------------------*/ + +/*----------------------------------- + Hardware Configuration defines parameters + -----------------------------------------*/ +/* I2S peripheral configuration defines */ +#define CODEC_I2S SPI2 +#define CODEC_I2S_CLK RCC_APB1Periph_SPI2 +#define CODEC_I2S_ADDRESS 0x4000380C +#define CODEC_I2S_GPIO_AF GPIO_AF_SPI2 +#define CODEC_I2S_IRQ SPI2_IRQn +#define CODEC_I2S_GPIO_CLOCK (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOI) +#define CODEC_I2S_WS_PIN GPIO_Pin_0 +#define CODEC_I2S_SCK_PIN GPIO_Pin_1 +#define CODEC_I2S_SD_PIN GPIO_Pin_3 +#define CODEC_I2S_MCK_PIN GPIO_Pin_6 +#define CODEC_I2S_WS_PINSRC GPIO_PinSource0 +#define CODEC_I2S_SCK_PINSRC GPIO_PinSource1 +#define CODEC_I2S_SD_PINSRC GPIO_PinSource3 +#define CODEC_I2S_MCK_PINSRC GPIO_PinSource6 +#define CODEC_I2S_GPIO GPIOI +#define CODEC_I2S_MCK_GPIO GPIOC + + + /* I2S DMA Stream definitions */ + #define AUDIO_MAL_DMA_CLOCK RCC_AHB1Periph_DMA1 + #define AUDIO_MAL_DMA_STREAM DMA1_Stream4 + #define AUDIO_MAL_DMA_CHANNEL DMA_Channel_0 + #define AUDIO_MAL_DMA_IRQ DMA1_Stream4_IRQn + #define AUDIO_MAL_DMA_FLAG_TC DMA_FLAG_TCIF4 + #define AUDIO_MAL_DMA_FLAG_HT DMA_FLAG_HTIF4 + #define AUDIO_MAL_DMA_FLAG_FE DMA_FLAG_FEIF4 + #define AUDIO_MAL_DMA_FLAG_TE DMA_FLAG_TEIF4 + #define AUDIO_MAL_DMA_FLAG_DME DMA_FLAG_DMEIF4 + #define AUDIO_MAL_DMA_PERIPH_DATA_SIZE DMA_PeripheralDataSize_HalfWord + #define AUDIO_MAL_DMA_MEM_DATA_SIZE DMA_MemoryDataSize_HalfWord + #define DMA_MAX_SZE 0xFFFF + + #define Audio_MAL_IRQHandler DMA1_Stream4_IRQHandler + +/* I2C peripheral configuration defines (control interface of the audio codec) */ +#define CODEC_I2C I2C1 +#define CODEC_I2C_CLK RCC_APB1Periph_I2C1 +#define CODEC_I2C_GPIO_CLOCK RCC_AHB1Periph_GPIOB +#define CODEC_I2C_GPIO_AF GPIO_AF_I2C1 +#define CODEC_I2C_GPIO GPIOB +#define CODEC_I2C_SCL_PIN GPIO_Pin_6 +#define CODEC_I2C_SDA_PIN GPIO_Pin_9 +#define CODEC_I2S_SCL_PINSRC GPIO_PinSource6 +#define CODEC_I2S_SDA_PINSRC GPIO_PinSource9 + +/* Maximum Timeout values for flags and events waiting loops. These timeouts are + not based on accurate values, they just guarantee that the application will + not remain stuck if the I2C communication is corrupted. + You may modify these timeout values depending on CPU frequency and application + conditions (interrupts routines ...). */ +#define CODEC_FLAG_TIMEOUT ((uint32_t)0x1000) +#define CODEC_LONG_TIMEOUT ((uint32_t)(300 * CODEC_FLAG_TIMEOUT)) +/*----------------------------------------------------------------------------*/ + +/*----------------------------------- + Audio Codec User defines + -----------------------------------------*/ +/* Codec output DEVICE */ +#define OUTPUT_DEVICE_SPEAKER 1 +#define OUTPUT_DEVICE_HEADPHONE 2 +#define OUTPUT_DEVICE_BOTH 3 +#define OUTPUT_DEVICE_AUTO 4 + +/* Volume Levels values */ +#define DEFAULT_VOLMIN 0x00 +#define DEFAULT_VOLMAX 0xFF +#define DEFAULT_VOLSTEP 0x04 + +#define AUDIO_PAUSE 0 +#define AUDIO_RESUME 1 + +/* Codec POWER DOWN modes */ +#define CODEC_PDWN_HW 1 +#define CODEC_PDWN_SW 2 + +/* MUTE commands */ +#define AUDIO_MUTE_ON 1 +#define AUDIO_MUTE_OFF 0 +/*----------------------------------------------------------------------------*/ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_AUDIO_CODEC_Exported_Macros + * @{ + */ +#define VOLUME_CONVERT(x) ((Volume > 100)? 100:((uint8_t)((Volume * 255) / 100))) +#define DMA_MAX(x) (((x) <= DMA_MAX_SZE)? (x):DMA_MAX_SZE) + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_AUDIO_CODEC_Exported_Functions + * @{ + */ + +uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq); +uint32_t EVAL_AUDIO_DeInit(void); +uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size); +uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd); +uint32_t EVAL_AUDIO_Stop(uint32_t CodecPowerDown_Mode); +uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume); +uint32_t EVAL_AUDIO_Mute(uint32_t Command); + +uint32_t Codec_SwitchOutput(uint8_t Output); + +/* User Callbacks: user has to implement these functions in his code if + they are needed. -----------------------------------------------------------*/ + +/* This function is called when the requested data has been completely transferred. + In Normal mode (when the define AUDIO_MAL_MODE_NORMAL is enabled) this function + is called at the end of the whole audio file. + In circular mode (when the define AUDIO_MAL_MODE_CIRCULAR is enabled) this + function is called at the end of the current buffer transmission. */ +void EVAL_AUDIO_TransferComplete_CallBack(uint32_t pBuffer, uint32_t Size); + +/* This function is called when half of the requested buffer has been transferred + This callback is useful in Circular mode only (when AUDIO_MAL_MODE_CIRCULAR + define is enabled)*/ +void EVAL_AUDIO_HalfTransfer_CallBack(uint32_t pBuffer, uint32_t Size); + +/* This function is called when an Interrupt due to transfer error on or peripheral + error occurs. */ +void EVAL_AUDIO_Error_CallBack(void* pData); + +/* Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition + occurs during communication (waiting on an event that doesn't occur, bus + errors, busy devices ...) on the Codec control interface (I2C). + You can use the default timeout callback implementation by uncommenting the + define USE_DEFAULT_TIMEOUT_CALLBACK in stm322xg_eval_audio_codec.h file. + Typically the user implementation of this callback should reset I2C peripheral + and re-initialize communication or in worst case reset all the application. */ +uint32_t Codec_TIMEOUT_UserCallback(void); + +#endif /* __STM322xG_EVAL_AUDIOCODEC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_onenand.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_onenand.c new file mode 100644 index 000000000..fa7522406 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_onenand.c @@ -0,0 +1,567 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_fsmc_onenand.c + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file provides a set of functions needed to drive the + * KFG1216U2A/B-DIB6 OneNAND memory mounted on STM322xG-EVAL evaluation + * board(MB786) RevA. + * + * Note: This memory is not available on the RevB of the board. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval_fsmc_onenand.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_FSMC_ONENAND + * @brief This file provides a set of functions needed to drive the + * KFG1216U2A/B-DIB6 OneNAND memory mounted on STM322xG-EVAL board. + * @{ + */ + +/** @defgroup STM322xG_EVAL_FSMC_ONENAND_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_ONENAND_Private_Defines + * @{ + */ +#define BANK1_ONENAND1_ADDR ((uint32_t)0x60000000) +#define ONENAND_BOOTPARTITION_ADDR ((uint32_t)BANK1_ONENAND1_ADDR) + + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_FSMC_ONENAND_Private_Macros + * @{ + */ +#define OneNAND_WRITE(Address, Data) (*(__IO uint16_t *)(Address) = (Data)) + +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_ONENAND_Private_Variables + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_ONENAND_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_ONENAND_Private_Functions + * @{ + */ + +/** + * @brief Configures the FSMC and GPIOs to interface with the OneNAND memory. + * This function must be called before any write/read operation on the + * OneNAND. + * @param None + * @retval None + */ +void OneNAND_Init(void) +{ + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + FSMC_NORSRAMTimingInitTypeDef p; + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOE | + RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOB, ENABLE); + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + +/*-- GPIO Configuration ------------------------------------------------------*/ + /* OneNAND Data lines configuration */ + GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOE, GPIO_PinSource7, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource8, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource9, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource10, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource12, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource13, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource14, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource15, GPIO_AF_FSMC); + + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | + GPIO_Pin_14 | GPIO_Pin_15 |GPIO_Pin_10; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | + GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |GPIO_Pin_15; + + GPIO_Init(GPIOE, &GPIO_InitStructure); + + /* OneNAND Address lines configuration */ + GPIO_PinAFConfig(GPIOF,GPIO_PinSource0, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource1, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource2, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource3, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource4, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource5, GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOF,GPIO_PinSource12, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource13, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource14, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource15, GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOG,GPIO_PinSource0, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource1, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource2, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource3, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource4, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource5, GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOD,GPIO_PinSource11, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource12, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource13, GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOE,GPIO_PinSource3, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource4, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource5, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource6, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource2, GPIO_AF_FSMC); + + GPIO_PinAFConfig(GPIOG,GPIO_PinSource13, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource14, GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5 |GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15; + + GPIO_Init(GPIOF, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_13 | GPIO_Pin_14; + + GPIO_Init(GPIOG, &GPIO_InitStructure); + + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; + + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4| GPIO_Pin_5 | GPIO_Pin_6; + + GPIO_Init(GPIOE, &GPIO_InitStructure); + + + /* NOE, NWE and CLK configuration */ + GPIO_PinAFConfig(GPIOD,GPIO_PinSource3, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource4, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource5, GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5 | GPIO_Pin_3; + + GPIO_Init(GPIOD, &GPIO_InitStructure); + + + /* NE1 configuration */ + GPIO_PinAFConfig(GPIOD, GPIO_PinSource7, GPIO_AF_FSMC); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /* NL configuration */ + GPIO_PinAFConfig(GPIOB,GPIO_PinSource7, GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* NWAIT Configuration */ + GPIO_PinAFConfig(GPIOD,GPIO_PinSource6, GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + /*-- FSMC Configuration ----------------------------------------------------*/ + p.FSMC_AddressSetupTime = 0x03; + p.FSMC_AddressHoldTime = 0x00; + p.FSMC_DataSetupTime = 0x0C; + p.FSMC_BusTurnAroundDuration = 0x01; + p.FSMC_CLKDivision = 0x2; + p.FSMC_DataLatency = 0x00; + p.FSMC_AccessMode = FSMC_AccessMode_B; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Enable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE); +} + +/** + * @brief Resets the OneNAND memory. + * @param None + * @retval None + */ +void OneNAND_Reset(void) +{ + OneNAND_WRITE(ONENAND_BOOTPARTITION_ADDR, OneNAND_CMD_RESET); +} + +/** + * @brief Reads OneNAND memory's Manufacturer and Device Code. + * @param OneNAND_ID: pointer to a OneNAND_IDTypeDef structure which will hold + * the Manufacturer and Device Code. + * @retval None + */ +void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID) +{ + uint16_t status = 0x0; + + /* Wait till no ongoing operation */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + + while((status & 0x8000) == 0x8000) + { + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + } + + /* Read ID data */ + OneNAND_ID->Manufacturer_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_MANUFACTERID); + OneNAND_ID->Device_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_DEVICEID); + + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION) = 0x40E0; +} + +/** + * @brief Unlocks the specified OneNAND memory block (128Kb). + * @param BlockNumber: specifies the block number to be erased. This parameter + * should be between 0 and 511. + * @retval OneNAND memory Interrupt Status. + */ +uint16_t OneNAND_UnlockBlock(uint16_t BlockNumber) +{ + uint16_t status = 0; + + /* Wait till no ongoing operation */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + + while((status & 0x8000) == 0x8000) + { + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + } + + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBLOCKADDRESS) = BlockNumber; + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000; + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_UNLOCK; + + /* Wait till the command is completed */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + + while((status & 0x8000) != 0x8000) + { + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + } + + /* Get the Controller Status */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + + return (status); +} + +/** + * @brief Erases the specified OneNAND memory block (128Kb). + * @param BlockNumber: specifies the block number to be erased. This parameter + * should be between 0 and 511. + * @retval OneNAND memory Interrupt Status. + */ +uint16_t OneNAND_EraseBlock(uint16_t BlockNumber) +{ + uint16_t status = 0x0; + + /* Wait till no ongoing operation */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + + while((status & 0x8000) == 0x8000) + { + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + } + + /* Erase operation */ + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = BlockNumber; + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000; + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_ERASE; + + /* Wait till no error is generated */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + + while((status & 0x0400) == 0x0400) + { + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + } + + /* Wait till the command is completed */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + + while((status & 0x8000) != 0x8000) + { + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + } + + /* Get the Controller Status */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + + return (status); +} + +/** + * @brief Writes a Half-word buffer to the OneNAND memory. + * @param pBuffer: pointer to buffer. + * @param WriteAddr: OneNAND memory internal address from which the data will be + * written. + * @param NumHalfwordToWrite: number of half-words to write. + * @retval OneNAND memory Controller Status. + */ +uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite) +{ + uint32_t datacounter = 0; + uint16_t status = 0; + + /* Load the buffer to be written into the DATA RAM0*/ + for(datacounter = 0; datacounter < NumHalfwordToWrite; datacounter++) + { + *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_0_0_ADD) + (2*datacounter)) = pBuffer[datacounter]; + } + + /* Write operation from DATA RAM0 to NAND address*/ + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/ + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2); /* NAND Flash start page address */ + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_0_0_REG;/* BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA).*/ + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000; + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_PROGRAM; /* Command */ + + /* Wait till the command is completed */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + + while((status & 0x8000) != 0x8000) + { + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + } + + /* Wait till the write interrupt is set */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + + while((status & 0x40) != 0x40) + { + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + } + + /* Get the Controller Status */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + + return (status); +} + +/** + * @brief Reads a block of data from the OneNAND memory using asynchronous mode. + * @param pBuffer: pointer to the buffer that receives the data read from the + * OneNAND memory. + * @param ReadAddr: OneNAND memory internal address to read from. + * @param NumHalfwordToRead: number of half-words to read. + * @retval None + */ +void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead) +{ + uint16_t datatmp = 0x0, index = 0; + __IO uint16_t status = 0; + + datatmp = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION); + + /* Set the asynchronous read mode */ + OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, (datatmp& 0x7FFF)); + + /* Load data from the read address to the DATA RAM 1 sector 1 */ + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/ + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2); + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG; + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000; + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */ + + /* Wait till the command is completed */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + + while((status & 0x8000) != 0x8000) + { + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + } + + /* Read Controller status */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + + /* Read data */ + for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */ + { + /* Read a Halfword from the memory */ + *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD)+ 2*index); + index++; + } +} + +/** + * @brief Reads a block of data from the OneNAND memory using synchronous mode. + * @param pBuffer: pointer to the buffer that receives the data read from the + * OneNAND memory. + * @param ReadAddr: OneNAND memory internal address to read from. + * @param NumHalfwordToRead: number of half-words to read. + * @retval None + */ +void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead) +{ + uint16_t index = 0; + __IO uint16_t status = 0; + + /* Set the asynchronous read mode */ + OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, 0xB4C0); + + + /* Load data from the read address to the DATA RAM 1 sector 1 */ + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/ + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2); + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG; + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000; + *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */ + + /* Wait till the command is completed */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + + while((status & 0x8000) != 0x8000) + { + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT); + } + + /* Read Controller status */ + status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS); + + /* Read data */ + for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */ + { + *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD + 2*index)); + index++; + } +} + +/** + * @brief Reads the OneNAND memory Interrupt status. + * @param None + * @retval OneNAND memory Interrupt Status. + */ +uint16_t OneNAND_ReadStatus(void) +{ + __IO uint16_t status = 0x0; + + /* Read Status */ + return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT)); +} + +/** + * @brief Reads the OneNAND Controller status. + * @param None + * @retval OneNAND Controller Status. + */ +uint16_t OneNAND_ReadControllerStatus(void) +{ + __IO uint16_t status = 0x0; + + /* Read Controller Status */ + return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_onenand.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_onenand.h new file mode 100644 index 000000000..145777dbc --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_onenand.h @@ -0,0 +1,196 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_fsmc_onenand.h + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file contains all the functions prototypes for the + * stm322xg_eval_fsmc_onenand.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM322xG_EVAL_FSMC_ONENAND_H +#define __STM322xG_EVAL_FSMC_ONENAND_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_FSMC_ONENAND + * @{ + */ + +/** @defgroup STM322xG_EVAL_FSMC_ONENAND_Exported_Types + * @{ + */ +typedef struct +{ + uint16_t Manufacturer_ID; + uint16_t Device_ID; +}OneNAND_IDTypeDef; + +/* OneNand Status */ +typedef enum +{ + OneNAND_SUCCESS = 0, + OneNAND_ONGOING, + OneNAND_ERROR, + OneNAND_TIMEOUT +}OneNAND_Status; + +typedef struct +{ + uint16_t Block; + uint16_t Page; +} OneNAND_ADDRESS; + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_FSMC_ONENAND_Exported_Constants + * @{ + */ +/** + * @brief OneNAND memory command + */ +#define OneNAND_CMD_ERASE ((uint16_t)0x0094) +#define OneNAND_CMD_PROGRAM ((uint16_t)0x0080) +#define OneNAND_CMD_RESET ((uint16_t)0x00F0) +#define OneNAND_CMD_READ_ID ((uint16_t)0x0090) +#define OneNAND_CMD_UNLOCK ((uint16_t)0x0023) +#define OneNAND_CMD_LOAD ((uint16_t)0x0000) + +/** + * @brief OneNand Register description + */ +#define OneNAND_REG_MANUFACTERID ((uint32_t)0x1E000) /* Manufacturer identification */ +#define OneNAND_REG_DEVICEID ((uint32_t)0x1E002) /* Device identification */ +#define OneNAND_REG_DATABUFFERSIZE ((uint32_t)0x1E006) /* Data Buffer size */ +#define OneNAND_REG_BOOTBUFFERSIZE ((uint32_t)0x1E008) /* Boot Buffer size */ +#define OneNAND_REG_AMOUNTOFBUFFERS ((uint32_t)0x1E00A) /* Amount of data/boot buffers */ +#define OneNAND_REG_TECHNOLOGY ((uint32_t)0x1E00C) /* Info about technology */ +#define OneNAND_REG_STARTADDRESS1 ((uint32_t)0x1E200) /* Nand Flash Block Address */ +#define OneNAND_REG_STARTADDRESS3 ((uint32_t)0x1E204) /* Destination Block address for copy back program */ +#define OneNAND_REG_STARTADDRESS4 ((uint32_t)0x1E206) /* Destination Page & sector address for copy back program */ +#define OneNAND_REG_STARTADDRESINT8_T ((uint32_t)0x1E20E) /* Nand Flash Page & sector address */ +#define OneNAND_REG_STARTBUFFER ((uint32_t)0x1E400) /* The meaning is with which buffer to start and how many + buffers to use for the data transfer */ +#define OneNAND_REG_COMMAND ((uint32_t)0x1E440) /* Host control and memory operation commands*/ +#define OneNAND_REG_SYSTEMCONFIGURATION ((uint32_t)0x1E442) /* Memory and host interface configuration */ +#define OneNAND_REG_CONTROLSTATUS ((uint32_t)0x1E480) /* Control status and result of memory operation */ +#define OneNAND_REG_INTERRUPT ((uint32_t)0x1E482) /* Memory Command Completion Interrupt Status */ +#define OneNAND_REG_STARTBLOCKADDRESS ((uint32_t)0x1E498) /* Start memory block address in Write Protection mode */ +#define OneNAND_REG_WRITEPROTECTIONSTATUS ((uint32_t)0x1E49C) /* Current memory Write Protection status */ + +/** + * @brief OneNand Memory partition description + */ +#define OneNAND_DATA_RAM_0_0_ADD ((uint32_t)0x0400) /* DataRAM Main page0/sector0 */ +#define OneNAND_DATA_RAM_0_0_REG ((uint32_t)0x0800) /* DataRAM 0_0 is selected with 4 sector */ + +#define OneNAND_DATA_RAM_0_1_ADD ((uint32_t)0x0600) /* DataRAM Main page0/sector1 */ +#define OneNAND_DATA_RAM_0_1_REG ((uint32_t)0x0900) /* DataRAM 0_1 is selected with 4 sector */ + +#define OneNAND_DATA_RAM_0_2_ADD ((uint32_t)0x0800) /* DataRAM Main page0/sector2 */ +#define OneNAND_DATA_RAM_0_2_REG ((uint32_t)0x0A00) /* DataRAM 0_2 is selected with 4 sector */ + +#define OneNAND_DATA_RAM_0_3_ADD ((uint32_t)0x0A00) /* DataRAM Main page0/sector3 */ +#define OneNAND_DATA_RAM_0_3_REG ((uint32_t)0x0B00) /* DataRAM 0_3 is selected with 4 sector */ + +#define OneNAND_DATA_RAM_1_0_ADD ((uint32_t)0x0C00) /* DataRAM Main page1/sector0 */ +#define OneNAND_DATA_RAM_1_0_REG ((uint32_t)0x0C00) /* DataRAM 1_0 is selected with 4 sector */ + +#define OneNAND_DATA_RAM_1_1_ADD ((uint32_t)0x0E00) /* DataRAM Main page1/sector1 */ +#define OneNAND_DATA_RAM_1_1_REG ((uint32_t)0x0D00) /* DataRAM 1_1 is selected with 4 sector */ + +#define OneNAND_DATA_RAM_1_2_ADD ((uint32_t)0x1000) /* DataRAM Main page1/sector2 */ +#define OneNAND_DATA_RAM_1_2_REG ((uint32_t)0x0E00) /* DataRAM 1_2 is selected with 4 sector */ + +#define OneNAND_DATA_RAM_1_3_ADD ((uint32_t)0x1200) /* DataRAM Main page1/sector3 */ +#define OneNAND_DATA_RAM_1_3_REG ((uint32_t)0x0F00) /* DataRAM 1_3 is selected with 4 sector */ + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_FSMC_ONENAND_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_FSMC_ONENAND_Exported_Functions + * @{ + */ +void OneNAND_Init(void); +void OneNAND_Reset(void); +void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID); +uint16_t OneNAND_UnlockBlock(uint16_t BlockNumber); +uint16_t OneNAND_EraseBlock(uint16_t BlockNumber); +uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite); +void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead); +void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead); +uint16_t OneNAND_ReadStatus(void); +uint16_t OneNAND_ReadControllerStatus(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM322xG_EVAL_FSMC_ONENAND_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_psram.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_psram.c new file mode 100644 index 000000000..c31dc64da --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_psram.c @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_fsmc_psram.c + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file provides a set of functions needed to drive the IS66WV25616BLL + * PSRAM memory mounted on STM322xG-EVAL evaluation board(MB786) RevA. + * + * Note: This memory is not available on the RevB of the board. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval_fsmc_psram.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_FSMC_PSRAM + * @brief This file provides a set of functions needed to drive the + * IS66WV25616BLL PSRAM memory mounted on STM322xG-EVAL board. + * @{ + */ + +/** @defgroup STM322xG_EVAL_FSMC_PSRAM_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_PSRAM_Private_Defines + * @{ + */ +/** + * @brief FSMC Bank 1 NOR/SRAM2 + */ +#define Bank1_SRAM2_ADDR ((uint32_t)0x64000000) +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_PSRAM_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_PSRAM_Private_Variables + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_PSRAM_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_PSRAM_Private_Functions + * @{ + */ + +/** + * @brief Configures the FSMC and GPIOs to interface with the PSRAM memory. + * This function must be called before any write/read operation + * on the PSRAM. + * @param None + * @retval None + */ +void PSRAM_Init(void) +{ + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + FSMC_NORSRAMTimingInitTypeDef p; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIOs clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | + RCC_AHB1Periph_GPIOG, ENABLE); + + /* Enable FSMC clock */ + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + +/*-- GPIOs Configuration ------------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + PSRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* GPIOD configuration */ + GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | + GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | + GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + + GPIO_Init(GPIOD, &GPIO_InitStructure); + + + /* GPIOE configuration */ + GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | + GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11| + GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + + GPIO_Init(GPIOE, &GPIO_InitStructure); + + + /* GPIOF configuration */ + GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5 | + GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + + GPIO_Init(GPIOF, &GPIO_InitStructure); + + + /* GPIOG configuration */ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource2 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource3 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource9 , GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5 |GPIO_Pin_9; + + GPIO_Init(GPIOG, &GPIO_InitStructure); + +/*-- FSMC Configuration ------------------------------------------------------*/ + p.FSMC_AddressSetupTime = 0x2; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 0xB; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + /*!< Enable FSMC Bank1_SRAM2 Bank */ + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); +} + +/** + * @brief Writes a Half-word buffer to the FSMC PSRAM memory. + * @param pBuffer : pointer to buffer. + * @param WriteAddr : PSRAM memory internal address from which the data will be + * written. + * @param NumHalfwordToWrite : number of half-words to write. + * @retval None + */ +void PSRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite) +{ + for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /* while there is data to write */ + { + /* Transfer data to the memory */ + *(uint16_t *) (Bank1_SRAM2_ADDR + WriteAddr) = *pBuffer++; + + /* Increment the address*/ + WriteAddr += 2; + } +} + +/** + * @brief Reads a block of data from the FSMC PSRAM memory. + * @param pBuffer : pointer to the buffer that receives the data read from the + * PSRAM memory. + * @param ReadAddr : PSRAM memory internal address to read from. + * @param NumHalfwordToRead : number of half-words to read. + * @retval None + */ +void PSRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead) +{ + for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /* while there is data to read */ + { + /* Read a half-word from the memory */ + *pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM2_ADDR + ReadAddr); + + /* Increment the address*/ + ReadAddr += 2; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_psram.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_psram.h new file mode 100644 index 000000000..629db1b60 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_psram.h @@ -0,0 +1,110 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_fsmc_psram.h + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file contains all the functions prototypes for the + * stm322xg_eval_fsmc_psram.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM322xG_EVAL_FSMC_PSRAM_H +#define __STM322xG_EVAL_FSMC_PSRAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_FSMC_PSRAM + * @{ + */ + +/** @defgroup STM322xG_EVAL_FSMC_PSRAM_Exported_Types + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_FSMC_PSRAM_Exported_Constants + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_FSMC_PSRAM_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_FSMC_PSRAM_Exported_Functions + * @{ + */ + +void PSRAM_Init(void); +void PSRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite); +void PSRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM322xG_EVAL_FSMC_PSRAM_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_sram.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_sram.c new file mode 100644 index 000000000..558db9f6a --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_sram.c @@ -0,0 +1,321 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_fsmc_sram.c + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file provides a set of functions needed to drive the + * IS61WV102416BLL SRAM memory mounted on STM322xG-EVAL evaluation + * board(MB786) RevB. + * + * Note: This memory is not available on the RevA of the board. + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval_fsmc_sram.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_FSMC_SRAM + * @brief This file provides a set of functions needed to drive the + * IS61WV102416BLL SRAM memory mounted on STM322xG-EVAL board. + * @{ + */ + +/** @defgroup STM322xG_EVAL_FSMC_SRAM_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_SRAM_Private_Defines + * @{ + */ +/** + * @brief FSMC Bank 1 NOR/SRAM2 + */ +#define Bank1_SRAM2_ADDR ((uint32_t)0x64000000) + +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_SRAM_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_SRAM_Private_Variables + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_SRAM_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_FSMC_SRAM_Private_Functions + * @{ + */ + +/** + * @brief Configures the FSMC and GPIOs to interface with the SRAM memory. + * This function must be called before any write/read operation + * on the SRAM. + * @param None + * @retval None + */ +void SRAM_Init(void) +{ + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + FSMC_NORSRAMTimingInitTypeDef p; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIOs clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | + RCC_AHB1Periph_GPIOG, ENABLE); + + /* Enable FSMC clock */ + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE2 <-> FSMC_A23 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE3 <-> FSMC_A19 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE4 <-> FSMC_A20 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE5 <-> FSMC_A21 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE6 <-> FSMC_A22 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE7 <-> FSMC_D4 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE8 <-> FSMC_D5 | PF14 <-> FSMC_A8 | + | PD13 <-> FSMC_A18 | PE9 <-> FSMC_D6 | PF15 <-> FSMC_A9 | + | PD14 <-> FSMC_D0 | PE10 <-> FSMC_D7 |------------------+ + | PD15 <-> FSMC_D1 | PE11 <-> FSMC_D8 | + +-------------------| PE12 <-> FSMC_D9 | + | PE13 <-> FSMC_D10 | + | PE14 <-> FSMC_D11 | + | PE15 <-> FSMC_D12 | + +--------------------+ +*/ + + /* GPIOD configuration */ + GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | + GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | + GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + + GPIO_Init(GPIOD, &GPIO_InitStructure); + + + /* GPIOE configuration */ + GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource2 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource3 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource4 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource5 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource6 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 | + GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11| + GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + + GPIO_Init(GPIOE, &GPIO_InitStructure); + + + /* GPIOF configuration */ + GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15; + + GPIO_Init(GPIOF, &GPIO_InitStructure); + + + /* GPIOG configuration */ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource2 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource3 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource9 , GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5 |GPIO_Pin_9; + + GPIO_Init(GPIOG, &GPIO_InitStructure); + +/*-- FSMC Configuration ------------------------------------------------------*/ + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + /*!< Enable FSMC Bank1_SRAM2 Bank */ + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); + +} + +/** + * @brief Writes a Half-word buffer to the FSMC SRAM memory. + * @param pBuffer : pointer to buffer. + * @param WriteAddr : SRAM memory internal address from which the data will be + * written. + * @param NumHalfwordToWrite : number of half-words to write. + * @retval None + */ +void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite) +{ + for (; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /* while there is data to write */ + { + /* Transfer data to the memory */ + *(uint16_t *) (Bank1_SRAM2_ADDR + WriteAddr) = *pBuffer++; + + /* Increment the address*/ + WriteAddr += 2; + } +} + +/** + * @brief Reads a block of data from the FSMC SRAM memory. + * @param pBuffer : pointer to the buffer that receives the data read from the + * SRAM memory. + * @param ReadAddr : SRAM memory internal address to read from. + * @param NumHalfwordToRead : number of half-words to read. + * @retval None + */ +void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead) +{ + for (; NumHalfwordToRead != 0; NumHalfwordToRead--) /* while there is data to read */ + { + /* Read a half-word from the memory */ + *pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM2_ADDR + ReadAddr); + + /* Increment the address*/ + ReadAddr += 2; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_sram.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_sram.h new file mode 100644 index 000000000..b0dff7ccd --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_fsmc_sram.h @@ -0,0 +1,110 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_fsmc_sram.h + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file contains all the functions prototypes for the + * stm322xg_eval_fsmc_sram.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM322xG_EVAL_FSMC_SRAM_H +#define __STM322xG_EVAL_FSMC_SRAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_FSMC_SRAM + * @{ + */ + +/** @defgroup STM322xG_EVAL_FSMC_SRAM_Exported_Types + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_FSMC_SRAM_Exported_Constants + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_FSMC_SRAM_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_FSMC_SRAM_Exported_Functions + * @{ + */ + +void SRAM_Init(void); +void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite); +void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM322xG_EVAL_FSMC_SRAM_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_i2c_ee.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_i2c_ee.c new file mode 100644 index 000000000..13336a18e --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_i2c_ee.c @@ -0,0 +1,814 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_i2c_ee.c + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file provides a set of functions needed to manage the I2C M24CXX + * EEPROM memory mounted on STM322xG-EVAL evaluation board(MB786) RevA + * and RevB. + * + * =================================================================== + * Note: This driver is intended for STM32F2xx families devices only. + * =================================================================== + * + * It implements a high level communication layer for read and write + * from/to this memory. The needed STM32 hardware resources (I2C and + * GPIO) are defined in stm322xg_eval.h file, and the initialization is + * performed in sEE_LowLevel_Init() function declared in stm322xg_eval.c + * file. + * You can easily tailor this driver to any other development board, + * by just adapting the defines for hardware resources and + * sEE_LowLevel_Init() function. + * + * @note In this driver, basic read and write functions (sEE_ReadBuffer() + * and sEE_WritePage()) use the DMA to perform the data transfer + * to/from EEPROM memory (except when number of requested data is + * equal to 1). Thus, after calling these two functions, user + * application may perform other tasks while DMA is transferring + * data. The application should then monitor the variable holding + * the number of data in order to determine when the transfer is + * completed (variable decremented to 0). Stopping transfer tasks + * are performed into DMA interrupt handlers (which are integrated + * into this driver). + * + * +-----------------------------------------------------------------+ + * | Pin assignment | + * +---------------------------------------+-----------+-------------+ + * | STM32 I2C Pins | sEE | Pin | + * +---------------------------------------+-----------+-------------+ + * | . | E0(GND) | 1 (0V) | + * | . | E1(GND) | 2 (0V) | + * | . | E2(GND) | 3 (0V) | + * | . | E0(VSS) | 4 (0V) | + * | sEE_I2C_SDA_PIN/ SDA | SDA | 5 | + * | sEE_I2C_SCL_PIN/ SCL | SCL | 6 | + * | . | /WC(VDD)| 7 (3.3V) | + * | . | VDD | 8 (3.3V) | + * +---------------------------------------+-----------+-------------+ + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval_i2c_ee.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_I2C_EE + * @brief This file includes the I2C EEPROM driver of STM32-EVAL boards. + * @{ + */ + +/** @defgroup STM322xG_EVAL_I2C_EE_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_I2C_EE_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_I2C_EE_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_I2C_EE_Private_Variables + * @{ + */ +__IO uint16_t sEEAddress = 0; +__IO uint32_t sEETimeout = sEE_LONG_TIMEOUT; +__IO uint16_t* sEEDataReadPointer; +__IO uint8_t* sEEDataWritePointer; +__IO uint8_t sEEDataNum; +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_I2C_EE_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_I2C_EE_Private_Functions + * @{ + */ + +/** + * @brief DeInitializes peripherals used by the I2C EEPROM driver. + * @param None + * @retval None + */ +void sEE_DeInit(void) +{ + sEE_LowLevel_DeInit(); +} + +/** + * @brief Initializes peripherals used by the I2C EEPROM driver. + * @param None + * @retval None + */ +void sEE_Init(void) +{ + I2C_InitTypeDef I2C_InitStructure; + + sEE_LowLevel_Init(); + + /*!< I2C configuration */ + /* sEE_I2C configuration */ + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStructure.I2C_OwnAddress1 = I2C_SLAVE_ADDRESS7; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + + /* sEE_I2C Peripheral Enable */ + I2C_Cmd(sEE_I2C, ENABLE); + /* Apply sEE_I2C configuration after enabling it */ + I2C_Init(sEE_I2C, &I2C_InitStructure); + + /* Enable the sEE_I2C peripheral DMA requests */ + I2C_DMACmd(sEE_I2C, ENABLE); + +#if defined (sEE_M24C64_32) + /*!< Select the EEPROM address according to the state of E0, E1, E2 pins */ + sEEAddress = sEE_HW_ADDRESS; +#elif defined (sEE_M24C08) + /*!< depending on the sEE Address selected in the stm322xg_eval_i2c_ee.h file */ + #ifdef sEE_Block0_ADDRESS + /*!< Select the sEE Block0 to write on */ + sEEAddress = sEE_Block0_ADDRESS; + #endif + + #ifdef sEE_Block1_ADDRESS + /*!< Select the sEE Block1 to write on */ + sEEAddress = sEE_Block1_ADDRESS; + #endif + + #ifdef sEE_Block2_ADDRESS + /*!< Select the sEE Block2 to write on */ + sEEAddress = sEE_Block2_ADDRESS; + #endif + + #ifdef sEE_Block3_ADDRESS + /*!< Select the sEE Block3 to write on */ + sEEAddress = sEE_Block3_ADDRESS; + #endif +#endif /*!< sEE_M24C64_32 */ +} + +/** + * @brief Reads a block of data from the EEPROM. + * @param pBuffer : pointer to the buffer that receives the data read from + * the EEPROM. + * @param ReadAddr : EEPROM's internal address to start reading from. + * @param NumByteToRead : pointer to the variable holding number of bytes to + * be read from the EEPROM. + * + * @note The variable pointed by NumByteToRead is reset to 0 when all the + * data are read from the EEPROM. Application should monitor this + * variable in order know when the transfer is complete. + * + * @note When number of data to be read is higher than 1, this function just + * configures the communication and enable the DMA channel to transfer data. + * Meanwhile, the user application may perform other tasks. + * When number of data to be read is 1, then the DMA is not used. The byte + * is read in polling mode. + * + * @retval sEE_OK (0) if operation is correctly performed, else return value + * different from sEE_OK (0) or the timeout user callback. + */ +uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead) +{ + /* Set the pointer to the Number of data to be read. This pointer will be used + by the DMA Transfer Completer interrupt Handler in order to reset the + variable to 0. User should check on this variable in order to know if the + DMA transfer has been complete or not. */ + sEEDataReadPointer = NumByteToRead; + + /*!< While the bus is busy */ + sEETimeout = sEE_LONG_TIMEOUT; + while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Send START condition */ + I2C_GenerateSTART(sEE_I2C, ENABLE); + + /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Send EEPROM address for write */ + I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter); + + /*!< Test on EV6 and clear it */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + +#ifdef sEE_M24C08 + + /*!< Send the EEPROM's internal address to read from: Only one byte address */ + I2C_SendData(sEE_I2C, ReadAddr); + +#elif defined (sEE_M24C64_32) + + /*!< Send the EEPROM's internal address to read from: MSB of the address first */ + I2C_SendData(sEE_I2C, (uint8_t)((ReadAddr & 0xFF00) >> 8)); + + /*!< Test on EV8 and clear it */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Send the EEPROM's internal address to read from: LSB of the address */ + I2C_SendData(sEE_I2C, (uint8_t)(ReadAddr & 0x00FF)); + +#endif /*!< sEE_M24C08 */ + + /*!< Test on EV8 and clear it */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF) == RESET) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Send STRAT condition a second time */ + I2C_GenerateSTART(sEE_I2C, ENABLE); + + /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Send EEPROM address for read */ + I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Receiver); + + /* If number of data to be read is 1, then DMA couldn't be used */ + /* One Byte Master Reception procedure (POLLING) ---------------------------*/ + if ((uint16_t)(*NumByteToRead) < 2) + { + /* Wait on ADDR flag to be set (ADDR is still not cleared at this level */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_ADDR) == RESET) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Disable Acknowledgment */ + I2C_AcknowledgeConfig(sEE_I2C, DISABLE); + + /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */ + (void)sEE_I2C->SR2; + + /*!< Send STOP Condition */ + I2C_GenerateSTOP(sEE_I2C, ENABLE); + + /* Wait for the byte to be received */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_RXNE) == RESET) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Read the byte received from the EEPROM */ + *pBuffer = I2C_ReceiveData(sEE_I2C); + + /*!< Decrement the read bytes counter */ + (uint16_t)(*NumByteToRead)--; + + /* Wait to make sure that STOP control bit has been cleared */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(sEE_I2C->CR1 & I2C_CR1_STOP) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Re-Enable Acknowledgment to be ready for another reception */ + I2C_AcknowledgeConfig(sEE_I2C, ENABLE); + } + else/* More than one Byte Master Reception procedure (DMA) -----------------*/ + { + /*!< Test on EV6 and clear it */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /* Configure the DMA Rx Channel with the buffer address and the buffer size */ + sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint16_t)(*NumByteToRead), sEE_DIRECTION_RX); + + /* Inform the DMA that the next End Of Transfer Signal will be the last one */ + I2C_DMALastTransferCmd(sEE_I2C, ENABLE); + + /* Enable the DMA Rx Stream */ + DMA_Cmd(sEE_I2C_DMA_STREAM_RX, ENABLE); + } + + /* If all operations OK, return sEE_OK (0) */ + return sEE_OK; +} + +/** + * @brief Writes more than one byte to the EEPROM with a single WRITE cycle. + * + * @note The number of bytes (combined to write start address) must not + * cross the EEPROM page boundary. This function can only write into + * the boundaries of an EEPROM page. + * This function doesn't check on boundaries condition (in this driver + * the function sEE_WriteBuffer() which calls sEE_WritePage() is + * responsible of checking on Page boundaries). + * + * @param pBuffer : pointer to the buffer containing the data to be written to + * the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @param NumByteToWrite : pointer to the variable holding number of bytes to + * be written into the EEPROM. + * + * @note The variable pointed by NumByteToWrite is reset to 0 when all the + * data are written to the EEPROM. Application should monitor this + * variable in order know when the transfer is complete. + * + * @note This function just configure the communication and enable the DMA + * channel to transfer data. Meanwhile, the user application may perform + * other tasks in parallel. + * + * @retval sEE_OK (0) if operation is correctly performed, else return value + * different from sEE_OK (0) or the timeout user callback. + */ +uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite) +{ + /* Set the pointer to the Number of data to be written. This pointer will be used + by the DMA Transfer Completer interrupt Handler in order to reset the + variable to 0. User should check on this variable in order to know if the + DMA transfer has been complete or not. */ + sEEDataWritePointer = NumByteToWrite; + + /*!< While the bus is busy */ + sEETimeout = sEE_LONG_TIMEOUT; + while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Send START condition */ + I2C_GenerateSTART(sEE_I2C, ENABLE); + + /*!< Test on EV5 and clear it */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Send EEPROM address for write */ + sEETimeout = sEE_FLAG_TIMEOUT; + I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter); + + /*!< Test on EV6 and clear it */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + +#ifdef sEE_M24C08 + + /*!< Send the EEPROM's internal address to write to : only one byte Address */ + I2C_SendData(sEE_I2C, WriteAddr); + +#elif defined(sEE_M24C64_32) + + /*!< Send the EEPROM's internal address to write to : MSB of the address first */ + I2C_SendData(sEE_I2C, (uint8_t)((WriteAddr & 0xFF00) >> 8)); + + /*!< Test on EV8 and clear it */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Send the EEPROM's internal address to write to : LSB of the address */ + I2C_SendData(sEE_I2C, (uint8_t)(WriteAddr & 0x00FF)); + +#endif /*!< sEE_M24C08 */ + + /*!< Test on EV8 and clear it */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /* Configure the DMA Tx Channel with the buffer address and the buffer size */ + sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint8_t)(*NumByteToWrite), sEE_DIRECTION_TX); + + /* Enable the DMA Tx Stream */ + DMA_Cmd(sEE_I2C_DMA_STREAM_TX, ENABLE); + + /* If all operations OK, return sEE_OK (0) */ + return sEE_OK; +} + +/** + * @brief Writes buffer of data to the I2C EEPROM. + * @param pBuffer : pointer to the buffer containing the data to be written + * to the EEPROM. + * @param WriteAddr : EEPROM's internal address to write to. + * @param NumByteToWrite : number of bytes to write to the EEPROM. + * @retval None + */ +void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) +{ + uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0; + uint16_t Addr = 0; + + Addr = WriteAddr % sEE_PAGESIZE; + count = sEE_PAGESIZE - Addr; + NumOfPage = NumByteToWrite / sEE_PAGESIZE; + NumOfSingle = NumByteToWrite % sEE_PAGESIZE; + + /*!< If WriteAddr is sEE_PAGESIZE aligned */ + if(Addr == 0) + { + /*!< If NumByteToWrite < sEE_PAGESIZE */ + if(NumOfPage == 0) + { + /* Store the number of data to be written */ + sEEDataNum = NumOfSingle; + /* Start writing data */ + sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); + /* Wait transfer through DMA to be complete */ + sEETimeout = sEE_LONG_TIMEOUT; + while (sEEDataNum > 0) + { + if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; + } + sEE_WaitEepromStandbyState(); + } + /*!< If NumByteToWrite > sEE_PAGESIZE */ + else + { + while(NumOfPage--) + { + /* Store the number of data to be written */ + sEEDataNum = sEE_PAGESIZE; + sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); + /* Wait transfer through DMA to be complete */ + sEETimeout = sEE_LONG_TIMEOUT; + while (sEEDataNum > 0) + { + if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; + } + sEE_WaitEepromStandbyState(); + WriteAddr += sEE_PAGESIZE; + pBuffer += sEE_PAGESIZE; + } + + if(NumOfSingle!=0) + { + /* Store the number of data to be written */ + sEEDataNum = NumOfSingle; + sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); + /* Wait transfer through DMA to be complete */ + sEETimeout = sEE_LONG_TIMEOUT; + while (sEEDataNum > 0) + { + if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; + } + sEE_WaitEepromStandbyState(); + } + } + } + /*!< If WriteAddr is not sEE_PAGESIZE aligned */ + else + { + /*!< If NumByteToWrite < sEE_PAGESIZE */ + if(NumOfPage== 0) + { + /*!< If the number of data to be written is more than the remaining space + in the current page: */ + if (NumByteToWrite > count) + { + /* Store the number of data to be written */ + sEEDataNum = count; + /*!< Write the data contained in same page */ + sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); + /* Wait transfer through DMA to be complete */ + sEETimeout = sEE_LONG_TIMEOUT; + while (sEEDataNum > 0) + { + if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; + } + sEE_WaitEepromStandbyState(); + + /* Store the number of data to be written */ + sEEDataNum = (NumByteToWrite - count); + /*!< Write the remaining data in the following page */ + sEE_WritePage((uint8_t*)(pBuffer + count), (WriteAddr + count), (uint8_t*)(&sEEDataNum)); + /* Wait transfer through DMA to be complete */ + sEETimeout = sEE_LONG_TIMEOUT; + while (sEEDataNum > 0) + { + if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; + } + sEE_WaitEepromStandbyState(); + } + else + { + /* Store the number of data to be written */ + sEEDataNum = NumOfSingle; + sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); + /* Wait transfer through DMA to be complete */ + sEETimeout = sEE_LONG_TIMEOUT; + while (sEEDataNum > 0) + { + if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; + } + sEE_WaitEepromStandbyState(); + } + } + /*!< If NumByteToWrite > sEE_PAGESIZE */ + else + { + NumByteToWrite -= count; + NumOfPage = NumByteToWrite / sEE_PAGESIZE; + NumOfSingle = NumByteToWrite % sEE_PAGESIZE; + + if(count != 0) + { + /* Store the number of data to be written */ + sEEDataNum = count; + sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); + /* Wait transfer through DMA to be complete */ + sEETimeout = sEE_LONG_TIMEOUT; + while (sEEDataNum > 0) + { + if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; + } + sEE_WaitEepromStandbyState(); + WriteAddr += count; + pBuffer += count; + } + + while(NumOfPage--) + { + /* Store the number of data to be written */ + sEEDataNum = sEE_PAGESIZE; + sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); + /* Wait transfer through DMA to be complete */ + sEETimeout = sEE_LONG_TIMEOUT; + while (sEEDataNum > 0) + { + if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; + } + sEE_WaitEepromStandbyState(); + WriteAddr += sEE_PAGESIZE; + pBuffer += sEE_PAGESIZE; + } + if(NumOfSingle != 0) + { + /* Store the number of data to be written */ + sEEDataNum = NumOfSingle; + sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); + /* Wait transfer through DMA to be complete */ + sEETimeout = sEE_LONG_TIMEOUT; + while (sEEDataNum > 0) + { + if((sEETimeout--) == 0) {sEE_TIMEOUT_UserCallback(); return;}; + } + sEE_WaitEepromStandbyState(); + } + } + } +} + +/** + * @brief Wait for EEPROM Standby state. + * + * @note This function allows to wait and check that EEPROM has finished the + * last operation. It is mostly used after Write operation: after receiving + * the buffer to be written, the EEPROM may need additional time to actually + * perform the write operation. During this time, it doesn't answer to + * I2C packets addressed to it. Once the write operation is complete + * the EEPROM responds to its address. + * + * @param None + * @retval sEE_OK (0) if operation is correctly performed, else return value + * different from sEE_OK (0) or the timeout user callback. + */ +uint32_t sEE_WaitEepromStandbyState(void) +{ + __IO uint16_t tmpSR1 = 0; + __IO uint32_t sEETrials = 0; + + /*!< While the bus is busy */ + sEETimeout = sEE_LONG_TIMEOUT; + while(I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BUSY)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /* Keep looping till the slave acknowledge his address or maximum number + of trials is reached (this number is defined by sEE_MAX_TRIALS_NUMBER define + in stm322xg_eval_i2c_ee.h file) */ + while (1) + { + /*!< Send START condition */ + I2C_GenerateSTART(sEE_I2C, ENABLE); + + /*!< Test on EV5 and clear it */ + sEETimeout = sEE_FLAG_TIMEOUT; + while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_MODE_SELECT)) + { + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + + /*!< Send EEPROM address for write */ + I2C_Send7bitAddress(sEE_I2C, sEEAddress, I2C_Direction_Transmitter); + + /* Wait for ADDR flag to be set (Slave acknowledged his address) */ + sEETimeout = sEE_LONG_TIMEOUT; + do + { + /* Get the current value of the SR1 register */ + tmpSR1 = sEE_I2C->SR1; + + /* Update the timeout value and exit if it reach 0 */ + if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback(); + } + /* Keep looping till the Address is acknowledged or the AF flag is + set (address not acknowledged at time) */ + while((tmpSR1 & (I2C_SR1_ADDR | I2C_SR1_AF)) == 0); + + /* Check if the ADDR flag has been set */ + if (tmpSR1 & I2C_SR1_ADDR) + { + /* Clear ADDR Flag by reading SR1 then SR2 registers (SR1 have already + been read) */ + (void)sEE_I2C->SR2; + + /*!< STOP condition */ + I2C_GenerateSTOP(sEE_I2C, ENABLE); + + /* Exit the function */ + return sEE_OK; + } + else + { + /*!< Clear AF flag */ + I2C_ClearFlag(sEE_I2C, I2C_FLAG_AF); + } + + /* Check if the maximum allowed number of trials has bee reached */ + if (sEETrials++ == sEE_MAX_TRIALS_NUMBER) + { + /* If the maximum number of trials has been reached, exit the function */ + return sEE_TIMEOUT_UserCallback(); + } + } +} + +/** + * @brief This function handles the DMA Tx Channel interrupt Handler. + * @param None + * @retval None + */ +void sEE_I2C_DMA_TX_IRQHandler(void) +{ + /* Check if the DMA transfer is complete */ + if(DMA_GetFlagStatus(sEE_I2C_DMA_STREAM_TX, sEE_TX_DMA_FLAG_TCIF) != RESET) + { + /* Disable the DMA Tx Stream and Clear TC flag */ + DMA_Cmd(sEE_I2C_DMA_STREAM_TX, DISABLE); + DMA_ClearFlag(sEE_I2C_DMA_STREAM_TX, sEE_TX_DMA_FLAG_TCIF); + + /*!< Wait till all data have been physically transferred on the bus */ + sEETimeout = sEE_LONG_TIMEOUT; + while(!I2C_GetFlagStatus(sEE_I2C, I2C_FLAG_BTF)) + { + if((sEETimeout--) == 0) sEE_TIMEOUT_UserCallback(); + } + + /*!< Send STOP condition */ + I2C_GenerateSTOP(sEE_I2C, ENABLE); + + /* Reset the variable holding the number of data to be written */ + *sEEDataWritePointer = 0; + } +} + +/** + * @brief This function handles the DMA Rx Channel interrupt Handler. + * @param None + * @retval None + */ +void sEE_I2C_DMA_RX_IRQHandler(void) +{ + /* Check if the DMA transfer is complete */ + if(DMA_GetFlagStatus(sEE_I2C_DMA_STREAM_RX, sEE_RX_DMA_FLAG_TCIF) != RESET) + { + /*!< Send STOP Condition */ + I2C_GenerateSTOP(sEE_I2C, ENABLE); + + /* Disable the DMA Rx Stream and Clear TC Flag */ + DMA_Cmd(sEE_I2C_DMA_STREAM_RX, DISABLE); + DMA_ClearFlag(sEE_I2C_DMA_STREAM_RX, sEE_RX_DMA_FLAG_TCIF); + + /* Reset the variable holding the number of data to be read */ + *sEEDataReadPointer = 0; + } +} + +#ifdef USE_DEFAULT_TIMEOUT_CALLBACK +/** + * @brief Basic management of the timeout situation. + * @param None. + * @retval None. + */ +uint32_t sEE_TIMEOUT_UserCallback(void) +{ + /* Block communication and all processes */ + while (1) + { + } +} +#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_i2c_ee.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_i2c_ee.h new file mode 100644 index 000000000..8ceed5fe7 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_i2c_ee.h @@ -0,0 +1,194 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_i2c_ee.h + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file contains all the functions prototypes for the + * stm322xg_eval_i2c_ee.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM322xG_EVAL_I2C_EE_H +#define __STM322xG_EVAL_I2C_EE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_I2C_EE + * @{ + */ + +/** @defgroup STM322xG_EVAL_I2C_EE_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_I2C_EE_Exported_Constants + * @{ + */ + +/* Uncomment the following line to use the default sEE_TIMEOUT_UserCallback() + function implemented in stm32_evel_i2c_ee.c file. + sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition + occure during communication (waiting on an event that doesn't occur, bus + errors, busy devices ...). */ +/* #define USE_DEFAULT_TIMEOUT_CALLBACK */ + +#if !defined (sEE_M24C08) && !defined (sEE_M24C64_32) +/* Use the defines below the choose the EEPROM type */ +/* #define sEE_M24C08*/ /* Support the device: M24C08. */ +/* note: Could support: M24C01, M24C02, M24C04 and M24C16 if the blocks and + HW address are correctly defined*/ +#define sEE_M24C64_32 /* Support the devices: M24C32 and M24C64 */ +#endif + +#ifdef sEE_M24C64_32 +/* For M24C32 and M24C64 devices, E0,E1 and E2 pins are all used for device + address selection (ne need for additional address lines). According to the + Harware connection on the board (on STM322xG-EVAL board E0 = E1 = E2 = 0) */ + + #define sEE_HW_ADDRESS 0xA0 /* E0 = E1 = E2 = 0 */ + +#elif defined (sEE_M24C08) +/* The M24C08W contains 4 blocks (128byte each) with the adresses below: E2 = 0 + EEPROM Addresses defines */ + #define sEE_Block0_ADDRESS 0xA0 /* E2 = 0 */ + /*#define sEE_Block1_ADDRESS 0xA2*/ /* E2 = 0 */ + /*#define sEE_Block2_ADDRESS 0xA4*/ /* E2 = 0 */ + /*#define sEE_Block3_ADDRESS 0xA6*/ /* E2 = 0 */ + +#endif /* sEE_M24C64_32 */ + +/* I2C clock speed configuration (in Hz) + WARNING: + Make sure that this define is not already declared in other files (ie. + stm322xg_eval.h file). It can be used in parallel by other modules. */ +#ifndef I2C_SPEED + #define I2C_SPEED 100000 +#endif /* I2C_SPEED */ + +#define I2C_SLAVE_ADDRESS7 0xA0 + +#if defined (sEE_M24C08) + #define sEE_PAGESIZE 16 +#elif defined (sEE_M24C64_32) + #define sEE_PAGESIZE 32 +#endif + +/* Maximum Timeout values for flags and events waiting loops. These timeouts are + not based on accurate values, they just guarantee that the application will + not remain stuck if the I2C communication is corrupted. + You may modify these timeout values depending on CPU frequency and application + conditions (interrupts routines ...). */ +#define sEE_FLAG_TIMEOUT ((uint32_t)0x1000) +#define sEE_LONG_TIMEOUT ((uint32_t)(10 * sEE_FLAG_TIMEOUT)) + +/* Maximum number of trials for sEE_WaitEepromStandbyState() function */ +#define sEE_MAX_TRIALS_NUMBER 300 + +/* Defintions for the state of the DMA transfer */ +#define sEE_STATE_READY 0 +#define sEE_STATE_BUSY 1 +#define sEE_STATE_ERROR 2 + +#define sEE_OK 0 +#define sEE_FAIL 1 + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_I2C_EE_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_I2C_EE_Exported_Functions + * @{ + */ +void sEE_DeInit(void); +void sEE_Init(void); +uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead); +uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite); +void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite); +uint32_t sEE_WaitEepromStandbyState(void); + +/* USER Callbacks: These are functions for which prototypes only are declared in + EEPROM driver and that should be implemented into user applicaiton. */ +/* sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition + occure during communication (waiting on an event that doesn't occur, bus + errors, busy devices ...). + You can use the default timeout callback implementation by uncommenting the + define USE_DEFAULT_TIMEOUT_CALLBACK in stm322xg_eval_i2c_ee.h file. + Typically the user implementation of this callback should reset I2C peripheral + and re-initialize communication or in worst case reset all the application. */ +uint32_t sEE_TIMEOUT_UserCallback(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM322xG_EVAL_I2C_EE_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_ioe.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_ioe.c new file mode 100644 index 000000000..e90310050 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_ioe.c @@ -0,0 +1,1619 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_ioe.c + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file provides a set of functions needed to manage the STMPE811 + * IO Expander devices mounted on STM322xG-EVAL evaluation board(MB786) + * RevA and RevB. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + /* File Info : --------------------------------------------------------------- + + Note: + ----- + - This driver uses the DMA method for sending and receiving data on I2C bus + which allow higher efficiency and reliability of the communication. + + SUPPORTED FEATURES: + - IO Read/write : Set/Reset and Read (Polling/Interrupt) + - Joystick: config and Read (Polling/Interrupt) + - Touch Screen Features: Single point mode (Polling/Interrupt) + - TempSensor Feature: accuracy not determined (Polling). + + UNSUPPORTED FEATURES: + - Row ADC Feature is not supported (not implemented on STM322xG_EVAL board) + ----------------------------------------------------------------------------*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval_ioe.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @defgroup STM322xG_EVAL_IOE + * @brief This file includes the IO Expander driver for STMPE811 IO Expander + * devices. + * @{ + */ + + +/** @defgroup STM322xG_EVAL_IOE_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_IOE_Private_Defines + * @{ + */ +#define TIMEOUT_MAX 0x3000 /* _x? (x - _x): (_x - x); + yDiff = y > _y? (y - _y): (_y - y); + if (xDiff + yDiff > 5) + { + _x = x; + _y = y; + } + } + /* Update the X position */ + TS_State.X = _x; + + /* Update the Y position */ + TS_State.Y = _y; + /* Update the Z position index */ + TS_State.Z = IOE_TS_Read_Z(); + + /* Clear the interrupt pending bit and enable the FIFO again */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01); + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00); + + /* Return pointer to the updated structure */ + return &TS_State; +} + +/** + * @brief Returns the temperature row value (in 16 bit format). + * @param None + * @retval The temperature row value. + */ +uint32_t IOE_TempSens_GetData(void) +{ + static __IO uint32_t tmp = 0; + + /* Acquire data enable */ + I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x03); + + /* Enable the TEMPSENS module */ + tmp = (uint32_t)((I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_DATA) & 0x03) << 8); + tmp |= (uint32_t)I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_DATA + 1); + + tmp = (uint32_t)((33 * tmp * 100) / 751); + tmp = (uint32_t)((tmp + 5) / 10); + + /* return the temperature row value */ + return tmp; +} + +/** + * @brief Checks the selected Global interrupt source pending bit + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param Global_IT: the Global interrupt source to be checked, could be: + * @arg Global_IT_GPIO : All IOs interrupt + * @arg Global_IT_ADC : ADC interrupt + * @arg Global_IT_TEMP : Temperature Sensor interrupts + * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt + * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt + * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt + * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt + * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt + * @retval Status of the checked flag. Could be SET or RESET. + */ +FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT) +{ + __IO uint8_t tmp = 0; + + /* get the Interrupt status */ + tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_STA); + + if ((tmp & (uint8_t)Global_IT) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/** + * @brief Clears the selected Global interrupt pending bit(s) + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param Global_IT: the Global interrupt to be cleared, could be any combination + * of the following values: + * @arg Global_IT_GPIO : All IOs interrupt + * @arg Global_IT_ADC : ADC interrupt + * @arg Global_IT_TEMP : Temperature Sensor interrupts + * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt + * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt + * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt + * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt + * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt + * @retval IOE_OK: if all initializations are OK. Other value if error. + */ +uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t Global_IT) +{ + /* Write 1 to the bits that have to be cleared */ + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_STA, Global_IT); + + /* If all OK return IOE_OK */ + return IOE_OK; +} + +/** + * @brief Checks the status of the selected IO interrupt pending bit + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be + * from 0 to 7. + * @retval Status of the checked flag. Could be SET or RESET. + */ +FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT) +{ + uint8_t tmp = 0; + + /* get the Interrupt status */ + tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA); + + if ((tmp & (uint8_t)IO_IT) != 0) + { + return SET; + } + else + { + return RESET; + } +} + +/** + * @brief Clears the selected IO interrupt pending bit(s). + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be + * from 0 to 7. + * @retval IOE_OK: if all initializations are OK. Other value if error. + */ +uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT) +{ + /* Write 1 to the bits that have to be cleared */ + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA, IO_IT); + + /* Clear the Edge detection pending bit*/ + I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_ED, IO_IT); + + /* Clear the Rising edge pending bit */ + I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_RE, IO_IT); + + /* Clear the Falling edge pending bit */ + I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_FE, IO_IT); + + /* If all OK return IOE_OK */ + return IOE_OK; +} + +/** + * @brief Checks if the selected device is correctly configured and + * communicates correctly on the I2C bus. + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @retval IOE_OK if IOE is operational. Other value if failure. + */ +uint8_t IOE_IsOperational(uint8_t DeviceAddr) +{ + /* Return Error if the ID is not correct */ + if( IOE_ReadID(DeviceAddr) != (uint16_t)STMPE811_ID ) + { + /* Check if a Timeout occurred */ + if (IOE_TimeOut == 0) + { + return(IOE_TimeoutUserCallback()); + } + else + { + return IOE_FAILURE; /* ID is not Correct */ + } + } + else + { + return IOE_OK; /* ID is correct */ + } +} + +/** + * @brief Resets the IO Expander by Software (SYS_CTRL1, RESET bit). + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @retval IOE_OK: if all initializations are OK. Other value if error. + */ +uint8_t IOE_Reset(uint8_t DeviceAddr) +{ + /* Power Down the IO_Expander */ + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x02); + + /* wait for a delay to insure registers erasing */ + _delay_(2); + + /* Power On the Codec after the power off => all registers are reinitialized*/ + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x00); + + /* If all OK return IOE_OK */ + return IOE_OK; +} + +/** + * @brief Reads the selected device's ID. + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @retval The Device ID (two bytes). + */ +uint16_t IOE_ReadID(uint8_t DeviceAddr) +{ + uint16_t tmp = 0; + + /* Read device ID */ + tmp = I2C_ReadDeviceRegister(DeviceAddr, 0); + tmp = (uint32_t)(tmp << 8); + tmp |= (uint32_t)I2C_ReadDeviceRegister(DeviceAddr, 1); + + /* Return the ID */ + return (uint16_t)tmp; +} + +/** + * @brief Configures the selected IO Expander functionalities. + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param IOE_TEMPSENS_FCT: the functions to be configured. could be any + * combination of the following values: + * @arg IOE_IO_FCT : IO function + * @arg IOE_TS_FCT : Touch Screen function + * @arg IOE_ADC_FCT : ADC function + * @arg IOE_TEMPSENS_FCT : Temperature Sensor function + * @retval IOE_OK: if all initializations are OK. Other value if error. + */ +uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState) +{ + uint8_t tmp = 0; + + /* Get the register value */ + tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2); + + if (NewState != DISABLE) + { + /* Set the Functionalities to be Enabled */ + tmp &= ~(uint8_t)Fct; + } + else + { + /* Set the Functionalities to be Disabled */ + tmp |= (uint8_t)Fct; + } + + /* Set the register value */ + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2, tmp); + + /* If all OK return IOE_OK */ + return IOE_OK; +} + +/** + * @brief Configures the selected pin direction (to be an input or an output) + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param IO_Pin: IO_Pin_x: Where x can be from 0 to 7. + * @param Direction: could be Direction_IN or Direction_OUT. + * @retval IOE_OK: if all initializations are OK. Other value if error. + */ +uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction) +{ + uint8_t tmp = 0; + + /* Get all the Pins direction */ + tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR); + + if (Direction != Direction_IN) + { + tmp |= (uint8_t)IO_Pin; + } + else + { + tmp &= ~(uint8_t)IO_Pin; + } + + /* Write the register new value */ + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR, tmp); + + /* If all OK return IOE_OK */ + return IOE_OK; +} + +/** + * @brief Enables or disables the Global interrupt. + * @param DeviceAddr: The address of the IOExpander, could be :I OE_1_ADDR + * or IOE_2_ADDR. + * @param NewState: could be ENABLE or DISABLE. + * @retval IOE_OK: if all initializations are OK. Other value if error. + */ +uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState) +{ + uint8_t tmp = 0; + + /* Read the Interrupt Control register */ + I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL); + + if (NewState != DISABLE) + { + /* Set the global interrupts to be Enabled */ + tmp |= (uint8_t)IOE_GIT_EN; + } + else + { + /* Set the global interrupts to be Disabled */ + tmp &= ~(uint8_t)IOE_GIT_EN; + } + + /* Write Back the Interrupt Control register */ + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL, tmp); + + /* If all OK return IOE_OK */ + return IOE_OK; +} + +/** + * @brief Configures the selected source to generate or not a global interrupt + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param Global_IT: the interrupt source to be configured, could be: + * @arg Global_IT_GPIO : All IOs interrupt + * @arg Global_IT_ADC : ADC interrupt + * @arg Global_IT_TEMP : Temperature Sensor interrupts + * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt + * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt + * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt + * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt + * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt + * @retval IOE_OK: if all initializations are OK. Other value if error. + */ +uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState) +{ + uint8_t tmp = 0; + + /* Get the current value of the INT_EN register */ + tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_EN); + + if (NewState != DISABLE) + { + /* Set the interrupts to be Enabled */ + tmp |= (uint8_t)Global_IT; + } + else + { + /* Set the interrupts to be Disabled */ + tmp &= ~(uint8_t)Global_IT; + } + /* Set the register */ + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_EN, tmp); + + /* If all OK return IOE_OK */ + return IOE_OK; +} + +/** + * @brief Configures the selected pins to generate an interrupt or not. + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param IO_IT: The IO interrupt to be configured. This parameter could be any + * combination of the following values: + * @arg IO_IT_x: where x can be from 0 to 7. + * @param NewState: could be ENABLE or DISABLE. + * @retval IOE_OK: if all initializations are OK. Other value if error. + */ +uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState) +{ + uint8_t tmp = 0; + + tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN); + + if (NewState != DISABLE) + { + /* Set the interrupts to be Enabled */ + tmp |= (uint8_t)IO_IT; + } + else + { + /* Set the interrupts to be Disabled */ + tmp &= ~(uint8_t)IO_IT; + } + + /* Set the register */ + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN, tmp); + + /* If all OK return IOE_OK */ + return IOE_OK; +} + +/** + * @brief Configures the touch Screen Controller (Single point detection) + * @param None + * @retval IOE_OK if all initializations are OK. Other value if error. + */ +uint8_t IOE_TS_Config(void) +{ + uint8_t tmp = 0; + + /* Enable TSC Fct: already done in IOE_Config */ + tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2); + tmp &= ~(uint32_t)(IOE_TS_FCT | IOE_ADC_FCT); + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp); + + /* Enable the TSC global interrupts */ + tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN); + tmp |= (uint32_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV); + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN, tmp); + + /* Select Sample Time, bit number and ADC Reference */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL1, 0x49); + + /* Wait for ~20 ms */ + _delay_(2); + + /* Select the ADC clock speed: 3.25 MHz */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL2, 0x01); + + /* Select TSC pins in non default mode */ + tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF); + tmp &= ~(uint8_t)TOUCH_IO_ALL; + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF, tmp); + + /* Select 2 nF filter capacitor */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CFG, 0x9A); + + /* Select single point reading */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_TH, 0x01); + + /* Write 0x01 to clear the FIFO memory content. */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01); + + /* Write 0x00 to put the FIFO back into operation mode */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00); + + /* set the data format for Z value: 7 fractional part and 1 whole part */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_FRACT_XYZ, 0x01); + + /* set the driving capability of the device for TSC pins: 50mA */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_I_DRIVE, 0x01); + + /* Use no tracking index, touchscreen controller operation mode (XYZ) and + enable the TSC */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL, 0x01); + + /* Clear all the status pending bits */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_STA, 0xFF); + + /* Initialize the TS structure to their default values */ + TS_State.TouchDetected = TS_State.X = TS_State.Y = TS_State.Z = 0; + + /* All configuration done */ + return IOE_OK; +} + +/** + * @brief Configures and enables the Temperature sensor module. + * @param None + * @retval IOE_OK if all initializations are OK. Other value if error. + */ +uint8_t IOE_TempSens_Config(void) +{ + __IO uint8_t tmp = 0; + + /* Enable Temperature Sensor Fct: already done in IOE_Config */ + tmp = I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_SYS_CTRL2); + tmp &= ~(uint32_t)(IOE_TEMPSENS_FCT | IOE_ADC_FCT); + I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_SYS_CTRL2, tmp); + + /* Enable the TEMPSENS module */ + I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x01); + + /* Aquire data enable */ + I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x3); + + /* All configuration done */ + return IOE_OK; +} + +/** + * @brief Configures the selected pin to be in Alternate function or not + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param IO_Pin: IO_Pin_x, Where x can be from 0 to 7. + * @param NewState: State of the AF for the selected pin, could be + * ENABLE or DISABLE. + * @retval IOE_OK: if all initializations are OK. Other value if error. + */ +uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState) +{ + uint8_t tmp = 0; + + /* Get the current state of the GPIO_AF register */ + tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF); + + if (NewState != DISABLE) + { + /* Enable the selected pins alternate function */ + tmp |= (uint8_t)IO_Pin; + } + else + { + /* Disable the selected pins alternate function */ + tmp &= ~(uint8_t)IO_Pin; + } + + /* Write back the new value in GPIO_AF register */ + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF, tmp); + + /* If all OK return IOE_OK */ + return IOE_OK; +} + +/** + * @brief Configures the Edge for which a transition is detectable for the + * the selected pin. + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param IO_Pin: IO_Pin_x, Where x can be from 0 to 7. + * @param Edge: The edge which will be detected. This parameter can be one or a + * a combination of following values: EDGE_FALLING and EDGE_RISING . + * @retval IOE_OK: if all initializations are OK. Other value if error. + */ +uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge) +{ + uint8_t tmp1 = 0, tmp2 = 0; + + /* Get the registers values */ + tmp1 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE); + tmp2 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE); + + /* Disable the Falling Edge */ + tmp1 &= ~(uint8_t)IO_Pin; + /* Disable the Falling Edge */ + tmp2 &= ~(uint8_t)IO_Pin; + + /* Enable the Falling edge if selected */ + if (Edge & EDGE_FALLING) + { + tmp1 |= (uint8_t)IO_Pin; + } + + /* Enable the Rising edge if selected */ + if (Edge & EDGE_RISING) + { + tmp2 |= (uint8_t)IO_Pin; + } + + /* Write back the registers values */ + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, tmp1); + I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, tmp2); + + /* if OK return 0 */ + return IOE_OK; +} + +/** + * @brief Configures the Interrupt line active state and format (level/edge) + * @param Polarity: could be + * @arg Polarity_Low: Interrupt line is active Low/Falling edge + * @arg Polarity_High: Interrupt line is active High/Rising edge + * @param Type: Interrupt line activity type, could be one of the following values + * @arg Type_Level: Interrupt line is active in level model + * @arg Type_Edge: Interrupt line is active in edge model + * @retval IOE_OK: if all initializations are OK. Other value if error. + */ +uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type) +{ + uint8_t tmp = 0; + + /* Get the register IOE_REG_INT_CTRL value */ + tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL); + + /* Mask the polarity and type bits */ + tmp &= ~(uint8_t)0x06; + + /* Modify the Interrupt Output line configuration */ + tmp |= (uint8_t)(Polarity | Type); + + /* Set the register */ + I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL, tmp); + + + /* Get the register IOE_REG_INT_CTRL value */ + tmp = I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_INT_CTRL); + /* Mask the polarity and type bits */ + tmp &= ~(uint8_t)0x06; + + /* Modify the Interrupt Output line configuration */ + tmp |= (uint8_t)(Polarity | Type); + + /* Set the register */ + I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_INT_CTRL, tmp); + + /* If all OK return IOE_OK */ + return IOE_OK; +} + +/** + * @brief Writes a value in a register of the device through I2C. + * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param RegisterAddr: The target register address + * @param RegisterValue: The target register value to be written + * @retval IOE_OK: if all operations are OK. Other value if error. + */ +uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue) +{ + uint8_t read_verif = 0; + uint8_t IOE_BufferTX = 0; + + /* Get Value to be written */ + IOE_BufferTX = RegisterValue; + + /* Configure DMA Peripheral */ + IOE_DMA_Config(IOE_DMA_TX, (uint8_t*)(&IOE_BufferTX)); + + /* Enable the I2C peripheral */ + I2C_GenerateSTART(IOE_I2C, ENABLE); + + /* Test on SB Flag */ + IOE_TimeOut = TIMEOUT_MAX; + while (I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB) == RESET) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Transmit the slave address and enable writing operation */ + I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter); + + /* Test on ADDR Flag */ + IOE_TimeOut = TIMEOUT_MAX; + while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Transmit the first address for r/w operations */ + I2C_SendData(IOE_I2C, RegisterAddr); + + /* Test on TXE FLag (data dent) */ + IOE_TimeOut = TIMEOUT_MAX; + while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Enable I2C DMA request */ + I2C_DMACmd(IOE_I2C,ENABLE); + + /* Enable DMA TX Channel */ + DMA_Cmd(IOE_DMA_TX_STREAM, ENABLE); + + /* Wait until DMA Transfer Complete */ + IOE_TimeOut = TIMEOUT_MAX; + while (!DMA_GetFlagStatus(IOE_DMA_TX_STREAM,IOE_DMA_TX_TCFLAG)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Wait until BTF Flag is set before generating STOP */ + IOE_TimeOut = 2 * TIMEOUT_MAX; + while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) + { + } + + /* Send STOP Condition */ + I2C_GenerateSTOP(IOE_I2C, ENABLE); + + /* Disable DMA TX Channel */ + DMA_Cmd(IOE_DMA_TX_STREAM, DISABLE); + + /* Disable I2C DMA request */ + I2C_DMACmd(IOE_I2C,DISABLE); + + /* Clear DMA TX Transfer Complete Flag */ + DMA_ClearFlag(IOE_DMA_TX_STREAM,IOE_DMA_TX_TCFLAG); + +#ifdef VERIFY_WRITTENDATA + /* Verify (if needed) that the loaded data is correct */ + + /* Read the just written register*/ + read_verif = I2C_ReadDeviceRegister(DeviceAddr, RegisterAddr); + /* Load the register and verify its value */ + if (read_verif != RegisterValue) + { + /* Control data wrongly transfered */ + read_verif = IOE_FAILURE; + } + else + { + /* Control data correctly transfered */ + read_verif = 0; + } +#endif + + /* Return the verifying value: 0 (Passed) or 1 (Failed) */ + return (read_verif); +} + +/** + * @brief Reads a register of the device through I2C. + * @param DeviceAddr: The address of the device, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param RegisterAddr: The target register address (between 00x and 0x24) + * @retval The value of the read register (0xAA if Timeout occurred) + */ +uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr) +{ + uint8_t IOE_BufferRX[2] = {0x00, 0x00}; + + /* Configure DMA Peripheral */ + IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX); + + /* Enable DMA NACK automatic generation */ + I2C_DMALastTransferCmd(IOE_I2C, ENABLE); + + /* Enable the I2C peripheral */ + I2C_GenerateSTART(IOE_I2C, ENABLE); + + /* Test on SB Flag */ + IOE_TimeOut = TIMEOUT_MAX; + while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Send device address for write */ + I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter); + + /* Test on ADDR Flag */ + IOE_TimeOut = TIMEOUT_MAX; + while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Send the device's internal address to write to */ + I2C_SendData(IOE_I2C, RegisterAddr); + + /* Test on TXE FLag (data dent) */ + IOE_TimeOut = TIMEOUT_MAX; + while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Send START condition a second time */ + I2C_GenerateSTART(IOE_I2C, ENABLE); + + /* Test on SB Flag */ + IOE_TimeOut = TIMEOUT_MAX; + while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Send IOExpander address for read */ + I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver); + + /* Test on ADDR Flag */ + IOE_TimeOut = TIMEOUT_MAX; + while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Enable I2C DMA request */ + I2C_DMACmd(IOE_I2C,ENABLE); + + /* Enable DMA RX Channel */ + DMA_Cmd(IOE_DMA_RX_STREAM, ENABLE); + + /* Wait until DMA Transfer Complete */ + IOE_TimeOut = 2 * TIMEOUT_MAX; + while (!DMA_GetFlagStatus(IOE_DMA_RX_STREAM,IOE_DMA_RX_TCFLAG)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Send STOP Condition */ + I2C_GenerateSTOP(IOE_I2C, ENABLE); + + /* Disable DMA RX Channel */ + DMA_Cmd(IOE_DMA_RX_STREAM, DISABLE); + + /* Disable I2C DMA request */ + I2C_DMACmd(IOE_I2C,DISABLE); + + /* Clear DMA RX Transfer Complete Flag */ + DMA_ClearFlag(IOE_DMA_RX_STREAM,IOE_DMA_RX_TCFLAG); + + /* return a pointer to the IOE_Buffer */ + return (uint8_t)IOE_BufferRX[0]; +} + + +/** + * @brief Reads a buffer of 2 bytes from the device registers. + * @param DeviceAddr: The address of the device, could be : IOE_1_ADDR + * or IOE_2_ADDR. + * @param RegisterAddr: The target register address (between 00x and 0x24) + * @retval A pointer to the buffer containing the two returned bytes (in halfword). + */ +uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint8_t RegisterAddr) +{ + uint8_t tmp= 0; + uint8_t IOE_BufferRX[2] = {0x00, 0x00}; + + /* Configure DMA Peripheral */ + IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX); + + /* Enable DMA NACK automatic generation */ + I2C_DMALastTransferCmd(IOE_I2C, ENABLE); + + /* Enable the I2C peripheral */ + I2C_GenerateSTART(IOE_I2C, ENABLE); + + /* Test on SB Flag */ + IOE_TimeOut = TIMEOUT_MAX; + while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Send device address for write */ + I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter); + + /* Test on ADDR Flag */ + IOE_TimeOut = TIMEOUT_MAX; + while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Send the device's internal address to write to */ + I2C_SendData(IOE_I2C, RegisterAddr); + + /* Test on TXE FLag (data dent) */ + IOE_TimeOut = TIMEOUT_MAX; + while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF))) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Send START condition a second time */ + I2C_GenerateSTART(IOE_I2C, ENABLE); + + /* Test on SB Flag */ + IOE_TimeOut = TIMEOUT_MAX; + while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Send IOExpander address for read */ + I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver); + + /* Test on ADDR Flag */ + IOE_TimeOut = TIMEOUT_MAX; + while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Enable I2C DMA request */ + I2C_DMACmd(IOE_I2C,ENABLE); + + /* Enable DMA RX Channel */ + DMA_Cmd(IOE_DMA_RX_STREAM, ENABLE); + + /* Wait until DMA Transfer Complete */ + IOE_TimeOut = 2 * TIMEOUT_MAX; + while (!DMA_GetFlagStatus(IOE_DMA_RX_STREAM, IOE_DMA_RX_TCFLAG)) + { + if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback()); + } + + /* Send STOP Condition */ + I2C_GenerateSTOP(IOE_I2C, ENABLE); + + /* Disable DMA RX Channel */ + DMA_Cmd(IOE_DMA_RX_STREAM, DISABLE); + + /* Disable I2C DMA request */ + I2C_DMACmd(IOE_I2C,DISABLE); + + /* Clear DMA RX Transfer Complete Flag */ + DMA_ClearFlag(IOE_DMA_RX_STREAM,IOE_DMA_RX_TCFLAG); + + /* Reorganize received data */ + tmp = IOE_BufferRX[0]; + IOE_BufferRX[0] = IOE_BufferRX[1]; + IOE_BufferRX[1] = tmp; + + /* return a pointer to the IOE_Buffer */ + return (*(__IO uint16_t *) IOE_BufferRX); +} + +/** + * @brief Return Touch Screen X position value + * @param None + * @retval X position. + */ +static uint16_t IOE_TS_Read_X(void) +{ + int32_t x, xr; + + x = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Y); + + /* first correction */ + xr = (x * 320) >> 12; + /* second correction */ + xr = ((xr * 32)/29) - 17; + + if(xr <= 0) + xr = 0; + + return (uint16_t)(xr); +} + +/** + * @brief Return Touch Screen Y position value + * @param None + * @retval Y position. + */ +static uint16_t IOE_TS_Read_Y(void) +{ + int32_t y, yr; + y= I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_X); + + yr= (y * 240) >> 12; + yr = ((yr * 240) / 217) - 12; + + if(yr <= 0) + yr = 0; + + return (uint16_t)(yr); +} + +/** + * @brief Return Touch Screen Z position value + * @param None + * @retval Z position. + */ +static uint16_t IOE_TS_Read_Z(void) +{ + uint32_t z; + z = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Z); + + + if(z <= 0) + z = 0; + + return (uint16_t)(z); +} + +/** + * @brief Initializes the GPIO pins used by the IO expander. + * @param None + * @retval None + */ +static void IOE_GPIO_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable IOE_I2C and IOE_I2C_GPIO_PORT & Alternate Function clocks */ + RCC_APB1PeriphClockCmd(IOE_I2C_CLK, ENABLE); + RCC_AHB1PeriphClockCmd(IOE_I2C_SCL_GPIO_CLK | IOE_I2C_SDA_GPIO_CLK | + IOE_IT_GPIO_CLK, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + /* Reset IOE_I2C IP */ + RCC_APB1PeriphResetCmd(IOE_I2C_CLK, ENABLE); + + /* Release reset signal of IOE_I2C IP */ + RCC_APB1PeriphResetCmd(IOE_I2C_CLK, DISABLE); + + /* Connect PXx to I2C_SCL*/ + GPIO_PinAFConfig(IOE_I2C_SCL_GPIO_PORT, IOE_I2C_SCL_SOURCE, IOE_I2C_SCL_AF); + /* Connect PXx to I2C_SDA*/ + GPIO_PinAFConfig(IOE_I2C_SDA_GPIO_PORT, IOE_I2C_SDA_SOURCE, IOE_I2C_SDA_AF); + + /* IOE_I2C SCL and SDA pins configuration */ + GPIO_InitStructure.GPIO_Pin = IOE_I2C_SCL_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(IOE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = IOE_I2C_SDA_PIN; + GPIO_Init(IOE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); + + /* Set EXTI pin as Input PullUp - IO_Expander_INT */ + GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure); + + /* Connect Button EXTI Line to Button GPIO Pin */ + SYSCFG_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE); +} + +/** + * @brief Configure the I2C Peripheral used to communicate with IO_Expanders. + * @param None + * @retval None + */ +static void IOE_I2C_Config(void) +{ + I2C_InitTypeDef I2C_InitStructure; + + /* IOE_I2C configuration */ + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStructure.I2C_OwnAddress1 = 0x00; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; + + I2C_Init(IOE_I2C, &I2C_InitStructure); +} + +/** + * @brief Configure the DMA Peripheral used to handle communication via I2C. + * @param None + * @retval None + */ + +static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer) +{ + DMA_InitTypeDef DMA_InitStructure; + + RCC_AHB1PeriphClockCmd(IOE_DMA_CLK, ENABLE); + + /* Initialize the DMA_Channel member */ + DMA_InitStructure.DMA_Channel = IOE_DMA_CHANNEL; + + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStructure.DMA_PeripheralBaseAddr = IOE_I2C_DR; + + /* Initialize the DMA_Memory0BaseAddr member */ + DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)buffer; + + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + + /* Initialize the DMA_MemoryInc member */ + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + + /* Initialize the DMA_Mode member */ + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; + + /* Initialize the DMA_Priority member */ + DMA_InitStructure.DMA_Priority = DMA_Priority_Low; + + /* Initialize the DMA_FIFOMode member */ + DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; + + /* Initialize the DMA_FIFOThreshold member */ + DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; + + /* Initialize the DMA_MemoryBurst member */ + DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; + + /* Initialize the DMA_PeripheralBurst member */ + DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; + + /* If using DMA for Reception */ + if (Direction == IOE_DMA_RX) + { + /* Initialize the DMA_DIR member */ + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; + + /* Initialize the DMA_BufferSize member */ + DMA_InitStructure.DMA_BufferSize = 2; + + DMA_DeInit(IOE_DMA_RX_STREAM); + + DMA_Init(IOE_DMA_RX_STREAM, &DMA_InitStructure); + } + /* If using DMA for Transmission */ + else if (Direction == IOE_DMA_TX) + { + /* Initialize the DMA_DIR member */ + DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; + + /* Initialize the DMA_BufferSize member */ + DMA_InitStructure.DMA_BufferSize = 1; + + DMA_DeInit(IOE_DMA_TX_STREAM); + + DMA_Init(IOE_DMA_TX_STREAM, &DMA_InitStructure); + } +} + + +/** + * @brief Configures the IO expander Interrupt line and GPIO in EXTI mode. + * @param None + * @retval None + */ +static void IOE_EXTI_Config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + /* Enable GPIO clock */ + RCC_AHB1PeriphClockCmd(IOE_IT_GPIO_CLK, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + /* Configure Button pin as input floating */ + GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure); + + /* Connect Button EXTI Line to Button GPIO Pin */ + SYSCFG_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE); + + /* Configure Button EXTI line */ + EXTI_InitStructure.EXTI_Line = IOE_IT_EXTI_LINE; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + + /* Enable and set Button EXTI Interrupt to the lowest priority */ + NVIC_InitStructure.NVIC_IRQChannel = IOE_IT_EXTI_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +#ifndef USE_Delay +/** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + */ +static void delay(__IO uint32_t nCount) +{ + __IO uint32_t index = 0; + for(index = (100000 * nCount); index != 0; index--) + { + } +} +#endif /* USE_Delay*/ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_ioe.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_ioe.h new file mode 100644 index 000000000..6f07800d1 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_ioe.h @@ -0,0 +1,565 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_ioe.h + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file contains all the functions prototypes for the + * stm322xg_eval_ioe.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + /* File Info : --------------------------------------------------------------- + SUPPORTED FEATURES: + - IO Read/write : Set/Reset and Read (Polling/Interrupt) + - Joystick: config and Read (Polling/Interrupt) + - Touch Screen Features: Single point mode (Polling/Interrupt) + - TempSensor Feature: accuracy not determined (Polling). + + UNSUPPORTED FEATURES: + - Row ADC Feature is not supported (not implemented on STM322xG_EVAL board) + ----------------------------------------------------------------------------*/ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM322xG_EVAL_IOE_H +#define __STM322xG_EVAL_IOE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @defgroup STM322xG_EVAL_IOE + * @{ + */ + + +/** @defgroup STM322xG_EVAL_IOE_Exported_Types + * @{ + */ + +/** + * @brief Touch Screen Information structure + */ +typedef struct +{ + uint16_t TouchDetected; + uint16_t X; + uint16_t Y; + uint16_t Z; +}TS_STATE; + +/** + * @brief Joystick State definitions + */ +#ifndef __STM322xG_EVAL_H +typedef enum +{ + JOY_NONE = 0, + JOY_SEL = 1, + JOY_DOWN = 2, + JOY_LEFT = 3, + JOY_RIGHT = 4, + JOY_UP = 5 +} JOYState_TypeDef +; +#endif /* __STM322xG_EVAL_H */ + +/** + * @brief IO_Expander Error codes + */ +typedef enum +{ + IOE_OK = 0, + IOE_FAILURE, + IOE_TIMEOUT, + PARAM_ERROR, + IOE1_NOT_OPERATIONAL, + IOE2_NOT_OPERATIONAL +}IOE_Status_TypDef; + +/** + * @brief IO bit values + */ +typedef enum +{ + BitReset = 0, + BitSet = 1 +}IOE_BitValue_TypeDef; + +/** + * @brief IOE DMA Direction + */ +typedef enum +{ + IOE_DMA_TX = 0, + IOE_DMA_RX = 1 +}IOE_DMADirection_TypeDef; + + +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_IOE_Exported_Constants + * @{ + */ + +/** + * @brief Uncomment the line below to enable verfying each written byte in write + * operation. The I2C_WriteDeviceRegister() function will then compare the + * written and read data and return error status if a mismatch occurs. + */ +/* #define VERIFY_WRITTENDATA */ + +/** + * @brief Uncomment the line below if you want to use user timeout callback. + * Function prototypes is declared in this file but function body may be + * implemented into user application. + */ +/* #define USE_TIMEOUT_USER_CALLBACK */ + +/** + * @brief Uncomment the line below if you want to use user defined Delay function + * (for precise timing), otherwise default _delay_ function defined within + * this driver is used (less precise timing). + */ +/* #define USE_Delay */ + +#ifdef USE_Delay +#include "main.h" + + #define _delay_ Delay /* !< User can provide more timing precise _delay_ function + (with 10ms time base), using SysTick for example */ +#else + #define _delay_ delay /* !< Default _delay_ function with less precise timing */ +#endif + +/*------------------------------------------------------------------------------ + Hardware Configuration +------------------------------------------------------------------------------*/ +/** + * @brief I2C port definitions + */ +#define IOE_I2C I2C1 +#define IOE_I2C_CLK RCC_APB1Periph_I2C1 +#define IOE_I2C_SCL_PIN GPIO_Pin_6 +#define IOE_I2C_SCL_GPIO_PORT GPIOB +#define IOE_I2C_SCL_GPIO_CLK RCC_AHB1Periph_GPIOB +#define IOE_I2C_SCL_SOURCE GPIO_PinSource6 +#define IOE_I2C_SCL_AF GPIO_AF_I2C1 +#define IOE_I2C_SDA_PIN GPIO_Pin_9 +#define IOE_I2C_SDA_GPIO_PORT GPIOB +#define IOE_I2C_SDA_GPIO_CLK RCC_AHB1Periph_GPIOB +#define IOE_I2C_SDA_SOURCE GPIO_PinSource9 +#define IOE_I2C_SDA_AF GPIO_AF_I2C1 +#define IOE_I2C_DR ((uint32_t)0x40005410) + +/* I2C clock speed configuration (in Hz) + WARNING: + Make sure that this define is not already declared in other files (ie. + stm322xg_eval.h file). It can be used in parallel by other modules. */ +#ifndef I2C_SPEED + #define I2C_SPEED 100000 +#endif /* I2C_SPEED */ + +/** + * @brief IOE DMA definitions + */ +#define IOE_DMA_CLK RCC_AHB1Periph_DMA1 +#define IOE_DMA_CHANNEL DMA_Channel_1 + +#ifndef IOE_DMA_TX_STREAM + #define IOE_DMA_TX_STREAM DMA1_Stream6 +#endif /* IOE_DMA_TX_STREAM */ + +#ifndef IOE_DMA_TX_TCFLAG + #define IOE_DMA_TX_TCFLAG DMA_FLAG_TCIF6 +#endif /* IOE_DMA_TX_TCFLAG */ + +#ifndef IOE_DMA_RX_STREAM + #define IOE_DMA_RX_STREAM DMA1_Stream0 +#endif /* IOE_DMA_RX_STREAM */ + +#ifndef IOE_DMA_RX_TCFLAG + #define IOE_DMA_RX_TCFLAG DMA_FLAG_TCIF0 +#endif /* IOE_DMA_RX_TCFLAG */ + +/** + * @brief IO Expander Interrupt line on EXTI + */ +#define IOE_IT_PIN GPIO_Pin_2 +#define IOE_IT_GPIO_PORT GPIOI +#define IOE_IT_GPIO_CLK RCC_AHB1Periph_GPIOI +#define IOE_IT_EXTI_PORT_SOURCE EXTI_PortSourceGPIOI +#define IOE_IT_EXTI_PIN_SOURCE EXTI_PinSource2 +#define IOE_IT_EXTI_LINE EXTI_Line2 +#define IOE_IT_EXTI_IRQn EXTI2_IRQn + +/** + * @brief Eval Board IO Pins definition + */ +#define AUDIO_RESET_PIN IO_Pin_2 /* IO_Exapnader_2 */ /* Output */ +#define MII_INT_PIN IO_Pin_0 /* IO_Exapnader_2 */ /* Output */ +#define VBAT_DIV_PIN IO_Pin_0 /* IO_Exapnader_1 */ /* Output */ +#define MEMS_INT1_PIN IO_Pin_3 /* IO_Exapnader_1 */ /* Input */ +#define MEMS_INT2_PIN IO_Pin_2 /* IO_Exapnader_1 */ /* Input */ + +/** + * @brief Eval Board both IO Exapanders Pins definition + */ +#define IO1_IN_ALL_PINS (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN) +#define IO2_IN_ALL_PINS (uint32_t)(JOY_IO_PINS) +#define IO1_OUT_ALL_PINS (uint32_t)(VBAT_DIV_PIN) +#define IO2_OUT_ALL_PINS (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN) + +/** + * @brief The 7 bits IO Expanders adresses and chip IDs + */ +#define IOE_1_ADDR 0x82 +#define IOE_2_ADDR 0x88 +#define STMPE811_ID 0x0811 + + +/*------------------------------------------------------------------------------ + Functional and Interrupt Management +------------------------------------------------------------------------------*/ +/** + * @brief IO Expander Functionalities definitions + */ +#define IOE_ADC_FCT 0x01 +#define IOE_TS_FCT 0x02 +#define IOE_IO_FCT 0x04 +#define IOE_TEMPSENS_FCT 0x08 + +/** + * @brief Interrupt source configuration definitons + */ +#define IOE_ITSRC_TSC 0x01 /* IO_Exapnder 1 */ +#define IOE_ITSRC_INMEMS 0x02 /* IO_Exapnder 1 */ +#define IOE_ITSRC_JOYSTICK 0x04 /* IO_Exapnder 2 */ +#define IOE_ITSRC_TEMPSENS 0x08 /* IO_Exapnder 2 */ + +/** + * @brief Glaobal Interrupts definitions + */ +#define IOE_GIT_GPIO 0x80 +#define IOE_GIT_ADC 0x40 +#define IOE_GIT_TEMP 0x20 +#define IOE_GIT_FE 0x10 +#define IOE_GIT_FF 0x08 +#define IOE_GIT_FOV 0x04 +#define IOE_GIT_FTH 0x02 +#define IOE_GIT_TOUCH 0x01 + + +/*------------------------------------------------------------------------------ + STMPE811 device register definition +------------------------------------------------------------------------------*/ +/** + * @brief Identification registers + */ +#define IOE_REG_CHP_ID 0x00 +#define IOE_REG_ID_VER 0x02 + +/** + * @brief General Control Registers + */ +#define IOE_REG_SYS_CTRL1 0x03 +#define IOE_REG_SYS_CTRL2 0x04 +#define IOE_REG_SPI_CFG 0x08 + +/** + * @brief Interrupt Control register + */ +#define IOE_REG_INT_CTRL 0x09 +#define IOE_REG_INT_EN 0x0A +#define IOE_REG_INT_STA 0x0B +#define IOE_REG_GPIO_INT_EN 0x0C +#define IOE_REG_GPIO_INT_STA 0x0D + +/** + * @brief GPIO Registers + */ +#define IOE_REG_GPIO_SET_PIN 0x10 +#define IOE_REG_GPIO_CLR_PIN 0x11 +#define IOE_REG_GPIO_MP_STA 0x12 +#define IOE_REG_GPIO_DIR 0x13 +#define IOE_REG_GPIO_ED 0x14 +#define IOE_REG_GPIO_RE 0x15 +#define IOE_REG_GPIO_FE 0x16 +#define IOE_REG_GPIO_AF 0x17 + +/** + * @brief ADC Registers + */ +#define IOE_REG_ADC_INT_EN 0x0E +#define IOE_REG_ADC_INT_STA 0x0F +#define IOE_REG_ADC_CTRL1 0x20 +#define IOE_REG_ADC_CTRL2 0x21 +#define IOE_REG_ADC_CAPT 0x22 +#define IOE_REG_ADC_DATA_CH0 0x30 /* 16-Bit register */ +#define IOE_REG_ADC_DATA_CH1 0x32 /* 16-Bit register */ +#define IOE_REG_ADC_DATA_CH2 0x34 /* 16-Bit register */ +#define IOE_REG_ADC_DATA_CH3 0x36 /* 16-Bit register */ +#define IOE_REG_ADC_DATA_CH4 0x38 /* 16-Bit register */ +#define IOE_REG_ADC_DATA_CH5 0x3A /* 16-Bit register */ +#define IOE_REG_ADC_DATA_CH6 0x3B /* 16-Bit register */ +#define IOE_REG_ADC_DATA_CH7 0x3C /* 16-Bit register */ + +/** + * @brief TouchScreen Registers + */ +#define IOE_REG_TSC_CTRL 0x40 +#define IOE_REG_TSC_CFG 0x41 +#define IOE_REG_WDM_TR_X 0x42 +#define IOE_REG_WDM_TR_Y 0x44 +#define IOE_REG_WDM_BL_X 0x46 +#define IOE_REG_WDM_BL_Y 0x48 +#define IOE_REG_FIFO_TH 0x4A +#define IOE_REG_FIFO_STA 0x4B +#define IOE_REG_FIFO_SIZE 0x4C +#define IOE_REG_TSC_DATA_X 0x4D +#define IOE_REG_TSC_DATA_Y 0x4F +#define IOE_REG_TSC_DATA_Z 0x51 +#define IOE_REG_TSC_DATA_XYZ 0x52 +#define IOE_REG_TSC_FRACT_XYZ 0x56 +#define IOE_REG_TSC_DATA 0x57 +#define IOE_REG_TSC_I_DRIVE 0x58 +#define IOE_REG_TSC_SHIELD 0x59 + +/** + * @brief Temperature Sensor registers + */ +#define IOE_REG_TEMP_CTRL 0x60 +#define IOE_REG_TEMP_DATA 0x61 +#define IOE_REG_TEMP_TH 0x62 + + +/*------------------------------------------------------------------------------ + Functions parameters defines +------------------------------------------------------------------------------*/ +/** + * @brief Touch Screen Pins definition + */ +#define TOUCH_YD IO_Pin_1 /* IO_Exapnader_1 */ /* Input */ +#define TOUCH_XD IO_Pin_2 /* IO_Exapnader_1 */ /* Input */ +#define TOUCH_YU IO_Pin_3 /* IO_Exapnader_1 */ /* Input */ +#define TOUCH_XU IO_Pin_4 /* IO_Exapnader_1 */ /* Input */ +#define TOUCH_IO_ALL (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4) + +/** + * @brief JOYSTICK Pins definition + */ +#define JOY_IO_SEL IO_Pin_7 +#define JOY_IO_DOWN IO_Pin_6 +#define JOY_IO_LEFT IO_Pin_5 +#define JOY_IO_RIGHT IO_Pin_4 +#define JOY_IO_UP IO_Pin_3 +#define JOY_IO_NONE JOY_IO_PINS +#define JOY_IO_PINS (uint32_t)(IO_Pin_3 | IO_Pin_4 | IO_Pin_5 | IO_Pin_6 | IO_Pin_7) + +/** + * @brief IO Pins + */ +#define IO_Pin_0 0x01 +#define IO_Pin_1 0x02 +#define IO_Pin_2 0x04 +#define IO_Pin_3 0x08 +#define IO_Pin_4 0x10 +#define IO_Pin_5 0x20 +#define IO_Pin_6 0x40 +#define IO_Pin_7 0x80 +#define IO_Pin_ALL 0xFF + +/** + * @brief IO Pin directions + */ +#define Direction_IN 0x00 +#define Direction_OUT 0x01 + +/** + * @brief Interrupt Line output parameters + */ +#define Polarity_Low 0x00 +#define Polarity_High 0x04 +#define Type_Level 0x00 +#define Type_Edge 0x02 + +/** + * @brief IO Interrupts + */ +#define IO_IT_0 0x01 +#define IO_IT_1 0x02 +#define IO_IT_2 0x04 +#define IO_IT_3 0x08 +#define IO_IT_4 0x10 +#define IO_IT_5 0x20 +#define IO_IT_6 0x40 +#define IO_IT_7 0x80 +#define ALL_IT 0xFF +#define IOE_JOY_IT (uint8_t)(IO_IT_3 | IO_IT_4 | IO_IT_5 | IO_IT_6 | IO_IT_7) +#define IOE_TS_IT (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2) +#define IOE_INMEMS_IT (uint8_t)(IO_IT_2 | IO_IT_3) + +/** + * @brief Edge detection value + */ +#define EDGE_FALLING 0x01 +#define EDGE_RISING 0x02 + +/** + * @brief Global interrupt Enable bit + */ +#define IOE_GIT_EN 0x01 + +/** + * @} + */ + + + +/** @defgroup STM322xG_EVAL_IOE_Exported_Macros + * @{ + */ +/** + * @} + */ + + + +/** @defgroup STM322xG_EVAL_IOE_Exported_Functions + * @{ + */ + +/** + * @brief Configuration and initialization functions + */ +uint8_t IOE_Config(void); +uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source); + +/** + * @brief Timeout user callback function. This function is called when a timeout + * condition occurs during communication with IO Expander. Only protoype + * of this function is decalred in IO Expander driver. Its implementation + * may be done into user application. This function may typically stop + * current operations and reset the I2C peripheral and IO Expander. + * To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK + * at the top of this file. + */ +#ifdef USE_TIMEOUT_USER_CALLBACK + uint8_t IOE_TimeoutUserCallback(void); +#else + #define IOE_TimeoutUserCallback() IOE_TIMEOUT +#endif /* USE_TIMEOUT_USER_CALLBACK */ + +/** + * @brief IO pins control functions + */ +uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal); +uint8_t IOE_ReadIOPin(uint32_t IO_Pin); +JOYState_TypeDef + IOE_JoyStickGetState(void); + +/** + * @brief Touch Screen controller functions + */ +TS_STATE* IOE_TS_GetState(void); + +/** + * @brief Interrupts Mangement functions + */ +FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT); +uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t IO_IT); +FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT); +uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT); + +/** + * @brief Temperature Sensor functions + */ +uint32_t IOE_TempSens_GetData(void); + +/** + * @brief IO-Expander Control functions + */ +uint8_t IOE_IsOperational(uint8_t DeviceAddr); +uint8_t IOE_Reset(uint8_t DeviceAddr); +uint16_t IOE_ReadID(uint8_t DeviceAddr); + +uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState); +uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction); +uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState); +uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState); +uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState); + +/** + * @brief Low Layer functions + */ +uint8_t IOE_TS_Config(void); +uint8_t IOE_TempSens_Config(void); +uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState); +uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge); +uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type); + +uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue); +uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr); +uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint8_t RegisterAddr); + +#ifdef __cplusplus +} +#endif +#endif /* __STM322xG_EVAL_IOE_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_lcd.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_lcd.c new file mode 100644 index 000000000..5bc078b6f --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_lcd.c @@ -0,0 +1,1438 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_lcd.c + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) + * and AM240320D5TOQW01H (LCD_ILI9325) Liquid Crystal Display Modules + * of STM322xG-EVAL evaluation board(MB786) RevA and RevB. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval_lcd.h" +#include "../Common/fonts.c" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @defgroup STM322xG_EVAL_LCD + * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320) + * and AM240320D5TOQW01H (LCD_ILI9325) Liquid Crystal Display Modules + * of STM322xG_EVAL board. + * @{ + */ + +/** @defgroup STM322xG_EVAL_LCD_Private_TypesDefinitions + * @{ + */ +typedef struct +{ + __IO uint16_t LCD_REG; + __IO uint16_t LCD_RAM; +} LCD_TypeDef; +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_LCD_Private_Defines + * @{ + */ +/* Note: LCD /CS is NE3 - Bank 3 of NOR/SRAM Bank 1~4 */ +#define LCD_BASE ((uint32_t)(0x60000000 | 0x08000000)) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define MAX_POLY_CORNERS 200 +#define POLY_Y(Z) ((int32_t)((Points + Z)->X)) +#define POLY_X(Z) ((int32_t)((Points + Z)->Y)) +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_LCD_Private_Macros + * @{ + */ +#define ABS(X) ((X) > 0 ? (X) : -(X)) +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_LCD_Private_Variables + * @{ + */ +static sFONT *LCD_Currentfonts; + + /* Global variables to set the written text color */ +__IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF; + +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_LCD_Private_FunctionPrototypes + * @{ + */ +#ifndef USE_Delay +static void delay(__IO uint32_t nCount); +#endif /* USE_Delay*/ +static void PutPixel(int16_t x, int16_t y); +static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed); + + +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_LCD_Private_Functions + * @{ + */ + +/** + * @brief DeInitializes the LCD. + * @param None + * @retval None + */ +void LCD_DeInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /*!< LCD Display Off */ + LCD_DisplayOff(); + + /* BANK 3 (of NOR/SRAM Bank 1~4) is disabled */ + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); + + /*!< LCD_SPI DeInit */ + FSMC_NORSRAMDeInit(FSMC_Bank1_NORSRAM3); + +/*-- GPIO Configuration ------------------------------------------------------*/ + /* SRAM Data lines configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | + GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_MCO); + + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | + GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | + GPIO_Pin_15; + + GPIO_Init(GPIOE, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_MCO); + + /* SRAM Address lines configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15; + GPIO_Init(GPIOF, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource0, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource1, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource2, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource3, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource4, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource5, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource12, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource13, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource14, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOF,GPIO_PinSource15, GPIO_AF_MCO); + + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | + GPIO_Pin_4 | GPIO_Pin_5; + + GPIO_Init(GPIOG, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOG,GPIO_PinSource0, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource1, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource2, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource3, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource4, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOG,GPIO_PinSource5, GPIO_AF_MCO); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; + + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOD,GPIO_PinSource11, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource12, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource13, GPIO_AF_MCO); + + /* NOE and NWE configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5; + + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource4, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOD,GPIO_PinSource5, GPIO_AF_MCO); + + /* NE3 configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + + GPIO_Init(GPIOG, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource12, GPIO_AF_MCO); + + /* NBL0, NBL1 configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOE,GPIO_PinSource0, GPIO_AF_MCO); + GPIO_PinAFConfig(GPIOE,GPIO_PinSource1, GPIO_AF_MCO); +} + +/** + * @brief Initializes the LCD. + * @param None + * @retval None + */ +void STM322xG_LCD_Init(void) +{ + __IO uint32_t lcdid = 0; + +/* Configure the LCD Control pins --------------------------------------------*/ + LCD_CtrlLinesConfig(); + +/* Configure the FSMC Parallel interface -------------------------------------*/ + LCD_FSMCConfig(); + + _delay_(5); /* delay 50 ms */ + + /* Read the LCD ID */ + lcdid = LCD_ReadReg(0x00); + + /* Check if the LCD is ILI9320 Controller */ + if(lcdid == 0x9320) + { + /* Start Initial Sequence ------------------------------------------------*/ + LCD_WriteReg(LCD_REG_229,0x8000); /* Set the internal vcore voltage */ + LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */ + LCD_WriteReg(LCD_REG_1, 0x0100); /* set SS and SM bit */ + LCD_WriteReg(LCD_REG_2, 0x0700); /* set 1 line inversion */ + LCD_WriteReg(LCD_REG_3, 0x1030); /* set GRAM write direction and BGR=1. */ + LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ + LCD_WriteReg(LCD_REG_8, 0x0202); /* set the back porch and front porch */ + LCD_WriteReg(LCD_REG_9, 0x0000); /* set non-display area refresh cycle ISC[3:0] */ + LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ + LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ + LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ + LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ + + /* Power On sequence -----------------------------------------------------*/ + LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ + LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ + LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ + + /* Adjust the Gamma Curve ------------------------------------------------*/ + LCD_WriteReg(LCD_REG_48, 0x0007); + LCD_WriteReg(LCD_REG_49, 0x0007); + LCD_WriteReg(LCD_REG_50, 0x0007); + LCD_WriteReg(LCD_REG_53, 0x0007); + LCD_WriteReg(LCD_REG_54, 0x0007); + LCD_WriteReg(LCD_REG_55, 0x0700); + LCD_WriteReg(LCD_REG_56, 0x0700); + LCD_WriteReg(LCD_REG_57, 0x0700); + LCD_WriteReg(LCD_REG_60, 0x0700); + LCD_WriteReg(LCD_REG_61, 0x1F00); + + /* Set GRAM area ---------------------------------------------------------*/ + LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ + LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ + LCD_WriteReg(LCD_REG_96, 0x2700); /* Gate Scan Line */ + LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ + LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ + + /* Partial Display Control -----------------------------------------------*/ + LCD_WriteReg(LCD_REG_128, 0x0000); + LCD_WriteReg(LCD_REG_129, 0x0000); + LCD_WriteReg(LCD_REG_130, 0x0000); + LCD_WriteReg(LCD_REG_131, 0x0000); + LCD_WriteReg(LCD_REG_132, 0x0000); + LCD_WriteReg(LCD_REG_133, 0x0000); + + /* Panel Control ---------------------------------------------------------*/ + LCD_WriteReg(LCD_REG_144, 0x0010); + LCD_WriteReg(LCD_REG_146, 0x0000); + LCD_WriteReg(LCD_REG_147, 0x0003); + LCD_WriteReg(LCD_REG_149, 0x0110); + LCD_WriteReg(LCD_REG_151, 0x0000); + LCD_WriteReg(LCD_REG_152, 0x0000); + + /* Set GRAM write direction and BGR = 1 */ + /* I/D=01 (Horizontal : increment, Vertical : decrement) */ + /* AM=1 (address is updated in vertical writing direction) */ + LCD_WriteReg(LCD_REG_3, 0x1018); + + LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ + } + else if(lcdid == 0x9325) /* Check if the LCD is ILI9325 Controller */ + { + /* Start Initial Sequence ------------------------------------------------*/ + LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */ + LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ + LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ + LCD_WriteReg(LCD_REG_3, 0x1018); /* Set GRAM write direction and BGR=1. */ + LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */ + LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ + LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ + LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */ + LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */ + LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */ + LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */ + + /* Power On sequence -----------------------------------------------------*/ + LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ + LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ + LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ + + /* Adjust the Gamma Curve (ILI9325)---------------------------------------*/ + LCD_WriteReg(LCD_REG_48, 0x0007); + LCD_WriteReg(LCD_REG_49, 0x0302); + LCD_WriteReg(LCD_REG_50, 0x0105); + LCD_WriteReg(LCD_REG_53, 0x0206); + LCD_WriteReg(LCD_REG_54, 0x0808); + LCD_WriteReg(LCD_REG_55, 0x0206); + LCD_WriteReg(LCD_REG_56, 0x0504); + LCD_WriteReg(LCD_REG_57, 0x0007); + LCD_WriteReg(LCD_REG_60, 0x0105); + LCD_WriteReg(LCD_REG_61, 0x0808); + + /* Set GRAM area ---------------------------------------------------------*/ + LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */ + LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */ + + LCD_WriteReg(LCD_REG_96, 0xA700); /* Gate Scan Line(GS=1, scan direction is G320~G1) */ + LCD_WriteReg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ + LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */ + + /* Partial Display Control -----------------------------------------------*/ + LCD_WriteReg(LCD_REG_128, 0x0000); + LCD_WriteReg(LCD_REG_129, 0x0000); + LCD_WriteReg(LCD_REG_130, 0x0000); + LCD_WriteReg(LCD_REG_131, 0x0000); + LCD_WriteReg(LCD_REG_132, 0x0000); + LCD_WriteReg(LCD_REG_133, 0x0000); + + /* Panel Control ---------------------------------------------------------*/ + LCD_WriteReg(LCD_REG_144, 0x0010); + LCD_WriteReg(LCD_REG_146, 0x0000); + LCD_WriteReg(LCD_REG_147, 0x0003); + LCD_WriteReg(LCD_REG_149, 0x0110); + LCD_WriteReg(LCD_REG_151, 0x0000); + LCD_WriteReg(LCD_REG_152, 0x0000); + + /* set GRAM write direction and BGR = 1 */ + /* I/D=00 (Horizontal : increment, Vertical : decrement) */ + /* AM=1 (address is updated in vertical writing direction) */ + LCD_WriteReg(LCD_REG_3, 0x1018); + + LCD_WriteReg(LCD_REG_7, 0x0133); /* 262K color and display ON */ + } + LCD_SetFont(&LCD_DEFAULT_FONT); +} + +/** + * @brief Sets the LCD Text and Background colors. + * @param _TextColor: specifies the Text Color. + * @param _BackColor: specifies the Background Color. + * @retval None + */ +void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor) +{ + TextColor = _TextColor; + BackColor = _BackColor; +} + +/** + * @brief Gets the LCD Text and Background colors. + * @param _TextColor: pointer to the variable that will contain the Text + Color. + * @param _BackColor: pointer to the variable that will contain the Background + Color. + * @retval None + */ +void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor) +{ + *_TextColor = TextColor; *_BackColor = BackColor; +} + +/** + * @brief Sets the Text color. + * @param Color: specifies the Text color code RGB(5-6-5). + * @retval None + */ +void LCD_SetTextColor(__IO uint16_t Color) +{ + TextColor = Color; +} + + +/** + * @brief Sets the Background color. + * @param Color: specifies the Background color code RGB(5-6-5). + * @retval None + */ +void LCD_SetBackColor(__IO uint16_t Color) +{ + BackColor = Color; +} + +/** + * @brief Sets the Text Font. + * @param fonts: specifies the font to be used. + * @retval None + */ +void LCD_SetFont(sFONT *fonts) +{ + LCD_Currentfonts = fonts; +} + +/** + * @brief Gets the Text Font. + * @param None. + * @retval the used font. + */ +sFONT *LCD_GetFont(void) +{ + return LCD_Currentfonts; +} + +/** + * @brief Clears the selected line. + * @param Line: the Line to be cleared. + * This parameter can be one of the following values: + * @arg Linex: where x can be 0..n + * @retval None + */ +void LCD_ClearLine(uint16_t Line) +{ + uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; + /* Send the string character by character on lCD */ + while (((refcolumn + 1)& 0xFFFF) >= LCD_Currentfonts->Width) + { + /* Display one character on LCD */ + LCD_DisplayChar(Line, refcolumn, ' '); + /* Decrement the column position by 16 */ + refcolumn -= LCD_Currentfonts->Width; + } +} + +/** + * @brief Clears the hole LCD. + * @param Color: the color of the background. + * @retval None + */ +void LCD_Clear(uint16_t Color) +{ + uint32_t index = 0; + + LCD_SetCursor(0x00, 0x013F); + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + for(index = 0; index < 76800; index++) + { + LCD->LCD_RAM = Color; + } +} + +/** + * @brief Sets the cursor position. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @retval None + */ +void LCD_SetCursor(uint16_t Xpos, uint16_t Ypos) +{ + LCD_WriteReg(LCD_REG_32, Xpos); + LCD_WriteReg(LCD_REG_33, Ypos); +} + +/** + * @brief Draws a character on LCD. + * @param Xpos: the Line where to display the character shape. + * @param Ypos: start column address. + * @param c: pointer to the character data. + * @retval None + */ +void LCD_DrawChar(uint16_t Xpos, uint16_t Ypos, const uint16_t *c) +{ + uint32_t index = 0, i = 0; + uint16_t Xaddress = 0; + Xaddress = Xpos; + + LCD_SetCursor(Xaddress, Ypos); + + for(index = 0; index < LCD_Currentfonts->Height; index++) + { + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + for(i = 0; i < LCD_Currentfonts->Width; i++) + { + + if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))|| + (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 ))) + + { + LCD_WriteRAM(BackColor); + } + else + { + LCD_WriteRAM(TextColor); + } + } + Xaddress++; + LCD_SetCursor(Xaddress, Ypos); + } +} + +/** + * @brief Displays one character (16dots width, 24dots height). + * @param Line: the Line where to display the character shape . + * This parameter can be one of the following values: + * @arg Linex: where x can be 0..9 + * @param Column: start column address. + * @param Ascii: character ascii code, must be between 0x20 and 0x7E. + * @retval None + */ +void LCD_DisplayChar(uint16_t Line, uint16_t Column, uint8_t Ascii) +{ + Ascii -= 32; + LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]); +} + +/** + * @brief Displays a maximum of 20 char on the LCD. + * @param Line: the Line where to display the character shape . + * This parameter can be one of the following values: + * @arg Linex: where x can be 0..9 + * @param *ptr: pointer to string to display on LCD. + * @retval None + */ +void LCD_DisplayStringLine(uint16_t Line, uint8_t *ptr) +{ + uint16_t refcolumn = LCD_PIXEL_WIDTH - 1; + + /* Send the string character by character on lCD */ + while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)) + { + /* Display one character on LCD */ + LCD_DisplayChar(Line, refcolumn, *ptr); + /* Decrement the column position by 16 */ + refcolumn -= LCD_Currentfonts->Width; + /* Point on the next character */ + ptr++; + } +} + +/** + * @brief Sets a display window + * @param Xpos: specifies the X bottom left position. + * @param Ypos: specifies the Y bottom left position. + * @param Height: display window height. + * @param Width: display window width. + * @retval None + */ +void LCD_SetDisplayWindow(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) +{ + /* Horizontal GRAM Start Address */ + if(Xpos >= Height) + { + LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1)); + } + else + { + LCD_WriteReg(LCD_REG_80, 0); + } + /* Horizontal GRAM End Address */ + LCD_WriteReg(LCD_REG_81, Xpos); + /* Vertical GRAM Start Address */ + if(Ypos >= Width) + { + LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1)); + } + else + { + LCD_WriteReg(LCD_REG_82, 0); + } + /* Vertical GRAM End Address */ + LCD_WriteReg(LCD_REG_83, Ypos); + LCD_SetCursor(Xpos, Ypos); +} + +/** + * @brief Disables LCD Window mode. + * @param None + * @retval None + */ +void LCD_WindowModeDisable(void) +{ + LCD_SetDisplayWindow(239, 0x13F, 240, 320); + LCD_WriteReg(LCD_REG_3, 0x1018); +} + +/** + * @brief Displays a line. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @param Length: line length. + * @param Direction: line direction. + * This parameter can be one of the following values: Vertical or Horizontal. + * @retval None + */ +void LCD_DrawLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction) +{ + uint32_t i = 0; + + LCD_SetCursor(Xpos, Ypos); + if(Direction == LCD_DIR_HORIZONTAL) + { + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + for(i = 0; i < Length; i++) + { + LCD_WriteRAM(TextColor); + } + } + else + { + for(i = 0; i < Length; i++) + { + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + LCD_WriteRAM(TextColor); + Xpos++; + LCD_SetCursor(Xpos, Ypos); + } + } +} + +/** + * @brief Displays a rectangle. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @param Height: display rectangle height. + * @param Width: display rectangle width. + * @retval None + */ +void LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width) +{ + LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); + LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); + + LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); + LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); +} + +/** + * @brief Displays a circle. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @param Radius + * @retval None + */ +void LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) +{ + int32_t D;/* Decision Variable */ + uint32_t CurX;/* Current X Value */ + uint32_t CurY;/* Current Y Value */ + + D = 3 - (Radius << 1); + CurX = 0; + CurY = Radius; + + while (CurX <= CurY) + { + LCD_SetCursor(Xpos + CurX, Ypos + CurY); + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos + CurX, Ypos - CurY); + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurX, Ypos + CurY); + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurX, Ypos - CurY); + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos + CurY, Ypos + CurX); + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos + CurY, Ypos - CurX); + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurY, Ypos + CurX); + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurY, Ypos - CurX); + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + LCD_WriteRAM(TextColor); + if (D < 0) + { + D += (CurX << 2) + 6; + } + else + { + D += ((CurX - CurY) << 2) + 10; + CurY--; + } + CurX++; + } +} + +/** + * @brief Displays a mono-color picture. + * @param Pict: pointer to the picture array. + * @retval None + */ +void LCD_DrawMonoPict(const uint32_t *Pict) +{ + uint32_t index = 0, i = 0; + LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); + LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */ + for(index = 0; index < 2400; index++) + { + for(i = 0; i < 32; i++) + { + if((Pict[index] & (1 << i)) == 0x00) + { + LCD_WriteRAM(BackColor); + } + else + { + LCD_WriteRAM(TextColor); + } + } + } +} + +/** + * @brief Displays a bitmap picture loaded in the internal Flash. + * @param BmpAddress: Bmp picture address in the internal Flash. + * @retval None + */ +void LCD_WriteBMP(uint32_t BmpAddress) +{ + uint32_t index = 0, size = 0; + /* Read bitmap size */ + size = *(__IO uint16_t *) (BmpAddress + 2); + size |= (*(__IO uint16_t *) (BmpAddress + 4)) << 16; + /* Get bitmap data address offset */ + index = *(__IO uint16_t *) (BmpAddress + 10); + index |= (*(__IO uint16_t *) (BmpAddress + 12)) << 16; + size = (size - index)/2; + BmpAddress += index; + /* Set GRAM write direction and BGR = 1 */ + /* I/D=00 (Horizontal : decrement, Vertical : decrement) */ + /* AM=1 (address is updated in vertical writing direction) */ + LCD_WriteReg(LCD_REG_3, 0x1008); + + LCD_WriteRAM_Prepare(); + + for(index = 0; index < size; index++) + { + LCD_WriteRAM(*(__IO uint16_t *)BmpAddress); + BmpAddress += 2; + } + + /* Set GRAM write direction and BGR = 1 */ + /* I/D = 01 (Horizontal : increment, Vertical : decrement) */ + /* AM = 1 (address is updated in vertical writing direction) */ + LCD_WriteReg(LCD_REG_3, 0x1018); +} + +/** + * @brief Displays a full rectangle. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @param Height: rectangle height. + * @param Width: rectangle width. + * @retval None + */ +void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) +{ + LCD_SetTextColor(TextColor); + + LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); + LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL); + + LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL); + LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL); + + Width -= 2; + Height--; + Ypos--; + + LCD_SetTextColor(BackColor); + + while(Height--) + { + LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL); + } + + LCD_SetTextColor(TextColor); +} + +/** + * @brief Displays a full circle. + * @param Xpos: specifies the X position. + * @param Ypos: specifies the Y position. + * @param Radius + * @retval None + */ +void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) +{ + int32_t D; /* Decision Variable */ + uint32_t CurX;/* Current X Value */ + uint32_t CurY;/* Current Y Value */ + + D = 3 - (Radius << 1); + + CurX = 0; + CurY = Radius; + + LCD_SetTextColor(BackColor); + + while (CurX <= CurY) + { + if(CurY > 0) + { + LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); + LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL); + } + + if(CurX > 0) + { + LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); + LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL); + } + if (D < 0) + { + D += (CurX << 2) + 6; + } + else + { + D += ((CurX - CurY) << 2) + 10; + CurY--; + } + CurX++; + } + + LCD_SetTextColor(TextColor); + LCD_DrawCircle(Xpos, Ypos, Radius); +} + +/** + * @brief Displays an uni-line (between two points). + * @param x1: specifies the point 1 x position. + * @param y1: specifies the point 1 y position. + * @param x2: specifies the point 2 x position. + * @param y2: specifies the point 2 y position. + * @retval None + */ +void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) +{ + int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, + yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, + curpixel = 0; + + deltax = ABS(x2 - x1); /* The difference between the x's */ + deltay = ABS(y2 - y1); /* The difference between the y's */ + x = x1; /* Start x off at the first pixel */ + y = y1; /* Start y off at the first pixel */ + + if (x2 >= x1) /* The x-values are increasing */ + { + xinc1 = 1; + xinc2 = 1; + } + else /* The x-values are decreasing */ + { + xinc1 = -1; + xinc2 = -1; + } + + if (y2 >= y1) /* The y-values are increasing */ + { + yinc1 = 1; + yinc2 = 1; + } + else /* The y-values are decreasing */ + { + yinc1 = -1; + yinc2 = -1; + } + + if (deltax >= deltay) /* There is at least one x-value for every y-value */ + { + xinc1 = 0; /* Don't change the x when numerator >= denominator */ + yinc2 = 0; /* Don't change the y for every iteration */ + den = deltax; + num = deltax / 2; + numadd = deltay; + numpixels = deltax; /* There are more x-values than y-values */ + } + else /* There is at least one y-value for every x-value */ + { + xinc2 = 0; /* Don't change the x for every iteration */ + yinc1 = 0; /* Don't change the y when numerator >= denominator */ + den = deltay; + num = deltay / 2; + numadd = deltax; + numpixels = deltay; /* There are more y-values than x-values */ + } + + for (curpixel = 0; curpixel <= numpixels; curpixel++) + { + PutPixel(x, y); /* Draw the current pixel */ + num += numadd; /* Increase the numerator by the top of the fraction */ + if (num >= den) /* Check if numerator >= denominator */ + { + num -= den; /* Calculate the new numerator value */ + x += xinc1; /* Change the x as appropriate */ + y += yinc1; /* Change the y as appropriate */ + } + x += xinc2; /* Change the x as appropriate */ + y += yinc2; /* Change the y as appropriate */ + } +} + +/** + * @brief Displays an poly-line (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @retval None + */ +void LCD_PolyLine(pPoint Points, uint16_t PointCount) +{ + int16_t X = 0, Y = 0; + + if(PointCount < 2) + { + return; + } + + while(--PointCount) + { + X = Points->X; + Y = Points->Y; + Points++; + LCD_DrawUniLine(X, Y, Points->X, Points->Y); + } +} + +/** + * @brief Displays an relative poly-line (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @param Closed: specifies if the draw is closed or not. + * 1: closed, 0 : not closed. + * @retval None + */ +static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed) +{ + int16_t X = 0, Y = 0; + pPoint First = Points; + + if(PointCount < 2) + { + return; + } + X = Points->X; + Y = Points->Y; + while(--PointCount) + { + Points++; + LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y); + X = X + Points->X; + Y = Y + Points->Y; + } + if(Closed) + { + LCD_DrawUniLine(First->X, First->Y, X, Y); + } +} + +/** + * @brief Displays a closed poly-line (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @retval None + */ +void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount) +{ + LCD_PolyLine(Points, PointCount); + LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y); +} + +/** + * @brief Displays a relative poly-line (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @retval None + */ +void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount) +{ + LCD_PolyLineRelativeClosed(Points, PointCount, 0); +} + +/** + * @brief Displays a closed relative poly-line (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @retval None + */ +void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount) +{ + LCD_PolyLineRelativeClosed(Points, PointCount, 1); +} + + +/** + * @brief Displays a full poly-line (between many points). + * @param Points: pointer to the points array. + * @param PointCount: Number of points. + * @retval None + */ +void LCD_FillPolyLine(pPoint Points, uint16_t PointCount) +{ + /* public-domain code by Darel Rex Finley, 2007 */ + uint16_t nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0, + j = 0, swap = 0; + uint16_t IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0; + + IMAGE_LEFT = IMAGE_RIGHT = Points->X; + IMAGE_TOP= IMAGE_BOTTOM = Points->Y; + + for(i = 1; i < PointCount; i++) + { + pixelX = POLY_X(i); + if(pixelX < IMAGE_LEFT) + { + IMAGE_LEFT = pixelX; + } + if(pixelX > IMAGE_RIGHT) + { + IMAGE_RIGHT = pixelX; + } + + pixelY = POLY_Y(i); + if(pixelY < IMAGE_TOP) + { + IMAGE_TOP = pixelY; + } + if(pixelY > IMAGE_BOTTOM) + { + IMAGE_BOTTOM = pixelY; + } + } + + LCD_SetTextColor(BackColor); + + /* Loop through the rows of the image. */ + for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) + { + /* Build a list of nodes. */ + nodes = 0; j = PointCount-1; + + for (i = 0; i < PointCount; i++) + { + if (((POLY_Y(i)<(double) pixelY) && (POLY_Y(j)>=(double) pixelY)) || \ + ((POLY_Y(j)<(double) pixelY) && (POLY_Y(i)>=(double) pixelY))) + { + nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); + } + j = i; + } + + /* Sort the nodes, via a simple "Bubble" sort. */ + i = 0; + while (i < nodes-1) + { + if (nodeX[i]>nodeX[i+1]) + { + swap = nodeX[i]; + nodeX[i] = nodeX[i+1]; + nodeX[i+1] = swap; + if(i) + { + i--; + } + } + else + { + i++; + } + } + + /* Fill the pixels between node pairs. */ + for (i = 0; i < nodes; i+=2) + { + if(nodeX[i] >= IMAGE_RIGHT) + { + break; + } + if(nodeX[i+1] > IMAGE_LEFT) + { + if (nodeX[i] < IMAGE_LEFT) + { + nodeX[i]=IMAGE_LEFT; + } + if(nodeX[i+1] > IMAGE_RIGHT) + { + nodeX[i+1] = IMAGE_RIGHT; + } + LCD_SetTextColor(BackColor); + LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL); + LCD_SetTextColor(TextColor); + PutPixel(pixelY, nodeX[i+1]); + PutPixel(pixelY, nodeX[i]); + /* for (j=nodeX[i]; jLCD_REG = LCD_Reg; + /* Write 16-bit Reg */ + LCD->LCD_RAM = LCD_RegValue; +} + +/** + * @brief Reads the selected LCD Register. + * @param LCD_Reg: address of the selected register. + * @retval LCD Register Value. + */ +uint16_t LCD_ReadReg(uint8_t LCD_Reg) +{ + /* Write 16-bit Index (then Read Reg) */ + LCD->LCD_REG = LCD_Reg; + /* Read 16-bit Reg */ + return (LCD->LCD_RAM); +} + +/** + * @brief Prepare to write to the LCD RAM. + * @param None + * @retval None + */ +void LCD_WriteRAM_Prepare(void) +{ + LCD->LCD_REG = LCD_REG_34; +} + +/** + * @brief Writes to the LCD RAM. + * @param RGB_Code: the pixel color in RGB mode (5-6-5). + * @retval None + */ +void LCD_WriteRAM(uint16_t RGB_Code) +{ + /* Write 16-bit GRAM Reg */ + LCD->LCD_RAM = RGB_Code; +} + +/** + * @brief Reads the LCD RAM. + * @param None + * @retval LCD RAM Value. + */ +uint16_t LCD_ReadRAM(void) +{ + /* Write 16-bit Index (then Read Reg) */ + LCD->LCD_REG = LCD_REG_34; /* Select GRAM Reg */ + /* Read 16-bit Reg */ + return LCD->LCD_RAM; +} + +/** + * @brief Power on the LCD. + * @param None + * @retval None + */ +void LCD_PowerOn(void) +{ +/* Power On sequence ---------------------------------------------------------*/ + LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude*/ + _delay_(20); /* Dis-charge capacitor power voltage (200ms) */ + LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ + LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ + _delay_(5); /* Delay 50 ms */ + LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ +} + +/** + * @brief Enables the Display. + * @param None + * @retval None + */ +void LCD_DisplayOn(void) +{ + /* Display On */ + LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */ +} + +/** + * @brief Disables the Display. + * @param None + * @retval None + */ +void LCD_DisplayOff(void) +{ + /* Display Off */ + LCD_WriteReg(LCD_REG_7, 0x0); +} + +/** + * @brief Configures LCD Control lines (FSMC Pins) in alternate function mode. + * @param None + * @retval None + */ +void LCD_CtrlLinesConfig(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOE | + RCC_AHB1Periph_GPIOF, ENABLE); + +/*-- GPIO Configuration ------------------------------------------------------*/ + /* SRAM Data lines, NOE and NWE configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | + GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15 | + GPIO_Pin_4 |GPIO_Pin_5;; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | + GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | + GPIO_Pin_15; + GPIO_Init(GPIOE, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FSMC); + GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FSMC); + + /* SRAM Address lines configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_Init(GPIOF, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOF, GPIO_PinSource0, GPIO_AF_FSMC); + + /* NE3 configuration */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + + GPIO_Init(GPIOG, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource10, GPIO_AF_FSMC); +} + +/** + * @brief Configures the Parallel interface (FSMC) for LCD(Parallel mode) + * @param None + * @retval None + */ +void LCD_FSMCConfig(void) +{ + FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; + FSMC_NORSRAMTimingInitTypeDef p; + + /* Enable FSMC clock */ + RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); + +/*-- FSMC Configuration ------------------------------------------------------*/ +/*----------------------- SRAM Bank 3 ----------------------------------------*/ + /* FSMC_Bank1_NORSRAM4 configuration */ + p.FSMC_AddressSetupTime = 3; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 9; + p.FSMC_BusTurnAroundDuration = 0; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + /* Color LCD configuration ------------------------------------ + LCD configured as follow: + - Data/Address MUX = Disable + - Memory Type = SRAM + - Data Width = 16bit + - Write Operation = Enable + - Extended Mode = Enable + - Asynchronous Wait = Disable */ + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + /* Enable FSMC NOR/SRAM Bank3 */ + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); +} + +/** + * @brief Displays a pixel. + * @param x: pixel x. + * @param y: pixel y. + * @retval None + */ +static void PutPixel(int16_t x, int16_t y) +{ + if(x < 0 || x > 239 || y < 0 || y > 319) + { + return; + } + LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL); +} + + +#ifndef USE_Delay +/** + * @brief Inserts a delay time. + * @param nCount: specifies the delay time length. + * @retval None + */ +static void delay(__IO uint32_t nCount) +{ + __IO uint32_t index = 0; + for(index = (100000 * nCount); index != 0; index--) + { + } +} +#endif /* USE_Delay*/ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_lcd.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_lcd.h new file mode 100644 index 000000000..32479af57 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_lcd.h @@ -0,0 +1,365 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_lcd.h + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file contains all the functions prototypes for the stm322xg_eval_lcd.c + * driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM322xG_EVAL_LCD_H +#define __STM322xG_EVAL_LCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" +#include "../Common/fonts.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_LCD + * @{ + */ + + +/** @defgroup STM322xG_EVAL_LCD_Exported_Types + * @{ + */ +typedef struct +{ + int16_t X; + int16_t Y; +} Point, * pPoint; +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_LCD_Exported_Constants + * @{ + */ + +/** + * @brief Uncomment the line below if you want to use user defined Delay function + * (for precise timing), otherwise default _delay_ function defined within + * this driver is used (less precise timing). + */ +/* #define USE_Delay */ + +#ifdef USE_Delay +#include "main.h" + #define _delay_ Delay /* !< User can provide more timing precise _delay_ function + (with 10ms time base), using SysTick for example */ +#else + #define _delay_ delay /* !< Default _delay_ function with less precise timing */ +#endif + +/** + * @brief LCD Registers + */ +#define LCD_REG_0 0x00 +#define LCD_REG_1 0x01 +#define LCD_REG_2 0x02 +#define LCD_REG_3 0x03 +#define LCD_REG_4 0x04 +#define LCD_REG_5 0x05 +#define LCD_REG_6 0x06 +#define LCD_REG_7 0x07 +#define LCD_REG_8 0x08 +#define LCD_REG_9 0x09 +#define LCD_REG_10 0x0A +#define LCD_REG_12 0x0C +#define LCD_REG_13 0x0D +#define LCD_REG_14 0x0E +#define LCD_REG_15 0x0F +#define LCD_REG_16 0x10 +#define LCD_REG_17 0x11 +#define LCD_REG_18 0x12 +#define LCD_REG_19 0x13 +#define LCD_REG_20 0x14 +#define LCD_REG_21 0x15 +#define LCD_REG_22 0x16 +#define LCD_REG_23 0x17 +#define LCD_REG_24 0x18 +#define LCD_REG_25 0x19 +#define LCD_REG_26 0x1A +#define LCD_REG_27 0x1B +#define LCD_REG_28 0x1C +#define LCD_REG_29 0x1D +#define LCD_REG_30 0x1E +#define LCD_REG_31 0x1F +#define LCD_REG_32 0x20 +#define LCD_REG_33 0x21 +#define LCD_REG_34 0x22 +#define LCD_REG_36 0x24 +#define LCD_REG_37 0x25 +#define LCD_REG_40 0x28 +#define LCD_REG_41 0x29 +#define LCD_REG_43 0x2B +#define LCD_REG_45 0x2D +#define LCD_REG_48 0x30 +#define LCD_REG_49 0x31 +#define LCD_REG_50 0x32 +#define LCD_REG_51 0x33 +#define LCD_REG_52 0x34 +#define LCD_REG_53 0x35 +#define LCD_REG_54 0x36 +#define LCD_REG_55 0x37 +#define LCD_REG_56 0x38 +#define LCD_REG_57 0x39 +#define LCD_REG_58 0x3A +#define LCD_REG_59 0x3B +#define LCD_REG_60 0x3C +#define LCD_REG_61 0x3D +#define LCD_REG_62 0x3E +#define LCD_REG_63 0x3F +#define LCD_REG_64 0x40 +#define LCD_REG_65 0x41 +#define LCD_REG_66 0x42 +#define LCD_REG_67 0x43 +#define LCD_REG_68 0x44 +#define LCD_REG_69 0x45 +#define LCD_REG_70 0x46 +#define LCD_REG_71 0x47 +#define LCD_REG_72 0x48 +#define LCD_REG_73 0x49 +#define LCD_REG_74 0x4A +#define LCD_REG_75 0x4B +#define LCD_REG_76 0x4C +#define LCD_REG_77 0x4D +#define LCD_REG_78 0x4E +#define LCD_REG_79 0x4F +#define LCD_REG_80 0x50 +#define LCD_REG_81 0x51 +#define LCD_REG_82 0x52 +#define LCD_REG_83 0x53 +#define LCD_REG_96 0x60 +#define LCD_REG_97 0x61 +#define LCD_REG_106 0x6A +#define LCD_REG_118 0x76 +#define LCD_REG_128 0x80 +#define LCD_REG_129 0x81 +#define LCD_REG_130 0x82 +#define LCD_REG_131 0x83 +#define LCD_REG_132 0x84 +#define LCD_REG_133 0x85 +#define LCD_REG_134 0x86 +#define LCD_REG_135 0x87 +#define LCD_REG_136 0x88 +#define LCD_REG_137 0x89 +#define LCD_REG_139 0x8B +#define LCD_REG_140 0x8C +#define LCD_REG_141 0x8D +#define LCD_REG_143 0x8F +#define LCD_REG_144 0x90 +#define LCD_REG_145 0x91 +#define LCD_REG_146 0x92 +#define LCD_REG_147 0x93 +#define LCD_REG_148 0x94 +#define LCD_REG_149 0x95 +#define LCD_REG_150 0x96 +#define LCD_REG_151 0x97 +#define LCD_REG_152 0x98 +#define LCD_REG_153 0x99 +#define LCD_REG_154 0x9A +#define LCD_REG_157 0x9D +#define LCD_REG_192 0xC0 +#define LCD_REG_193 0xC1 +#define LCD_REG_229 0xE5 + +/** + * @brief LCD color + */ +#define LCD_COLOR_WHITE 0xFFFF +#define LCD_COLOR_BLACK 0x0000 +#define LCD_COLOR_GREY 0xF7DE +#define LCD_COLOR_BLUE 0x001F +#define LCD_COLOR_BLUE2 0x051F +#define LCD_COLOR_RED 0xF800 +#define LCD_COLOR_MAGENTA 0xF81F +#define LCD_COLOR_GREEN 0x07E0 +#define LCD_COLOR_CYAN 0x7FFF +#define LCD_COLOR_YELLOW 0xFFE0 + +/** + * @brief LCD Lines depending on the chosen fonts. + */ +#define LCD_LINE_0 LINE(0) +#define LCD_LINE_1 LINE(1) +#define LCD_LINE_2 LINE(2) +#define LCD_LINE_3 LINE(3) +#define LCD_LINE_4 LINE(4) +#define LCD_LINE_5 LINE(5) +#define LCD_LINE_6 LINE(6) +#define LCD_LINE_7 LINE(7) +#define LCD_LINE_8 LINE(8) +#define LCD_LINE_9 LINE(9) +#define LCD_LINE_10 LINE(10) +#define LCD_LINE_11 LINE(11) +#define LCD_LINE_12 LINE(12) +#define LCD_LINE_13 LINE(13) +#define LCD_LINE_14 LINE(14) +#define LCD_LINE_15 LINE(15) +#define LCD_LINE_16 LINE(16) +#define LCD_LINE_17 LINE(17) +#define LCD_LINE_18 LINE(18) +#define LCD_LINE_19 LINE(19) +#define LCD_LINE_20 LINE(20) +#define LCD_LINE_21 LINE(21) +#define LCD_LINE_22 LINE(22) +#define LCD_LINE_23 LINE(23) +#define LCD_LINE_24 LINE(24) +#define LCD_LINE_25 LINE(25) +#define LCD_LINE_26 LINE(26) +#define LCD_LINE_27 LINE(27) +#define LCD_LINE_28 LINE(28) +#define LCD_LINE_29 LINE(29) + +/** + * @brief LCD default font + */ +#define LCD_DEFAULT_FONT Font16x24 + +/** + * @brief LCD Direction + */ +#define LCD_DIR_HORIZONTAL 0x0000 +#define LCD_DIR_VERTICAL 0x0001 + +/** + * @brief LCD Size (Width and Height) + */ +#define LCD_PIXEL_WIDTH 0x0140 +#define LCD_PIXEL_HEIGHT 0x00F0 + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_LCD_Exported_Macros + * @{ + */ +#define ASSEMBLE_RGB(R ,G, B) ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3)) +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_LCD_Exported_Functions + * @{ + */ +/** @defgroup + * @{ + */ +void LCD_DeInit(void); +void STM322xG_LCD_Init(void); +void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); +void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); +void LCD_SetTextColor(__IO uint16_t Color); +void LCD_SetBackColor(__IO uint16_t Color); +void LCD_ClearLine(uint16_t Line); +void LCD_Clear(uint16_t Color); +void LCD_SetCursor(uint16_t Xpos, uint16_t Ypos); +void LCD_DrawChar(uint16_t Xpos, uint16_t Ypos, const uint16_t *c); +void LCD_DisplayChar(uint16_t Line, uint16_t Column, uint8_t Ascii); +void LCD_SetFont(sFONT *fonts); +sFONT *LCD_GetFont(void); +void LCD_DisplayStringLine(uint16_t Line, uint8_t *ptr); +void LCD_SetDisplayWindow(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); +void LCD_WindowModeDisable(void); +void LCD_DrawLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction); +void LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width); +void LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius); +void LCD_DrawMonoPict(const uint32_t *Pict); +void LCD_WriteBMP(uint32_t BmpAddress); +void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); +void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); +void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius); +void LCD_PolyLine(pPoint Points, uint16_t PointCount); +void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount); +void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount); +void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount); +void LCD_FillPolyLine(pPoint Points, uint16_t PointCount); +/** + * @} + */ + +/** @defgroup + * @{ + */ +void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue); +uint16_t LCD_ReadReg(uint8_t LCD_Reg); +void LCD_WriteRAM_Prepare(void); +void LCD_WriteRAM(uint16_t RGB_Code); +uint16_t LCD_ReadRAM(void); +void LCD_PowerOn(void); +void LCD_DisplayOn(void); +void LCD_DisplayOff(void); +/** + * @} + */ + +/** @defgroup + * @{ + */ +void LCD_CtrlLinesConfig(void); +void LCD_FSMCConfig(void); +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM322xG_EVAL_LCD_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_sdio_sd.c b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_sdio_sd.c new file mode 100644 index 000000000..f0b9478c5 --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_sdio_sd.c @@ -0,0 +1,2820 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_sdio_sd.c + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file provides a set of functions needed to manage the SDIO SD + * Card memory mounted on STM322xG-EVAL evaluation board. + * + * + * @verbatim + * + * =================================================================== + * How to use this driver + * =================================================================== + * It implements a high level communication layer for read and write + * from/to this memory. The needed STM32 hardware resources (SDIO and + * GPIO) are defined in stm322xg_eval.h file, and the initialization is + * performed in SD_LowLevel_Init() function declared in stm322xg_eval.c + * file. + * You can easily tailor this driver to any other development board, + * by just adapting the defines for hardware resources and + * SD_LowLevel_Init() function. + * + * A - SD Card Initialization and configuration + * ============================================ + * - To initialize the SD Card, use the SD_Init() function. It + * Initializes the SD Card and put it into StandBy State (Ready + * for data transfer). This function provide the following operations: + * + * 1 - Apply the SD Card initialization process at 400KHz and check + * the SD Card type (Standard Capacity or High Capacity). You + * can change or adapt this frequency by adjusting the + * "SDIO_INIT_CLK_DIV" define inside the stm322xg_eval.h file. + * The SD Card frequency (SDIO_CK) is computed as follows: + * + * +---------------------------------------------+ + * | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) | + * +---------------------------------------------+ + * + * In initialization mode and according to the SD Card standard, + * make sure that the SDIO_CK frequency don't exceed 400KHz. + * + * 2 - Get the SD CID and CSD data. All these information are + * managed by the SDCardInfo structure. This structure provide + * also ready computed SD Card capacity and Block size. + * + * 3 - Configure the SD Card Data transfer frequency. By Default, + * the card transfer frequency is set to 24MHz. You can change + * or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV" + * define inside the stm322xg_eval.h file. + * The SD Card frequency (SDIO_CK) is computed as follows: + * + * +---------------------------------------------+ + * | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) | + * +---------------------------------------------+ + * + * In transfer mode and according to the SD Card standard, + * make sure that the SDIO_CK frequency don't exceed 25MHz + * and 50MHz in High-speed mode switch. + * To be able to use a frequency higher than 24MHz, you should + * use the SDIO peripheral in bypass mode. Refer to the + * corresponding reference manual for more details. + * + * 4 - Select the corresponding SD Card according to the address + * read with the step 2. + * + * 5 - Configure the SD Card in wide bus mode: 4-bits data. + * + * B - SD Card Read operation + * ========================== + * - You can read SD card by using two function: SD_ReadBlock() and + * SD_ReadMultiBlocks() functions. These functions support only + * 512-byte block length. + * - The SD_ReadBlock() function read only one block (512-byte). This + * function can transfer the data using DMA controller or using + * polling mode. To select between DMA or polling mode refer to + * "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm322xg_eval_sdio_sd.h + * file and uncomment the corresponding line. By default the SD DMA + * mode is selected + * - The SD_ReadMultiBlocks() function read only mutli blocks (multiple + * of 512-byte). + * - Any read operation should be followed by two functions to check + * if the DMA Controller and SD Card status. + * - SD_ReadWaitOperation(): this function insure that the DMA + * controller has finished all data transfer. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. + * + * - The DMA transfer is finished by the SDIO Data End interrupt. + * User has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler() + * and SD_ProcessDMAIRQ() function inside the DMA2_Streamx_IRQHandler(). + * Don't forget to enable the SDIO_IRQn and DMA2_Stream3_IRQn or + * DMA2_Stream6_IRQn interrupts using the NVIC controller. + * + * C - SD Card Write operation + * =========================== + * - You can write SD card by using two function: SD_WriteBlock() and + * SD_WriteMultiBlocks() functions. These functions support only + * 512-byte block length. + * - The SD_WriteBlock() function write only one block (512-byte). This + * function can transfer the data using DMA controller or using + * polling mode. To select between DMA or polling mode refer to + * "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm322xg_eval_sdio_sd.h + * file and uncomment the corresponding line. By default the SD DMA + * mode is selected + * - The SD_WriteMultiBlocks() function write only mutli blocks (multiple + * of 512-byte). + * - Any write operation should be followed by two functions to check + * if the DMA Controller and SD Card status. + * - SD_ReadWaitOperation(): this function insure that the DMA + * controller has finished all data transfer. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. + * + * - The DMA transfer is finished by the SDIO Data End interrupt. + * User has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler() + * and SD_ProcessDMAIRQ() function inside the DMA2_Streamx_IRQHandler(). + * Don't forget to enable the SDIO_IRQn and DMA2_Stream3_IRQn or + * DMA2_Stream6_IRQn interrupts using the NVIC controller. + * + * + * D - SD card status + * ================== + * - At any time, you can check the SD Card status and get the SD card + * state by using the SD_GetStatus() function. This function checks + * first if the SD card is still connected and then get the internal + * SD Card transfer state. + * - You can also get the SD card SD Status register by using the + * SD_SendSDStatus() function. + * + * E - Programming Model (Selecting DMA for SDIO data Transfer) + * ============================================================ + * Status = SD_Init(); // Initialization Step as described in section A + * + * // SDIO Interrupt ENABLE + * NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn; + * NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + * NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + * NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + * NVIC_Init(&NVIC_InitStructure); + * // DMA2 STREAMx Interrupt ENABLE + * NVIC_InitStructure.NVIC_IRQChannel = SD_SDIO_DMA_IRQn; + * NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + * NVIC_Init(&NVIC_InitStructure); + * + * // Write operation as described in Section C + * Status = SD_WriteBlock(buffer, address, 512); + * Status = SD_WaitWriteOperation(); + * while(SD_GetStatus() != SD_TRANSFER_OK); + * + * Status = SD_WriteMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS); + * Status = SD_WaitWriteOperation(); + * while(SD_GetStatus() != SD_TRANSFER_OK); + * + * // Read operation as described in Section B + * Status = SD_ReadBlock(buffer, address, 512); + * Status = SD_WaitReadOperation(); + * while(SD_GetStatus() != SD_TRANSFER_OK); + * + * Status = SD_ReadMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS); + * Status = SD_WaitReadOperation(); + * while(SD_GetStatus() != SD_TRANSFER_OK); + * + * - Add the SDIO and DMA2 StreamX (3 or 6) IRQ Handlers: + * void SDIO_IRQHandler(void) + * { + * SD_ProcessIRQ(); + * } + * void SD_SDIO_DMA_IRQHANDLER(void) + * { + * SD_ProcessDMAIRQ(); + * } + * + * F - Programming Model (Selecting Polling for SDIO data Transfer) + * ================================================================ + * //Only SD Card Single Block operation are managed. + * Status = SD_Init(); // Initialization Step as described in section + * + * // Write operation as described in Section C + * Status = SD_WriteBlock(buffer, address, 512); + * + * // Read operation as described in Section B + * Status = SD_ReadBlock(buffer, address, 512); + * + * STM32 SDIO Pin assignment + * ========================= + * +-----------------------------------------------------------+ + * | Pin assignment | + * +-----------------------------+---------------+-------------+ + * | STM32 SDIO Pins | SD | Pin | + * +-----------------------------+---------------+-------------+ + * | SDIO D2 | D2 | 1 | + * | SDIO D3 | D3 | 2 | + * | SDIO CMD | CMD | 3 | + * | | VCC | 4 (3.3 V)| + * | SDIO CLK | CLK | 5 | + * | | GND | 6 (0 V) | + * | SDIO D0 | D0 | 7 | + * | SDIO D1 | D1 | 8 | + * +-----------------------------+---------------+-------------+ + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval_sdio_sd.h" + + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_SDIO_SD + * @brief This file provides all the SD Card driver firmware functions. + * @{ + */ + +/** @defgroup STM322xG_EVAL_SDIO_SD_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_SDIO_SD_Private_Defines + * @{ + */ + +/** + * @brief SDIO Static flags, TimeOut, FIFO Address + */ +#define NULL 0 +#define SDIO_STATIC_FLAGS ((uint32_t)0x000005FF) +#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000) + +/** + * @brief Mask for errors Card Status R1 (OCR Register) + */ +#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) +#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000) +#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000) +#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000) +#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000) +#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) +#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) +#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000) +#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000) +#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000) +#define SD_OCR_CC_ERROR ((uint32_t)0x00100000) +#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) +#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) +#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) +#define SD_OCR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000) +#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000) +#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000) +#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000) +#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008) +#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008) + +/** + * @brief Masks for R6 Response + */ +#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000) +#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000) +#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000) + +#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000) +#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) +#define SD_STD_CAPACITY ((uint32_t)0x00000000) +#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) + +#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) +#define SD_ALLZERO ((uint32_t)0x00000000) + +#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) +#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) +#define SD_CARD_LOCKED ((uint32_t)0x02000000) + +#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF) +#define SD_0TO7BITS ((uint32_t)0x000000FF) +#define SD_8TO15BITS ((uint32_t)0x0000FF00) +#define SD_16TO23BITS ((uint32_t)0x00FF0000) +#define SD_24TO31BITS ((uint32_t)0xFF000000) +#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) + +#define SD_HALFFIFO ((uint32_t)0x00000008) +#define SD_HALFFIFOBYTES ((uint32_t)0x00000020) + +/** + * @brief Command Class Supported + */ +#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080) +#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040) +#define SD_CCCC_ERASE ((uint32_t)0x00000020) + +/** + * @brief Following commands are SD Card Specific commands. + * SDIO_APP_CMD should be sent before sending these commands. + */ +#define SDIO_SEND_IF_COND ((uint32_t)0x00000008) + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_SDIO_SD_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_SDIO_SD_Private_Variables + * @{ + */ + +static uint32_t CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; +static uint32_t CSD_Tab[4], CID_Tab[4], RCA = 0; +static uint8_t SDSTATUS_Tab[16]; +__IO uint32_t StopCondition = 0; +__IO SD_Error TransferError = SD_OK; +__IO uint32_t TransferEnd = 0, DMAEndOfTransfer = 0; +SD_CardInfo SDCardInfo; + +SDIO_InitTypeDef SDIO_InitStructure; +SDIO_CmdInitTypeDef SDIO_CmdInitStructure; +SDIO_DataInitTypeDef SDIO_DataInitStructure; +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_SDIO_SD_Private_Function_Prototypes + * @{ + */ +static SD_Error CmdError(void); +static SD_Error CmdResp1Error(uint8_t cmd); +static SD_Error CmdResp7Error(void); +static SD_Error CmdResp3Error(void); +static SD_Error CmdResp2Error(void); +static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca); +static SD_Error SDEnWideBus(FunctionalState NewState); +static SD_Error IsCardProgramming(uint8_t *pstatus); +static SD_Error FindSCR(uint16_t rca, uint32_t *pscr); +uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes); + +/** + * @} + */ + + +/** @defgroup STM322xG_EVAL_SDIO_SD_Private_Functions + * @{ + */ + +/** + * @brief DeInitializes the SDIO interface. + * @param None + * @retval None + */ +void SD_DeInit(void) +{ + SD_LowLevel_DeInit(); +} + +/** + * @brief Initializes the SD Card and put it into StandBy State (Ready for data + * transfer). + * @param None + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_Init(void) +{ + __IO SD_Error errorstatus = SD_OK; + + /* SDIO Peripheral Low Level Init */ + SD_LowLevel_Init(); + + SDIO_DeInit(); + + errorstatus = SD_PowerON(); + + if (errorstatus != SD_OK) + { + /*!< CMD Response TimeOut (wait for CMDSENT flag) */ + return(errorstatus); + } + + errorstatus = SD_InitializeCards(); + + if (errorstatus != SD_OK) + { + /*!< CMD Response TimeOut (wait for CMDSENT flag) */ + return(errorstatus); + } + + /*!< Configure the SDIO peripheral */ + /*!< SDIO_CK = SDIOCLK / (SDIO_TRANSFER_CLK_DIV + 2) */ + /*!< on STM32F2xx devices, SDIOCLK is fixed to 48MHz */ + SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + + /*----------------- Read CSD/CID MSD registers ------------------*/ + errorstatus = SD_GetCardInfo(&SDCardInfo); + + if (errorstatus == SD_OK) + { + /*----------------- Select Card --------------------------------*/ + errorstatus = SD_SelectDeselect((uint32_t) (SDCardInfo.RCA << 16)); + } + + if (errorstatus == SD_OK) + { + errorstatus = SD_EnableWideBusOperation(SDIO_BusWide_4b); + } + + return(errorstatus); +} + +/** + * @brief Gets the cuurent sd card data transfer status. + * @param None + * @retval SDTransferState: Data Transfer state. + * This value can be: + * - SD_TRANSFER_OK: No data transfer is acting + * - SD_TRANSFER_BUSY: Data transfer is acting + */ +SDTransferState SD_GetStatus(void) +{ + SDCardState cardstate = SD_CARD_TRANSFER; + + cardstate = SD_GetState(); + + if (cardstate == SD_CARD_TRANSFER) + { + return(SD_TRANSFER_OK); + } + else if(cardstate == SD_CARD_ERROR) + { + return (SD_TRANSFER_ERROR); + } + else + { + return(SD_TRANSFER_BUSY); + } +} + +/** + * @brief Returns the current card's state. + * @param None + * @retval SDCardState: SD Card Error or SD Card Current State. + */ +SDCardState SD_GetState(void) +{ + uint32_t resp1 = 0; + + if(SD_Detect()== SD_PRESENT) + { + if (SD_SendStatus(&resp1) != SD_OK) + { + return SD_CARD_ERROR; + } + else + { + return (SDCardState)((resp1 >> 9) & 0x0F); + } + } + else + { + return SD_CARD_ERROR; + } +} + +/** + * @brief Detect if SD card is correctly plugged in the memory slot. + * @param None + * @retval Return if SD is detected or not + */ +uint8_t SD_Detect(void) +{ + __IO uint8_t status = SD_PRESENT; + + /*!< Check GPIO to detect SD */ + if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_RESET) + { + status = SD_NOT_PRESENT; + } + return status; +} + +/** + * @brief Enquires cards about their operating voltage and configures + * clock controls. + * @param None + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_PowerON(void) +{ + __IO SD_Error errorstatus = SD_OK; + uint32_t response = 0, count = 0, validvoltage = 0; + uint32_t SDType = SD_STD_CAPACITY; + + /*!< Power ON Sequence -----------------------------------------------------*/ + /*!< Configure the SDIO peripheral */ + /*!< SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) */ + /*!< on STM32F2xx devices, SDIOCLK is fixed to 48MHz */ + /*!< SDIO_CK for initialization should not exceed 400 KHz */ + SDIO_InitStructure.SDIO_ClockDiv = SDIO_INIT_CLK_DIV; + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + + /*!< Set Power State to ON */ + SDIO_SetPowerState(SDIO_PowerState_ON); + + /*!< Enable SDIO Clock */ + SDIO_ClockCmd(ENABLE); + + /*!< CMD0: GO_IDLE_STATE ---------------------------------------------------*/ + /*!< No CMD response required */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_GO_IDLE_STATE; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdError(); + + if (errorstatus != SD_OK) + { + /*!< CMD Response TimeOut (wait for CMDSENT flag) */ + return(errorstatus); + } + + /*!< CMD8: SEND_IF_COND ----------------------------------------------------*/ + /*!< Send CMD8 to verify SD card interface operating condition */ + /*!< Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /*!< CMD Response: R7 */ + SDIO_CmdInitStructure.SDIO_Argument = SD_CHECK_PATTERN; + SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_IF_COND; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp7Error(); + + if (errorstatus == SD_OK) + { + CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; /*!< SD Card 2.0 */ + SDType = SD_HIGH_CAPACITY; + } + else + { + /*!< CMD55 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + } + /*!< CMD55 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + /*!< If errorstatus is Command TimeOut, it is a MMC card */ + /*!< If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) + or SD card 1.x */ + if (errorstatus == SD_OK) + { + /*!< SD CARD */ + /*!< Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)) + { + + /*!< SEND CMD55 APP_CMD with RCA as 0 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + SDIO_CmdInitStructure.SDIO_Argument = SD_VOLTAGE_WINDOW_SD | SDType; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_OP_COND; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp3Error(); + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + response = SDIO_GetResponse(SDIO_RESP1); + validvoltage = (((response >> 31) == 1) ? 1 : 0); + count++; + } + if (count >= SD_MAX_VOLT_TRIAL) + { + errorstatus = SD_INVALID_VOLTRANGE; + return(errorstatus); + } + + if (response &= SD_HIGH_CAPACITY) + { + CardType = SDIO_HIGH_CAPACITY_SD_CARD; + } + + }/*!< else MMC Card */ + + return(errorstatus); +} + +/** + * @brief Turns the SDIO output signals off. + * @param None + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_PowerOFF(void) +{ + SD_Error errorstatus = SD_OK; + + /*!< Set Power State to OFF */ + SDIO_SetPowerState(SDIO_PowerState_OFF); + + return(errorstatus); +} + +/** + * @brief Intialises all cards or single card as the case may be Card(s) come + * into standby state. + * @param None + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_InitializeCards(void) +{ + SD_Error errorstatus = SD_OK; + uint16_t rca = 0x01; + + if (SDIO_GetPowerState() == SDIO_PowerState_OFF) + { + errorstatus = SD_REQUEST_NOT_APPLICABLE; + return(errorstatus); + } + + if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) + { + /*!< Send CMD2 ALL_SEND_CID */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ALL_SEND_CID; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp2Error(); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + CID_Tab[0] = SDIO_GetResponse(SDIO_RESP1); + CID_Tab[1] = SDIO_GetResponse(SDIO_RESP2); + CID_Tab[2] = SDIO_GetResponse(SDIO_RESP3); + CID_Tab[3] = SDIO_GetResponse(SDIO_RESP4); + } + if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_SECURE_DIGITAL_IO_COMBO_CARD == CardType) + || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) + { + /*!< Send CMD3 SET_REL_ADDR with argument 0 */ + /*!< SD Card publishes its RCA. */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_REL_ADDR; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp6Error(SD_CMD_SET_REL_ADDR, &rca); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + } + + if (SDIO_SECURE_DIGITAL_IO_CARD != CardType) + { + RCA = rca; + + /*!< Send CMD9 SEND_CSD with argument as card's RCA */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)(rca << 16); + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_CSD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp2Error(); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + CSD_Tab[0] = SDIO_GetResponse(SDIO_RESP1); + CSD_Tab[1] = SDIO_GetResponse(SDIO_RESP2); + CSD_Tab[2] = SDIO_GetResponse(SDIO_RESP3); + CSD_Tab[3] = SDIO_GetResponse(SDIO_RESP4); + } + + errorstatus = SD_OK; /*!< All cards get intialized */ + + return(errorstatus); +} + +/** + * @brief Returns information about specific card. + * @param cardinfo: pointer to a SD_CardInfo structure that contains all SD card + * information. + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo) +{ + SD_Error errorstatus = SD_OK; + uint8_t tmp = 0; + + cardinfo->CardType = (uint8_t)CardType; + cardinfo->RCA = (uint16_t)RCA; + + /*!< Byte 0 */ + tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24); + cardinfo->SD_csd.CSDStruct = (tmp & 0xC0) >> 6; + cardinfo->SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2; + cardinfo->SD_csd.Reserved1 = tmp & 0x03; + + /*!< Byte 1 */ + tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16); + cardinfo->SD_csd.TAAC = tmp; + + /*!< Byte 2 */ + tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8); + cardinfo->SD_csd.NSAC = tmp; + + /*!< Byte 3 */ + tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF); + cardinfo->SD_csd.MaxBusClkFrec = tmp; + + /*!< Byte 4 */ + tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24); + cardinfo->SD_csd.CardComdClasses = tmp << 4; + + /*!< Byte 5 */ + tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16); + cardinfo->SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4; + cardinfo->SD_csd.RdBlockLen = tmp & 0x0F; + + /*!< Byte 6 */ + tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8); + cardinfo->SD_csd.PartBlockRead = (tmp & 0x80) >> 7; + cardinfo->SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6; + cardinfo->SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5; + cardinfo->SD_csd.DSRImpl = (tmp & 0x10) >> 4; + cardinfo->SD_csd.Reserved2 = 0; /*!< Reserved */ + + if ((CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || (CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) + { + cardinfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; + + /*!< Byte 7 */ + tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); + cardinfo->SD_csd.DeviceSize |= (tmp) << 2; + + /*!< Byte 8 */ + tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); + cardinfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; + + cardinfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; + cardinfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); + + /*!< Byte 9 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); + cardinfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; + cardinfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; + cardinfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; + /*!< Byte 10 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); + cardinfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; + + cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ; + cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2)); + cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen); + cardinfo->CardCapacity *= cardinfo->CardBlockSize; + } + else if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + /*!< Byte 7 */ + tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF); + cardinfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; + + /*!< Byte 8 */ + tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24); + + cardinfo->SD_csd.DeviceSize |= (tmp << 8); + + /*!< Byte 9 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16); + + cardinfo->SD_csd.DeviceSize |= (tmp); + + /*!< Byte 10 */ + tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); + + cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) * 512 * 1024; + cardinfo->CardBlockSize = 512; + } + + + cardinfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; + cardinfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; + + /*!< Byte 11 */ + tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF); + cardinfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; + cardinfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); + + /*!< Byte 12 */ + tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24); + cardinfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; + cardinfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; + cardinfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; + cardinfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; + + /*!< Byte 13 */ + tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16); + cardinfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; + cardinfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; + cardinfo->SD_csd.Reserved3 = 0; + cardinfo->SD_csd.ContentProtectAppli = (tmp & 0x01); + + /*!< Byte 14 */ + tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8); + cardinfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; + cardinfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6; + cardinfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5; + cardinfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4; + cardinfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2; + cardinfo->SD_csd.ECC = (tmp & 0x03); + + /*!< Byte 15 */ + tmp = (uint8_t)(CSD_Tab[3] & 0x000000FF); + cardinfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1; + cardinfo->SD_csd.Reserved4 = 1; + + + /*!< Byte 0 */ + tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24); + cardinfo->SD_cid.ManufacturerID = tmp; + + /*!< Byte 1 */ + tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16); + cardinfo->SD_cid.OEM_AppliID = tmp << 8; + + /*!< Byte 2 */ + tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8); + cardinfo->SD_cid.OEM_AppliID |= tmp; + + /*!< Byte 3 */ + tmp = (uint8_t)(CID_Tab[0] & 0x000000FF); + cardinfo->SD_cid.ProdName1 = tmp << 24; + + /*!< Byte 4 */ + tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24); + cardinfo->SD_cid.ProdName1 |= tmp << 16; + + /*!< Byte 5 */ + tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16); + cardinfo->SD_cid.ProdName1 |= tmp << 8; + + /*!< Byte 6 */ + tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8); + cardinfo->SD_cid.ProdName1 |= tmp; + + /*!< Byte 7 */ + tmp = (uint8_t)(CID_Tab[1] & 0x000000FF); + cardinfo->SD_cid.ProdName2 = tmp; + + /*!< Byte 8 */ + tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24); + cardinfo->SD_cid.ProdRev = tmp; + + /*!< Byte 9 */ + tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16); + cardinfo->SD_cid.ProdSN = tmp << 24; + + /*!< Byte 10 */ + tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8); + cardinfo->SD_cid.ProdSN |= tmp << 16; + + /*!< Byte 11 */ + tmp = (uint8_t)(CID_Tab[2] & 0x000000FF); + cardinfo->SD_cid.ProdSN |= tmp << 8; + + /*!< Byte 12 */ + tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24); + cardinfo->SD_cid.ProdSN |= tmp; + + /*!< Byte 13 */ + tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16); + cardinfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; + cardinfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8; + + /*!< Byte 14 */ + tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8); + cardinfo->SD_cid.ManufactDate |= tmp; + + /*!< Byte 15 */ + tmp = (uint8_t)(CID_Tab[3] & 0x000000FF); + cardinfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; + cardinfo->SD_cid.Reserved2 = 1; + + return(errorstatus); +} + +/** + * @brief Enables wide bus opeartion for the requeseted card if supported by + * card. + * @param WideMode: Specifies the SD card wide bus mode. + * This parameter can be one of the following values: + * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) + * @arg SDIO_BusWide_4b: 4-bit data transfer + * @arg SDIO_BusWide_1b: 1-bit data transfer + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus) +{ + SD_Error errorstatus = SD_OK; + uint8_t tmp = 0; + + errorstatus = SD_SendSDStatus((uint32_t *)SDSTATUS_Tab); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /*!< Byte 0 */ + tmp = (uint8_t)((SDSTATUS_Tab[0] & 0xC0) >> 6); + cardstatus->DAT_BUS_WIDTH = tmp; + + /*!< Byte 0 */ + tmp = (uint8_t)((SDSTATUS_Tab[0] & 0x20) >> 5); + cardstatus->SECURED_MODE = tmp; + + /*!< Byte 2 */ + tmp = (uint8_t)((SDSTATUS_Tab[2] & 0xFF)); + cardstatus->SD_CARD_TYPE = tmp << 8; + + /*!< Byte 3 */ + tmp = (uint8_t)((SDSTATUS_Tab[3] & 0xFF)); + cardstatus->SD_CARD_TYPE |= tmp; + + /*!< Byte 4 */ + tmp = (uint8_t)(SDSTATUS_Tab[4] & 0xFF); + cardstatus->SIZE_OF_PROTECTED_AREA = tmp << 24; + + /*!< Byte 5 */ + tmp = (uint8_t)(SDSTATUS_Tab[5] & 0xFF); + cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 16; + + /*!< Byte 6 */ + tmp = (uint8_t)(SDSTATUS_Tab[6] & 0xFF); + cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 8; + + /*!< Byte 7 */ + tmp = (uint8_t)(SDSTATUS_Tab[7] & 0xFF); + cardstatus->SIZE_OF_PROTECTED_AREA |= tmp; + + /*!< Byte 8 */ + tmp = (uint8_t)((SDSTATUS_Tab[8] & 0xFF)); + cardstatus->SPEED_CLASS = tmp; + + /*!< Byte 9 */ + tmp = (uint8_t)((SDSTATUS_Tab[9] & 0xFF)); + cardstatus->PERFORMANCE_MOVE = tmp; + + /*!< Byte 10 */ + tmp = (uint8_t)((SDSTATUS_Tab[10] & 0xF0) >> 4); + cardstatus->AU_SIZE = tmp; + + /*!< Byte 11 */ + tmp = (uint8_t)(SDSTATUS_Tab[11] & 0xFF); + cardstatus->ERASE_SIZE = tmp << 8; + + /*!< Byte 12 */ + tmp = (uint8_t)(SDSTATUS_Tab[12] & 0xFF); + cardstatus->ERASE_SIZE |= tmp; + + /*!< Byte 13 */ + tmp = (uint8_t)((SDSTATUS_Tab[13] & 0xFC) >> 2); + cardstatus->ERASE_TIMEOUT = tmp; + + /*!< Byte 13 */ + tmp = (uint8_t)((SDSTATUS_Tab[13] & 0x3)); + cardstatus->ERASE_OFFSET = tmp; + + return(errorstatus); +} + +/** + * @brief Enables wide bus opeartion for the requeseted card if supported by + * card. + * @param WideMode: Specifies the SD card wide bus mode. + * This parameter can be one of the following values: + * @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC) + * @arg SDIO_BusWide_4b: 4-bit data transfer + * @arg SDIO_BusWide_1b: 1-bit data transfer + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_EnableWideBusOperation(uint32_t WideMode) +{ + SD_Error errorstatus = SD_OK; + + /*!< MMC Card doesn't support this feature */ + if (SDIO_MULTIMEDIA_CARD == CardType) + { + errorstatus = SD_UNSUPPORTED_FEATURE; + return(errorstatus); + } + else if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) + { + if (SDIO_BusWide_8b == WideMode) + { + errorstatus = SD_UNSUPPORTED_FEATURE; + return(errorstatus); + } + else if (SDIO_BusWide_4b == WideMode) + { + errorstatus = SDEnWideBus(ENABLE); + + if (SD_OK == errorstatus) + { + /*!< Configure the SDIO peripheral */ + SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + } + } + else + { + errorstatus = SDEnWideBus(DISABLE); + + if (SD_OK == errorstatus) + { + /*!< Configure the SDIO peripheral */ + SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; + SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; + SDIO_Init(&SDIO_InitStructure); + } + } + } + + return(errorstatus); +} + +/** + * @brief Selects od Deselects the corresponding card. + * @param addr: Address of the Card to be selected. + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_SelectDeselect(uint32_t addr) +{ + SD_Error errorstatus = SD_OK; + + /*!< Send CMD7 SDIO_SEL_DESEL_CARD */ + SDIO_CmdInitStructure.SDIO_Argument = addr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEL_DESEL_CARD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SEL_DESEL_CARD); + + return(errorstatus); +} + +/** + * @brief Allows to read one block from a specified address in a card. The Data + * transfer can be managed by DMA mode or Polling mode. + * @note This operation should be followed by two functions to check if the + * DMA Controller and SD Card status. + * - SD_ReadWaitOperation(): this function insure that the DMA + * controller has finished all data transfer. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. + * @param readbuff: pointer to the buffer that will contain the received data + * @param ReadAddr: Address from where data are to be read. + * @param BlockSize: the SD card Data block size. The Block size should be 512. + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize) +{ + SD_Error errorstatus = SD_OK; +#if defined (SD_POLLING_MODE) + uint32_t count = 0, *tempbuff = (uint32_t *)readbuff; +#endif + + TransferError = SD_OK; + TransferEnd = 0; + StopCondition = 0; + + SDIO->DCTRL = 0x0; + + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + ReadAddr /= 512; + } + + /* Set Block Size for Card */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + /*!< Send CMD17 READ_SINGLE_BLOCK */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_SINGLE_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_READ_SINGLE_BLOCK); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + +#if defined (SD_POLLING_MODE) + /*!< In case of single block transfer, no need of stop transfer at all.*/ + /*!< Polling mode */ + while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) + { + if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) + { + for (count = 0; count < 8; count++) + { + *(tempbuff + count) = SDIO_ReadData(); + } + tempbuff += 8; + } + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); + errorstatus = SD_DATA_TIMEOUT; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); + errorstatus = SD_DATA_CRC_FAIL; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_RXOVERR); + errorstatus = SD_RX_OVERRUN; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_STBITERR); + errorstatus = SD_START_BIT_ERR; + return(errorstatus); + } + count = SD_DATATIMEOUT; + while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0)) + { + *tempbuff = SDIO_ReadData(); + tempbuff++; + count--; + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + +#elif defined (SD_DMA_MODE) + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); + SDIO_DMACmd(ENABLE); + SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, BlockSize); +#endif + + return(errorstatus); +} + +/** + * @brief Allows to read blocks from a specified address in a card. The Data + * transfer can be managed by DMA mode or Polling mode. + * @note This operation should be followed by two functions to check if the + * DMA Controller and SD Card status. + * - SD_ReadWaitOperation(): this function insure that the DMA + * controller has finished all data transfer. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. + * @param readbuff: pointer to the buffer that will contain the received data. + * @param ReadAddr: Address from where data are to be read. + * @param BlockSize: the SD card Data block size. The Block size should be 512. + * @param NumberOfBlocks: number of blocks to be read. + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) +{ + SD_Error errorstatus = SD_OK; + TransferError = SD_OK; + TransferEnd = 0; + StopCondition = 1; + + SDIO->DCTRL = 0x0; + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + ReadAddr /= 512; + } + + /*!< Set Block Size for Card */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + /*!< Send CMD18 READ_MULT_BLOCK with argument data address */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_MULT_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_READ_MULT_BLOCK); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); + SDIO_DMACmd(ENABLE); + SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, (NumberOfBlocks * BlockSize)); + + return(errorstatus); +} + +/** + * @brief This function waits until the SDIO DMA data transfer is finished. + * This function should be called after SDIO_ReadMultiBlocks() function + * to insure that all data sent by the card are already transferred by + * the DMA controller. + * @param None. + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_WaitReadOperation(void) +{ + SD_Error errorstatus = SD_OK; + uint32_t timeout; + + timeout = SD_DATATIMEOUT; + + while ((DMAEndOfTransfer == 0x00) && (TransferEnd == 0) && (TransferError == SD_OK) && (timeout > 0)) + { + timeout--; + } + + DMAEndOfTransfer = 0x00; + + timeout = SD_DATATIMEOUT; + + while(((SDIO->STA & SDIO_FLAG_RXACT)) && (timeout > 0)) + { + timeout--; + } + + if (StopCondition == 1) + { + errorstatus = SD_StopTransfer(); + StopCondition = 0; + } + + if ((timeout == 0) && (errorstatus == SD_OK)) + { + errorstatus = SD_DATA_TIMEOUT; + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + if (TransferError != SD_OK) + { + return(TransferError); + } + else + { + return(errorstatus); + } +} + +/** + * @brief Allows to write one block starting from a specified address in a card. + * The Data transfer can be managed by DMA mode or Polling mode. + * @note This operation should be followed by two functions to check if the + * DMA Controller and SD Card status. + * - SD_ReadWaitOperation(): this function insure that the DMA + * controller has finished all data transfer. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. + * @param writebuff: pointer to the buffer that contain the data to be transferred. + * @param WriteAddr: Address from where data are to be read. + * @param BlockSize: the SD card Data block size. The Block size should be 512. + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize) +{ + SD_Error errorstatus = SD_OK; + +#if defined (SD_POLLING_MODE) + uint32_t bytestransferred = 0, count = 0, restwords = 0; + uint32_t *tempbuff = (uint32_t *)writebuff; +#endif + + TransferError = SD_OK; + TransferEnd = 0; + StopCondition = 0; + + SDIO->DCTRL = 0x0; + + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + WriteAddr /= 512; + } + + /* Set Block Size for Card */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + /*!< Send CMD24 WRITE_SINGLE_BLOCK */ + SDIO_CmdInitStructure.SDIO_Argument = WriteAddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_WRITE_SINGLE_BLOCK); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + /*!< In case of single data block transfer no need of stop command at all */ +#if defined (SD_POLLING_MODE) + while (!(SDIO->STA & (SDIO_FLAG_DBCKEND | SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_STBITERR))) + { + if (SDIO_GetFlagStatus(SDIO_FLAG_TXFIFOHE) != RESET) + { + if ((512 - bytestransferred) < 32) + { + restwords = ((512 - bytestransferred) % 4 == 0) ? ((512 - bytestransferred) / 4) : (( 512 - bytestransferred) / 4 + 1); + for (count = 0; count < restwords; count++, tempbuff++, bytestransferred += 4) + { + SDIO_WriteData(*tempbuff); + } + } + else + { + for (count = 0; count < 8; count++) + { + SDIO_WriteData(*(tempbuff + count)); + } + tempbuff += 8; + bytestransferred += 32; + } + } + } + if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); + errorstatus = SD_DATA_TIMEOUT; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); + errorstatus = SD_DATA_CRC_FAIL; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_TXUNDERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_TXUNDERR); + errorstatus = SD_TX_UNDERRUN; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_STBITERR); + errorstatus = SD_START_BIT_ERR; + return(errorstatus); + } +#elif defined (SD_DMA_MODE) + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); + SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, BlockSize); + SDIO_DMACmd(ENABLE); +#endif + + return(errorstatus); +} + +/** + * @brief Allows to write blocks starting from a specified address in a card. + * The Data transfer can be managed by DMA mode only. + * @note This operation should be followed by two functions to check if the + * DMA Controller and SD Card status. + * - SD_ReadWaitOperation(): this function insure that the DMA + * controller has finished all data transfer. + * - SD_GetStatus(): to check that the SD Card has finished the + * data transfer and it is ready for data. + * @param WriteAddr: Address from where data are to be read. + * @param writebuff: pointer to the buffer that contain the data to be transferred. + * @param BlockSize: the SD card Data block size. The Block size should be 512. + * @param NumberOfBlocks: number of blocks to be written. + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) +{ + SD_Error errorstatus = SD_OK; + + TransferError = SD_OK; + TransferEnd = 0; + StopCondition = 1; + + SDIO->DCTRL = 0x0; + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + BlockSize = 512; + WriteAddr /= 512; + } + + /* Set Block Size for Card */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + /*!< To improve performance */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) (RCA << 16); + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + /*!< To improve performance */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)NumberOfBlocks; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCK_COUNT; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCK_COUNT); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + + /*!< Send CMD25 WRITE_MULT_BLOCK with argument data address */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)WriteAddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_MULT_BLOCK; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_WRITE_MULT_BLOCK); + + if (SD_OK != errorstatus) + { + return(errorstatus); + } + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize; + SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE); + SDIO_DMACmd(ENABLE); + SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, (NumberOfBlocks * BlockSize)); + + return(errorstatus); +} + +/** + * @brief This function waits until the SDIO DMA data transfer is finished. + * This function should be called after SDIO_WriteBlock() and + * SDIO_WriteMultiBlocks() function to insure that all data sent by the + * card are already transferred by the DMA controller. + * @param None. + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_WaitWriteOperation(void) +{ + SD_Error errorstatus = SD_OK; + uint32_t timeout; + + timeout = SD_DATATIMEOUT; + + while ((DMAEndOfTransfer == 0x00) && (TransferEnd == 0) && (TransferError == SD_OK) && (timeout > 0)) + { + timeout--; + } + + DMAEndOfTransfer = 0x00; + + timeout = SD_DATATIMEOUT; + + while(((SDIO->STA & SDIO_FLAG_TXACT)) && (timeout > 0)) + { + timeout--; + } + + if (StopCondition == 1) + { + errorstatus = SD_StopTransfer(); + StopCondition = 0; + } + + if ((timeout == 0) && (errorstatus == SD_OK)) + { + errorstatus = SD_DATA_TIMEOUT; + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + if (TransferError != SD_OK) + { + return(TransferError); + } + else + { + return(errorstatus); + } +} + +/** + * @brief Gets the cuurent data transfer state. + * @param None + * @retval SDTransferState: Data Transfer state. + * This value can be: + * - SD_TRANSFER_OK: No data transfer is acting + * - SD_TRANSFER_BUSY: Data transfer is acting + */ +SDTransferState SD_GetTransferState(void) +{ + if (SDIO->STA & (SDIO_FLAG_TXACT | SDIO_FLAG_RXACT)) + { + return(SD_TRANSFER_BUSY); + } + else + { + return(SD_TRANSFER_OK); + } +} + +/** + * @brief Aborts an ongoing data transfer. + * @param None + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_StopTransfer(void) +{ + SD_Error errorstatus = SD_OK; + + /*!< Send CMD12 STOP_TRANSMISSION */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_STOP_TRANSMISSION; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_STOP_TRANSMISSION); + + return(errorstatus); +} + +/** + * @brief Allows to erase memory area specified for the given card. + * @param startaddr: the start address. + * @param endaddr: the end address. + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr) +{ + SD_Error errorstatus = SD_OK; + uint32_t delay = 0; + __IO uint32_t maxdelay = 0; + uint8_t cardstate = 0; + + /*!< Check if the card coomnd class supports erase command */ + if (((CSD_Tab[1] >> 20) & SD_CCCC_ERASE) == 0) + { + errorstatus = SD_REQUEST_NOT_APPLICABLE; + return(errorstatus); + } + + maxdelay = 120000 / ((SDIO->CLKCR & 0xFF) + 2); + + if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) + { + errorstatus = SD_LOCK_UNLOCK_FAILED; + return(errorstatus); + } + + if (CardType == SDIO_HIGH_CAPACITY_SD_CARD) + { + startaddr /= 512; + endaddr /= 512; + } + + /*!< According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ + if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType)) + { + /*!< Send CMD32 SD_ERASE_GRP_START with argument as addr */ + SDIO_CmdInitStructure.SDIO_Argument = startaddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_START; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_START); + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /*!< Send CMD33 SD_ERASE_GRP_END with argument as addr */ + SDIO_CmdInitStructure.SDIO_Argument = endaddr; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_END; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_END); + if (errorstatus != SD_OK) + { + return(errorstatus); + } + } + + /*!< Send CMD38 ERASE */ + SDIO_CmdInitStructure.SDIO_Argument = 0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ERASE; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_ERASE); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + for (delay = 0; delay < maxdelay; delay++) + {} + + /*!< Wait till the card is in programming state */ + errorstatus = IsCardProgramming(&cardstate); + delay = SD_DATATIMEOUT; + while ((delay > 0) && (errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate))) + { + errorstatus = IsCardProgramming(&cardstate); + delay--; + } + + return(errorstatus); +} + +/** + * @brief Returns the current card's status. + * @param pcardstatus: pointer to the buffer that will contain the SD card + * status (Card Status register). + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_SendStatus(uint32_t *pcardstatus) +{ + SD_Error errorstatus = SD_OK; + + if (pcardstatus == NULL) + { + errorstatus = SD_INVALID_PARAMETER; + return(errorstatus); + } + + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SEND_STATUS); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + *pcardstatus = SDIO_GetResponse(SDIO_RESP1); + + return(errorstatus); +} + +/** + * @brief Returns the current SD card's status. + * @param psdstatus: pointer to the buffer that will contain the SD card status + * (SD Status register). + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_SendSDStatus(uint32_t *psdstatus) +{ + SD_Error errorstatus = SD_OK; + uint32_t count = 0; + + if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) + { + errorstatus = SD_LOCK_UNLOCK_FAILED; + return(errorstatus); + } + + /*!< Set block size for card if it is not equal to current block size for card. */ + SDIO_CmdInitStructure.SDIO_Argument = 64; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /*!< CMD55 */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = 64; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + /*!< Send ACMD13 SD_APP_STAUS with argument as card's RCA.*/ + SDIO_CmdInitStructure.SDIO_Argument = 0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_STAUS; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + errorstatus = CmdResp1Error(SD_CMD_SD_APP_STAUS); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) + { + if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET) + { + for (count = 0; count < 8; count++) + { + *(psdstatus + count) = SDIO_ReadData(); + } + psdstatus += 8; + } + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); + errorstatus = SD_DATA_TIMEOUT; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); + errorstatus = SD_DATA_CRC_FAIL; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_RXOVERR); + errorstatus = SD_RX_OVERRUN; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_STBITERR); + errorstatus = SD_START_BIT_ERR; + return(errorstatus); + } + + count = SD_DATATIMEOUT; + while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0)) + { + *psdstatus = SDIO_ReadData(); + psdstatus++; + count--; + } + /*!< Clear all the static status flags*/ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + return(errorstatus); +} + +/** + * @brief Allows to process all the interrupts that are high. + * @param None + * @retval SD_Error: SD Card Error code. + */ +SD_Error SD_ProcessIRQSrc(void) +{ + if (SDIO_GetITStatus(SDIO_IT_DATAEND) != RESET) + { + TransferError = SD_OK; + SDIO_ClearITPendingBit(SDIO_IT_DATAEND); + TransferEnd = 1; + } + else if (SDIO_GetITStatus(SDIO_IT_DCRCFAIL) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_DCRCFAIL); + TransferError = SD_DATA_CRC_FAIL; + } + else if (SDIO_GetITStatus(SDIO_IT_DTIMEOUT) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_DTIMEOUT); + TransferError = SD_DATA_TIMEOUT; + } + else if (SDIO_GetITStatus(SDIO_IT_RXOVERR) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_RXOVERR); + TransferError = SD_RX_OVERRUN; + } + else if (SDIO_GetITStatus(SDIO_IT_TXUNDERR) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_TXUNDERR); + TransferError = SD_TX_UNDERRUN; + } + else if (SDIO_GetITStatus(SDIO_IT_STBITERR) != RESET) + { + SDIO_ClearITPendingBit(SDIO_IT_STBITERR); + TransferError = SD_START_BIT_ERR; + } + + SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | + SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR | + SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE); + return(TransferError); +} + +/** + * @brief This function waits until the SDIO DMA data transfer is finished. + * @param None. + * @retval None. + */ +void SD_ProcessDMAIRQ(void) +{ + if(DMA2->LISR & SD_SDIO_DMA_FLAG_TCIF) + { + DMAEndOfTransfer = 0x01; + DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_TCIF|SD_SDIO_DMA_FLAG_FEIF); + } +} + +/** + * @brief Checks for error conditions for CMD0. + * @param None + * @retval SD_Error: SD Card Error code. + */ +static SD_Error CmdError(void) +{ + SD_Error errorstatus = SD_OK; + uint32_t timeout; + + timeout = SDIO_CMD0TIMEOUT; /*!< 10000 */ + + while ((timeout > 0) && (SDIO_GetFlagStatus(SDIO_FLAG_CMDSENT) == RESET)) + { + timeout--; + } + + if (timeout == 0) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + return(errorstatus); + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + return(errorstatus); +} + +/** + * @brief Checks for error conditions for R7 response. + * @param None + * @retval SD_Error: SD Card Error code. + */ +static SD_Error CmdResp7Error(void) +{ + SD_Error errorstatus = SD_OK; + uint32_t status; + uint32_t timeout = SDIO_CMD0TIMEOUT; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) && (timeout > 0)) + { + timeout--; + status = SDIO->STA; + } + + if ((timeout == 0) || (status & SDIO_FLAG_CTIMEOUT)) + { + /*!< Card is not V2.0 complient or card does not support the set voltage range */ + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + + if (status & SDIO_FLAG_CMDREND) + { + /*!< Card is SD V2.0 compliant */ + errorstatus = SD_OK; + SDIO_ClearFlag(SDIO_FLAG_CMDREND); + return(errorstatus); + } + return(errorstatus); +} + +/** + * @brief Checks for error conditions for R1 response. + * @param cmd: The sent command index. + * @retval SD_Error: SD Card Error code. + */ +static SD_Error CmdResp1Error(uint8_t cmd) +{ + SD_Error errorstatus = SD_OK; + uint32_t status; + uint32_t response_r1; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + else if (status & SDIO_FLAG_CCRCFAIL) + { + errorstatus = SD_CMD_CRC_FAIL; + SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); + return(errorstatus); + } + + /*!< Check response received is of desired command */ + if (SDIO_GetCommandResponse() != cmd) + { + errorstatus = SD_ILLEGAL_CMD; + return(errorstatus); + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + /*!< We have received response, retrieve it for analysis */ + response_r1 = SDIO_GetResponse(SDIO_RESP1); + + if ((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO) + { + return(errorstatus); + } + + if (response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) + { + return(SD_ADDR_OUT_OF_RANGE); + } + + if (response_r1 & SD_OCR_ADDR_MISALIGNED) + { + return(SD_ADDR_MISALIGNED); + } + + if (response_r1 & SD_OCR_BLOCK_LEN_ERR) + { + return(SD_BLOCK_LEN_ERR); + } + + if (response_r1 & SD_OCR_ERASE_SEQ_ERR) + { + return(SD_ERASE_SEQ_ERR); + } + + if (response_r1 & SD_OCR_BAD_ERASE_PARAM) + { + return(SD_BAD_ERASE_PARAM); + } + + if (response_r1 & SD_OCR_WRITE_PROT_VIOLATION) + { + return(SD_WRITE_PROT_VIOLATION); + } + + if (response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) + { + return(SD_LOCK_UNLOCK_FAILED); + } + + if (response_r1 & SD_OCR_COM_CRC_FAILED) + { + return(SD_COM_CRC_FAILED); + } + + if (response_r1 & SD_OCR_ILLEGAL_CMD) + { + return(SD_ILLEGAL_CMD); + } + + if (response_r1 & SD_OCR_CARD_ECC_FAILED) + { + return(SD_CARD_ECC_FAILED); + } + + if (response_r1 & SD_OCR_CC_ERROR) + { + return(SD_CC_ERROR); + } + + if (response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) + { + return(SD_GENERAL_UNKNOWN_ERROR); + } + + if (response_r1 & SD_OCR_STREAM_READ_UNDERRUN) + { + return(SD_STREAM_READ_UNDERRUN); + } + + if (response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) + { + return(SD_STREAM_WRITE_OVERRUN); + } + + if (response_r1 & SD_OCR_CID_CSD_OVERWRIETE) + { + return(SD_CID_CSD_OVERWRITE); + } + + if (response_r1 & SD_OCR_WP_ERASE_SKIP) + { + return(SD_WP_ERASE_SKIP); + } + + if (response_r1 & SD_OCR_CARD_ECC_DISABLED) + { + return(SD_CARD_ECC_DISABLED); + } + + if (response_r1 & SD_OCR_ERASE_RESET) + { + return(SD_ERASE_RESET); + } + + if (response_r1 & SD_OCR_AKE_SEQ_ERROR) + { + return(SD_AKE_SEQ_ERROR); + } + return(errorstatus); +} + +/** + * @brief Checks for error conditions for R3 (OCR) response. + * @param None + * @retval SD_Error: SD Card Error code. + */ +static SD_Error CmdResp3Error(void) +{ + SD_Error errorstatus = SD_OK; + uint32_t status; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + return(errorstatus); +} + +/** + * @brief Checks for error conditions for R2 (CID or CSD) response. + * @param None + * @retval SD_Error: SD Card Error code. + */ +static SD_Error CmdResp2Error(void) +{ + SD_Error errorstatus = SD_OK; + uint32_t status; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + else if (status & SDIO_FLAG_CCRCFAIL) + { + errorstatus = SD_CMD_CRC_FAIL; + SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); + return(errorstatus); + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + return(errorstatus); +} + +/** + * @brief Checks for error conditions for R6 (RCA) response. + * @param cmd: The sent command index. + * @param prca: pointer to the variable that will contain the SD card relative + * address RCA. + * @retval SD_Error: SD Card Error code. + */ +static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca) +{ + SD_Error errorstatus = SD_OK; + uint32_t status; + uint32_t response_r1; + + status = SDIO->STA; + + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + else if (status & SDIO_FLAG_CCRCFAIL) + { + errorstatus = SD_CMD_CRC_FAIL; + SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); + return(errorstatus); + } + + /*!< Check response received is of desired command */ + if (SDIO_GetCommandResponse() != cmd) + { + errorstatus = SD_ILLEGAL_CMD; + return(errorstatus); + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + /*!< We have received response, retrieve it. */ + response_r1 = SDIO_GetResponse(SDIO_RESP1); + + if (SD_ALLZERO == (response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) + { + *prca = (uint16_t) (response_r1 >> 16); + return(errorstatus); + } + + if (response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) + { + return(SD_GENERAL_UNKNOWN_ERROR); + } + + if (response_r1 & SD_R6_ILLEGAL_CMD) + { + return(SD_ILLEGAL_CMD); + } + + if (response_r1 & SD_R6_COM_CRC_FAILED) + { + return(SD_COM_CRC_FAILED); + } + + return(errorstatus); +} + +/** + * @brief Enables or disables the SDIO wide bus mode. + * @param NewState: new state of the SDIO wide bus mode. + * This parameter can be: ENABLE or DISABLE. + * @retval SD_Error: SD Card Error code. + */ +static SD_Error SDEnWideBus(FunctionalState NewState) +{ + SD_Error errorstatus = SD_OK; + + uint32_t scr[2] = {0, 0}; + + if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) + { + errorstatus = SD_LOCK_UNLOCK_FAILED; + return(errorstatus); + } + + /*!< Get SCR Register */ + errorstatus = FindSCR(RCA, scr); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /*!< If wide bus operation to be enabled */ + if (NewState == ENABLE) + { + /*!< If requested card supports wide bus operation */ + if ((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) + { + /*!< Send CMD55 APP_CMD with argument as card's RCA.*/ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ + SDIO_CmdInitStructure.SDIO_Argument = 0x2; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + return(errorstatus); + } + else + { + errorstatus = SD_REQUEST_NOT_APPLICABLE; + return(errorstatus); + } + } /*!< If wide bus operation to be disabled */ + else + { + /*!< If requested card supports 1 bit mode operation */ + if ((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) + { + /*!< Send CMD55 APP_CMD with argument as card's RCA.*/ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ + SDIO_CmdInitStructure.SDIO_Argument = 0x00; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + return(errorstatus); + } + else + { + errorstatus = SD_REQUEST_NOT_APPLICABLE; + return(errorstatus); + } + } +} + +/** + * @brief Checks if the SD card is in programming state. + * @param pstatus: pointer to the variable that will contain the SD card state. + * @retval SD_Error: SD Card Error code. + */ +static SD_Error IsCardProgramming(uint8_t *pstatus) +{ + SD_Error errorstatus = SD_OK; + __IO uint32_t respR1 = 0, status = 0; + + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + status = SDIO->STA; + while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))) + { + status = SDIO->STA; + } + + if (status & SDIO_FLAG_CTIMEOUT) + { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT); + return(errorstatus); + } + else if (status & SDIO_FLAG_CCRCFAIL) + { + errorstatus = SD_CMD_CRC_FAIL; + SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL); + return(errorstatus); + } + + status = (uint32_t)SDIO_GetCommandResponse(); + + /*!< Check response received is of desired command */ + if (status != SD_CMD_SEND_STATUS) + { + errorstatus = SD_ILLEGAL_CMD; + return(errorstatus); + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + + /*!< We have received response, retrieve it for analysis */ + respR1 = SDIO_GetResponse(SDIO_RESP1); + + /*!< Find out card status */ + *pstatus = (uint8_t) ((respR1 >> 9) & 0x0000000F); + + if ((respR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) + { + return(errorstatus); + } + + if (respR1 & SD_OCR_ADDR_OUT_OF_RANGE) + { + return(SD_ADDR_OUT_OF_RANGE); + } + + if (respR1 & SD_OCR_ADDR_MISALIGNED) + { + return(SD_ADDR_MISALIGNED); + } + + if (respR1 & SD_OCR_BLOCK_LEN_ERR) + { + return(SD_BLOCK_LEN_ERR); + } + + if (respR1 & SD_OCR_ERASE_SEQ_ERR) + { + return(SD_ERASE_SEQ_ERR); + } + + if (respR1 & SD_OCR_BAD_ERASE_PARAM) + { + return(SD_BAD_ERASE_PARAM); + } + + if (respR1 & SD_OCR_WRITE_PROT_VIOLATION) + { + return(SD_WRITE_PROT_VIOLATION); + } + + if (respR1 & SD_OCR_LOCK_UNLOCK_FAILED) + { + return(SD_LOCK_UNLOCK_FAILED); + } + + if (respR1 & SD_OCR_COM_CRC_FAILED) + { + return(SD_COM_CRC_FAILED); + } + + if (respR1 & SD_OCR_ILLEGAL_CMD) + { + return(SD_ILLEGAL_CMD); + } + + if (respR1 & SD_OCR_CARD_ECC_FAILED) + { + return(SD_CARD_ECC_FAILED); + } + + if (respR1 & SD_OCR_CC_ERROR) + { + return(SD_CC_ERROR); + } + + if (respR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) + { + return(SD_GENERAL_UNKNOWN_ERROR); + } + + if (respR1 & SD_OCR_STREAM_READ_UNDERRUN) + { + return(SD_STREAM_READ_UNDERRUN); + } + + if (respR1 & SD_OCR_STREAM_WRITE_OVERRUN) + { + return(SD_STREAM_WRITE_OVERRUN); + } + + if (respR1 & SD_OCR_CID_CSD_OVERWRIETE) + { + return(SD_CID_CSD_OVERWRITE); + } + + if (respR1 & SD_OCR_WP_ERASE_SKIP) + { + return(SD_WP_ERASE_SKIP); + } + + if (respR1 & SD_OCR_CARD_ECC_DISABLED) + { + return(SD_CARD_ECC_DISABLED); + } + + if (respR1 & SD_OCR_ERASE_RESET) + { + return(SD_ERASE_RESET); + } + + if (respR1 & SD_OCR_AKE_SEQ_ERROR) + { + return(SD_AKE_SEQ_ERROR); + } + + return(errorstatus); +} + +/** + * @brief Find the SD card SCR register value. + * @param rca: selected card address. + * @param pscr: pointer to the buffer that will contain the SCR value. + * @retval SD_Error: SD Card Error code. + */ +static SD_Error FindSCR(uint16_t rca, uint32_t *pscr) +{ + uint32_t index = 0; + SD_Error errorstatus = SD_OK; + uint32_t tempscr[2] = {0, 0}; + + /*!< Set Block Size To 8 Bytes */ + /*!< Send CMD55 APP_CMD with argument as card's RCA */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)8; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + /*!< Send CMD55 APP_CMD with argument as card's RCA */ + SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_APP_CMD); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT; + SDIO_DataInitStructure.SDIO_DataLength = 8; + SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_8b; + SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO; + SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable; + SDIO_DataConfig(&SDIO_DataInitStructure); + + + /*!< Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ + SDIO_CmdInitStructure.SDIO_Argument = 0x0; + SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_SEND_SCR; + SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short; + SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable; + SDIO_SendCommand(&SDIO_CmdInitStructure); + + errorstatus = CmdResp1Error(SD_CMD_SD_APP_SEND_SCR); + + if (errorstatus != SD_OK) + { + return(errorstatus); + } + + while (!(SDIO->STA & (SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))) + { + if (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) + { + *(tempscr + index) = SDIO_ReadData(); + index++; + } + } + + if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT); + errorstatus = SD_DATA_TIMEOUT; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL); + errorstatus = SD_DATA_CRC_FAIL; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_RXOVERR); + errorstatus = SD_RX_OVERRUN; + return(errorstatus); + } + else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET) + { + SDIO_ClearFlag(SDIO_FLAG_STBITERR); + errorstatus = SD_START_BIT_ERR; + return(errorstatus); + } + + /*!< Clear all the static flags */ + SDIO_ClearFlag(SDIO_STATIC_FLAGS); + + *(pscr + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); + + *(pscr) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); + + return(errorstatus); +} + +/** + * @brief Converts the number of bytes in power of two and returns the power. + * @param NumberOfBytes: number of bytes. + * @retval None + */ +uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes) +{ + uint8_t count = 0; + + while (NumberOfBytes != 1) + { + NumberOfBytes >>= 1; + count++; + } + return(count); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_sdio_sd.h b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_sdio_sd.h new file mode 100644 index 000000000..d410b37fa --- /dev/null +++ b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Utilities/STM32_EVAL/STM322xG_EVAL/stm322xg_eval_sdio_sd.h @@ -0,0 +1,406 @@ +/** + ****************************************************************************** + * @file stm322xg_eval_sdio_sd.h + * @author MCD Application Team + * @version V5.0.3 + * @date 09-March-2012 + * @brief This file contains all the functions prototypes for the SD Card + * stm322xg_eval_sdio_sd driver firmware library. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM322xG_EVAL_SDIO_SD_H +#define __STM322xG_EVAL_SDIO_SD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm322xg_eval.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL + * @{ + */ + +/** @addtogroup STM322xG_EVAL_SDIO_SD + * @{ + */ + +/** @defgroup STM322xG_EVAL_SDIO_SD_Exported_Types + * @{ + */ +typedef enum +{ +/** + * @brief SDIO specific error defines + */ + SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */ + SD_DATA_CRC_FAIL = (2), /*!< Data bock sent/received (CRC check Failed) */ + SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */ + SD_DATA_TIMEOUT = (4), /*!< Data time out */ + SD_TX_UNDERRUN = (5), /*!< Transmit FIFO under-run */ + SD_RX_OVERRUN = (6), /*!< Receive FIFO over-run */ + SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in widE bus mode */ + SD_CMD_OUT_OF_RANGE = (8), /*!< CMD's argument was out of range.*/ + SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */ + SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ + SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs.*/ + SD_BAD_ERASE_PARAM = (12), /*!< An Invalid selection for erase groups */ + SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */ + SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ + SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */ + SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */ + SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */ + SD_CC_ERROR = (18), /*!< Internal card controller error */ + SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or Unknown error */ + SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */ + SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */ + SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */ + SD_WP_ERASE_SKIP = (23), /*!< only partial address space was erased */ + SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */ + SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ + SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */ + SD_INVALID_VOLTRANGE = (27), + SD_ADDR_OUT_OF_RANGE = (28), + SD_SWITCH_ERROR = (29), + SD_SDIO_DISABLED = (30), + SD_SDIO_FUNCTION_BUSY = (31), + SD_SDIO_FUNCTION_FAILED = (32), + SD_SDIO_UNKNOWN_FUNCTION = (33), + +/** + * @brief Standard error defines + */ + SD_INTERNAL_ERROR, + SD_NOT_CONFIGURED, + SD_REQUEST_PENDING, + SD_REQUEST_NOT_APPLICABLE, + SD_INVALID_PARAMETER, + SD_UNSUPPORTED_FEATURE, + SD_UNSUPPORTED_HW, + SD_ERROR, + SD_OK = 0 +} SD_Error; + +/** + * @brief SDIO Transfer state + */ +typedef enum +{ + SD_TRANSFER_OK = 0, + SD_TRANSFER_BUSY = 1, + SD_TRANSFER_ERROR +} SDTransferState; + +/** + * @brief SD Card States + */ +typedef enum +{ + SD_CARD_READY = ((uint32_t)0x00000001), + SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), + SD_CARD_STANDBY = ((uint32_t)0x00000003), + SD_CARD_TRANSFER = ((uint32_t)0x00000004), + SD_CARD_SENDING = ((uint32_t)0x00000005), + SD_CARD_RECEIVING = ((uint32_t)0x00000006), + SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), + SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), + SD_CARD_ERROR = ((uint32_t)0x000000FF) +}SDCardState; + + +/** + * @brief Card Specific Data: CSD Register + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access-time 1 */ + __IO uint8_t NSAC; /*!< Data read access-time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserded */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGrouop; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File Format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< always 1*/ +} SD_CSD; + +/** + * @brief Card Identification Data: CID Register + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< ManufacturerID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2*/ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< always 1 */ +} SD_CID; + +/** + * @brief SD Card Status + */ +typedef struct +{ + __IO uint8_t DAT_BUS_WIDTH; + __IO uint8_t SECURED_MODE; + __IO uint16_t SD_CARD_TYPE; + __IO uint32_t SIZE_OF_PROTECTED_AREA; + __IO uint8_t SPEED_CLASS; + __IO uint8_t PERFORMANCE_MOVE; + __IO uint8_t AU_SIZE; + __IO uint16_t ERASE_SIZE; + __IO uint8_t ERASE_TIMEOUT; + __IO uint8_t ERASE_OFFSET; +} SD_CardStatus; + + +/** + * @brief SD Card information + */ +typedef struct +{ + SD_CSD SD_csd; + SD_CID SD_cid; + uint64_t CardCapacity; /*!< Card Capacity */ + uint32_t CardBlockSize; /*!< Card Block Size */ + uint16_t RCA; + uint8_t CardType; +} SD_CardInfo; + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_SDIO_SD_Exported_Constants + * @{ + */ + +/** + * @brief SDIO Commands Index + */ +#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) +#define SD_CMD_SEND_OP_COND ((uint8_t)1) +#define SD_CMD_ALL_SEND_CID ((uint8_t)2) +#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */ +#define SD_CMD_SET_DSR ((uint8_t)4) +#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) +#define SD_CMD_HS_SWITCH ((uint8_t)6) +#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) +#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) +#define SD_CMD_SEND_CSD ((uint8_t)9) +#define SD_CMD_SEND_CID ((uint8_t)10) +#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD Card doesn't support it */ +#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) +#define SD_CMD_SEND_STATUS ((uint8_t)13) +#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) +#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) +#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) +#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) +#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) +#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) +#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< SD Card doesn't support it */ +#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< SD Card doesn't support it */ +#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) +#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) +#define SD_CMD_PROG_CID ((uint8_t)26) /*!< reserved for manufacturers */ +#define SD_CMD_PROG_CSD ((uint8_t)27) +#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) +#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) +#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) +#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< To set the address of the first write + block to be erased. (For SD card only) */ +#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< To set the address of the last write block of the + continuous range to be erased. (For SD card only) */ +#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< To set the address of the first write block to be erased. + (For MMC card only spec 3.31) */ + +#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< To set the address of the last write block of the + continuous range to be erased. (For MMC card only spec 3.31) */ + +#define SD_CMD_ERASE ((uint8_t)38) +#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD Card doesn't support it */ +#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD Card doesn't support it */ +#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) +#define SD_CMD_APP_CMD ((uint8_t)55) +#define SD_CMD_GEN_CMD ((uint8_t)56) +#define SD_CMD_NO_CMD ((uint8_t)64) + +/** + * @brief Following commands are SD Card Specific commands. + * SDIO_APP_CMD should be sent before sending these commands. + */ +#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< For SD Card only */ +#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< For SD Card only */ +#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< For SD Card only */ +#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O Card only */ +#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O Card only */ + +/** + * @brief Following commands are SD Card Specific security commands. + * SDIO_APP_CMD should be sent before sending these commands. + */ +#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD Card only */ +#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD Card only */ +#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD Card only */ +#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD Card only */ +#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD Card only */ +#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD Card only */ + +/* Uncomment the following line to select the SDIO Data transfer mode */ +#if !defined (SD_DMA_MODE) && !defined (SD_POLLING_MODE) +#define SD_DMA_MODE ((uint32_t)0x00000000) +/*#define SD_POLLING_MODE ((uint32_t)0x00000002)*/ +#endif + +/** + * @brief SD detection on its memory slot + */ +#define SD_PRESENT ((uint8_t)0x01) +#define SD_NOT_PRESENT ((uint8_t)0x00) + +/** + * @brief Supported SD Memory Cards + */ +#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) +#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) +#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) +#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) +#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) +#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) +#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) +#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) + +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_SDIO_SD_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM322xG_EVAL_SDIO_SD_Exported_Functions + * @{ + */ +void SD_DeInit(void); +SD_Error SD_Init(void); +SDTransferState SD_GetStatus(void); +SDCardState SD_GetState(void); +uint8_t SD_Detect(void); +SD_Error SD_PowerON(void); +SD_Error SD_PowerOFF(void); +SD_Error SD_InitializeCards(void); +SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo); +SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus); +SD_Error SD_EnableWideBusOperation(uint32_t WideMode); +SD_Error SD_SelectDeselect(uint32_t addr); +SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize); +SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); +SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize); +SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); +SDTransferState SD_GetTransferState(void); +SD_Error SD_StopTransfer(void); +SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr); +SD_Error SD_SendStatus(uint32_t *pcardstatus); +SD_Error SD_SendSDStatus(uint32_t *psdstatus); +SD_Error SD_ProcessIRQSrc(void); +void SD_ProcessDMAIRQ(void); +SD_Error SD_WaitReadOperation(void); +SD_Error SD_WaitWriteOperation(void); +#ifdef __cplusplus +} +#endif + +#endif /* __STM322xG_EVAL_SDIO_SD_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/_htmresc/CMSIS_Logo_Final.jpg b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/_htmresc/CMSIS_Logo_Final.jpg new file mode 100644 index 000000000..e04560175 Binary files /dev/null and b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/_htmresc/CMSIS_Logo_Final.jpg differ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/_htmresc/logo.bmp b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/_htmresc/logo.bmp new file mode 100644 index 000000000..18a621e81 Binary files /dev/null and b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/_htmresc/logo.bmp differ diff --git a/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/stm32f2xx_stdperiph_lib_um.chm b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/stm32f2xx_stdperiph_lib_um.chm new file mode 100644 index 000000000..95f2e4ab6 Binary files /dev/null and b/src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/stm32f2xx_stdperiph_lib_um.chm differ diff --git a/src/x9d/spi.c b/src/x9d/aspi.cpp similarity index 91% rename from src/x9d/spi.c rename to src/x9d/aspi.cpp index 0f76b6195..b6e4f2c31 100644 --- a/src/x9d/spi.c +++ b/src/x9d/aspi.cpp @@ -9,8 +9,11 @@ * * ****************************************************************************** */ -#include "spi.h" -#include "hal.h" + +#include "../open9x.h" + +#define __no_operation __NOP + /** **********send command to lcd************** */ diff --git a/src/x9d/spi.h b/src/x9d/aspi.h similarity index 94% rename from src/x9d/spi.h rename to src/x9d/aspi.h index 7ddce36e5..de5332512 100644 --- a/src/x9d/spi.h +++ b/src/x9d/aspi.h @@ -8,8 +8,8 @@ * * ****************************************************************************** */ -#ifndef _SPI_H_ -#define _SPI_H_ +#ifndef _ASPI_H_ +#define _ASPI_H_ #include "stm32f2xx.h" diff --git a/src/x9d/audio_driver.cpp b/src/x9d/audio_driver.cpp new file mode 100644 index 000000000..8721d81a8 --- /dev/null +++ b/src/x9d/audio_driver.cpp @@ -0,0 +1,102 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "../open9x.h" + +volatile uint8_t Buzzer_count ; + +// Must NOT be in flash, PDC needs a RAM source. +// Amplitude reduced to 30% to allow for voice volume +uint16_t Sine_values[] = +{ + 2048,2085,2123,2160,2197,2233,2268,2303,2336,2369, + 2400,2430,2458,2485,2510,2533,2554,2573,2590,2605, + 2618,2629,2637,2643,2646,2648,2646,2643,2637,2629, + 2618,2605,2590,2573,2554,2533,2510,2485,2458,2430, + 2400,2369,2336,2303,2268,2233,2197,2160,2123,2085, + 2048,2010,1972,1935,1898,1862,1826,1792,1758,1726, + 1695,1665,1637,1610,1585,1562,1541,1522,1505,1490, + 1477,1466,1458,1452,1448,1448,1448,1452,1458,1466, + 1477,1490,1505,1522,1541,1562,1585,1610,1637,1665, + 1695,1726,1758,1792,1826,1862,1898,1935,1972,2010 +}; + +// Sound routines +void startSound() +{ +} + +uint32_t currentFrequency = 0; + +uint32_t getFrequency() +{ + return currentFrequency; +} + +void setFrequency(uint32_t frequency) +{ + if (currentFrequency != frequency) { + currentFrequency = frequency; + } +} + +// Start TIMER1 at 100000Hz, used for DACC trigger +void start_timer1() +{ +} + + +// Configure DAC0 (or DAC1 for REVA) +// Not sure why PB14 has not be allocated to the DAC, although it is an EXTRA function +// So maybe it is automatically done +void initDac() +{ +} + +void end_sound() +{ +} + +// Set up for volume control (TWI0) +// Need PA3 and PA4 set to peripheral A +void init_twi() +{ +} + +void setVolume( unsigned char volume ) +{ +} +/* +void read_volume() +{ +} */ diff --git a/src/x9d/audio_driver.h b/src/x9d/audio_driver.h new file mode 100644 index 000000000..6c2a8c760 --- /dev/null +++ b/src/x9d/audio_driver.h @@ -0,0 +1,60 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef audio_driver_h +#define audio_driver_h + +#define NUM_VOL_LEVELS 24 + +void startSound( void ) ; +void setFrequency( uint32_t frequency ); +uint32_t getFrequency(); +void start_timer1( void ); +void initDac( void ) ; +void end_sound( void ) ; + +extern uint16_t *nextAudioData; +extern uint16_t nextAudioSize; + +inline void toneStart() +{ +} + +inline void toneStop() +{ +} + +extern void init_twi( void ) ; +extern void setVolume( register uint8_t volume ) ; + +#endif diff --git a/src/x9d/buttons.c b/src/x9d/buttons.c index 975d1a3bb..ae1cf170b 100644 --- a/src/x9d/buttons.c +++ b/src/x9d/buttons.c @@ -1,9 +1,6 @@ -#include "stm32f2xx.h" -#include "hal.h" -#include "buttons.h" +#include "../open9x.h" - -void Buttons_Init() //ÉÏÀ­ÊäÈë״̬ +void Buttons_Init() { GPIO_InitTypeDef GPIO_InitStructure; /* GPIOC GPIOD clock enable */ @@ -56,7 +53,7 @@ void detect_buttons() { /*short t_pin;short t_pin1; static short key_down_interval; - key_down_interval++;//¼ÆÊýÑ­»·¶àÉÙ´ÎÓмü°´Ï + key_down_interval++; t_pin = (~(GPIOC->IDR)) &(PIN_BUTTON_UP | PIN_BUTTON_ENTER | PIN_BUTTON_DOWN); t_pin1=(~(GPIOB->IDR)) &(PIN_POWER | PIN_BIND); @@ -132,4 +129,4 @@ void detect_buttons() pin_status = t_pin; pin_status1=t_pin1;*/ -} \ No newline at end of file +} diff --git a/src/x9d/buttons.h b/src/x9d/buttons.h deleted file mode 100644 index c91a2b5a2..000000000 --- a/src/x9d/buttons.h +++ /dev/null @@ -1,5 +0,0 @@ -#ifndef _BUTTONS_H_ -#define _BUTTONS_H_ - - -#endif \ No newline at end of file diff --git a/src/x9d/diskio.cpp b/src/x9d/diskio.cpp new file mode 100644 index 000000000..bafc0f307 --- /dev/null +++ b/src/x9d/diskio.cpp @@ -0,0 +1,138 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/*-----------------------------------------------------------------------*/ +/* MMCv3/SDv1/SDv2 (in SPI mode) control module (C)ChaN, 2010 */ +/*-----------------------------------------------------------------------*/ +/* Only rcvr_spi(), xmit_spi(), sdPoll10ms() and some macros */ +/* are platform dependent. */ +/*-----------------------------------------------------------------------*/ + +#include +#include "../FatFs/diskio.h" +#include "../FatFs/ff.h" +#include "../CoOS/kernel/CoOS.h" + + + +uint32_t Card_ID[4] ; +uint32_t Card_SCR[2] ; +uint32_t Card_CSD[4] ; +int32_t Card_state; // = SD_ST_STARTUP ; +volatile uint32_t Card_initialized = 0; +uint32_t Sd_rca ; +uint32_t Cmd_A41_resp ; +uint8_t cardType; +uint32_t transSpeed; + +/*-----------------------------------------------------------------------*/ +/* Lock / unlock functions */ +/*-----------------------------------------------------------------------*/ +int ff_cre_syncobj (BYTE vol, _SYNC_t *mutex) +{ + *mutex = CoCreateMutex(); + return 1; +} + +int ff_req_grant (_SYNC_t mutex) +{ + CoEnterMutexSection(mutex); + return 1; +} + +void ff_rel_grant (_SYNC_t mutex) +{ + CoLeaveMutexSection(mutex); +} + +int ff_del_syncobj (_SYNC_t mutex) +{ + return 1; +} + +DSTATUS disk_initialize ( + BYTE drv /* Physical drive nmuber (0) */ + ) +{ + return RES_NOTRDY; +} + +DSTATUS disk_status ( + BYTE drv /* Physical drive number (0) */ + ) +{ + return RES_NOTRDY; +} + + +DRESULT disk_read ( + BYTE drv, /* Physical drive nmuber (0) */ + BYTE *buff, /* Pointer to the data buffer to store read data */ + DWORD sector, /* Start sector number (LBA) */ + BYTE count /* Sector count (1..255) */ + ) +{ + return RES_NOTRDY; +} + +DRESULT disk_write ( + BYTE drv, /* Physical drive nmuber (0) */ + const BYTE *buff, /* Pointer to the data to be written */ + DWORD sector, /* Start sector number (LBA) */ + BYTE count /* Sector count (1..255) */ + ) +{ + return RES_NOTRDY; +} + +DRESULT disk_ioctl ( + BYTE drv, /* Physical drive nmuber (0) */ + BYTE ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ + ) +{ + return RES_NOTRDY; +} + +void sdInit() +{ +} + +void sdMountPoll() +{ +} + +uint32_t sd_card_mounted( void ) +{ + return 0; // CardIsConnected() && Card_state == SD_ST_MOUNTED; +} diff --git a/src/x9d/eeprom_driver.cpp b/src/x9d/eeprom_driver.cpp new file mode 100644 index 000000000..087fbdc9a --- /dev/null +++ b/src/x9d/eeprom_driver.cpp @@ -0,0 +1,52 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "../open9x.h" + +void init_spi() +{ +} + +void eeprom_write_enable() +{ +} + +uint32_t eeprom_read_status() +{ + return !Spi_complete; +} + +uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count ) +{ + return 0; +} diff --git a/src/x9d/keys_driver.cpp b/src/x9d/keys_driver.cpp new file mode 100644 index 000000000..afdf552bc --- /dev/null +++ b/src/x9d/keys_driver.cpp @@ -0,0 +1,169 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "../open9x.h" + + +// keys: +// KEY_EXIT PA31 (PC24) +// KEY_MENU PB6 (PB5) +// KEY_DOWN LCD5 PC3 (PC5) +// KEY_UP LCD6 PC2 (PC1) +// KEY_RIGHT LCD4 PC4 (PC4) +// KEY_LEFT LCD3 PC5 (PC3) +// Reqd. bit 6 LEFT, 5 RIGHT, 4 UP, 3 DOWN 2 EXIT 1 MENU +// LCD pins 5 DOWN, 4 RIGHT, 3 LEFT, 1 UP +uint32_t readKeys() +{ + register uint32_t x = GPIOC->IDR; // 6 LEFT, 5 RIGHT, 4 DOWN, 3 UP + register uint32_t y = 0; + + if (x & 0x00000020) + y |= 0x02 << KEY_ENTER; + if (x & 0x00000010) + y |= 0x02 << KEY_PLUS; + if (x & 0x00000008) + y |= 0x02 << KEY_MINUS; + if (x & 0x00000002) + y |= 0x02 << KEY_MENU; + if (x & 0x00000040) + y |= 0x02 << KEY_PAGE; + if (x & 0x01000000) + y |= 0x02 << KEY_EXIT; + + // printf("readKeys(): %x => %x\n", x, y); fflush(stdout); + + return y ; +} + +uint32_t readTrims() +{ +#if 0 + + uint32_t trims; + uint32_t trima; + + trims = 0; + + trima = PIOA->PIO_PDSR; + +// TRIM_LH_DOWN PA7 (PA23) +#if defined(REVA) + if ( ( trima & 0x0080 ) == 0 ) +#else + if ((trima & 0x00800000) == 0) +#endif + { + trims |= 1; + } + +// TRIM_LV_DOWN PA27 (PA24) +#if defined(REVA) + if ( ( trima & 0x08000000 ) == 0 ) +#else + if ((trima & 0x01000000) == 0) +#endif + { + trims |= 4; + } + +// TRIM_RV_UP PA30 (PA1) +#if defined(REVA) + if ( ( trima & 0x40000000 ) == 0 ) +#else + if ((trima & 0x00000002) == 0) +#endif + { + trims |= 0x20; + } + +// TRIM_RH_DOWN PA29 (PA0) +#if defined(REVA) + if ( ( trima & 0x20000000 ) == 0 ) +#else + if ((trima & 0x00000001) == 0) +#endif + { + trims |= 0x40; + } + +// TRIM_LH_UP PB4 + if ((PIOB->PIO_PDSR & 0x10) == 0) { + trims |= 2; + } + + trima = PIOC->PIO_PDSR; +// TRIM_LV_UP PC28 + if ((trima & 0x10000000) == 0) { + trims |= 8; + } + +// TRIM_RV_DOWN PC10 + if ((trima & 0x00000400) == 0) { + trims |= 0x10; + } + +// TRIM_RH_UP PC9 + if ((trima & 0x00000200) == 0) { + trims |= 0x80; + } + + return trims; +#endif + return 0; +} + +uint8_t keyDown() +{ + return ~readKeys() & 0x7E ; +} + +/* TODO common to ARM */ +void readKeysAndTrims() +{ + register uint32_t i; + + uint8_t enuk = KEY_MENU; + uint8_t in = ~readKeys(); + for (i = 1; i < 7; i++) { + keys[enuk].input(in & (1 << i), (EnumKeys) enuk); + ++enuk; + } + + in = readTrims(); + + for (i = 1; i < 256; i <<= 1) { + keys[enuk].input(in & i, (EnumKeys) enuk); + ++enuk; + } +} diff --git a/src/x9d/lcd_driver.cpp b/src/x9d/lcd_driver.cpp index c31144b96..359160228 100644 --- a/src/x9d/lcd_driver.cpp +++ b/src/x9d/lcd_driver.cpp @@ -9,7 +9,7 @@ ****************************************************************************** */ -#include "open9x.h" +#include "../open9x.h" #define WriteData(x) AspiData(x) #define WriteCommand(x) AspiCmd(x) @@ -118,3 +118,7 @@ void lcdInit() LCD_Hardware_Init(); LCD_Init(); } + +void lcdSetRefVolt(uint8_t val) +{ +} diff --git a/src/x9d/pulses_driver.cpp b/src/x9d/pulses_driver.cpp new file mode 100644 index 000000000..a8c5ab21b --- /dev/null +++ b/src/x9d/pulses_driver.cpp @@ -0,0 +1,52 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "../open9x.h" + +void init_main_ppm( uint32_t period, uint32_t out_enable ) +{ +} + +void disable_main_ppm() +{ +} + +// Initialise the SSC to allow PXX output. +// TD is on PA17, peripheral A +void init_ssc() +{ +} + +void disable_ssc() +{ +} diff --git a/src/x9d/rtc_driver.cpp b/src/x9d/rtc_driver.cpp new file mode 100644 index 000000000..2a6561a67 --- /dev/null +++ b/src/x9d/rtc_driver.cpp @@ -0,0 +1,43 @@ +/* + * Authors (alphabetical order) + * - Bertrand Songis + * - Bryan J. Rentoul (Gruvin) + * - Cameron Weeks + * - Erez Raviv + * - Jean-Pierre Parisy + * - Karl Szmutny + * - Michael Blandford + * - Michal Hlavinka + * - Pat Mackenzie + * - Philip Moss + * - Rob Thomson + * - Romolo Manfredini + * - Thomas Husterer + * + * open9x is based on code named + * gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/, + * er9x by Erez Raviv: http://code.google.com/p/er9x/, + * and the original (and ongoing) project by + * Thomas Husterer, th9x: http://code.google.com/p/th9x/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "../open9x.h" + + +void rtc_settime(struct gtm * t) +{ +} + +void rtc_init() +{ +}