diff --git a/radio/src/targets/horus/board.cpp b/radio/src/targets/horus/board.cpp index 5b07f0687..9cebbfd85 100644 --- a/radio/src/targets/horus/board.cpp +++ b/radio/src/targets/horus/board.cpp @@ -135,6 +135,7 @@ void boardInit() TELEMETRY_RCC_APB1Periph | TRAINER_RCC_APB1Periph | AUDIO_RCC_APB1Periph | + INTMODULE_RCC_APB1Periph | EXTMODULE_RCC_APB1Periph | GPS_RCC_APB1Periph, ENABLE); @@ -142,7 +143,9 @@ void boardInit() BL_RCC_APB2Periph | ADC_RCC_APB2Periph | HAPTIC_RCC_APB2Periph | - INTMODULE_RCC_APB2Periph, ENABLE); + INTMODULE_RCC_APB2Periph | + EXTMODULE_RCC_APB2Periph, + ENABLE); pwrInit(); delaysInit(); diff --git a/radio/src/targets/horus/extmodule_driver.cpp b/radio/src/targets/horus/extmodule_driver.cpp index a580c48da..57a541a41 100644 --- a/radio/src/targets/horus/extmodule_driver.cpp +++ b/radio/src/targets/horus/extmodule_driver.cpp @@ -24,14 +24,14 @@ void extmoduleSendNextFrame(); void extmoduleStop() { + EXTERNAL_MODULE_OFF(); + NVIC_DisableIRQ(EXTMODULE_DMA_IRQn); NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn); EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA EXTMODULE_TIMER->DIER &= ~(TIM_DIER_CC2IE | TIM_DIER_UDE); EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; - - EXTERNAL_MODULE_OFF(); } void extmoduleNoneStart() @@ -91,14 +91,21 @@ void extmodulePpmStart() EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; // Stop timer EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) EXTMODULE_TIMER->ARR = 45000; - // CH1 PWM mode 1, CH1 out is OFF if CNT= 13 + EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2; // PWM mode 1 + EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; + EXTMODULE_TIMER->EGR = 1; // Reloads register values now + EXTMODULE_TIMER->DIER = TIM_DIER_UDE; // Update DMA request + EXTMODULE_TIMER->CR1 = TIM_CR1_CEN; // Start timer +#else EXTMODULE_TIMER->CCR1 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1P : 0); EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high EXTMODULE_TIMER->EGR = 1; // Reloads register values now EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Update DMA request - EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE; // PWM mode 1 + EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE; // PWM mode 1 EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; // Start timer +#endif extmoduleSendNextFrame(); @@ -125,6 +132,17 @@ void extmodulePxxStart() EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) EXTMODULE_TIMER->ARR = 18000; + +#if PCBREV >= 13 + EXTMODULE_TIMER->CCER = TIM_CCER_CC3E | TIM_CCER_CC3NE; + EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs + EXTMODULE_TIMER->CCR3 = 18; + EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0; // Force O/P high + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update + EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2; + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; +#else EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP; // TIM_CCER_CC1E | TIM_CCER_CC1P; EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs EXTMODULE_TIMER->CCR1 = 18; @@ -133,6 +151,7 @@ void extmodulePxxStart() EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; +#endif extmoduleSendNextFrame(); @@ -160,6 +179,17 @@ void extmoduleDsm2Start() EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) EXTMODULE_TIMER->ARR = 44000; // 22mS + +#if PCBREV >= 13 + EXTMODULE_TIMER->CCER = TIM_CCER_CC3E | TIM_CCER_CC3P; + EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs + EXTMODULE_TIMER->CCR3 = 0; + EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0; // Force O/P high + EXTMODULE_TIMER->EGR = 1; // Restart + EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update + EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; + EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; +#else EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P; EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs EXTMODULE_TIMER->CCR1 = 0; @@ -168,6 +198,7 @@ void extmoduleDsm2Start() EXTMODULE_TIMER->DIER |= TIM_DIER_UDE; // Enable DMA on update EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0; EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN; +#endif extmoduleSendNextFrame(); @@ -209,11 +240,19 @@ void extmoduleCrossfireStart() void extmoduleSendNextFrame() { if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) { +#if PCBREV >= 13 + EXTMODULE_TIMER->CCR3 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; + EXTMODULE_TIMER->CCER = TIM_CCER_CC3E | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC3P : 0); + EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance + EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#else EXTMODULE_TIMER->CCR1 = GET_PPM_DELAY(EXTERNAL_MODULE)*2; EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1P : 0); EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_1 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#endif EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].ppm.pulses); EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].ppm.ptr - modulePulsesData[EXTERNAL_MODULE].ppm.pulses; @@ -222,7 +261,11 @@ void extmoduleSendNextFrame() else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) { EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].pxx.ptr - 1) - 4000; // 2mS in advance EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA +#if PCBREV >= 13 + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#else EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_1 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#endif EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].pxx.pulses); EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].pxx.ptr - modulePulsesData[EXTERNAL_MODULE].pxx.pulses; @@ -231,7 +274,11 @@ void extmoduleSendNextFrame() else if (IS_DSM2_PROTOCOL(s_current_protocol[EXTERNAL_MODULE]) || IS_MULTIMODULE_PROTOCOL(s_current_protocol[EXTERNAL_MODULE])) { EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - 1) - 4000; // 2mS in advance EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA +#if PCBREV >= 13 + EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#else EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_1 | DMA_SxCR_MSIZE_1 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1; +#endif EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR); EXTMODULE_DMA_STREAM->M0AR = CONVERT_PTR_UINT(modulePulsesData[EXTERNAL_MODULE].dsm2.pulses); EXTMODULE_DMA_STREAM->NDTR = modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - modulePulsesData[EXTERNAL_MODULE].dsm2.pulses; diff --git a/radio/src/targets/horus/hal.h b/radio/src/targets/horus/hal.h index 979ed94bb..97a4e96ed 100644 --- a/radio/src/targets/horus/hal.h +++ b/radio/src/targets/horus/hal.h @@ -233,9 +233,26 @@ #define SD_SDIO_INIT_CLK_DIV SD_SDIO_CLK_DIV(400000) #define SD_SDIO_TRANSFER_CLK_DIV SD_SDIO_CLK_DIV(24000000) +// EEPROM +#if PCBREV >= 13 +#define EEPROM_RCC_AHB1Periph RCC_AHB1Periph_GPIOA +#define EEPROM_RCC_APB1Periph RCC_APB1Periph_SPI1 +#define EEPROM_SPI_CS_GPIO GPIOA +#define EEPROM_SPI_CS_GPIO_PIN GPIO_Pin_15 // PA.15 +#define EEPROM_SPI_SCK_GPIO GPIOA +#define EEPROM_SPI_SCK_GPIO_PIN GPIO_Pin_5 // PA.05 +#define EEPROM_SPI_SCK_GPIO_PinSource GPIO_PinSource5 +#define EEPROM_SPI_MISO_GPIO GPIOA +#define EEPROM_SPI_MISO_GPIO_PIN GPIO_Pin_6 // PA.06 +#define EEPROM_SPI_MISO_GPIO_PinSource GPIO_PinSource6 +#define EEPROM_SPI_MOSI_GPIO GPIOA +#define EEPROM_SPI_MOSI_GPIO_PIN GPIO_Pin_7 // PA.07 +#define EEPROM_SPI_MOSI_GPIO_PinSource GPIO_PinSource7 +#endif + // Audio #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOH) -#define AUDIO_RCC_APB1Periph (RCC_APB1Periph_SPI2) +#define AUDIO_RCC_APB1Periph RCC_APB1Periph_SPI2 #define AUDIO_SHUTDOWN_GPIO GPIOI #define AUDIO_SHUTDOWN_GPIO_PIN GPIO_Pin_9 // PI.09 #define AUDIO_XDCS_GPIO GPIOI @@ -281,7 +298,6 @@ // Internal Module #define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) -#define INTMODULE_RCC_APB2Periph (RCC_APB2Periph_TIM1 | RCC_APB2Periph_USART1) #define INTMODULE_PWR_GPIO GPIOA #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_8 // PA.08 #define INTMODULE_TX_GPIO GPIOB @@ -298,30 +314,60 @@ #define INTMODULE_DMA_STREAM_IRQHandler DMA2_Stream7_IRQHandler #define INTMODULE_DMA_FLAG_TC DMA_IT_TCIF7 #define INTMODULE_DMA_CHANNEL DMA_Channel_4 +#if PCBREV >= 13 +#define INTMODULE_RCC_APB1Periph RCC_APB1Periph_TIM2 +#define INTMODULE_RCC_APB2Periph RCC_APB2Periph_USART1 +#define INTMODULE_TIMER TIM2 +#define INTMODULE_TIMER_IRQn TIM2_IRQn +#define INTMODULE_TIMER_IRQHandler TIM2_IRQHandler +#define INTMODULE_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) +#else +#define INTMODULE_RCC_APB1Periph 0 +#define INTMODULE_RCC_APB2Periph (RCC_APB2Periph_TIM1 | RCC_APB2Periph_USART1) #define INTMODULE_TIMER TIM1 -#define INTMODULE_TIMER_CC_IRQn TIM1_CC_IRQn -#define INTMODULE_TIMER_CC_IRQHandler TIM1_CC_IRQHandler +#define INTMODULE_TIMER_IRQn TIM1_CC_IRQn +#define INTMODULE_TIMER_IRQHandler TIM1_CC_IRQHandler #define INTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) +#endif // External Module -#define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) -#define EXTMODULE_RCC_APB1Periph RCC_APB1Periph_TIM2 #define EXTMODULE_PWR_GPIO GPIOB #define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_3 // PB.03 +#if PCBREV >= 13 +#define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) +#define EXTMODULE_RCC_APB1Periph 0 +#define EXTMODULE_RCC_APB2Periph RCC_APB2Periph_TIM1 +#define EXTMODULE_PPM_GPIO GPIOA +#define EXTMODULE_PPM_GPIO_PIN GPIO_Pin_10 // PA.10 +#define EXTMODULE_PPM_GPIO_PinSource GPIO_PinSource10 +#define EXTMODULE_PPM_GPIO_AF GPIO_AF_TIM1 +#define EXTMODULE_TIMER TIM1 +#define EXTMODULE_TIMER_IRQn TIM1_CC_IRQn +#define EXTMODULE_TIMER_IRQHandler TIM1_CC_IRQHandler +#define EXTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) +#define EXTMODULE_DMA_CHANNEL DMA_Channel_6 +#define EXTMODULE_DMA_STREAM DMA2_Stream5 +#define EXTMODULE_DMA_IRQn DMA2_Stream5_IRQn +#define EXTMODULE_DMA_IRQHandler DMA2_Stream5_IRQHandler +#define EXTMODULE_DMA_FLAG_TC DMA_IT_TCIF5 +#else +#define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) +#define EXTMODULE_RCC_APB1Periph RCC_APB1Periph_TIM2 +#define EXTMODULE_RCC_APB2Periph 0 #define EXTMODULE_PPM_GPIO GPIOA #define EXTMODULE_PPM_GPIO_PIN GPIO_Pin_15 // PA.15 #define EXTMODULE_PPM_GPIO_PinSource GPIO_PinSource15 -#define EXTMODULE_TIMER TIM2 #define EXTMODULE_PPM_GPIO_AF GPIO_AF_TIM2 -#define EXTMODULE_DMA DMA1 +#define EXTMODULE_TIMER TIM2 +#define EXTMODULE_TIMER_IRQn TIM2_IRQn +#define EXTMODULE_TIMER_IRQHandler TIM2_IRQHandler +#define EXTMODULE_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define EXTMODULE_DMA_CHANNEL DMA_Channel_3 #define EXTMODULE_DMA_STREAM DMA1_Stream7 #define EXTMODULE_DMA_IRQn DMA1_Stream7_IRQn #define EXTMODULE_DMA_IRQHandler DMA1_Stream7_IRQHandler #define EXTMODULE_DMA_FLAG_TC DMA_IT_TCIF7 -#define EXTMODULE_TIMER_IRQn TIM2_IRQn -#define EXTMODULE_TIMER_IRQHandler TIM2_IRQHandler -#define EXTMODULE_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) +#endif // Trainer Port #define TRAINER_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_DMA1) diff --git a/radio/src/targets/horus/pulses_driver.cpp b/radio/src/targets/horus/pulses_driver.cpp index 6757080a8..dde368962 100644 --- a/radio/src/targets/horus/pulses_driver.cpp +++ b/radio/src/targets/horus/pulses_driver.cpp @@ -114,7 +114,7 @@ void intmoduleStop() { INTERNAL_MODULE_OFF(); - NVIC_DisableIRQ(INTMODULE_TIMER_CC_IRQn); + NVIC_DisableIRQ(INTMODULE_TIMER_IRQn); INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN; @@ -124,7 +124,6 @@ void intmoduleNoneStart() { INTERNAL_MODULE_OFF(); - // Timer1, channel 3 GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitStructure.GPIO_Pin = INTMODULE_TX_GPIO_PIN; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; @@ -148,8 +147,8 @@ void intmoduleNoneStart() INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt INTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - NVIC_EnableIRQ(INTMODULE_TIMER_CC_IRQn); - NVIC_SetPriority(INTMODULE_TIMER_CC_IRQn, 7); + NVIC_EnableIRQ(INTMODULE_TIMER_IRQn); + NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7); } void intmodulePxxStart() @@ -197,7 +196,6 @@ void intmodulePxxStart() INTMODULE_TIMER->CCR2 = 15000; // Update time INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz) INTMODULE_TIMER->CCER = TIM_CCER_CC3E; - INTMODULE_TIMER->CCER = TIM_CCER_CC3E; INTMODULE_TIMER->CCMR2 = 0; INTMODULE_TIMER->EGR = 1; // Restart @@ -206,8 +204,8 @@ void intmodulePxxStart() INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt INTMODULE_TIMER->CR1 |= TIM_CR1_CEN; - NVIC_EnableIRQ(INTMODULE_TIMER_CC_IRQn); - NVIC_SetPriority(INTMODULE_TIMER_CC_IRQn, 7); + NVIC_EnableIRQ(INTMODULE_TIMER_IRQn); + NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7); } extern "C" void INTMODULE_DMA_STREAM_IRQHandler(void) @@ -219,16 +217,8 @@ extern "C" void INTMODULE_DMA_STREAM_IRQHandler(void) } } -extern "C" void INTMODULE_TIMER_CC_IRQHandler() +void intmoduleSendNextFrame() { - DEBUG_INTERRUPT(INT_TIM1CC); - DEBUG_TIMER_SAMPLE(debugTimerIntPulses); - DEBUG_TIMER_START(debugTimerIntPulsesDuration); - - INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag - - setupPulses(INTERNAL_MODULE); - if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) { DMA_InitTypeDef DMA_InitStructure; DMA_DeInit(INTMODULE_DMA_STREAM); @@ -252,7 +242,17 @@ extern "C" void INTMODULE_TIMER_CC_IRQHandler() DMA_Cmd(INTMODULE_DMA_STREAM, ENABLE); USART_DMACmd(INTMODULE_USART, USART_DMAReq_Tx, ENABLE); } +} - // INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; +extern "C" void INTMODULE_TIMER_IRQHandler() +{ + DEBUG_INTERRUPT(INT_TIM1CC); + DEBUG_TIMER_SAMPLE(debugTimerIntPulses); + DEBUG_TIMER_START(debugTimerIntPulsesDuration); + + INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag + setupPulses(INTERNAL_MODULE); + intmoduleSendNextFrame(); + DEBUG_TIMER_STOP(debugTimerIntPulsesDuration); } diff --git a/radio/src/targets/taranis/pulses_driver.cpp b/radio/src/targets/taranis/pulses_driver.cpp index 2303a890c..66f3ff6e1 100644 --- a/radio/src/targets/taranis/pulses_driver.cpp +++ b/radio/src/targets/taranis/pulses_driver.cpp @@ -262,7 +262,7 @@ void intmoduleSendNextFrame() } #if defined(TARANIS_INTERNAL_PPM) else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) { - INTMODULE_TIMER->CCR3 = GET_PPM_DEAY(INTERNAL_MODULE)*2; + INTMODULE_TIMER->CCR3 = GET_PPM_DELAY(INTERNAL_MODULE)*2; INTMODULE_TIMER->CCER = TIM_CCER_CC3E | (GET_PPM_POLARITY(INTERNAL_MODULE) ? 0 : TIM_CCER_CC3P); INTMODULE_TIMER->CCR2 = *(modulePulsesData[INTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance INTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA