feat: Support for Flysky ST16 (#6071)
Co-authored-by: raphaelcoeffic <1050031+raphaelcoeffic@users.noreply.github.com> Co-authored-by: Peter Feerick <peter.feerick@gmail.com> Co-authored-by: philmoz <phil.a.mitchell@gmail.com> Co-authored-by: Malte Langermann <malte@langermann.net>
This commit is contained in:
richardclli
co-authored by
raphaelcoeffic
Peter Feerick
philmoz
Malte Langermann
raphaelcoeffic
Peter Feerick
philmoz
Malte Langermann
parent
94965c1d09
commit
f82c3dea8c
@@ -0,0 +1,222 @@
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#include <stdint.h>
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#include "stm32_cmsis.h"
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#include "system_clock.h"
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#include "stm32_hal.h"
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#define NAKED __attribute__((naked))
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#define BOOTSTRAP __attribute__((section(".bootstrap")))
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// Linker script symbols
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extern uint32_t _sisr_vector;
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extern uint32_t SDRAM_START;
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extern "C" NAKED BOOTSTRAP
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void Reset_Handler()
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{
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asm inline (
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"ldr sp, =_estack \n"
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);
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#if defined(BOOT)
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asm inline (
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"bl SystemInit \n"
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"bl SystemClock_Config \n"
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"bl CPU_CACHE_Enable \n"
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);
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#endif
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// Copy code into normal RAM
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asm inline (
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"ldr r0, =_stext \n"
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"ldr r1, =_etext \n"
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"ldr r2, =_text_load \n"
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"bl naked_copy \n"
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);
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#if defined(BOOT)
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asm inline (
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"bl MPU_Init \n"
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);
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#endif
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// Copy / setup ISR vector
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asm inline (
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"ldr r0, =_sisr_vector \n"
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"ldr r1, =_eisr_vector \n"
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"ldr r2, =_isr_load \n"
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"bl naked_copy \n"
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"bl set_vtor \n"
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);
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// Copy code into fast RAM
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asm inline (
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"ldr r0, =_siram \n"
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"ldr r1, =_eiram \n"
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"ldr r2, =_stext_iram \n"
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"bl naked_copy \n"
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);
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// Copy initialized data segment
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asm inline (
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"ldr r0, =_sdata \n"
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"ldr r1, =_edata \n"
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"ldr r2, =_sidata \n"
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"bl naked_copy \n"
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);
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#if defined(BOOT)
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asm inline (
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"bl pwrResetHandler \n"
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);
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#endif
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// Zero fill bss segment
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asm inline (
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"ldr r2, =_sbss \n"
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"ldr r4, =_ebss \n"
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"movs r3, 0 \n"
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"b LoopFillZerobss \n"
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"FillZerobss: \n"
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"str r3, [r2] \n"
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"adds r2, r2, 4 \n"
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"LoopFillZerobss: \n"
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"cmp r2, r4 \n"
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"bcc FillZerobss \n"
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);
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asm inline (
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"bl clean_dcache \n"
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// Call static constructors
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"bl __libc_init_array \n"
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"bl SystemCoreClockUpdate \n"
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// Call the application's entry point
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"bl main \n"
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"bx lr \n"
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);
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}
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extern "C" BOOTSTRAP void set_vtor() {
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SCB->VTOR = (intptr_t)&_sisr_vector;
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}
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extern "C" NAKED BOOTSTRAP void naked_copy() {
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// r0: destination start
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// r1: destination end
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// r2: source start
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asm inline (
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"cmp r0, r2 \n"
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"beq SkipCopy \n"
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"movs r3, 0 \n"
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"b LoopCopyInit \n"
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"CopyInit: \n"
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"ldr r4, [r2, r3] \n"
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"str r4, [r0, r3] \n"
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"adds r3, r3, #4 \n"
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"LoopCopyInit: \n"
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"adds r4, r0, r3 \n"
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"cmp r4, r1 \n"
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"bcc CopyInit \n"
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"SkipCopy: \n"
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"bx lr \n"
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);
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}
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extern "C" BOOTSTRAP
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void CPU_CACHE_Enable()
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{
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/* Enable I-Cache */
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SCB_EnableICache();
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/* Enable D-Cache */
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SCB_EnableDCache();
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}
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extern "C" __attribute__((used))
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void MPU_Init()
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{
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MPU_Region_InitTypeDef MPU_InitStruct = {0};
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/* Disables the MPU */
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HAL_MPU_Disable();
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/*
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* Region 0: overwrite default setting to prevent speculative
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* read to unavailable memories.
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* Range: 0x60000000 to 0xE0000000
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*
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* Set as strongly ordered, code execution disabled
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*/
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER0;
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MPU_InitStruct.BaseAddress = 0;
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MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
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MPU_InitStruct.SubRegionDisable = 0x87;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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#if defined(FIRMWARE_QSPI)
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/* Region 2: QSPI memory range, bank1 */
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER2;
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MPU_InitStruct.BaseAddress = 0x90000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_8MB;
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MPU_InitStruct.SubRegionDisable = 0x0;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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#endif
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#if defined(SDRAM)
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/* Region 3: SDRAM memory range */
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER3;
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MPU_InitStruct.BaseAddress = (uint32_t)&SDRAM_START;
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MPU_InitStruct.Size = MPU_REGION_SIZE_8MB;
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MPU_InitStruct.SubRegionDisable = 0x0;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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#endif
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/* Region 3: SRAM1 memory range */
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.Number = MPU_REGION_NUMBER4;
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MPU_InitStruct.BaseAddress = 0x30000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
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MPU_InitStruct.SubRegionDisable = 0x0;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
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/* Enable bus fault exception */
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SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
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}
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extern "C" void clean_dcache() {
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SCB_CleanDCache();
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}
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