Review line ending handling (#4820)
* New line end handling rules * Normalize all the line endings
This commit is contained in:
3djc
@@ -1,270 +1,270 @@
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/*
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* Copyright (C) OpenTX
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*
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* Based on code named
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* th9x - http://code.google.com/p/th9x
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* er9x - http://code.google.com/p/er9x
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* gruvin9x - http://code.google.com/p/gruvin9x
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*
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* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "opentx.h"
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void intmoduleStop(void);
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void extmoduleStop(void);
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void intmoduleNoneStart(void);
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void intmodulePxxStart(void);
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void extmoduleNoneStart(void);
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void extmodulePpmStart(void);
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void extmodulePxxStart(void);
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#if defined(DSM2)
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void extmoduleDsm2Start(void);
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#endif
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void extmoduleCrossfireStart(void);
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void init_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleNoneStart();
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else
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extmoduleNoneStart();
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}
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void disable_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleStop();
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else
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extmoduleStop();
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}
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void init_ppm(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmodulePpmStart();
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}
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}
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void disable_ppm(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleStop();
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}
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}
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void init_pxx(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmodulePxxStart();
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else
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extmodulePxxStart();
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}
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void disable_pxx(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleStop();
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else
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extmoduleStop();
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}
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#if defined(DSM2)
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void init_dsm2(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleDsm2Start();
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}
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}
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void disable_dsm2(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleStop();
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}
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}
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#endif
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#if defined(MULTIMODULE)
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void init_multimodule(uint32_t port)
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{
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init_dsm2(port);
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}
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void disable_multimodule(uint32_t port)
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{
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disable_dsm2(port);
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}
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#endif
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void init_crossfire(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleCrossfireStart();
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}
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}
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void disable_crossfire(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleStop();
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}
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}
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void intmoduleStop()
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{
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INTERNAL_MODULE_OFF();
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NVIC_DisableIRQ(INTMODULE_TIMER_IRQn);
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INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE;
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
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}
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void intmoduleNoneStart()
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{
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INTERNAL_MODULE_OFF();
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = INTMODULE_TX_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(INTMODULE_TX_GPIO, &GPIO_InitStructure);
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GPIO_SetBits(INTMODULE_TX_GPIO, INTMODULE_TX_GPIO_PIN); // Set high
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
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INTMODULE_TIMER->ARR = 36000; // 18mS
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INTMODULE_TIMER->CCR2 = 32000; // Update time
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INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz)
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E;
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INTMODULE_TIMER->CCMR2 = 0;
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INTMODULE_TIMER->EGR = 1; // Restart
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INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
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INTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
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NVIC_EnableIRQ(INTMODULE_TIMER_IRQn);
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NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
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}
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void intmodulePxxStart()
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{
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NVIC_InitTypeDef NVIC_InitStructure;
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GPIO_InitTypeDef GPIO_InitStructure;
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INTERNAL_MODULE_ON();
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NVIC_InitStructure.NVIC_IRQChannel = INTMODULE_DMA_STREAM_IRQ;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pre-emption priority. */;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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// TX Pin
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GPIO_PinAFConfig(INTMODULE_TX_GPIO, INTMODULE_TX_GPIO_PinSource, INTMODULE_GPIO_AF);
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GPIO_InitStructure.GPIO_Pin = INTMODULE_TX_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_Init(INTMODULE_TX_GPIO, &GPIO_InitStructure);
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// RX Pin
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GPIO_PinAFConfig(INTMODULE_RX_GPIO, INTMODULE_RX_GPIO_PinSource, INTMODULE_GPIO_AF);
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GPIO_InitStructure.GPIO_Pin = INTMODULE_RX_GPIO_PIN;
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GPIO_Init(INTMODULE_RX_GPIO, &GPIO_InitStructure);
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// UART config
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USART_DeInit(INTMODULE_USART);
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USART_InitTypeDef USART_InitStructure;
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USART_InitStructure.USART_BaudRate = 115200;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(INTMODULE_USART, &USART_InitStructure);
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USART_Cmd(INTMODULE_USART, ENABLE);
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// Timer
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
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INTMODULE_TIMER->ARR = 18000; // 9mS
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INTMODULE_TIMER->CCR2 = 15000; // Update time
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INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz)
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E;
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INTMODULE_TIMER->CCMR2 = 0;
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INTMODULE_TIMER->EGR = 1; // Restart
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INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
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INTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
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NVIC_EnableIRQ(INTMODULE_TIMER_IRQn);
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NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
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}
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extern "C" void INTMODULE_DMA_STREAM_IRQHandler(void)
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{
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DEBUG_INTERRUPT(INT_DMA2S7);
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if (DMA_GetITStatus(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC)) {
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// TODO we could send the 8 next channels here (when needed)
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DMA_ClearITPendingBit(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC);
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}
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}
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void intmoduleSendNextFrame()
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{
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if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
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DMA_InitTypeDef DMA_InitStructure;
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DMA_DeInit(INTMODULE_DMA_STREAM);
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DMA_InitStructure.DMA_Channel = INTMODULE_DMA_CHANNEL;
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DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&INTMODULE_USART->DR);
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DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
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DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(modulePulsesData[INTERNAL_MODULE].pxx_uart.pulses);
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DMA_InitStructure.DMA_BufferSize = modulePulsesData[INTERNAL_MODULE].pxx_uart.ptr - modulePulsesData[INTERNAL_MODULE].pxx_uart.pulses;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
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DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
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DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
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DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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DMA_Init(INTMODULE_DMA_STREAM, &DMA_InitStructure);
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DMA_Cmd(INTMODULE_DMA_STREAM, ENABLE);
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USART_DMACmd(INTMODULE_USART, USART_DMAReq_Tx, ENABLE);
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}
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}
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extern "C" void INTMODULE_TIMER_IRQHandler()
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{
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DEBUG_INTERRUPT(INT_TIM1CC);
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DEBUG_TIMER_SAMPLE(debugTimerIntPulses);
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DEBUG_TIMER_START(debugTimerIntPulsesDuration);
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag
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setupPulses(INTERNAL_MODULE);
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intmoduleSendNextFrame();
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DEBUG_TIMER_STOP(debugTimerIntPulsesDuration);
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}
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/*
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* Copyright (C) OpenTX
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*
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* Based on code named
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* th9x - http://code.google.com/p/th9x
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* er9x - http://code.google.com/p/er9x
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* gruvin9x - http://code.google.com/p/gruvin9x
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*
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* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#include "opentx.h"
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void intmoduleStop(void);
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void extmoduleStop(void);
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void intmoduleNoneStart(void);
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void intmodulePxxStart(void);
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void extmoduleNoneStart(void);
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void extmodulePpmStart(void);
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void extmodulePxxStart(void);
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#if defined(DSM2)
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void extmoduleDsm2Start(void);
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#endif
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void extmoduleCrossfireStart(void);
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void init_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleNoneStart();
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else
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extmoduleNoneStart();
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}
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void disable_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleStop();
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else
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extmoduleStop();
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}
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void init_ppm(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmodulePpmStart();
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}
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}
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void disable_ppm(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleStop();
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}
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}
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void init_pxx(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmodulePxxStart();
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else
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extmodulePxxStart();
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}
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void disable_pxx(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleStop();
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else
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extmoduleStop();
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}
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#if defined(DSM2)
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void init_dsm2(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleDsm2Start();
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}
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}
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void disable_dsm2(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleStop();
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}
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}
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#endif
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#if defined(MULTIMODULE)
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void init_multimodule(uint32_t port)
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{
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init_dsm2(port);
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}
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void disable_multimodule(uint32_t port)
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{
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disable_dsm2(port);
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}
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#endif
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void init_crossfire(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleCrossfireStart();
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}
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}
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void disable_crossfire(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleStop();
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}
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}
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void intmoduleStop()
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{
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INTERNAL_MODULE_OFF();
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NVIC_DisableIRQ(INTMODULE_TIMER_IRQn);
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INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE;
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
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}
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void intmoduleNoneStart()
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{
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INTERNAL_MODULE_OFF();
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = INTMODULE_TX_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
|
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(INTMODULE_TX_GPIO, &GPIO_InitStructure);
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GPIO_SetBits(INTMODULE_TX_GPIO, INTMODULE_TX_GPIO_PIN); // Set high
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
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INTMODULE_TIMER->ARR = 36000; // 18mS
|
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INTMODULE_TIMER->CCR2 = 32000; // Update time
|
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INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz)
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E;
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INTMODULE_TIMER->CCMR2 = 0;
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INTMODULE_TIMER->EGR = 1; // Restart
|
||||
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INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p
|
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
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INTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
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NVIC_EnableIRQ(INTMODULE_TIMER_IRQn);
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NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
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}
|
||||
|
||||
void intmodulePxxStart()
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||||
{
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||||
NVIC_InitTypeDef NVIC_InitStructure;
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||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
INTERNAL_MODULE_ON();
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||||
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||||
NVIC_InitStructure.NVIC_IRQChannel = INTMODULE_DMA_STREAM_IRQ;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; /* Not used as 4 bits are used for the pre-emption priority. */;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
|
||||
// TX Pin
|
||||
GPIO_PinAFConfig(INTMODULE_TX_GPIO, INTMODULE_TX_GPIO_PinSource, INTMODULE_GPIO_AF);
|
||||
GPIO_InitStructure.GPIO_Pin = INTMODULE_TX_GPIO_PIN;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
||||
GPIO_Init(INTMODULE_TX_GPIO, &GPIO_InitStructure);
|
||||
|
||||
// RX Pin
|
||||
GPIO_PinAFConfig(INTMODULE_RX_GPIO, INTMODULE_RX_GPIO_PinSource, INTMODULE_GPIO_AF);
|
||||
GPIO_InitStructure.GPIO_Pin = INTMODULE_RX_GPIO_PIN;
|
||||
GPIO_Init(INTMODULE_RX_GPIO, &GPIO_InitStructure);
|
||||
|
||||
// UART config
|
||||
USART_DeInit(INTMODULE_USART);
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(INTMODULE_USART, &USART_InitStructure);
|
||||
USART_Cmd(INTMODULE_USART, ENABLE);
|
||||
|
||||
// Timer
|
||||
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
|
||||
INTMODULE_TIMER->ARR = 18000; // 9mS
|
||||
INTMODULE_TIMER->CCR2 = 15000; // Update time
|
||||
INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz)
|
||||
INTMODULE_TIMER->CCER = TIM_CCER_CC3E;
|
||||
INTMODULE_TIMER->CCMR2 = 0;
|
||||
INTMODULE_TIMER->EGR = 1; // Restart
|
||||
|
||||
INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p
|
||||
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
|
||||
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
|
||||
INTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
|
||||
|
||||
NVIC_EnableIRQ(INTMODULE_TIMER_IRQn);
|
||||
NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
|
||||
}
|
||||
|
||||
extern "C" void INTMODULE_DMA_STREAM_IRQHandler(void)
|
||||
{
|
||||
DEBUG_INTERRUPT(INT_DMA2S7);
|
||||
if (DMA_GetITStatus(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC)) {
|
||||
// TODO we could send the 8 next channels here (when needed)
|
||||
DMA_ClearITPendingBit(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC);
|
||||
}
|
||||
}
|
||||
|
||||
void intmoduleSendNextFrame()
|
||||
{
|
||||
if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
|
||||
DMA_InitTypeDef DMA_InitStructure;
|
||||
DMA_DeInit(INTMODULE_DMA_STREAM);
|
||||
DMA_InitStructure.DMA_Channel = INTMODULE_DMA_CHANNEL;
|
||||
DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&INTMODULE_USART->DR);
|
||||
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
|
||||
DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(modulePulsesData[INTERNAL_MODULE].pxx_uart.pulses);
|
||||
DMA_InitStructure.DMA_BufferSize = modulePulsesData[INTERNAL_MODULE].pxx_uart.ptr - modulePulsesData[INTERNAL_MODULE].pxx_uart.pulses;
|
||||
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
|
||||
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
|
||||
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
|
||||
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
|
||||
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
|
||||
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
|
||||
DMA_Init(INTMODULE_DMA_STREAM, &DMA_InitStructure);
|
||||
|
||||
DMA_Cmd(INTMODULE_DMA_STREAM, ENABLE);
|
||||
USART_DMACmd(INTMODULE_USART, USART_DMAReq_Tx, ENABLE);
|
||||
}
|
||||
}
|
||||
|
||||
extern "C" void INTMODULE_TIMER_IRQHandler()
|
||||
{
|
||||
DEBUG_INTERRUPT(INT_TIM1CC);
|
||||
DEBUG_TIMER_SAMPLE(debugTimerIntPulses);
|
||||
DEBUG_TIMER_START(debugTimerIntPulsesDuration);
|
||||
|
||||
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag
|
||||
setupPulses(INTERNAL_MODULE);
|
||||
intmoduleSendNextFrame();
|
||||
|
||||
DEBUG_TIMER_STOP(debugTimerIntPulsesDuration);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user