fa12b27438
Co-authored-by: raphaelcoeffic <1050031+raphaelcoeffic@users.noreply.github.com> Co-authored-by: Peter Feerick <peter.feerick@gmail.com>
337 lines
8.8 KiB
C++
337 lines
8.8 KiB
C++
/*
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* Copyright (C) EdgeTX
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*
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* Based on code named
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* opentx - https://github.com/opentx/opentx
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* th9x - http://code.google.com/p/th9x
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* er9x - http://code.google.com/p/er9x
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* gruvin9x - http://code.google.com/p/gruvin9x
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*
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* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "module_port.h"
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#include "dataconstants.h" // MAX_MODULES
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#include "myeeprom.h" // g_eeGeneral
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#include <string.h>
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extern const etx_module_t* const _modules[];
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extern const uint8_t _n_modules;
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static etx_module_state_t _module_states[MAX_MODULES];
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static uint8_t _module_power;
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#if defined(CONFIGURABLE_MODULE_PORT)
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// supplemental configurable port
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static etx_module_port_t _extra_module_port;
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void modulePortConfigExtra(const etx_module_port_t* port)
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{
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memcpy(&_extra_module_port, port, sizeof(_extra_module_port));
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}
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#endif
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void modulePortInit()
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{
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memset(_module_states, 0, sizeof(_module_states));
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_module_power = 0;
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#if defined(CONFIGURABLE_MODULE_PORT)
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memset(&_extra_module_port, 0, sizeof(_extra_module_port));
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_extra_module_port.type = 0xFF; // some invalid type
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#endif
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}
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static void modulePortClear(etx_module_state_t* st)
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{
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memset(st, 0, sizeof(etx_module_state_t));
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}
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static bool _init_serial_driver(etx_module_driver_t* d, const etx_module_port_t* port,
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const etx_serial_init* params)
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{
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auto drv = port->drv.serial;
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auto ctx = drv->init(port->hw_def, params);
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if (!ctx) return false;
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d->ctx = ctx;
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d->port = port;
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// S.PORT specific HW settings
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if (port->port == ETX_MOD_PORT_SPORT && params->baudrate >= 400000) {
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// enable over-sampling by 8
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if (drv->setHWOption) drv->setHWOption(d->ctx, ETX_HWOption_OVER8);
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// one-bit
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if (g_eeGeneral.uartSampleMode == UART_SAMPLE_MODE_ONEBIT) {
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if (drv->setHWOption) drv->setHWOption(d->ctx, ETX_HWOption_ONEBIT);
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}
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}
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// setup polarity
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if (port->set_inverted) {
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port->set_inverted(params->polarity == ETX_Pol_Inverted);
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}
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return true;
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}
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static bool _init_timer_driver(etx_module_driver_t* d, const etx_module_port_t* port,
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const etx_timer_config_t* cfg)
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{
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auto drv = port->drv.timer;
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auto ctx = drv->init(port->hw_def, cfg);
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if (!ctx) return false;
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d->ctx = ctx;
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d->port = port;
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// setup polarity
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if (port->set_inverted) {
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port->set_inverted(false);
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}
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return true;
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}
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static bool _match_port(const etx_module_port_t* p, uint8_t type, uint8_t port,
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uint8_t polarity, uint8_t direction, bool softserial_fallback)
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{
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if ((p->dir_flags & direction) != direction) {
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return false;
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}
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if (p->type == type && p->port == port) {
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// either polarity matches or can be set
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if (polarity != ETX_Pol_Inverted ||
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p->set_inverted ||
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port == ETX_MOD_PORT_SOFT_INV ||
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port == ETX_MOD_PORT_SPORT_INV) {
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return true;
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}
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}
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// soft-serial fallback (1. USART -> 2. SOFT-SERIAL)
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if (softserial_fallback && polarity == ETX_Pol_Inverted) {
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if (port == ETX_MOD_PORT_UART && p->port == ETX_MOD_PORT_SOFT_INV) {
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return true;
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}
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if (port == ETX_MOD_PORT_SPORT && p->port == ETX_MOD_PORT_SPORT_INV) {
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return true;
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}
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}
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return false;
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}
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static const etx_module_port_t* _find_port(uint8_t module, uint8_t type,
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uint8_t port, uint8_t polarity,
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uint8_t direction,
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bool softserial_fallback)
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{
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if (module >= MAX_MODULES || module >= _n_modules || !_modules[module])
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return nullptr;
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uint8_t n_ports = _modules[module]->n_ports;
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const etx_module_port_t* p = _modules[module]->ports;
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const etx_module_port_t* found_port = nullptr;
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while(n_ports > 0) {
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if (_match_port(p, type, port, polarity, direction, softserial_fallback)) {
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found_port = p;
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break;
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}
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++p; --n_ports;
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}
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#if defined(CONFIGURABLE_MODULE_PORT)
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if (!found_port &&
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polarity == ETX_Pol_Normal &&
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module == EXTERNAL_MODULE &&
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_extra_module_port.type == type &&
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_extra_module_port.port == port) {
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found_port = &_extra_module_port;
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}
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#endif
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return found_port;
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}
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const etx_module_t* modulePortGetModuleDescription(uint8_t module)
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{
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if (module >= _n_modules) return nullptr;
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return _modules[module];
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}
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const etx_module_port_t* modulePortFind(uint8_t module, uint8_t type,
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uint8_t port, uint8_t polarity,
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uint8_t direction)
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{
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return _find_port(module, type, port, polarity, direction, false);
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}
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void modulePortSetPower(uint8_t module, uint8_t enable)
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{
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if (module >= _n_modules) return;
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auto mod = _modules[module];
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if (mod && mod->set_pwr) {
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mod->set_pwr(enable);
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if (enable) {
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_module_power |= (1 << module);
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} else {
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_module_power &= ~(1 << module);
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}
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}
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}
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bool modulePortPowered(uint8_t module)
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{
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if (module >= _n_modules) return false;
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return _module_power & (1 << module);
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}
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etx_module_state_t* modulePortInitSerial(uint8_t module, uint8_t port,
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const etx_serial_init* params,
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bool softserial_fallback)
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{
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const etx_module_port_t* found_port = _find_port(module, ETX_MOD_TYPE_SERIAL,
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port, params->polarity,
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params->direction,
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softserial_fallback);
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if (!found_port) return nullptr;
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auto state = &(_module_states[module]);
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const uint8_t duplex = ETX_Dir_TX_RX;
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uint8_t dir = params->direction & duplex;
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bool init_ok = false;
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if (dir == duplex) {
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// init RX first, in case TX was already done previously
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init_ok = _init_serial_driver(&state->rx, found_port, params);
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// do not overwrite TX state if it has already been set:
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// -> support using S.PORT in bidir mode
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if (!state->tx.port) {
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state->tx.port = state->rx.port;
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state->tx.ctx = state->rx.ctx;
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}
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} else if (dir == ETX_Dir_TX) {
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init_ok = _init_serial_driver(&state->tx, found_port, params);
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} else if (dir == ETX_Dir_RX) {
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init_ok = _init_serial_driver(&state->rx, found_port, params);
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}
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return init_ok ? state : nullptr;
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}
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etx_module_state_t* modulePortInitTimer(uint8_t module, uint8_t port,
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const etx_timer_config_t* cfg)
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{
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const etx_module_port_t* found_port = _find_port(
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module, ETX_MOD_TYPE_TIMER, port, ETX_Pol_Normal, ETX_MOD_DIR_TX, false);
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if (!found_port) return nullptr;
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auto state = &(_module_states[module]);
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bool init_ok = _init_timer_driver(&state->tx, found_port, cfg);
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return init_ok ? state : nullptr;
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}
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static void _deinit_driver(etx_module_driver_t* d)
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{
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auto p = d->port;
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auto ctx = d->ctx;
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if (p->type == ETX_MOD_TYPE_SERIAL) {
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auto drv = p->drv.serial;
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drv->deinit(ctx);
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} else if (p->type == ETX_MOD_TYPE_TIMER) {
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auto drv = p->drv.timer;
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drv->deinit(ctx);
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}
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}
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void modulePortDeInit(etx_module_state_t* st)
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{
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if (st->tx.port != nullptr) {
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_deinit_driver(&st->tx);
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}
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if (st->rx.port != nullptr && st->rx.port != st->tx.port) {
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_deinit_driver(&st->rx);
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}
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modulePortClear(st);
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}
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void modulePortDeInitRxPort(etx_module_state_t* st)
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{
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if (st->rx.port) {
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_deinit_driver(&st->rx);
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memset(&st->rx, 0, sizeof(etx_module_driver_t));
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}
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}
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etx_module_state_t* modulePortGetState(uint8_t module)
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{
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if (module >= MAX_MODULES) return nullptr;
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return &(_module_states[module]);
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}
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uint8_t modulePortGetModule(etx_module_state_t* st)
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{
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return st - _module_states;
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}
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bool modulePortIsPortUsedByModule(uint8_t module, uint8_t port)
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{
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auto mod_st = modulePortGetState(module);
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if (!mod_st) return false;
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auto tx_port = mod_st->tx.port;
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auto rx_port = mod_st->rx.port;
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return (tx_port && tx_port->port == port) ||
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(rx_port && rx_port->port == port);
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}
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bool modulePortIsPortUsed(uint8_t port)
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{
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return modulePortGetModuleForPort(port) >= 0;
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}
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int8_t modulePortGetModuleForPort(uint8_t port)
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{
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for (uint8_t module = 0; module < MAX_MODULES; module++) {
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if (modulePortIsPortUsedByModule(module, port)) {
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return module;
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}
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}
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return -1;
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}
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bool modulePortHasRx(uint8_t module)
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{
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auto mod_st = modulePortGetState(module);
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if (!mod_st) return false;
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return mod_st && mod_st->rx.port;
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}
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