bsongis
4a1ae0eaa4
Issue 204 fixed (Tx Batt spoken) [X9D] It was impossible to avoid a Format on EEPROM Alert [all] Function v1==x modified to v1~=x (needs to be tested) Developers list updated
136 lines
4.4 KiB
C++
136 lines
4.4 KiB
C++
/*
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* Authors (alphabetical order)
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* - Andre Bernet <bernet.andre@gmail.com>
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* - Andreas Weitl
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* - Bertrand Songis <bsongis@gmail.com>
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* - Bryan J. Rentoul (Gruvin) <gruvin@gmail.com>
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* - Cameron Weeks <th9xer@gmail.com>
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* - Erez Raviv
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* - Gabriel Birkus
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* - Jean-Pierre Parisy
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* - Karl Szmutny
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* - Michael Blandford
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* - Michal Hlavinka
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* - Pat Mackenzie
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* - Philip Moss
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* - Rob Thomson
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* - Romolo Manfredini <romolo.manfredini@gmail.com>
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* - Thomas Husterer
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*
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* open9x is based on code named
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* gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/,
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* er9x by Erez Raviv: http://code.google.com/p/er9x/,
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* and the original (and ongoing) project by
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* Thomas Husterer, th9x: http://code.google.com/p/th9x/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "../open9x.h"
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void init_main_ppm( uint32_t period, uint32_t out_enable )
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{
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register Pio *pioptr ;
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register Pwm *pwmptr ;
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setupPulsesPPM(0) ;
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if ( out_enable )
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{
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pioptr = PIOA ;
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pioptr->PIO_ABCDSR[0] &= ~PIO_PA17 ; // Peripheral C
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pioptr->PIO_ABCDSR[1] |= PIO_PA17 ; // Peripheral C
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pioptr->PIO_PDR = PIO_PA17 ; // Disable bit A17 Assign to peripheral
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}
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pwmptr = PWM ;
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// PWM3 for PPM output
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pwmptr->PWM_CH_NUM[3].PWM_CMR = 0x0000000B ; // CLKA
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if (g_model.pulsePol)
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pwmptr->PWM_CH_NUM[3].PWM_CMR |= 0x00000200 ; // CPOL
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pwmptr->PWM_CH_NUM[3].PWM_CPDR = period ; // Period in half uS
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pwmptr->PWM_CH_NUM[3].PWM_CPDRUPD = period ; // Period in half uS
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pwmptr->PWM_CH_NUM[3].PWM_CDTY = g_model.ppmDelay*100+600; // Duty in half uS
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pwmptr->PWM_CH_NUM[3].PWM_CDTYUPD = g_model.ppmDelay*100+600; // Duty in half uS
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pwmptr->PWM_ENA = PWM_ENA_CHID3 ; // Enable channel 3
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pwmptr->PWM_IER1 = PWM_IER1_CHID3 ;
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#if !defined(REVA)
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configure_pins( PIO_PC15, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_B | PIN_PORTC | PIN_NO_PULLUP ) ;
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#endif
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#if !defined(REVA)
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// PWM1 for PPM2
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pwmptr->PWM_CH_NUM[1].PWM_CMR = 0x0000000B ; // CLKB
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if (g_model.pulsePol)
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pwmptr->PWM_CH_NUM[1].PWM_CMR |= 0x00000200 ; // CPOL
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pwmptr->PWM_CH_NUM[1].PWM_CPDR = period ; // Period
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pwmptr->PWM_CH_NUM[1].PWM_CPDRUPD = period ; // Period
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pwmptr->PWM_CH_NUM[1].PWM_CDTY = g_model.ppmDelay*100+600 ; // Duty
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pwmptr->PWM_CH_NUM[1].PWM_CDTYUPD = g_model.ppmDelay*100+600 ; // Duty
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pwmptr->PWM_ENA = PWM_ENA_CHID1 ; // Enable channel 1
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#endif
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pwmptr->PWM_IER1 = PWM_IER1_CHID1 ;
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NVIC_EnableIRQ(PWM_IRQn) ;
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}
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void disable_main_ppm()
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{
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register Pio *pioptr ;
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pioptr = PIOA ;
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pioptr->PIO_PER = PIO_PA17 ; // Assign A17 to PIO
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PWM->PWM_IDR1 = PWM_IDR1_CHID3 ;
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}
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void disable_ppm2()
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{
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register Pio *pioptr ;
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pioptr = PIOC ;
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pioptr->PIO_PER = PIO_PC17 ; // Assign A17 to PIO
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PWM->PWM_IDR1 = PWM_IDR1_CHID1 ;
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NVIC_DisableIRQ(PWM_IRQn) ;
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}
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// Initialise the SSC to allow PXX output.
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// TD is on PA17, peripheral A
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void init_ssc()
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{
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register Ssc *sscptr ;
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PMC->PMC_PCER0 |= 0x00400000L ; // Enable peripheral clock to SSC
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configure_pins( PIO_PA17, PIN_PERIPHERAL | PIN_INPUT | PIN_PER_A | PIN_PORTA | PIN_NO_PULLUP ) ;
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sscptr = SSC ;
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sscptr->SSC_CMR = Master_frequency / (125000*2) ; // 8uS per bit
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sscptr->SSC_TCMR = 0 ; // 0000 0000 0000 0000 0000 0000 0000 0000
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sscptr->SSC_TFMR = 0x00000027 ; // 0000 0000 0000 0000 0000 0000 1010 0111 (8 bit data, lsb)
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sscptr->SSC_CR = SSC_CR_TXEN ;
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}
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void disable_ssc()
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{
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register Pio *pioptr ;
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register Ssc *sscptr ;
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// Revert back to pwm output
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pioptr = PIOA ;
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pioptr->PIO_PER = PIO_PA17 ; // Assign A17 to PIO
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sscptr = SSC ;
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sscptr->SSC_CR = SSC_CR_TXDIS ;
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}
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