622 lines
24 KiB
C++
622 lines
24 KiB
C++
/*
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* Copyright (C) OpenTX
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*
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* Based on code named
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* th9x - http://code.google.com/p/th9x
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* er9x - http://code.google.com/p/er9x
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* gruvin9x - http://code.google.com/p/gruvin9x
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*
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* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "../../opentx.h"
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void setupPulses(unsigned int port);
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void setupPulsesPPM(unsigned int port);
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void setupPulsesPXX(unsigned int port);
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static void intmodulePxxStart( void ) ;
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static void intmodulePxxStop( void ) ;
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#if defined(TARANIS_INTERNAL_PPM)
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static void intmodulePpmStart( void ) ;
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static void intmodulePpmStop( void ) ;
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#endif
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static void extmodulePxxStart( void ) ;
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static void extmodulePxxStop( void ) ;
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#if defined(DSM2)
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static void extmoduleDsm2Start( void ) ;
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static void extmoduleDsm2Stop( void ) ;
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#endif
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static void extmodulePpmStart( void ) ;
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static void extmodulePpmStop( void ) ;
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static void intmoduleNoneStart( void ) ;
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static void intmoduleNoneStop( void ) ;
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static void extmoduleNoneStart( void ) ;
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static void extmoduleNoneStop( void ) ;
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static void extmoduleCrossfireStart( void ) ;
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static void extmoduleCrossfireStop( void ) ;
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void init_pxx(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmodulePxxStart() ;
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else
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extmodulePxxStart() ;
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}
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void disable_pxx(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmodulePxxStop() ;
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else
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extmodulePxxStop() ;
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}
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#if defined(DSM2)
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void init_dsm2(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleDsm2Start();
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}
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}
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void disable_dsm2(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleDsm2Stop();
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}
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}
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#endif
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void init_ppm(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmodulePpmStart();
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}
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#if defined(TARANIS_INTERNAL_PPM)
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else if (port == INTERNAL_MODULE) {
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intmodulePpmStart();
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}
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#endif
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}
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void disable_ppm(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmodulePpmStop();
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}
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#if defined(TARANIS_INTERNAL_PPM)
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else if (port == INTERNAL_MODULE) {
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intmodulePpmStop();
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}
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#endif
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}
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void set_external_ppm_parameters(uint32_t idleTime, uint32_t delay, uint32_t positive)
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{
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EXTMODULE_TIMER->CCR2 = idleTime;
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EXTMODULE_TIMER->CCR1 = delay;
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// we are using complementary output so logic has to be reversed here
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EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | (positive ? 0 : TIM_CCER_CC1NP);
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}
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#if defined(TARANIS_INTERNAL_PPM)
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void set_internal_ppm_parameters(uint32_t idleTime, uint32_t delay, uint32_t positive)
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{
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INTMODULE_TIMER->CCR2 = idleTime;
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INTMODULE_TIMER->CCR3 = delay;
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E | (positive ? TIM_CCER_CC3P : 0);
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}
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#endif
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void init_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleNoneStart();
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else
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extmoduleNoneStart();
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}
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void disable_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleNoneStop();
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else
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extmoduleNoneStop();
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}
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void init_crossfire(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleCrossfireStart();
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}
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}
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void disable_crossfire(uint32_t port)
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{
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if (port == EXTERNAL_MODULE)
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extmoduleCrossfireStop();
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}
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static void intmoduleNoneStart()
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{
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INTERNAL_MODULE_OFF();
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// Timer1, channel 3
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = INTMODULE_PPM_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT ;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(INTMODULE_PPM_GPIO, &GPIO_InitStructure);
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GPIO_SetBits(INTMODULE_PPM_GPIO, INTMODULE_PPM_GPIO_PIN) ; // Set high
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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INTMODULE_TIMER->ARR = 36000 ; // 18mS
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INTMODULE_TIMER->CCR2 = 32000 ; // Update time
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INTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E ;
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INTMODULE_TIMER->CCMR2 = 0 ;
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INTMODULE_TIMER->EGR = 1 ; // Restart
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INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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INTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
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NVIC_EnableIRQ(INTMODULE_TIMER_IRQn) ;
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NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
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}
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static void intmoduleNoneStop()
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{
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NVIC_DisableIRQ(INTMODULE_TIMER_IRQn) ;
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INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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}
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static void extmoduleNoneStart()
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{
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if (!IS_TRAINER_EXTERNAL_MODULE()) {
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EXTERNAL_MODULE_OFF();
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}
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT ;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
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GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high
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EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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EXTMODULE_TIMER->ARR = 36000 ; // 18mS
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EXTMODULE_TIMER->CCR2 = 32000 ; // Update time
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EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
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EXTMODULE_TIMER->CCMR2 = 0 ;
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EXTMODULE_TIMER->EGR = 1 ; // Restart
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EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
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EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
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EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
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NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
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NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
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}
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static void extmoduleNoneStop()
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{
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NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
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EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
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EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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}
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static void extmoduleCrossfireStart()
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{
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EXTERNAL_MODULE_ON();
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT ;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
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GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high
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EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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EXTMODULE_TIMER->ARR = 5000 ; // 2.5mS
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EXTMODULE_TIMER->CCR2 = 32000 ; // Update time
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EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
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EXTMODULE_TIMER->CCMR2 = 0 ;
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EXTMODULE_TIMER->EGR = 1 ; // Restart
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EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
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EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
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EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
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NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
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NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
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}
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static void extmoduleCrossfireStop()
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{
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NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
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EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
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EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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if (!IS_TRAINER_EXTERNAL_MODULE()) {
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EXTERNAL_MODULE_OFF();
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}
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}
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static void intmodulePxxStart()
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{
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INTERNAL_MODULE_ON();
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// Timer1, channel 3
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setupPulsesPXX(INTERNAL_MODULE) ; // TODO not here!
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_PinAFConfig(INTMODULE_PPM_GPIO, INTMODULE_PPM_GPIO_PinSource, INTMODULE_PPM_GPIO_AF);
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GPIO_InitStructure.GPIO_Pin = INTMODULE_PPM_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(INTMODULE_PPM_GPIO, &GPIO_InitStructure);
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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INTMODULE_TIMER->ARR = 18000 ; // 9mS
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INTMODULE_TIMER->CCR2 = 15000 ; // Update time
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INTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E ;
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INTMODULE_TIMER->CR2 = TIM_CR2_OIS3 ; // O/P idle high
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INTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs
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INTMODULE_TIMER->CCR3 = modulePulsesData[INTERNAL_MODULE].pxx.pulses[0];
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INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0 ; // Force O/P high
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INTMODULE_TIMER->EGR = 1 ; // Restart
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INTMODULE_TIMER->DIER |= TIM_DIER_CC3DE ; // Enable DMA on CC3 match
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INTMODULE_TIMER->DCR = 15 ; // DMA to CC1
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// Enable the DMA channel here, DMA2 stream 6, channel 6
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DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
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DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
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DMA2_Stream6->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
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| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
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DMA2_Stream6->PAR = CONVERT_PTR_UINT(&INTMODULE_TIMER->DMAR);
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DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&modulePulsesData[INTERNAL_MODULE].pxx.pulses[1]);
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DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA
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INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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INTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
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NVIC_EnableIRQ(INTMODULE_TIMER_IRQn);
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NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
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}
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static void intmodulePxxStop()
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{
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DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
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NVIC_DisableIRQ(INTMODULE_TIMER_IRQn) ;
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INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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INTERNAL_MODULE_OFF();
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}
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#if defined(TARANIS_INTERNAL_PPM)
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// PPM output
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// Timer 1, channel 1 on PA8 for prototype
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// Pin is AF1 function for timer 1
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static void intmodulePpmStart()
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{
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INTERNAL_MODULE_ON();
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// Timer1
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configure_pins(INTMODULE_PPM_GPIO_PIN, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25);
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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// setupPulsesPPM() is also configuring registers,
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// so it has to be called after the peripheral is enabled
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setupPulsesPPM(INTERNAL_MODULE) ;
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INTMODULE_TIMER->ARR = *modulePulsesData[INTERNAL_MODULE].ppm.ptr++ ;
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INTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E ;
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INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 ; // PWM mode 1
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INTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC2PE ; // PWM mode 1
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INTMODULE_TIMER->BDTR = TIM_BDTR_MOE ;
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INTMODULE_TIMER->EGR = 1 ;
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INTMODULE_TIMER->DIER = TIM_DIER_UDE ;
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INTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear flag
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ;
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INTMODULE_TIMER->DIER |= TIM_DIER_UIE ;
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INTMODULE_TIMER->CR1 = TIM_CR1_CEN ;
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NVIC_EnableIRQ(INTMODULE_TIMER_IRQn) ;
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NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
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NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn) ;
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NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 7);
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}
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static void intmodulePpmStop()
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{
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NVIC_DisableIRQ(INTMODULE_TIMER_IRQn) ;
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NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn) ;
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INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE & ~TIM_DIER_UIE ;
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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INTERNAL_MODULE_OFF();
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}
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#endif // #if defined(TARANIS_INTERNAL_PPM)
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#if !defined(SIMU)
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extern "C" void TIM1_CC_IRQHandler()
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{
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INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // stop this interrupt
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag
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DMA2_Stream6->CR &= ~DMA_SxCR_EN; // disable DMA, it will have the whole of the execution time of setupPulses() to actually stop
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setupPulses(INTERNAL_MODULE);
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if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
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DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6;
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DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&modulePulsesData[INTERNAL_MODULE].pxx.pulses[1]);
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DMA2_Stream6->CR |= DMA_SxCR_EN; // enable DMA
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INTMODULE_TIMER->CCR3 = modulePulsesData[INTERNAL_MODULE].pxx.pulses[0];
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // enable this interrupt
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}
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#if defined(TARANIS_INTERNAL_PPM)
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else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) {
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INTMODULE_TIMER->DIER |= TIM_DIER_UDE;
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INTMODULE_TIMER->SR &= ~TIM_SR_UIF;
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INTMODULE_TIMER->DIER |= TIM_DIER_UIE;
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}
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#endif
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else {
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE;
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}
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}
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extern "C" void TIM1_UP_TIM10_IRQHandler()
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{
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INTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear flag
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INTMODULE_TIMER->ARR = *modulePulsesData[INTERNAL_MODULE].ppm.ptr++ ;
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if (*modulePulsesData[INTERNAL_MODULE].ppm.ptr == 0) {
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear this flag
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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}
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}
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#endif
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void extmodulePxxStart()
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{
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EXTERNAL_MODULE_ON();
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setupPulsesPXX(EXTERNAL_MODULE);
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF);
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GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
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EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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|
EXTMODULE_TIMER->ARR = 18000 ; // 9mS
|
|
EXTMODULE_TIMER->CCR2 = 15000 ; // Update time
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EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
|
|
EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE ;
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EXTMODULE_TIMER->CR2 = TIM_CR2_OIS1 ; // O/P idle high
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|
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs
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EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0];
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EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
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EXTMODULE_TIMER->EGR = 1 ; // Restart
|
|
|
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EXTMODULE_TIMER->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
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|
EXTMODULE_TIMER->DCR = 13 ; // DMA to CC1
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|
|
|
// Enable the DMA channel here, DMA2 stream 2, channel 7
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|
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
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|
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
|
|
DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
|
|
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
|
|
DMA2_Stream2->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->DMAR);
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|
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]);
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DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
|
|
|
|
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
|
|
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
|
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
|
|
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
|
|
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
|
|
}
|
|
|
|
static void extmodulePxxStop()
|
|
{
|
|
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
|
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
|
|
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
|
|
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
|
|
if (!IS_TRAINER_EXTERNAL_MODULE()) {
|
|
EXTERNAL_MODULE_OFF();
|
|
}
|
|
}
|
|
|
|
#if defined(DSM2)
|
|
static void extmoduleDsm2Start()
|
|
{
|
|
EXTERNAL_MODULE_ON();
|
|
|
|
setupPulsesDSM2(EXTERNAL_MODULE);
|
|
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
|
GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF);
|
|
GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN;
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
|
GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
|
|
|
|
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
|
|
EXTMODULE_TIMER->ARR = 44000 ; // 22mS
|
|
EXTMODULE_TIMER->CCR2 = 40000 ; // Update time
|
|
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
|
|
EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ;
|
|
EXTMODULE_TIMER->CR2 = TIM_CR2_OIS1 ; // O/P idle high
|
|
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs
|
|
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[0];
|
|
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
|
|
EXTMODULE_TIMER->EGR = 1 ; // Restart
|
|
|
|
EXTMODULE_TIMER->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
|
|
EXTMODULE_TIMER->DCR = 13 ; // DMA to CC1
|
|
|
|
// Enable the DMA channel here, DMA2 stream 2, channel 7
|
|
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
|
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
|
|
DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
|
|
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
|
|
DMA2_Stream2->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->DMAR);
|
|
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[1]);
|
|
// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
|
|
// DMA2_Stream2->NDTR = 100 ;
|
|
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
|
|
|
|
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
|
|
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
|
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
|
|
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
|
|
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
|
|
}
|
|
|
|
static void extmoduleDsm2Stop()
|
|
{
|
|
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
|
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
|
|
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
|
|
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
|
|
if (!IS_TRAINER_EXTERNAL_MODULE()) {
|
|
EXTERNAL_MODULE_OFF();
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static void extmodulePpmStart()
|
|
{
|
|
EXTERNAL_MODULE_ON();
|
|
|
|
configure_pins(EXTMODULE_PPM_GPIO_PIN, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_3 | PIN_OS25);
|
|
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
|
|
|
|
// setupPulsesPPM() is also configuring registers,
|
|
// so it has to be called after the peripheral is enabled
|
|
setupPulsesPPM(EXTERNAL_MODULE) ;
|
|
|
|
EXTMODULE_TIMER->ARR = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++ ;
|
|
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
|
|
|
|
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE ; // PWM mode 1
|
|
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE ;
|
|
EXTMODULE_TIMER->EGR = 1 ;
|
|
EXTMODULE_TIMER->DIER = TIM_DIER_UDE ;
|
|
|
|
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear flag
|
|
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
|
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ;
|
|
EXTMODULE_TIMER->DIER |= TIM_DIER_UIE ;
|
|
|
|
EXTMODULE_TIMER->CR1 = TIM_CR1_CEN ;
|
|
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
|
|
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
|
|
NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn) ;
|
|
NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 7);
|
|
}
|
|
|
|
static void extmodulePpmStop()
|
|
{
|
|
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
|
|
NVIC_DisableIRQ(TIM8_UP_TIM13_IRQn) ;
|
|
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE & ~TIM_DIER_UIE ;
|
|
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
|
|
if (!IS_TRAINER_EXTERNAL_MODULE()) {
|
|
EXTERNAL_MODULE_OFF();
|
|
}
|
|
}
|
|
|
|
#if !defined(SIMU)
|
|
extern "C" void TIM8_CC_IRQHandler()
|
|
{
|
|
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
|
|
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
|
|
|
setupPulses(EXTERNAL_MODULE) ;
|
|
|
|
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) {
|
|
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
|
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
|
|
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]);
|
|
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
|
|
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0];
|
|
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
}
|
|
#if defined(DSM2)
|
|
else if (s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) {
|
|
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
|
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
|
|
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[1]);
|
|
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
|
|
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[0];
|
|
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
}
|
|
#endif
|
|
else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
|
|
EXTMODULE_TIMER->DIER |= TIM_DIER_UDE ;
|
|
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear this flag
|
|
EXTMODULE_TIMER->DIER |= TIM_DIER_UIE ; // Enable this interrupt
|
|
}
|
|
else {
|
|
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
}
|
|
}
|
|
|
|
extern "C" void TIM8_UP_TIM13_IRQHandler()
|
|
{
|
|
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear flag
|
|
|
|
EXTMODULE_TIMER->ARR = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++ ;
|
|
if (*modulePulsesData[EXTERNAL_MODULE].ppm.ptr == 0) {
|
|
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear this flag
|
|
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
}
|
|
}
|
|
#endif
|