930 lines
28 KiB
C
930 lines
28 KiB
C
//#include <ioavr.h>
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#include <inttypes.h>
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#include <avr/io.h>
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#include <avr/pgmspace.h>
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#include <avr/boot.h>
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#include "stdint.h"
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//#include <inavr.h>
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#include "Common_Define.h"
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#include <util/delay.h>
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#include <avr/wdt.h>
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#include <avr/interrupt.h>
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#include <avr/sleep.h>
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#include "USI_TWI_Slave.h"
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#define sbi(port,bit) (port |= (1<<bit)) //set bit in port
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#define cbi(port,bit) (port &= ~(1<<bit)) //clear bit in port
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#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
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#define FORCE_INDIRECT(ptr) __asm__ __volatile__ ("" : "=e" (ptr) : "0" (ptr))
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#define NOINLINE __attribute__ ((noinline))
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// Version number, sent in first byte of response
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#define VERSION 0x03
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/*****************************************************************************/
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// USI_TWI write states.
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#define USI_TWI_WRITE_ADDR_HI_BYTE (0x00)
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#define USI_TWI_WRITE_ADDR_LO_BYTE (0x01)
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#define USI_TWI_WRITE_DATA_BYTE (0x02)
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// USI_TWI overflow states.
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#define USI_TWI_OVERFLOW_STATE_NONE (0x00)
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#define USI_TWI_OVERFLOW_STATE_ACK_PR_RX (0x01)
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#define USI_TWI_OVERFLOW_STATE_DATA_RX (0x02)
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#define USI_TWI_OVERFLOW_STATE_ACK_PR_TX (0x03)
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#define USI_TWI_OVERFLOW_STATE_PR_ACK_TX (0x04)
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#define USI_TWI_OVERFLOW_STATE_DATA_TX (0x05)
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#define DATA_SIZE 16 // Receive data buffer size
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#define TEMPERATURE 0b01001011
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// Signature row addresses
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#define TSOFFSET 5
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#define TSGAIN 7
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// Bits in AdcControl
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#define ADC_RUNNING 0x80
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#define ADC_COUNT_MASK 0x0F
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uint8_t AdcControl ;
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uint16_t AdcTotal ;
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int8_t T_offset ;
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uint8_t T_gain ;
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int16_t T_mult ;
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// USI_TWI state values.
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static uint8_t USI_TWI_SLAVE_Write_State;
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static uint8_t USI_TWI_SLAVE_Overflow_State;
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static uint8_t Command_Flag;
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// TWI flag values.
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// static uint8_t USI_TWI_SLAVE_Address_Update;
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// Slave Each page address values.
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//static uint16_t USI_TWI_SLAVE_PAGE_Address;
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uint8_t DataBuffer[DATA_SIZE];
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static uint8_t *bufferPtr ;
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static uint8_t Value;
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uint8_t Tx_buffer[22] ;
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int8_t Temperature;
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static uint8_t Tx_index ;
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typedef struct
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{
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unsigned char second; //enter the current time, date, month, and year
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unsigned char minute;
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unsigned char hour;
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unsigned char date;
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unsigned char month;
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unsigned int year;
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} t_time ;
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t_time Time ;
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uint8_t ActivityFlag ;
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void main (void) __attribute__((noreturn)) ;
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char not_leap(void) ; //check for leap year
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void updateTime(uint8_t amount) ;
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void set_clock( uint8_t speed ) ;
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void checkPowerSave( void ) ;
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static void Disable_WatchDogTimer(void) ;
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static void Init_WatchDogTimer(void) ;
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void enableAdc( void ) ;
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void disableAdc( void ) ;
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char not_leap(void) //check for leap year
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{
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t_time *p = &Time ;
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FORCE_INDIRECT(p) ;
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if (!(p->year%100))
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return (char)(p->year%400);
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else
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return (char)(p->year%4);
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}
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void updateTime(uint8_t amount)
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{
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t_time *p = &Time ;
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FORCE_INDIRECT(p) ;
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if (++p->second >= 60) //keep track of time, date, month, and year
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{
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p->second -= 60 ;
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if (++p->minute >= 60)
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{
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p->minute=0;
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if (++p->hour >= 24)
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{
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p->hour=0;
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if (++p->date >= 32)
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{
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p->month++;
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p->date=1;
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}
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else if (p->date == 31)
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{
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if ((p->month==4) || (p->month==6) || (p->month==9) || (p->month==11))
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{
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p->month++;
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p->date=1;
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}
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}
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else if (p->date==30)
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{
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if(p->month==2)
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{
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p->month++;
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p->date=1;
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}
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}
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else if (p->date==29)
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{
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if((p->month==2) && (not_leap()))
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{
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p->month++;
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p->date=1;
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}
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}
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if (p->month >= 13)
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{
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p->month=1;
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p->year++;
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}
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}
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}
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}
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}
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ISR(TIMER0_OVF_vect)
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{
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TCCR0B = 5 ; // Divide/128
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while((ASSR & 0b00011011) != 0x00);/*Wait until TCNT0, OCR0A, TCCR0A and TCCR0B updated*/
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updateTime(1) ;
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}
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void checkPowerSave()
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{
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if ( PINB & 0x05 )
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{
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ActivityFlag = 0 ;
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return ; // I2C line(s) are high, power is ON
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}
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if ( ActivityFlag < 3 )
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{
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return ;
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}
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// The AVR toolchain includes a header file, sleep.h, which has functions for setting
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//sleep mode, disabling BOD, and putting the device into sleep. These functions are
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//called:
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//.. set_sleep_mode() – selects which sleep mode to use when the sleep
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//instruction is executed
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//.. sleep_enable() – enables sleep modes
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//.. sleep_bod_disable() – disables BOD while sleeping
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//.. sleep_cpu() – executes the sleep instruction
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CLKPR = 0x80 ; // Do inline for quick response
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CLKPR = 0 ; // Full speed 8.0MHz
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set_sleep_mode(SLEEP_MODE_PWR_SAVE);
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TIMSK0 |= (1 << TOIE0) ;
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disableAdc() ;
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PRR = 0x3B ; // Power off USI
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Disable_WatchDogTimer() ;
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set_clock( 2 ) ; // Slow to 2.0 MHz
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while ( ( PINB & 0x05 ) == 0 ) // I2C lines are low
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{
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sleep_enable();
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sleep_bod_disable();
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sei();
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sleep_cpu();
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sleep_disable();
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cli() ;
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wdt_reset() ;
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}
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PRR = 0x39 ; // USI re-powered
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Init_WatchDogTimer() ;
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USI_TWI_SLAVE_Init();
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enableAdc() ;
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TIMSK0 &= ~(1 << TOIE0) ;
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USISR = (1<<USISIF) | (1<<USIOIF) | (1<<USIPF) ; // Clear interrupt flags.
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set_clock( 5 ) ; // Slow to 0.25MHz
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ActivityFlag = 0 ;
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}
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/******************************************************************************/
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/* Local variables */
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//static uint8_t TWI_RxBuf[TWI_RX_BUFFER_SIZE];
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//static volatile uint8_t TWI_RxHead;
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//static volatile uint8_t TWI_RxTail;
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//static uint8_t TWI_TxBuf[TWI_TX_BUFFER_SIZE];
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//static volatile uint8_t TWI_TxHead;
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//static volatile uint8_t TWI_TxTail;
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#define USI_TWI_SlaveAddress 0x35
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//********** USI_TWI functions **********//
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static void USI_TWI_SLAVE_Init()
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{
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// USI_TWI_SlaveAddress = TWI_OwnAddress;
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DDR_USI &= ~(1<<PORT_USI_SDA); // Set SDA as input
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PORT_USI &= ~(1<<PORT_USI_SDA); // Set SDA high
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DDR_USI |= (1<<PORT_USI_SCL); // Set SCL as output
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PORT_USI |= (1<<PORT_USI_SCL); // Set SCL high
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USICR = /*(0<<USISIE)|(0<<USIOIE)|*/ // Disable Start Condition Interrupt. Disable Overflow Interrupt.
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(1<<USIWM1)|(1<<USIWM0)| // Set USI in Two-wire mode. No USI Counter overflow prior
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// to first Start Condition (potentail failure)
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(1<<USICS1)|(0<<USICS0)|(0<<USICLK)| // Shift Register Clock Source = External, positive edge
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(0<<USITC);
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// Clear the interrupt flags and reset the counter.
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USISR = (1<<USISIF) | (1<<USIOIF) | (1<<USIPF) | // Clear interrupt flags.
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(1<<USIDC) |(0x0<<USICNT0); // USI to sample 8 bits or 16 edge toggles.
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// USI TWI Start condition interrupt enable.
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// USICR |= (1<<USISIE); // Not needed, all are polled
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}
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// the below function is added by
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/*****************************************************************************/
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static void USI_TWI_SLAVE_Abort()
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{
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USICR = /*(0<<USISIE)|(0<<USIOIE)|*/ // Disable Start Condition Interrupt. Disable Overflow Interrupt.
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(0<<USIWM1)|(0<<USIWM0)| // reset USI in Two-wire mode. No USI Counter overflow prior
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// to first Start Condition (potentail failure)
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(0<<USICS1)|(0<<USICS0)|(0<<USICLK)| // Shift Register Clock Source = internal, positive edge
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(0<<USITC);
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// Reset SCL and SDA lines of TWI Communication interface
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DDR_USI &= ~(1<<PORT_USI_SDA);
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PORT_USI &= ~(1<<PORT_USI_SDA); // Set SDA low
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// PORTA &= ~8 ;
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DDR_USI |= ~(1<<PORT_USI_SCL);
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PORT_USI |= ~(1<<PORT_USI_SCL); // Set SCL low
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// Clear the USI DATA register.
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USIDR = 0x00;
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// Clear the interrupt flags and reset the counter.
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USISR = (1<<USISIF) | (1<<USIOIF) | (1<<USIPF) | // Clear interrupt flags.
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(1<<USIDC) |(0x0<<USICNT0); // USI to sample 8 bits or 16 edge toggles.
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}
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static void USI_TWI_SLAVE_ReadAndProcessPacket ()
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{
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set_clock( 5 ) ; // Slow to 0.25MHz
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while(1)
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{
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// Check for USI TWI start condition.
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if (USISR & (1<<USISIF))
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{
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CLKPR = 0x80 ; // Do inline for quick response
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CLKPR = 0 ; // Full speed 8.0MHz
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// Process the USI TWI start condition.
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USI_TWI_SLAVE_Process_Start_Condition();
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}
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// Check for USI_TWI_SLAVE overflow condition.
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if (USISR & (1<<USIOIF))
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{
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ActivityFlag = 0 ;
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// Handle the TWI overflow condition.
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USI_TWI_SLAVE_Process_Overflow_Condition();
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/* as this part is already taken care...
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// Should we update the twi address?
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if (USI_TWI_SLAVE_Address_Update)
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{
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// Mark the bootloader as active.
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bootloader_active = 1;
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// Check for the special address to exit the bootloader.
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if (USI_TWI_SLAVE_PAGE_Address != 0xffff)
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{
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// Set the twi address. This will load the corresponding page from
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// flash into the programming buffer for reading and writing.
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// prog_buffer_set_address(USI_TWI_SLAVE_PAGE_Address);
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}
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// Reset the flag.
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USI_TWI_SLAVE_Address_Update = 0;
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}
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.....Till here.........*/
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}
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// Check for TWI stop condition.
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if (USISR & (1<<USIPF))
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{
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// Clear the stop condition flag.
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USISR = (1<<USIPF);
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// Check for the special address to exit the bootloader.
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if ( Run_boot )
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{
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// Set the flag to have the bootloader eixt.
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break ;
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}
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else
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{
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USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_NONE ;
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Command_Flag = 0 ;
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}
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set_clock( 5 ) ; // Slow to 0.25MHz
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}
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wdt_reset() ;
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if ( TIFR0 & 1 )
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{
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CLKPR = 0x80 ; // Do inline for quick response
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CLKPR = 0 ; // Full speed 8.0MHz
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TIFR0 = 1 ; // CLEAR flag (write 1)
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updateTime(1) ;
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t_time *p = &Time ;
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uint8_t *q = &Tx_buffer[1] ;
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// FORCE_INDIRECT(p) ;
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*q++ = p->second ;
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*q++ = p->minute ;
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*q++ = p->hour ;
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*q++ = p->date ;
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*q++ = p->month ;
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*q++ = p->year ;
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*q++ = p->year >> 8 ;
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*q++ = Temperature ;
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*q++ = T_offset ;
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*q++ = T_gain ;
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// *q++ = MCUSR ;
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if ( ActivityFlag < 255 )
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{
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ActivityFlag += 1 ;
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}
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set_clock( 5 ) ; // Slow to 0.25MHz
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}
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checkPowerSave() ;
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if ( ( AdcControl & ADC_RUNNING ) == 0 )
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{
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ADMUX = TEMPERATURE ; // Internal 1.1V REF and ADCx
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ADCSRA |= (1<<ADSC); // do single conversion
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AdcControl |= ADC_RUNNING ;
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}
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else
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{
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if ( ( ADCSRA & (1<<ADSC) ) == 0 )
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{
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AdcControl &= ~ADC_RUNNING ;
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AdcControl += 1 ;
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if ( ( AdcControl & ADC_COUNT_MASK ) > 1 )
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{ // Skip first conversion
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AdcTotal += ADCW ;
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}
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if ( ( AdcControl & ADC_COUNT_MASK ) >= 9 )
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{
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AdcTotal += 4 ;
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AdcTotal >>= 3 ;
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{
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int16_t temp ;
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temp = AdcTotal ;
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temp -= 298 ;
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temp += T_offset ;
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temp *= T_mult ;
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temp >>= 8 ;
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temp += 25 ;
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Temperature = temp ;
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}
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AdcControl = 0 ;
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AdcTotal = 0 ;
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// if (AdcTotal < 0x00f6)
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// {
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// Temperature=-40;
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// }
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// else if (AdcTotal < 0x0144)
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// {
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// Temperature=((AdcTotal*78)/65)-40;
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// }
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// else
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// {
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// Temperature=((((AdcTotal-324)*600)/74)+250)/10;
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// }
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}
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}
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}
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} // while
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// Disable_WatchDogTimer(); // After Reset the WDT state does not change
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// void (*FuncPtr) (void) = (void (*)(void)) (0x0080); // Set up function pointer to address 0x0080
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// FuncPtr ();
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TCCR0B = 0 ;
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USICR = 0 ;
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USISR = 0 ;
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PRR = 0 ;
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CLKPR = 0x80 ; // Do inline for quick response
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CLKPR = 0 ; // Full speed 8.0MHz
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((void (*)(void)) (0))() ;
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}
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/******************************************************************************/
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//Description:
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// Process the USI TWI start condition. This is called when the TWI master initiates
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// communication with a USI TWI slave by asserting the TWI start condition.
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/******************************************************************************/
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static void USI_TWI_SLAVE_Process_Start_Condition(void)
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{
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// Wait until the "Start Condition" is complete when SCL goes low. If we fail to wait
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// for SCL to go low we may miscount the number of clocks pulses for the data because
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// the transition of SCL could be mistaken as one of the data clock pulses.
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while ((PIN_USI & (1<<PORT_USI_SCL)));
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// Reset the overflow state.
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USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_NONE;
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// Clear the interrupt flags and reset the counter.
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USISR = (1<<USISIF) | (1<<USIOIF) | (1<<USIPF) | // Clear interrupt flags.
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(0x00<<USICNT0); // USI to sample 8 bits or 16 edge toggles.
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// Update the interrupt enable, wire mode and clock settings.
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USICR = /*(1<<USISIE) | (1<<USIOIE) |*/ // Enable Overflow and Start Condition Interrupt.
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(1<<USIWM1) | (1<<USIWM0) | // Maintain USI in two-wire mode with clock stretching.
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(1<<USICS1) | (0<<USICS0) | (0<<USICLK) | // Shift Register Clock Source = External, positive edge
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(0<<USITC); // No toggle of clock pin.
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}
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/******************************************************************************/
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/*******************************************************************************
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Description:
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Processes the USI_TWI_SLAVE overflow condition.
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This is called when the USI TWI 4-bit counterboverflows indicating the
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TWI master has clocked in/out a databyte or a singleback/nack byte following a
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databyte transfer.
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*******************************************************************************/
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void USI_TWI_SLAVE_Process_Overflow_Condition(void)
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{
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// Buffer the USI data.
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uint8_t Usi_Data = USIDR;
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// Handle the interrupt based on the overflow state.
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switch (USI_TWI_SLAVE_Overflow_State)
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{
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/***********************************************************************/
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// Handle the first byte transmitted from master -- the slave address.
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case USI_TWI_SLAVE_OVERFLOW_STATE_NONE:
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// Are we receiving our address?
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if ((Usi_Data >> 1) == USI_TWI_SlaveAddress)
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{
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// Yes. Are we to send or receive data?
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if((Usi_Data & 0x01) == 0x01)
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{
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//USI TWI Slave has to transmit the data byte
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USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_ACK_PR_TX;
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Tx_buffer[0] = VERSION ; // Version number
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Tx_index = 0 ;
|
||
}
|
||
else
|
||
{
|
||
//USI TWI Slave has to Receive the data byte
|
||
USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_ACK_PR_RX;
|
||
}
|
||
|
||
// Reset the write state.
|
||
//.. added the below statement at Command_flag=1
|
||
//USI_TWI_SLAVE_Write_State = USI_TWI_SLAVE_WRITE_ADDR_HI_BYTE;
|
||
|
||
// Set SDA for output.
|
||
PORT_USI |= (1<<PORT_USI_SDA);
|
||
DDR_USI |= (1<<PORT_USI_SDA);
|
||
|
||
// Load data for ACK.
|
||
USIDR = 0;
|
||
|
||
// Reload counter for ACK -- two clock transitions.
|
||
USISR = 0x0E;
|
||
|
||
}
|
||
else
|
||
{
|
||
// No. Reset USI to detect start condition. Update the interrupt enable,
|
||
// wire mode and clock settings. Note: At this time the wire mode must
|
||
// not be set to hold the SCL line low when the counter overflows.
|
||
// Otherwise, this TWI slave will interfere with other TWI slaves.
|
||
USICR = /*(1<<USISIE) | (0<<USIOIE) |*/ // Enable Start Condition Interrupt. Disable overflow.
|
||
(1<<USIWM1) | (0<<USIWM0) | // Maintain USI in two-wire mode without clock stretching.
|
||
(1<<USICS1) | (0<<USICS0) | (0<<USICLK) | // Shift Register Clock Source = External, positive edge
|
||
(0<<USITC); // No toggle of clock pin.
|
||
}
|
||
|
||
break;
|
||
/***********************************************************************/
|
||
// Ack sent to master so prepare to receive more data.
|
||
case USI_TWI_SLAVE_OVERFLOW_STATE_ACK_PR_RX:
|
||
|
||
if(Command_Flag == 0)
|
||
{
|
||
// Update our state.
|
||
USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_CMD_RX;
|
||
}
|
||
else if(Command_Flag == 1)
|
||
{
|
||
// Update our state.
|
||
USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_DATA_RX;
|
||
}
|
||
// else if(Command_Flag == 2)
|
||
// {
|
||
// // Update our state.
|
||
// USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_DATA_TX_AVERSION;
|
||
// }
|
||
// else if(Command_Flag == 3)
|
||
// {
|
||
// // Update our state.
|
||
// USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_DATA_TX_BVERSION;
|
||
// }
|
||
// else if(Command_Flag == 4)
|
||
// {
|
||
// // Update our state.
|
||
// USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_DATA_TX_GETERRCONDN;
|
||
// }
|
||
|
||
|
||
// Set SDA for input
|
||
DDR_USI &= ~(1<<PORT_USI_SDA);
|
||
PORT_USI &= ~(1<<PORT_USI_SDA);
|
||
|
||
break;
|
||
/**************************************************************************/
|
||
|
||
|
||
case USI_TWI_SLAVE_OVERFLOW_STATE_CMD_RX:
|
||
|
||
// Update our state
|
||
USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_NONE;
|
||
|
||
// Check the command received type.
|
||
if(Usi_Data == TWI_CMD_REBOOT)
|
||
{
|
||
// reset the controller ...
|
||
USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_ACK_PR_RX ;
|
||
// set this flag to receive data
|
||
Command_Flag = 0 ;
|
||
Run_boot = 1 ;
|
||
}
|
||
else if(Usi_Data == TWI_CMD_WRITE_DATA)
|
||
{
|
||
// set this flag to receive data
|
||
Command_Flag =1;
|
||
// ReceiveType = TWI_CMD_SETDATETIME ;
|
||
USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_ACK_PR_RX ;
|
||
USI_TWI_SLAVE_Write_State = USI_TWI_SLAVE_WRITE_DATA_BYTE;
|
||
bufferPtr = DataBuffer ;
|
||
Value = 0 ;
|
||
}
|
||
// else if(Usi_Data == TWI_CMD_BVERSION)
|
||
// {
|
||
// // set this flag to receive data
|
||
// Command_Flag =3;
|
||
|
||
// }
|
||
// else if(Usi_Data == TWI_CMD_ERASEFLASH)
|
||
// {
|
||
// // erase the flash here itself .......
|
||
|
||
// // set this flag to receive data
|
||
// Command_Flag =0;
|
||
|
||
// }
|
||
// else if(Usi_Data == TWI_CMD_GETERRCONDN)
|
||
// {
|
||
// // set this flag to receive data
|
||
// Command_Flag =4;
|
||
|
||
// }
|
||
else
|
||
{
|
||
// set this flag to receive data
|
||
Command_Flag =0;
|
||
|
||
USI_TWI_SLAVE_Abort();
|
||
}
|
||
// Set SDA for output.
|
||
PORT_USI |= (1<<PORT_USI_SDA);
|
||
DDR_USI |= (1<<PORT_USI_SDA);
|
||
|
||
// Load data for ACK.
|
||
USIDR = 0;
|
||
|
||
// Reload counter for ACK -- two clock transitions.
|
||
USISR = 0x0E;
|
||
break;
|
||
|
||
// Data received from master so prepare to send ACK.
|
||
case USI_TWI_SLAVE_OVERFLOW_STATE_DATA_RX:
|
||
|
||
// Update our state.
|
||
USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_ACK_PR_RX;
|
||
|
||
// Always make sure the Command_Flag is 1
|
||
Command_Flag = 1;
|
||
|
||
// Check the TWI write state to determine what type of byte we received.
|
||
// if (USI_TWI_SLAVE_Write_State == USI_TWI_SLAVE_WRITE_ADDR_HI_BYTE)
|
||
// {
|
||
// // Set the twi address high byte.
|
||
// USI_TWI_SLAVE_PAGE_Address = Usi_Data;
|
||
|
||
// // Set the next state.
|
||
// USI_TWI_SLAVE_Write_State = USI_TWI_SLAVE_WRITE_ADDR_LO_BYTE;
|
||
// }
|
||
// else if (USI_TWI_SLAVE_Write_State == USI_TWI_SLAVE_WRITE_ADDR_LO_BYTE)
|
||
// {
|
||
// // Set the address low byte.
|
||
// USI_TWI_SLAVE_PAGE_Address = (USI_TWI_SLAVE_PAGE_Address << 8) | Usi_Data;
|
||
|
||
// // Set the programming address.
|
||
//// USI_TWI_SLAVE_Address_Update = 1;
|
||
// Value = 0;
|
||
// bufferPtr = pageBuffer ;
|
||
|
||
// // Set the next state.
|
||
// USI_TWI_SLAVE_Write_State = USI_TWI_SLAVE_WRITE_DATA_BYTE;
|
||
// }
|
||
// else
|
||
{
|
||
// Write the data to the buffer.
|
||
//USI_TWI_SLAVE_prog_buffer_set_byte(Usi_Data);
|
||
|
||
*bufferPtr = Usi_Data;
|
||
|
||
// Increment the byte address within the page.
|
||
//++prog_byte_address;
|
||
|
||
++bufferPtr;
|
||
++Value;
|
||
// Check the byte address for wrapping. // check later
|
||
|
||
if ( DataBuffer[0] == TWI_SUBCMD_SETDATETIME )
|
||
{
|
||
if (Value >= 8 ) // Size of time structure+1
|
||
{
|
||
if ( Value == 8 )
|
||
{
|
||
// Set the date and time
|
||
t_time *p = &Time ;
|
||
FORCE_INDIRECT(p) ;
|
||
|
||
p->second = DataBuffer[1] ;
|
||
p->minute = DataBuffer[2] ;
|
||
p->hour = DataBuffer[3] ;
|
||
p->date= DataBuffer[4] ;
|
||
p->month = DataBuffer[5] ;
|
||
p->year = DataBuffer[6] + ( DataBuffer[7] << 8 ) ;
|
||
}
|
||
Value = 9 ;
|
||
bufferPtr = &DataBuffer[DATA_SIZE-1] ;
|
||
}
|
||
}
|
||
if ( Value > DATA_SIZE )
|
||
{
|
||
Value = DATA_SIZE ;
|
||
bufferPtr = &DataBuffer[DATA_SIZE-1] ; // Overwrite last byte
|
||
}
|
||
}
|
||
|
||
// Set SDA for output.
|
||
PORT_USI |= (1<<PORT_USI_SDA);
|
||
DDR_USI |= (1<<PORT_USI_SDA);
|
||
// PORTA |= 8 ;
|
||
|
||
// Load data for ACK.
|
||
USIDR = 0;
|
||
|
||
// Reload counter for ACK -- two clock transitions.
|
||
USISR = 0x0E;
|
||
|
||
break;
|
||
/***********************************************************************/
|
||
|
||
case USI_TWI_SLAVE_OVERFLOW_STATE_DATA_TX_AVERSION:
|
||
|
||
// Update our state.
|
||
USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_PR_ACK_TX;
|
||
|
||
// Set SDA for input.
|
||
DDR_USI &= ~(1<<PORT_USI_SDA);
|
||
// PORTA &= ~8 ;
|
||
PORT_USI &= ~(1<<PORT_USI_SDA);
|
||
|
||
// Reload counter for ACK -- two clock transitions.
|
||
USISR = 0x0E;
|
||
|
||
break;
|
||
|
||
/***********************************************************************/
|
||
case USI_TWI_SLAVE_OVERFLOW_STATE_DATA_TX_BVERSION:
|
||
|
||
break;
|
||
/***********************************************************************/
|
||
case USI_TWI_SLAVE_OVERFLOW_STATE_DATA_TX_GETERRCONDN:
|
||
|
||
break;
|
||
/***********************************************************************/
|
||
// ACK received from master. Reset USI state if NACK received.
|
||
case USI_TWI_SLAVE_OVERFLOW_STATE_PR_ACK_TX:
|
||
|
||
// Check the lowest bit for NACK? If set, the master does not want more data.
|
||
if (Usi_Data & 0x01)
|
||
{
|
||
// Update our state.
|
||
USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_NONE;
|
||
|
||
// Reset USI to detect start condition. Update the interrupt enable,
|
||
// wire mode and clock settings. Note: At this time the wire mode must
|
||
// not be set to hold the SCL line low when the counter overflows.
|
||
// Otherwise, this TWI slave will interfere with other TWI slaves.
|
||
USICR = /*(1<<USISIE) | (0<<USIOIE) |*/ // Enable Start Condition Interrupt. Disable overflow.
|
||
(1<<USIWM1) | (0<<USIWM0) | // Maintain USI in two-wire mode without clock stretching.
|
||
(1<<USICS1) | (0<<USICS0) | (0<<USICLK) | // Shift Register Clock Source = External, positive edge
|
||
(0<<USITC); // No toggle of clock pin.
|
||
|
||
|
||
// Clear the overflow interrupt flag and release the hold on SCL.
|
||
USISR |= (1<<USIOIF);
|
||
|
||
return;
|
||
}
|
||
|
||
|
||
|
||
/***********************************************************************/
|
||
// Handle sending a byte of data.
|
||
case USI_TWI_SLAVE_OVERFLOW_STATE_ACK_PR_TX:
|
||
|
||
// Update our state.
|
||
// USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_DATA_TX;
|
||
USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_DATA_TX_AVERSION;
|
||
|
||
// Set SDA for output.
|
||
PORT_USI |= (1<<PORT_USI_SDA);
|
||
DDR_USI |= (1<<PORT_USI_SDA);
|
||
// PORTA |= 8 ;
|
||
|
||
// Get the data to send.
|
||
// USIDR = prog_buffer_get_byte();
|
||
|
||
USIDR = Tx_buffer[Tx_index++] ; // Send this for testing
|
||
|
||
break;
|
||
/***********************************************************************/
|
||
|
||
// Data sent to to master so prepare to receive ack.
|
||
case USI_TWI_SLAVE_OVERFLOW_STATE_DATA_TX:
|
||
|
||
// Update our state.
|
||
USI_TWI_SLAVE_Overflow_State = USI_TWI_SLAVE_OVERFLOW_STATE_PR_ACK_TX;
|
||
|
||
// Set SDA for input.
|
||
DDR_USI &= ~(1<<PORT_USI_SDA);
|
||
// PORTA &= ~8 ;
|
||
PORT_USI &= ~(1<<PORT_USI_SDA);
|
||
|
||
// Reload counter for ACK -- two clock transitions.
|
||
USISR = 0x0E;
|
||
|
||
break;
|
||
/***********************************************************************/
|
||
}
|
||
// Clear the overflow interrupt flag and release the hold on SCL.
|
||
USISR |= (1<<USIOIF);
|
||
}
|
||
|
||
uint8_t state = 0;
|
||
// __no_init uint8_t pageBuffer[PAGE_SIZE];
|
||
//uint16_t time_lapse_sec = 0;
|
||
#define gtimeout WDT_TIMEOUT_8s
|
||
// uint8_t volatile gtimeout;
|
||
//uint8_t statusCode = 0;
|
||
|
||
/***********************************************************************/
|
||
|
||
static void Disable_WatchDogTimer (void)
|
||
{
|
||
/*
|
||
Timed sequence
|
||
Interrupts are already disabled else additional code may go in to avoid
|
||
the servicing of interrupt in between the timed sequence
|
||
*/
|
||
wdt_reset();
|
||
WDTCR = (1 << WDCE) | ( 1 << WDE ) ;
|
||
MCUSR = 0 ;
|
||
WDTCR = 0 ;
|
||
|
||
}
|
||
|
||
/***********************************************************************/
|
||
|
||
static void Init_WatchDogTimer (void)
|
||
{
|
||
/*
|
||
Timed sequence to initialize watchdog timer
|
||
for the given mode set in gtimeout variable
|
||
Cross calls during maximum optimization can
|
||
cause more than 4 cycles delay between change
|
||
enable for WDT and setting values
|
||
*/
|
||
wdt_reset();
|
||
WDTCR = (1 << WDCE) | ( 1 << WDE ) ;
|
||
WDTCR = ( 1 << WDE ) | gtimeout ;
|
||
}
|
||
|
||
|
||
/***********************************************************************/
|
||
NOINLINE void set_clock( uint8_t speed )
|
||
{
|
||
volatile uint8_t *ptr ;
|
||
ptr = &CLKPR ;
|
||
*ptr = 0x80 ;
|
||
*ptr = speed ;
|
||
}
|
||
|
||
/***********************************************************************/
|
||
// Main Starts from here
|
||
void main (void)
|
||
{
|
||
|
||
USI_TWI_SLAVE_Init();
|
||
//__enable_interrupt();
|
||
|
||
Init_WatchDogTimer() ;
|
||
|
||
/*RTC 32.768kHz, div 128 */
|
||
{
|
||
PRR = 0x39 ;
|
||
TCCR0A = 0 ;
|
||
TCCR0B = 5 ; // Divide/128
|
||
ASSR = 0x20 ; // Async mode
|
||
while((ASSR & 0b00011011) != 0x00);/*Wait until TCNT0, OCR0A, TCCR0A and TCCR0B updated*/
|
||
TIFR0 = 0x01;/*Clear T0 int flag*/
|
||
|
||
}
|
||
t_time *p = &Time ;
|
||
FORCE_INDIRECT(p) ;
|
||
|
||
p->second = 5 ;
|
||
p->minute = 6 ;
|
||
p->hour = 16 ;
|
||
p->date= 23 ;
|
||
p->month = 9 ;
|
||
p->year = 2012 ;
|
||
|
||
bufferPtr = DataBuffer ;
|
||
|
||
T_offset = boot_signature_byte_get( TSOFFSET ) ;
|
||
T_gain = boot_signature_byte_get( TSGAIN ) ;
|
||
T_mult = 32768U / T_gain ;
|
||
|
||
enableAdc() ;
|
||
for(;;)
|
||
{
|
||
USI_TWI_SLAVE_ReadAndProcessPacket() ;
|
||
}
|
||
}
|
||
|
||
|
||
// Enable ADC
|
||
void enableAdc()
|
||
{
|
||
cbi( PRR, PRADC ) ; // Power the ADC
|
||
ADCSRA = (1 << ADEN) | (1 << ADPS2) | (1 << ADPS1); // set ADC prescaler to , 8MHz / 64 = 125kHz
|
||
}
|
||
|
||
// Disable ADC
|
||
void disableAdc()
|
||
{
|
||
ADCSRA = (1 << ADPS2) | (1 << ADPS1) | (1 << ADPS0) ; // set ADC prescaler to , 8MHz / 256 = 30kHz
|
||
sbi( PRR, PRADC ) ; // Power Down the ADC
|
||
}
|
||
|