237 lines
8.7 KiB
C++
237 lines
8.7 KiB
C++
/*
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* Authors (alphabetical order)
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* - Andre Bernet <bernet.andre@gmail.com>
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* - Bertrand Songis <bsongis@gmail.com>
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* - Bryan J. Rentoul (Gruvin) <gruvin@gmail.com>
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* - Cameron Weeks <th9xer@gmail.com>
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* - Erez Raviv
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* - Jean-Pierre Parisy
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* - Karl Szmutny <shadow@privy.de>
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* - Michael Blandford
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* - Michal Hlavinka
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* - Pat Mackenzie
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* - Philip Moss
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* - Rob Thomson
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* - Romolo Manfredini <romolo.manfredini@gmail.com>
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* - Thomas Husterer
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*
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* open9x is based on code named
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* gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/,
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* er9x by Erez Raviv: http://code.google.com/p/er9x/,
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* and the original (and ongoing) project by
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* Thomas Husterer, th9x: http://code.google.com/p/th9x/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "../open9x.h"
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bool dacIdle = true;
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uint32_t currentFrequency = 0;
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uint32_t getFrequency()
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{
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return currentFrequency;
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}
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void setFrequency(uint32_t frequency)
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{
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if (currentFrequency != frequency) {
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currentFrequency = frequency;
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register uint32_t timer = (PERI1_FREQUENCY * TIMER_MULT_APB1) / frequency - 1 ; // MCK/8 and 100 000 Hz
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TIM6->CR1 &= ~TIM_CR1_CEN ;
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TIM6->CNT = 0 ;
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TIM6->ARR = limit<uint32_t>(2, timer, 65535) ;
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TIM6->CR1 |= TIM_CR1_CEN ;
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}
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}
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// Start TIMER6 at 100000Hz, used for DAC trigger
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void dacTimerInit()
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{
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// Now for timer 6
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RCC->APB1ENR |= RCC_APB1ENR_TIM6EN ; // Enable clock
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TIM6->PSC = 0 ; // Max speed
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TIM6->ARR = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 100000 - 1 ; // 10 uS, 100 kHz
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TIM6->CR2 = 0 ;
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TIM6->CR2 = 0x20 ;
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TIM6->CR1 = TIM_CR1_CEN ;
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}
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// Configure DAC0 (or DAC1 for REVA)
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// Not sure why PB14 has not be allocated to the DAC, although it is an EXTRA function
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// So maybe it is automatically done
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void dacInit()
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{
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dacTimerInit();
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
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configure_pins( 0x0010, PIN_ANALOG | PIN_PORTA ) ;
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RCC->APB1ENR |= RCC_APB1ENR_DACEN ; // Enable clock
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RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN ; // Enable DMA1 clock
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// Chan 7, 16-bit wide, Medium priority, memory increments
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DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA
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DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
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DMA1_Stream5->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 |
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DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_CIRC ;
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DMA1_Stream5->PAR = (uint32_t) &DAC->DHR12R1 ;
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DMA1_Stream5->M0AR = CONVERT_PTR(Sine_values);
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DMA1_Stream5->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
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DMA1_Stream5->NDTR = 100 ;
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DAC->DHR12R1 = 2010 ;
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DAC->SR = DAC_SR_DMAUDR1 ; // Write 1 to clear flag
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DAC->CR = DAC_CR_TEN1 | DAC_CR_EN1 ; // Enable DAC
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NVIC_SetPriority( DMA1_Stream5_IRQn, 2 ) ; // High priority interrupt
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NVIC_EnableIRQ(TIM6_DAC_IRQn) ;
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NVIC_EnableIRQ(DMA1_Stream5_IRQn) ;
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}
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// Sound routines
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void audioInit()
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{
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dacInit() ;
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// TODO - for volume, shared with EEPROM?
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}
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void audioEnd()
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{
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DAC->CR = 0 ;
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TIM6->CR1 = 0 ;
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// Also need to turn off any possible interrupts
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NVIC_DisableIRQ(TIM6_DAC_IRQn) ;
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NVIC_DisableIRQ(DMA1_Stream5_IRQn) ;
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}
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#ifndef SIMU
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extern "C" void TIM6_DAC_IRQHandler()
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{
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DAC->CR &= ~DAC_CR_DMAEN1 ; // Stop DMA requests
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DAC->CR &= ~DAC_CR_DMAUDRIE1 ; // Stop underrun interrupt
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DAC->SR = DAC_SR_DMAUDR1 ; // Write 1 to clear flag
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}
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extern "C" void DMA1_Stream5_IRQHandler()
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{
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DMA1_Stream5->CR &= ~DMA_SxCR_TCIE ; // Stop interrupt
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DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear flags
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DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA channel
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if (nextAudioData) {
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DMA1_Stream5->M0AR = CONVERT_PTR(nextAudioData);
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DMA1_Stream5->NDTR = nextAudioSize*2;
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DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
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DMA1_Stream5->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE ; // Enable DMA channel
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DAC->SR = DAC_SR_DMAUDR1; // Write 1 to clear flag
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nextAudioData = NULL;
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}
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else {
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dacIdle = true;
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}
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}
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#endif
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#if 0
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static void Audio_GPIO_Init()
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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/* EnableI2C GPIO clocks */
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RCC_AHB1PeriphClockCmd(CODEC_I2S_GPIO_CLOCK, ENABLE);//GPIOA C
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/* CODEC_I2S pins configuration: WS, SCK and SD pins -----------------------------*/
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GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);
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GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(CODEC_I2S_WS_GPIO, &GPIO_InitStructure);
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/* Connect pins to I2S peripheral */
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GPIO_PinAFConfig(CODEC_I2S_WS_GPIO, CODEC_I2S_WS_PINSRC, CODEC_I2S_GPIO_AF);
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GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, CODEC_I2S_GPIO_AF);
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GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SD_PINSRC, CODEC_I2S_GPIO_AF);
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#ifdef CODEC_MCLK_ENABLED
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/* CODEC_I2S pins configuration: MCK pin */
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GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure);
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/* Connect pins to I2S peripheral */
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GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF);
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#endif /* CODEC_MCLK_ENABLED */
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/*CODEC_I2S_MUTE & CODEC_I2S_FLT GPIO CONFIG*/
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GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MUTE;// | CODEC_I2S_FLT;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);
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GPIO_SetBits(CODEC_I2S_GPIO,CODEC_I2S_MUTE);
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// GPIO_SetBits(CODEC_I2S_CTL_GPIO,CODEC_I2S_FLT);
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}
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void audioInit()
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{
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I2S_InitTypeDef I2S_InitStructure;
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Audio_GPIO_Init();
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/*CONFIG the I2S_RCC ,MUST before enabling the I2S APB clock*/
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//PLLI2SN 302,PLLI2SR 2,I2SDIV 53,I2SODD 1,FS 44.1KHZ,16bit,Error 0.0011%
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RCC_PLLI2SConfig(302,2);
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RCC_PLLI2SCmd(ENABLE);
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RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S);
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/* Enable the CODEC_I2S peripheral clock */
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RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, ENABLE);
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/* CODEC_I2S peripheral configuration */
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SPI_I2S_DeInit(CODEC_I2S);
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I2S_InitStructure.I2S_AudioFreq = AudioFreq;
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I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
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I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
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I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;//clk 0 when idle state
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I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
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#ifdef CODEC_MCLK_ENABLED
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I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;
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#elif defined(CODEC_MCLK_DISABLED)
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I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
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#else
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#error "No selection for the MCLK output has been defined !"
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#endif /* CODEC_MCLK_ENABLED */
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/* Initialize the I2S peripheral with the structure above */
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I2S_Init(CODEC_I2S, &I2S_InitStructure);
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I2S_Cmd(CODEC_I2S, ENABLE);
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//interrupt
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#ifdef CODEC_USE_INT
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SPI_I2S_ITConfig(CODEC_I2S,SPI_I2S_IT_TXE,ENABLE);
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#elif defined(CODEC_USE_DMA)
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#error "DMA is not initialized"
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#endif
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}
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#endif
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