626 lines
23 KiB
C++
626 lines
23 KiB
C++
/*
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* Authors (alphabetical order)
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* - Andre Bernet <bernet.andre@gmail.com>
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* - Andreas Weitl
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* - Bertrand Songis <bsongis@gmail.com>
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* - Bryan J. Rentoul (Gruvin) <gruvin@gmail.com>
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* - Cameron Weeks <th9xer@gmail.com>
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* - Erez Raviv
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* - Gabriel Birkus
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* - Jean-Pierre Parisy
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* - Karl Szmutny
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* - Michael Blandford
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* - Michal Hlavinka
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* - Pat Mackenzie
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* - Philip Moss
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* - Rob Thomson
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* - Romolo Manfredini <romolo.manfredini@gmail.com>
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* - Thomas Husterer
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*
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* opentx is based on code named
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* gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/,
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* er9x by Erez Raviv: http://code.google.com/p/er9x/,
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* and the original (and ongoing) project by
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* Thomas Husterer, th9x: http://code.google.com/p/th9x/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "../../opentx.h"
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void setupPulses(unsigned int port);
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void setupPulsesPPM(unsigned int port);
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void setupPulsesPXX(unsigned int port);
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uint16_t *ppmStreamPtr[NUM_MODULES];
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extern uint16_t ppmStream[NUM_MODULES+1][20];
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extern uint16_t pxxStream[NUM_MODULES][400];
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extern uint16_t dsm2Stream[400];
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static void init_pa10_pxx( void ) ;
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static void disable_pa10_pxx( void ) ;
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static void init_pa10_ppm( void ) ;
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static void disable_pa10_ppm( void ) ;
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static void init_pa7_pxx( void ) ;
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static void disable_pa7_pxx( void ) ;
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#if defined(DSM2)
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static void init_pa7_dsm2( void ) ;
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static void disable_pa7_dsm2( void ) ;
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#endif
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static void init_pa7_ppm( void ) ;
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static void disable_pa7_ppm( void ) ;
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static void init_pa10_none( void ) ;
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static void disable_pa10_none( void ) ;
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static void init_pa7_none( void ) ;
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static void disable_pa7_none( void ) ;
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void init_pxx(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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init_pa10_pxx() ;
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else
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init_pa7_pxx() ;
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}
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void disable_pxx(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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disable_pa10_pxx() ;
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else
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disable_pa7_pxx() ;
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}
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#if defined(DSM2)
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void init_dsm2(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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init_pa7_dsm2();
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}
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}
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void disable_dsm2(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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disable_pa7_dsm2();
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}
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}
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#endif
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void init_ppm(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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init_pa10_ppm(); // TODO needed?
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else
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init_pa7_ppm();
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}
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void disable_ppm(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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disable_pa10_ppm(); // TODO needed?
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else
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disable_pa7_ppm();
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}
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void init_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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init_pa10_none();
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else
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init_pa7_none();
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}
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void disable_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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disable_pa10_none();
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else
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disable_pa7_none();
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}
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static void init_pa10_none()
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{
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INTERNAL_RF_OFF();
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// Timer1, channel 3
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GPIO_InitTypeDef GPIO_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_INTPPM, ENABLE);
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GPIO_InitStructure.GPIO_Pin = PIN_INTPPM_OUT;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT ;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(GPIO_INTPPM, &GPIO_InitStructure);
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GPIO_SetBits(GPIO_INTPPM, PIN_INTPPM_OUT) ; // Set high
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN ; // Enable clock
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TIM1->CR1 &= ~TIM_CR1_CEN ;
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TIM1->ARR = 36000 ; // 18mS
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TIM1->CCR2 = 32000 ; // Update time
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TIM1->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
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TIM1->CCER = TIM_CCER_CC3E ;
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TIM1->CCMR2 = 0 ;
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TIM1->EGR = 1 ; // Restart
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TIM1->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
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TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag
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TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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TIM1->CR1 |= TIM_CR1_CEN ;
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NVIC_EnableIRQ(TIM1_CC_IRQn) ;
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NVIC_SetPriority(TIM1_CC_IRQn, 7);
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}
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static void disable_pa10_none()
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{
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NVIC_DisableIRQ(TIM1_CC_IRQn) ;
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TIM1->DIER &= ~TIM_DIER_CC2IE ;
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TIM1->CR1 &= ~TIM_CR1_CEN ;
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}
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static void init_pa7_none()
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{
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EXTERNAL_RF_OFF();
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// Timer8
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GPIO_InitTypeDef GPIO_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_EXTPPM, ENABLE);
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GPIO_InitStructure.GPIO_Pin = PIN_EXTPPM_OUT;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT ;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(GPIO_EXTPPM, &GPIO_InitStructure);
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GPIO_SetBits(GPIO_EXTPPM, PIN_EXTPPM_OUT) ; // Set high
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RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock
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TIM8->CR1 &= ~TIM_CR1_CEN ;
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TIM8->ARR = 36000 ; // 18mS
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TIM8->CCR2 = 32000 ; // Update time
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TIM8->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
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TIM8->CCMR2 = 0 ;
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TIM8->EGR = 1 ; // Restart
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TIM8->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
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TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
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TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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TIM8->CR1 |= TIM_CR1_CEN ;
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NVIC_EnableIRQ(TIM8_CC_IRQn) ;
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NVIC_SetPriority(TIM8_CC_IRQn, 7);
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}
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static void disable_pa7_none()
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{
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NVIC_DisableIRQ(TIM8_CC_IRQn) ;
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TIM8->DIER &= ~TIM_DIER_CC2IE ;
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TIM8->CR1 &= ~TIM_CR1_CEN ;
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}
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static void init_pa10_pxx()
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{
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INTERNAL_RF_ON();
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// Timer1, channel 3
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setupPulsesPXX(INTERNAL_MODULE) ; // TODO not here!
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// RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
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GPIO_InitTypeDef GPIO_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_INTPPM, ENABLE);
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GPIO_PinAFConfig(GPIO_INTPPM, GPIO_PinSource_INTPPM, GPIO_AF_TIM1);
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GPIO_InitStructure.GPIO_Pin = PIN_INTPPM_OUT;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(GPIO_INTPPM, &GPIO_InitStructure);
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN ; // Enable clock
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RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock
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TIM1->CR1 &= ~TIM_CR1_CEN ;
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TIM1->ARR = 18000 ; // 9mS
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TIM1->CCR2 = 15000 ; // Update time
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TIM1->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
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TIM1->CCER = TIM_CCER_CC3E ;
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TIM1->CR2 = TIM_CR2_OIS3 ; // O/P idle high
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TIM1->BDTR = TIM_BDTR_MOE ; // Enable outputs
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TIM1->CCR3 = pxxStream[INTERNAL_MODULE][0];
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TIM1->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0 ; // Force O/P high
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TIM1->EGR = 1 ; // Restart
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// TIM1->SR &= ~TIM_SR_UIF ; // Clear flag
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// TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag
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TIM1->DIER |= TIM_DIER_CC3DE ; // Enable DMA on CC3 match
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TIM1->DCR = 15 ; // DMA to CC1
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// TIM1->CR1 = TIM_CR1_OPM ; // Just run once
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// Enable the DMA channel here, DMA2 stream 6, channel 6
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DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
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DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
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DMA2_Stream6->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
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| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
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DMA2_Stream6->PAR = CONVERT_PTR(&TIM1->DMAR);
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DMA2_Stream6->M0AR = CONVERT_PTR(&pxxStream[INTERNAL_MODULE][1]);
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// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
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// DMA2_Stream2->NDTR = 100 ;
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DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA
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TIM1->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
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TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag
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TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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TIM1->CR1 |= TIM_CR1_CEN ;
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NVIC_EnableIRQ(TIM1_CC_IRQn);
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NVIC_SetPriority(TIM1_CC_IRQn, 7);
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}
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static void disable_pa10_pxx()
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{
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DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
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NVIC_DisableIRQ(TIM1_CC_IRQn) ;
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TIM1->DIER &= ~TIM_DIER_CC2IE ;
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TIM1->CR1 &= ~TIM_CR1_CEN ;
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INTERNAL_RF_OFF();
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}
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// PPM output
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// Timer 1, channel 1 on PA8 for prototype
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// Pin is AF1 function for timer 1
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static void init_pa10_ppm()
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{
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INTERNAL_RF_ON();
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// Timer1
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setupPulsesPPM(INTERNAL_MODULE) ;
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ppmStreamPtr[INTERNAL_MODULE] = ppmStream[INTERNAL_MODULE];
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//RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_INTPPM, ENABLE);
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configure_pins( PIN_INTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ;
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN ; // Enable clock
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TIM1->CR1 &= ~TIM_CR1_CEN ;
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TIM1->ARR = *ppmStreamPtr[INTERNAL_MODULE]++ ;
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TIM1->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
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TIM1->CCER = TIM_CCER_CC3E ;
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TIM1->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 ; // PWM mode 1
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TIM1->CCMR1 = TIM_CCMR1_OC2PE ; // PWM mode 1
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TIM1->CCR3 = (g_model.moduleData[INTERNAL_MODULE].ppmDelay*50+300)*2;
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TIM1->BDTR = TIM_BDTR_MOE ;
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TIM1->EGR = 1 ;
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TIM1->DIER = TIM_DIER_UDE ;
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TIM1->SR &= ~TIM_SR_UIF ; // Clear flag
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TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag
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TIM1->DIER |= TIM_DIER_CC2IE ;
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TIM1->DIER |= TIM_DIER_UIE ;
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TIM1->CR1 = TIM_CR1_CEN ;
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NVIC_EnableIRQ(TIM1_CC_IRQn) ;
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NVIC_SetPriority(TIM1_CC_IRQn, 7);
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NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn) ;
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NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 7);
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}
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static void disable_pa10_ppm()
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{
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NVIC_DisableIRQ(TIM1_CC_IRQn) ;
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NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn) ;
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TIM1->DIER &= ~TIM_DIER_CC2IE & ~TIM_DIER_UIE ;
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TIM1->CR1 &= ~TIM_CR1_CEN ;
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INTERNAL_RF_OFF();
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}
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extern "C" void TIM1_CC_IRQHandler()
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{
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TIM1->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
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TIM1->SR &= ~TIM_SR_CC2IF ; // Clear flag
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setupPulses(INTERNAL_MODULE) ;
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if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
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DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
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DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
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DMA2_Stream6->M0AR = CONVERT_PTR(&pxxStream[INTERNAL_MODULE][1]);
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DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA
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TIM1->CCR3 = pxxStream[INTERNAL_MODULE][0];
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TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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}
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else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) {
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ppmStreamPtr[INTERNAL_MODULE] = ppmStream[INTERNAL_MODULE];
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TIM1->DIER |= TIM_DIER_UDE ;
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TIM1->SR &= ~TIM_SR_UIF ; // Clear this flag
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TIM1->DIER |= TIM_DIER_UIE ; // Enable this interrupt
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}
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else {
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TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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}
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}
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extern "C" void TIM1_UP_TIM10_IRQHandler()
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{
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TIM1->SR &= ~TIM_SR_UIF ; // Clear flag
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TIM1->ARR = *ppmStreamPtr[INTERNAL_MODULE]++ ;
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if ( *ppmStreamPtr[INTERNAL_MODULE] == 0 )
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{
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TIM1->SR &= ~TIM_SR_CC2IF ; // Clear this flag
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TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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}
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}
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static void init_pa7_pxx()
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{
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EXTERNAL_RF_ON();
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// Timer8
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setupPulsesPXX(EXTERNAL_MODULE);
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
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#if defined(REV3)
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configure_pins( PIN_INTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ;
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#else
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GPIO_InitTypeDef GPIO_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_EXTPPM, ENABLE);
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GPIO_PinAFConfig(GPIO_EXTPPM, GPIO_PinSource_EXTPPM, GPIO_AF_TIM8);
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GPIO_InitStructure.GPIO_Pin = PIN_EXTPPM_OUT;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(GPIO_EXTPPM, &GPIO_InitStructure);
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#endif
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RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock
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RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock
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TIM8->CR1 &= ~TIM_CR1_CEN ;
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TIM8->ARR = 18000 ; // 9mS
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TIM8->CCR2 = 15000 ; // Update time
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TIM8->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
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#if defined(REV3)
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TIM8->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P ;
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#else
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TIM8->CCER = TIM_CCER_CC1NE ;
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#endif
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TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high
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TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs
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TIM8->CCR1 = pxxStream[EXTERNAL_MODULE][0] ;
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TIM8->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
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TIM8->EGR = 1 ; // Restart
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// TIM8->SR &= ~TIM_SR_UIF ; // Clear flag
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// TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
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TIM8->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
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TIM8->DCR = 13 ; // DMA to CC1
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// TIM8->CR1 = TIM_CR1_OPM ; // Just run once
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// Enable the DMA channel here, DMA2 stream 2, channel 7
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DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
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DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
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DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
|
|
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
|
|
DMA2_Stream2->PAR = CONVERT_PTR(&TIM8->DMAR);
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|
DMA2_Stream2->M0AR = CONVERT_PTR(&pxxStream[EXTERNAL_MODULE][1]);
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// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
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// DMA2_Stream2->NDTR = 100 ;
|
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DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
|
|
|
|
TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
|
|
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
|
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
TIM8->CR1 |= TIM_CR1_CEN ;
|
|
NVIC_EnableIRQ(TIM8_CC_IRQn) ;
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|
NVIC_SetPriority(TIM8_CC_IRQn, 7);
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|
}
|
|
|
|
static void disable_pa7_pxx()
|
|
{
|
|
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
|
NVIC_DisableIRQ(TIM8_CC_IRQn) ;
|
|
TIM8->DIER &= ~TIM_DIER_CC2IE ;
|
|
TIM8->CR1 &= ~TIM_CR1_CEN ;
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|
EXTERNAL_RF_OFF();
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|
}
|
|
|
|
#if defined(DSM2)
|
|
static void init_pa7_dsm2()
|
|
{
|
|
EXTERNAL_RF_ON();
|
|
|
|
// Timer8
|
|
setupPulsesDSM2(EXTERNAL_MODULE);
|
|
|
|
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
|
|
#if defined(REV3)
|
|
configure_pins( PIN_INTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ;
|
|
#else
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_EXTPPM, ENABLE);
|
|
GPIO_PinAFConfig(GPIO_EXTPPM, GPIO_PinSource_EXTPPM, GPIO_AF_TIM8);
|
|
GPIO_InitStructure.GPIO_Pin = PIN_EXTPPM_OUT;
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
|
GPIO_Init(GPIO_EXTPPM, &GPIO_InitStructure);
|
|
#endif
|
|
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock
|
|
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock
|
|
|
|
TIM8->CR1 &= ~TIM_CR1_CEN ;
|
|
TIM8->ARR = 44000 ; // 22mS
|
|
TIM8->CCR2 = 40000 ; // Update time
|
|
TIM8->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
|
|
#if defined(REV3)
|
|
TIM8->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P ;
|
|
#else
|
|
TIM8->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ;
|
|
#endif
|
|
TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high
|
|
TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs
|
|
TIM8->CCR1 = dsm2Stream[0] ;
|
|
TIM8->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
|
|
TIM8->EGR = 1 ; // Restart
|
|
|
|
// TIM8->SR &= ~TIM_SR_UIF ; // Clear flag
|
|
// TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
|
TIM8->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
|
|
TIM8->DCR = 13 ; // DMA to CC1
|
|
|
|
// TIM8->CR1 = TIM_CR1_OPM ; // Just run once
|
|
// Enable the DMA channel here, DMA2 stream 2, channel 7
|
|
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
|
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
|
|
DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
|
|
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
|
|
DMA2_Stream2->PAR = CONVERT_PTR(&TIM8->DMAR);
|
|
DMA2_Stream2->M0AR = CONVERT_PTR(&dsm2Stream[1]);
|
|
// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
|
|
// DMA2_Stream2->NDTR = 100 ;
|
|
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
|
|
|
|
TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
|
|
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
|
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
TIM8->CR1 |= TIM_CR1_CEN ;
|
|
NVIC_EnableIRQ(TIM8_CC_IRQn) ;
|
|
NVIC_SetPriority(TIM8_CC_IRQn, 7);
|
|
}
|
|
|
|
static void disable_pa7_dsm2()
|
|
{
|
|
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
|
NVIC_DisableIRQ(TIM8_CC_IRQn) ;
|
|
TIM8->DIER &= ~TIM_DIER_CC2IE ;
|
|
TIM8->CR1 &= ~TIM_CR1_CEN ;
|
|
EXTERNAL_RF_OFF();
|
|
}
|
|
#endif
|
|
|
|
// PPM output
|
|
// Timer 1, channel 1 on PA8 for prototype
|
|
// Pin is AF1 function for timer 1
|
|
static void init_pa7_ppm()
|
|
{
|
|
EXTERNAL_RF_ON();
|
|
// Timer1
|
|
setupPulsesPPM(EXTERNAL_MODULE) ;
|
|
ppmStreamPtr[EXTERNAL_MODULE] = ppmStream[EXTERNAL_MODULE];
|
|
|
|
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
|
|
#if defined(REV3)
|
|
configure_pins( 0x0100, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ;
|
|
#else
|
|
configure_pins( PIN_EXTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_3 | PIN_OS25 | PIN_PUSHPULL ) ;
|
|
#endif
|
|
RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock
|
|
|
|
TIM8->CR1 &= ~TIM_CR1_CEN ;
|
|
|
|
TIM8->ARR = *ppmStreamPtr[EXTERNAL_MODULE]++ ;
|
|
TIM8->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
|
|
#if defined(REV3)
|
|
TIM8->CCER = TIM_CCER_CC1E ;
|
|
#else
|
|
TIM8->CCER = TIM_CCER_CC1NE;
|
|
if(!g_model.moduleData[EXTERNAL_MODULE].ppmPulsePol)
|
|
TIM8->CCER |= TIM_CCER_CC1NP;
|
|
#endif
|
|
TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE ; // PWM mode 1
|
|
TIM8->CCR1 = (g_model.moduleData[EXTERNAL_MODULE].ppmDelay*50+300)*2;
|
|
TIM8->BDTR = TIM_BDTR_MOE ;
|
|
TIM8->EGR = 1 ;
|
|
TIM8->DIER = TIM_DIER_UDE ;
|
|
|
|
TIM8->SR &= ~TIM_SR_UIF ; // Clear flag
|
|
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
|
TIM8->DIER |= TIM_DIER_CC2IE ;
|
|
TIM8->DIER |= TIM_DIER_UIE ;
|
|
|
|
TIM8->CR1 = TIM_CR1_CEN ;
|
|
NVIC_EnableIRQ(TIM8_CC_IRQn) ;
|
|
NVIC_SetPriority(TIM8_CC_IRQn, 7);
|
|
NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn) ;
|
|
NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 7);
|
|
}
|
|
|
|
static void disable_pa7_ppm()
|
|
{
|
|
NVIC_DisableIRQ(TIM8_CC_IRQn) ;
|
|
NVIC_DisableIRQ(TIM8_UP_TIM13_IRQn) ;
|
|
TIM8->DIER &= ~TIM_DIER_CC2IE & ~TIM_DIER_UIE ;
|
|
TIM8->CR1 &= ~TIM_CR1_CEN ;
|
|
EXTERNAL_RF_OFF();
|
|
}
|
|
|
|
extern "C" void TIM8_CC_IRQHandler()
|
|
{
|
|
TIM8->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
|
|
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
|
|
|
setupPulses(EXTERNAL_MODULE) ;
|
|
|
|
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) {
|
|
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
|
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
|
|
DMA2_Stream2->M0AR = CONVERT_PTR(&pxxStream[EXTERNAL_MODULE][1]);
|
|
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
|
|
TIM8->CCR1 = pxxStream[EXTERNAL_MODULE][0];
|
|
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
}
|
|
#if defined(DSM2)
|
|
else if (s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) {
|
|
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
|
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
|
|
DMA2_Stream2->M0AR = CONVERT_PTR(&dsm2Stream[1]);
|
|
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
|
|
TIM8->CCR1 = dsm2Stream[0];
|
|
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
}
|
|
#endif
|
|
else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
|
|
ppmStreamPtr[EXTERNAL_MODULE] = ppmStream[EXTERNAL_MODULE];
|
|
TIM8->DIER |= TIM_DIER_UDE ;
|
|
TIM8->SR &= ~TIM_SR_UIF ; // Clear this flag
|
|
TIM8->DIER |= TIM_DIER_UIE ; // Enable this interrupt
|
|
}
|
|
else {
|
|
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
}
|
|
}
|
|
|
|
extern "C" void TIM8_UP_TIM13_IRQHandler()
|
|
{
|
|
TIM8->SR &= ~TIM_SR_UIF ; // Clear flag
|
|
|
|
TIM8->ARR = *ppmStreamPtr[EXTERNAL_MODULE]++ ;
|
|
if (*ppmStreamPtr[EXTERNAL_MODULE] == 0) {
|
|
TIM8->SR &= ~TIM_SR_CC2IF ; // Clear this flag
|
|
TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
|
}
|
|
}
|
|
|