be496b66b6
Co-authored-by: philmoz <phil.a.mitchell@gmail.com> Co-authored-by: 3djc <3djc@gh.com> Co-authored-by: Peter Feerick <5500713+pfeerick@users.noreply.github.com>
116 lines
3.5 KiB
C
116 lines
3.5 KiB
C
/*
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* Copyright (C) EdgeTX
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*
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* Based on code named
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* opentx - https://github.com/opentx/opentx
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* th9x - http://code.google.com/p/th9x
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* er9x - http://code.google.com/p/er9x
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* gruvin9x - http://code.google.com/p/gruvin9x
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*
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* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "stm32h7xx_ll_pwr.h"
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#include "stm32h7xx_ll_rcc.h"
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#include "stm32h7xx_ll_system.h"
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#include "stm32h7xx_ll_bus.h"
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#define BOOTSTRAP __attribute__((section(".bootstrap")))
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BOOTSTRAP void SystemClock_Config(void)
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{
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/* Power Configuration */
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LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
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while (LL_PWR_IsActiveFlag_VOS() == 0){
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}
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/* Enable HSE oscillator */
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LL_RCC_HSE_Enable();
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while (LL_RCC_HSE_IsReady() != 1) {
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}
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/* Set FLASH latency */
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LL_FLASH_SetLatency(LL_FLASH_LATENCY_5);
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/* Main PLL configuration and activation */
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LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
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LL_RCC_PLL1P_Enable();
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LL_RCC_PLL1Q_Enable();
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LL_RCC_PLL1R_Enable();
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LL_RCC_PLL1FRACN_Disable();
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LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4);
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LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
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LL_RCC_PLL1_SetM(3);
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LL_RCC_PLL1_SetN(60);
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LL_RCC_PLL1_SetP(2);
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LL_RCC_PLL1_SetQ(20);
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LL_RCC_PLL1_SetR(2);
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LL_RCC_PLL1_Enable();
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while (LL_RCC_PLL1_IsReady() != 1) {
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}
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/* Set Sys & AHB & APB1 & APB2 & APB4 prescaler */
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LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1);
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LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
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LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
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LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
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LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_2);
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/* Set PLL1 as System Clock Source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) {
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}
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/* Config & activate PLL2 */
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LL_RCC_PLL2P_Enable();
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LL_RCC_PLL2FRACN_Disable();
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LL_RCC_PLL2_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4);
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LL_RCC_PLL2_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
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LL_RCC_PLL2_SetM(24);
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LL_RCC_PLL2_SetN(96);
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LL_RCC_PLL2_SetP(17); // 11.294 MHz
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LL_RCC_PLL2_Enable();
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while (LL_RCC_PLL2_IsReady() != 1) {
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}
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/* Config & activate PLL3 */
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LL_RCC_PLL3P_Enable();
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LL_RCC_PLL3Q_Enable();
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LL_RCC_PLL3R_Enable();
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LL_RCC_PLL3FRACN_Disable();
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LL_RCC_PLL3_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4);
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LL_RCC_PLL3_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
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LL_RCC_PLL3_SetM(1);
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LL_RCC_PLL3_SetN(4);
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LL_RCC_PLL3_SetP(2);
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LL_RCC_PLL3_SetQ(2);
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#if defined(RADIO_TX16SMK3)
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LL_RCC_PLL3_SetR(8); // 24 MHz
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#else
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LL_RCC_PLL3_SetR(18);
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#endif
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LL_RCC_PLL3_Enable();
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while (LL_RCC_PLL3_IsReady() != 1) {
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}
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/* Enable SRAM1, SRAM2 & SRAM3 */
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_D2SRAM1 |
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LL_AHB2_GRP1_PERIPH_D2SRAM2 |
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LL_AHB2_GRP1_PERIPH_D2SRAM3);
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/* Set periph clock sources */
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LL_RCC_SetSPIClockSource(LL_RCC_SPI123_CLKSOURCE_PLL1Q);
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LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL1Q);
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LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSOURCE_CLKP);
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}
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