gruvin@gmail.com
c71ee46e5f
$ make ... PORTH_TIMING=YES See code comments for details. This is used to analyse real-world timing of mixer interrupt, setupPulses and PPM or DSM=SERIAL or DSM2=PPM data output streams. NOTE: Not compatible to SOUND=YES (SOMO14)
303 lines
8.4 KiB
C++
303 lines
8.4 KiB
C++
/*
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* Authors (alphabetical order)
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* - Bertrand Songis <bsongis@gmail.com>
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* - Bryan J. Rentoul (Gruvin) <gruvin@gmail.com>
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* - Cameron Weeks <th9xer@gmail.com>
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* - Erez Raviv
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* - Jean-Pierre Parisy
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* - Karl Szmutny <shadow@privy.de>
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* - Michael Blandford
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* - Michal Hlavinka
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* - Pat Mackenzie
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* - Philip Moss
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* - Rob Thomson
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* - Romolo Manfredini <romolo.manfredini@gmail.com>
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* - Thomas Husterer
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*
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* open9x is based on code named
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* gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/,
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* er9x by Erez Raviv: http://code.google.com/p/er9x/,
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* and the original (and ongoing) project by
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* Thomas Husterer, th9x: http://code.google.com/p/th9x/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "open9x.h"
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#ifndef SIMU
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inline void board_init()
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{
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// Set up I/O port data directions and initial states
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DDRA = 0xff; PORTA = 0x00; // LCD data
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DDRB = 0b11000111; PORTB = 0b00111111; // 7:SPKR, 6:PPM_OUT, 5:TrainSW, 4:IDL2_SW, SDCARD[3:MISO 2:MOSI 1:SCK 0:CS]
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DDRC = 0x3f; PORTC = 0xc0; // 7:AilDR, 6:EleDR, LCD[5,4,3,2,1], 0:BackLight
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DDRD = 0b11000000; PORTD = 0b11111100; // 7:VIB, 6:LED BL, 5:RENC2_PUSH, 4:RENC1_PUSH, 3:RENC2_B, 2:RENC2_A, 1:I2C_SDA, 0:I2C_SCL
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DDRE = 0b00001010; PORTE = 0b11110100; // 7:PPM_IN, 6: RENC1_B, 5:RENC1_A, 4:USB_DNEG, 3:BUZZER, 2:USB_DPOS, 1:TELEM_TX, 0:TELEM_RX(pull-up off)
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DDRF = 0x00; PORTF = 0x00; // 7-4:JTAG, 3:ADC_REF_1.2V input, 2-0:ADC_SPARE_2-0
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DDRG = 0b00010000; PORTG = 0xff; // 7-6:N/A, 5:GearSW, 4: Sim_Ctrl[out], 3:IDL1_Sw, 2:TCut_Sw, 1:RF_Power[in], 0: RudDr_Sw
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#ifdef PORTH_TIMING
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DDRH = 0b11110000; PORTH = 0b11011111; // PORTH:7-6 enabled for timing analysis output ... see below ...
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#else
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DDRH = 0b10110000; PORTH = 0b11011111; // [7:0 DSM/PPM TX-caddy control. 1=PPM, 0=DSM ]
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// [6:SOMO14D-BUSY 5:SOMO14D-DATA 4:SOMO14D-CLK] [2:VIB_OPTION -- setting to input for now]
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// [1:TxD 0:RxD Spare serial port]
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#endif
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DDRJ = 0x00; PORTJ = 0xff; // 7-0:Trim switch inputs
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DDRK = 0x00; PORTK = 0x00; // anain. No pull-ups!
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#ifdef REV0
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DDRL = 0x80; PORTL = 0x7f; // 7: Hold_PWR_On (1=On, default Off), 6:Jack_Presence_TTL, 5-0: User Button inputs
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#else
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DDRL = 0x80; PORTL = 0xff; // 7: Hold_PWR_On (1=On, default Off), 6:Jack_Presence_TTL, 5-0: User Button inputs
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#endif
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ADMUX=ADC_VREF_TYPE;
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ADCSRA=0x85; // ADC enabled, pre-scaler division=32 (no interrupt, no auto-triggering)
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ADCSRB=(1<<MUX5);
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/**** Set up timer/counter 0 ****/
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/** Move old 64A Timer0 functions to Timer2 and use WGM on OC0(A) (PB7) for spkear tone output **/
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// TCNT0 10ms = 16MHz/1024/156(.25) periodic timer (100ms interval)
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// cycles at 9.984ms but includes 1:4 duty cycle correction to /157 to average at 10.0ms
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TCCR2B = (0b111 << CS20); // Norm mode, clk/1024 (differs from ATmega64 chip)
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OCR2A = 156;
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TIMSK2 |= (1<<OCIE2A) | (1<<TOIE2); // Enable Output-Compare and Overflow interrrupts
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// Set up Phase correct Waveform Gen. mode, at clk/64 = 250,000 counts/second
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// (Higher speed allows for finer control of frquencies in the audio range.)
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// Used for audio tone generation
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TCCR0B = (1<<WGM02) | (0b011 << CS00);
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TCCR0A = (0b01<<WGM00);
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/***************************************************/
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/* Rotary encoder interrupt set-up (V4 board only) */
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// All external interrupts initialise to disabled. But maybe not after
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// a WDT or BOD event? So to be safe ...
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EIMSK = 0; // disable ALL external interrupts.
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// encoder 1
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EICRB = (1<<ISC60) | (1<<ISC50); // 01 = interrupt on any edge
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EIFR = (3<<INTF5); // clear the int. flag in case it got set when changing modes
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// encoder 2
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EICRA = (1<<ISC30) | (1<<ISC20); // do the same for encoder 1
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EIFR = (3<<INTF2);
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#if defined(EXTRA_ROTARY_ENCODERS)
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EIMSK = (3<<INT5); // enable the ONE rot. enc. ext. int. pairs.
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#else
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EIMSK = (3<<INT5) | (3<<INT2); // enable the two rot. enc. ext. int. pairs.
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#endif
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/***************************************************/
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/*
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* SOMO set-up (V4 board only)
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*/
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OCR4A = 0x7d;
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TCCR4B = (1 << WGM42) | (3<<CS40); // CTC OCR1A, 16MHz / 64 (4us ticks)
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/* Mixer interrupt */
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OCR5A = 0x7d * 40; /* 20ms */
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TCCR5B = (1 << WGM52) | (3<<CS50); // CTC OCR1A, 16MHz / 64 (4us ticks)
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TIMSK5 |= (1<<OCIE5A);
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#if defined(EXTRA_ROTARY_ENCODERS)
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//configure uart1 here
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DDRD &= ~(1 << 2);
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PORTD &= ~(1 << 2);
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#define EXTRA_ROTARY_ENCODERS_USART_BAUD 9600UL
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UBRR1 = F_CPU/(16*EXTRA_ROTARY_ENCODERS_USART_BAUD)-1;
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//9 bit mode
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UCSR1C = (1<<USBS1)|(3<<UCSZ10);
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UCSR1B = (1<<RXEN1)|(0<<TXEN1)|(1<<UCSZ12);
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UCSR1B |= 1 << RXCIE1; //enable interrupt on rx
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#endif //EXTRA_ROTARY_ENCODERS
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}
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#if defined(EXTRA_ROTARY_ENCODERS)
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uint8_t vpotToChange = 0;
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uint8_t vpot_mod_state = 0;
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ISR(USART1_RX_vect)
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{
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//receive data from extension board
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//bit 9 = 1 mean encoder number, following byte with bit 9 = 0 is increment value
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/* Get status and 9th bit, then data */
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/* from buffer */
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uint16_t resh = UCSR1B;
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uint16_t resl = UDR1;
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uint16_t res = 0;
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/* Filter the 9th bit, then return */
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resh = (resh >> 1) & 0x01;
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res = ((resh << 8) | resl);
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if((res == 0x180) | (res == 0x1C0)){ //button REb filter
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keys[BTN_REa].input((res & 0x1C0) == 0x1C0, BTN_REa);
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} else if((res & 0x100) == 0x100){ //rotary filter
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vpotToChange = res & 0xEF;
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vpot_mod_state = 1;
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}
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else {
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if(vpot_mod_state & (vpotToChange < NUM_ROTARY_ENCODERS))
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{
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int8_t vpot_inc = res & 0xFF;
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if(vpot_inc){
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incRotaryEncoder(vpotToChange, vpot_inc);
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}
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vpot_mod_state = 0;
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}
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}
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}
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#endif //EXTRA_ROTARY_ENCODERS
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#endif
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uint8_t check_soft_power()
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{
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#if !defined(SIMU) && !defined(REV0)
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if ((PING & 0b00000010) && (~PINL & 0b01000000))
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return e_power_off;
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#endif
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return e_power_on;
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}
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void soft_power_off()
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{
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#ifndef REV0
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PORTL = 0x7f;
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#endif
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}
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#ifndef SIMU
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FORCEINLINE
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#endif
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uint8_t keyDown()
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{
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return (~PINL) & 0x3F;
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}
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bool keyState(EnumKeys enuk)
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{
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uint8_t result = 0 ;
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if (enuk < (int)DIM(keys))
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return keys[enuk].state() ? 1 : 0;
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switch(enuk){
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case SW_ElevDR:
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result = PINC & (1<<INP_C_ElevDR);
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break;
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case SW_AileDR:
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result = PINC & (1<<INP_C_AileDR);
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break;
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case SW_RuddDR:
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result = PING & (1<<INP_G_RuddDR);
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break;
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// INP_G_ID1 INP_B_ID2
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// id0 0 1
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// id1 1 1
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// id2 1 0
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case SW_ID0:
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result = !(PING & (1<<INP_G_ID1));
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break;
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case SW_ID1:
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result = (PING & (1<<INP_G_ID1))&& (PINB & (1<<INP_B_ID2));
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break;
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case SW_ID2:
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result = !(PINB & (1<<INP_B_ID2));
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break;
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case SW_Gear:
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result = PING & (1<<INP_G_Gear);
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break;
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case SW_ThrCt:
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result = PING & (1<<INP_G_ThrCt);
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break;
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case SW_Trainer:
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result = PINB & (1<<INP_B_Trainer);
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break;
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default:
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break;
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}
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return result;
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}
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#ifndef SIMU
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FORCEINLINE
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#endif
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void readKeysAndTrims()
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{
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/* Original keys were connected to PORTB as follows:
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Bit Key
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7 other use
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6 LEFT
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5 RIGHT
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4 UP
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3 DOWN
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2 EXIT
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1 MENU
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0 other use
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*/
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uint8_t enuk = KEY_MENU;
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#if !defined(EXTRA_ROTARY_ENCODERS)
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keys[BTN_REa].input(~PIND & 0x20, BTN_REa);
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#endif //!EXTRA_ROTARY_ENCODERS
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keys[BTN_REb].input(~PIND & 0x10, BTN_REb);
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uint8_t tin = ~PINL;
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uint8_t in;
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in = (tin & 0x0f) << 3;
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in |= (tin & 0x30) >> 3;
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for(int i=1; i<7; i++)
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{
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//INP_B_KEY_MEN 1 .. INP_B_KEY_LFT 6
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keys[enuk].input(in & (1<<i),(EnumKeys)enuk);
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++enuk;
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}
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// Trim switches ...
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static const pm_uchar crossTrim[] PROGMEM ={
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1<<INP_J_TRM_LH_DWN,
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1<<INP_J_TRM_LH_UP,
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1<<INP_J_TRM_LV_DWN,
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1<<INP_J_TRM_LV_UP,
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1<<INP_J_TRM_RV_DWN,
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1<<INP_J_TRM_RV_UP,
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1<<INP_J_TRM_RH_DWN,
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1<<INP_J_TRM_RH_UP
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};
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in = ~PINJ;
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for (int i=0; i<8; i++) {
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// INP_D_TRM_RH_UP 0 .. INP_D_TRM_LH_UP 7
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keys[enuk].input(in & pgm_read_byte(crossTrim+i),(EnumKeys)enuk);
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++enuk;
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}
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}
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