205 lines
7.7 KiB
C++
205 lines
7.7 KiB
C++
/*
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* Authors (alphabetical order)
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* - Andre Bernet <bernet.andre@gmail.com>
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* - Andreas Weitl
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* - Bertrand Songis <bsongis@gmail.com>
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* - Bryan J. Rentoul (Gruvin) <gruvin@gmail.com>
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* - Cameron Weeks <th9xer@gmail.com>
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* - Erez Raviv
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* - Gabriel Birkus
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* - Jean-Pierre Parisy
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* - Karl Szmutny
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* - Michael Blandford
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* - Michal Hlavinka
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* - Pat Mackenzie
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* - Philip Moss
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* - Rob Thomson
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* - Romolo Manfredini <romolo.manfredini@gmail.com>
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* - Thomas Husterer
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*
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* opentx is based on code named
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* gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/,
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* er9x by Erez Raviv: http://code.google.com/p/er9x/,
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* and the original (and ongoing) project by
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* Thomas Husterer, th9x: http://code.google.com/p/th9x/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "../../opentx.h"
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#define PIN_ANALOG 0x0003
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#define PIN_PORTA 0x0000
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#define PIN_PORTB 0x0100
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#define PIN_PORTC 0x0200
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#define STICK_LV 3
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#define STICK_LH 2
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#define STICK_RV 0
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#define STICK_RH 1
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#define POT_L 6
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#define POT_R 8
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#define POT_XTRA 9
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#define SLIDE_L 14
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#define SLIDE_R 15
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#define BATTERY 10
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#if defined(REV9E)
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#define SLIDER_L2 8 // PIN_FLP_J3 (SLIDER3) = ANC3_IN8
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#define SLIDER_R2 7 // PIN_FLP_J4 (SLIDER4) = ADC3_IN7
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#define POT_4 6 // PIN_FLP_J5 (POT4) = ADC3_IN6
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#endif
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// Sample time should exceed 1uS
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#define SAMPTIME 2 // sample time = 28 cycles
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uint16_t Analog_values[NUMBER_ANALOG];
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#if defined(REV9E)
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const int8_t ana_direction[NUMBER_ANALOG] = {1,-1,1,-1, -1,1,-1, -1,1, 1, -1,-1,1};
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#elif defined(REVPLUS)
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const int8_t ana_direction[NUMBER_ANALOG] = {1,-1,1,-1, -1,1,-1, -1,1, 1};
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#elif defined(REV4a)
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const int8_t ana_direction[NUMBER_ANALOG] = {1,-1,1,-1, -1,-1,0, -1,1, 1};
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#else
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const int8_t ana_direction[NUMBER_ANALOG] = {1,-1,1,-1, -1,1,0, -1,1, 1};
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#endif
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#if defined(REV9E)
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#define NUMBER_ANALOG_ADC1 10
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#define NUMBER_ANALOG_ADC3 3
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// mapping from Analog_values order to enum Analogs
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const uint8_t ana_mapping[NUMBER_ANALOG] = { 0 /*STICK1*/, 1 /*STICK2*/, 2 /*STICK3*/, 3 /*STICK4*/,
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4 /*POT1*/, 5 /*POT2*/, 6 /*POT3*/, 12 /*POT4*/,
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7 /*SLIDER1*/, 8 /*SLIDER2*/, 10 /*SLIDER3*/, 11 /*SLIDER4*/,
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9 /*TX_VOLTAGE*/ };
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#else
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#define NUMBER_ANALOG_ADC1 10
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#define NUMBER_ANALOG_ADC3 0
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// mapping from Analog_values order to enum Analogs
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const uint8_t ana_mapping[NUMBER_ANALOG] = { 0 /*STICK1*/, 1 /*STICK2*/, 2 /*STICK3*/, 3 /*STICK4*/,
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4 /*POT1*/, 5 /*POT2*/, 6 /*POT3*/,
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7 /*SLIDER1*/, 8 /*SLIDER2*/,
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9 /*TX_VOLTAGE*/ };
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#endif
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void adcInit()
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{
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // Enable clock
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RCC->AHB1ENR |= RCC_AHB1Periph_GPIOADC; // Enable ports A&C clocks
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RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; // Enable DMA2 clock
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configure_pins(PIN_STK_J1 | PIN_STK_J2 | PIN_STK_J3 | PIN_STK_J4 |
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PIN_FLP_J1, PIN_ANALOG | PIN_PORTA);
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#if defined(REV9E)
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configure_pins(PIN_FLP_J2 | PIN_FLP_J6, PIN_ANALOG|PIN_PORTB);
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#elif defined(REVPLUS)
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configure_pins(PIN_FLP_J2 | PIN_FLP_J3, PIN_ANALOG|PIN_PORTB);
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#else
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configure_pins(PIN_FLP_J2, PIN_ANALOG|PIN_PORTB);
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#endif
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configure_pins(PIN_SLD_J1 | PIN_SLD_J2 | PIN_MVOLT, PIN_ANALOG | PIN_PORTC);
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ADC1->CR1 = ADC_CR1_SCAN;
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ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_DDS;
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ADC1->SQR1 = (NUMBER_ANALOG_ADC1-1) << 20 ; // bits 23:20 = number of conversions
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ADC1->SQR2 = (POT_XTRA<<0) + (SLIDE_L<<5) + (SLIDE_R<<10) + (BATTERY<<15); // conversions 7 and more
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ADC1->SQR3 = (STICK_LH<<0) + (STICK_LV<<5) + (STICK_RV<<10) + (STICK_RH<<15) + (POT_L<<20) + (POT_R<<25); // conversions 1 to 6
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ADC1->SMPR1 = SAMPTIME + (SAMPTIME<<3) + (SAMPTIME<<6) + (SAMPTIME<<9) + (SAMPTIME<<12) + (SAMPTIME<<15) + (SAMPTIME<<18) + (SAMPTIME<<21) + (SAMPTIME<<24);
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ADC1->SMPR2 = SAMPTIME + (SAMPTIME<<3) + (SAMPTIME<<6) + (SAMPTIME<<9) + (SAMPTIME<<12) + (SAMPTIME<<15) + (SAMPTIME<<18) + (SAMPTIME<<21) + (SAMPTIME<<24) + (SAMPTIME<<27) ;
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ADC->CCR = 0 ; //ADC_CCR_ADCPRE_0 ; // Clock div 2
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DMA2_Stream0->CR = DMA_SxCR_PL | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC;
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DMA2_Stream0->PAR = CONVERT_PTR_UINT(&ADC1->DR);
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DMA2_Stream0->M0AR = CONVERT_PTR_UINT(Analog_values);
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DMA2_Stream0->NDTR = NUMBER_ANALOG_ADC1;
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DMA2_Stream0->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
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#if defined(REV9E)
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RCC->APB2ENR |= RCC_APB2ENR_ADC3EN ; // Enable clock
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configure_pins( PIN_FLP_J3 | PIN_FLP_J4 | PIN_FLP_J5, PIN_ANALOG | PIN_PORTF ) ;
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ADC3->CR1 = ADC_CR1_SCAN ;
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ADC3->CR2 = ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_DDS ;
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ADC3->SQR1 = (NUMBER_ANALOG_ADC3-1) << 20 ; // NUMBER_ANALOG Channels
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ADC3->SQR2 = 0;
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ADC3->SQR3 = (SLIDER_L2<<0) + (SLIDER_R2<<5) + (POT_4<<10) ; // conversions 1 to 3
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ADC3->SMPR1 = SAMPTIME + (SAMPTIME<<3) + (SAMPTIME<<6);
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ADC3->SMPR2 = 0;
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// Enable the DMA channel here, DMA2 stream 1, channel 2
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DMA2_Stream1->CR = DMA_SxCR_PL | DMA_SxCR_CHSEL_1 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC;
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DMA2_Stream1->PAR = CONVERT_PTR_UINT(&ADC3->DR);
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DMA2_Stream1->M0AR = CONVERT_PTR_UINT(Analog_values + NUMBER_ANALOG_ADC1);
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DMA2_Stream1->NDTR = NUMBER_ANALOG_ADC3;
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DMA2_Stream1->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
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#endif // #if defined(REV9E)
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}
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void adcRead()
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{
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DMA2_Stream0->CR &= ~DMA_SxCR_EN ; // Disable DMA
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ADC1->SR &= ~(uint32_t) ( ADC_SR_EOC | ADC_SR_STRT | ADC_SR_OVR ) ;
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DMA2->LIFCR = DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 |DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0 ; // Write ones to clear bits
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DMA2_Stream0->CR |= DMA_SxCR_EN ; // Enable DMA
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ADC1->CR2 |= (uint32_t)ADC_CR2_SWSTART ;
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#if defined(REV9E)
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DMA2_Stream1->CR &= ~DMA_SxCR_EN ; // Disable DMA
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ADC3->SR &= ~(uint32_t) ( ADC_SR_EOC | ADC_SR_STRT | ADC_SR_OVR ) ;
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DMA2->LIFCR = DMA_LIFCR_CTCIF1 | DMA_LIFCR_CHTIF1 |DMA_LIFCR_CTEIF1 | DMA_LIFCR_CDMEIF1 | DMA_LIFCR_CFEIF1 ; // Write ones to clear bits
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DMA2_Stream1->CR |= DMA_SxCR_EN ; // Enable DMA
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ADC3->CR2 |= (uint32_t)ADC_CR2_SWSTART ;
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#endif // #if defined(REV9E)
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#if defined(REV9E)
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for (unsigned int i=0; i<10000; i++) {
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if ((DMA2->LISR & DMA_LISR_TCIF0) && (DMA2->LISR & DMA_LISR_TCIF1)) {
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break;
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}
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}
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DMA2_Stream0->CR &= ~DMA_SxCR_EN ; // Disable DMA
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DMA2_Stream1->CR &= ~DMA_SxCR_EN ; // Disable DMA
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#else
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for (unsigned int i=0; i<10000; i++) {
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if (DMA2->LISR & DMA_LISR_TCIF0) {
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break;
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}
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}
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DMA2_Stream0->CR &= ~DMA_SxCR_EN ; // Disable DMA
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#endif
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// adc direction correct
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for (uint32_t i=0; i<NUMBER_ANALOG; i++) {
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if (ana_direction[i] < 0) {
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Analog_values[i] = 4096-Analog_values[i];
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}
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#if !defined(REVPLUS)
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else if (ana_direction[i] == 0) {
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Analog_values[i] = 0;
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}
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#endif
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}
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}
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// TODO
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void adcStop()
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{
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}
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uint16_t getAnalogValue(uint32_t value)
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{
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return Analog_values[ana_mapping[value]];
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}
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