Arne SchwabeandBertrand Songis
ad8cd2546e
* Ignore deprecated register warning for the the STM include files Ignore the warning with the use of #pragma which is not elegant but otherwise we would have to change the vendor files * Remove usage of register in C/C++ files. Modern compilers ignore it anyway and C++11 actually deprecates it. Removing also removes a number of clang warnings about this
254 lines
8.4 KiB
C
254 lines
8.4 KiB
C
/*
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* Copyright (C) OpenTX
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*
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* Based on code named
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* th9x - http://code.google.com/p/th9x
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* er9x - http://code.google.com/p/er9x
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* gruvin9x - http://code.google.com/p/gruvin9x
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*
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* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/**
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* \file
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*
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* \par Purpose
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*
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* Provides the low-level initialization function that gets called on chip startup.
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*/
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/*----------------------------------------------------------------------------
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* Headers
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*----------------------------------------------------------------------------*/
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#include "board_lowlevel.h"
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/*----------------------------------------------------------------------------
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* Local definitions
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*----------------------------------------------------------------------------*/
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/** Define clock timeout */
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#define CLOCK_TIMEOUT 5000
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/** Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.*/
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#define PMC_PLLA_SET_BIT29 (0x1 << 29)
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/** Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.*/
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#define PMC_PLLA_COUNT (0xBF << 8)
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/** The PLLA Clock frequency is the PLLA input frequency multiplied by 8*/
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#define PMC_PLLA_MULTIPIER (0x07 << 16)
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/** PLLA Divider is bypassed.*/
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#define PMC_PLLA_DIV (0x01)
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void revert_osc( void ) ;
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/*----------------------------------------------------------------------------
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* Local functions
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* returns master_frequency
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*----------------------------------------------------------------------------*/
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// *** WARNING, this is called BEFORE .data and .bss have been initialised
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// *** GLOBAL variables are NOT useable
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static uint32_t BOARD_ConfigurePmc(void)
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{
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/* TODO: configurate PLL in new way */
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//#if 0
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// uint32_t timeout = 0;
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// /** 1: Checking the Main Oscillator Frequency (Optional) and Initialize main oscillator */
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// /** 1.1 Initialize main oscillator */
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// // TODO:
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// /** 2. Setting PLL and Divider*/
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// /** 2.1 Initialize PLLA*/
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// PMC->CKGR_PLLAR = ( PMC_PLLA_SET_BIT29 |
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// PMC_PLLA_MULTIPIER |
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// PMC_PLLA_COUNT |
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// PMC_PLLA_DIV
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// );
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// timeout = 0;
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// /** 2.2 Wait for the LOCKA bit to be set by polling the status register.*/
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// while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT));
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// /** 2.3 wait for the MCKRDY bit to be set by polling the status register*/
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// timeout = 0;
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// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
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// /** 3. Selection of Master Clock and Processor Clock*/
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// PMC->PMC_MCKR |= PMC_MCKR_PRES_CLK_2;
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// /** 3.1 wait for the MCKRDY bit to be set by polling the status register*/
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// timeout = 0;
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// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
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// /** 3.2 PLLA Clock is selected */
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// PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK;
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// /** 3.3 wait for the MCKRDY bit to be set by polling the status register*/
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// timeout = 0;
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// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
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//#endif
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#if 1 // old as sam3u
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#define AT91C_CKGR_MUL_SHIFT 16
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//#define AT91C_CKGR_OUT_SHIFT 14
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#define AT91C_CKGR_PLLCOUNT_SHIFT 8
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#define AT91C_CKGR_DIV_SHIFT 0
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// Settings at 72MHz/2 = 36MHz
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#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST & (0x8 << 8))
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#define BOARD_PLLR ((1 << 29) | (0x5 << AT91C_CKGR_MUL_SHIFT) \
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| (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x2 << AT91C_CKGR_DIV_SHIFT))
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#define BOARD_MCKR (PMC_MCKR_CSS_PLLA_CLK)
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// Define clock timeout
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#undef CLOCK_TIMEOUT
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#define CLOCK_TIMEOUT 0xFFFFFFFF
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uint32_t timeout = 0 ;
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Pmc *pmcptr ;
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pmcptr = PMC ;
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/* Enable NRST reset
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************************************/
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//AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN;
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/* Select external slow clock
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****************************/
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// if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST) {
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// SUPC->SUPC_CR = SUPC_CR_XTALSEL_CRYSTAL_SEL | ((uint32_t)0xA5 << 24);
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// timeout = 0;
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// while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) );
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// }
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/* Initialize main oscillator
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****************************/
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if(!(pmcptr->CKGR_MOR & CKGR_MOR_MOSCSEL))
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{
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pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
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timeout = 0;
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while (!(pmcptr->PMC_SR & PMC_SR_MOSCXTS) && (++timeout < CLOCK_TIMEOUT));
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}
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/* Switch to 3-20MHz Xtal oscillator */
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pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
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timeout = 0;
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while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT));
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pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK;
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timeout = 0;
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while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT));
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/* Initialize PLLA 72 MHz */
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pmcptr->CKGR_PLLAR = BOARD_PLLR;
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timeout = 0;
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while (!(pmcptr->PMC_SR & PMC_SR_LOCKA) && (++timeout < CLOCK_TIMEOUT));
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/* Initialize UTMI for USB usage, can be disabled if not using USB for the sake of saving power*/
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//AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN;
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//timeout = 0;
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//while (!(PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT));
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/* Switch to fast clock
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**********************/
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// PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK;
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// timeout = 0;
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// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
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// Switch to PLLA as main clock 36MHz
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PMC->PMC_MCKR = BOARD_MCKR;
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timeout = 0;
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
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#endif
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return 36000000L; // Master_frequency
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}
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void revert_osc()
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{
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uint32_t timeout = 0;
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Pmc *pmcptr;
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pmcptr = PMC;
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// Switch back to the internal oscillator
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pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
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timeout = 0;
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while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT));
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pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_SLOW_CLK;
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timeout = 0;
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while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT));
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pmcptr->CKGR_PLLAR = 1 << 29; // Stop PLLA
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}
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#if defined(BOOT)
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// extern void sam_bootx( void ) ;
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// extern void dispUSB( void ) ;
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// extern uint32_t init
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// ReadTrims( void ) ;
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// extern void run_application( void ) ;
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static void lowLevelUsbCheck( void )
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{
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PMC->PMC_PCER0 = (1<<ID_PIOC) ; // Enable clock to PIOC
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PIOC->PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect)
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uint32_t i ;
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for ( i = 0 ; i < 50 ; i += 1 ) {
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__asm("nop") ;
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}
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for ( i = 0 ; i < 10 ; i += 1 ) {
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if ( PIOC->PIO_PDSR & 0x02000000 ) {
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PMC->PMC_PCDR0 = (1<<ID_PIOC) ; // Disable clock to PIOC
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dispUSB() ;
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sam_bootx() ;
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}
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}
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uint32_t x = initReadTrims() ;
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if ((x & 0x42) != 0x42) {
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run_application();
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}
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}
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#endif
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/*----------------------------------------------------------------------------
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* Exported functions
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*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/**
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* \brief Performs the low-level initialization of the chip. This includes EFC,
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* master clock and watchdog configuration.
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*/
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/*----------------------------------------------------------------------------*/
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uint32_t SystemInit (void)
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{
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#if defined(BOOT)
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lowLevelUsbCheck() ;
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#endif
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// Set 2 cycle (1 WS) for Embedded Flash Access
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// Max clock is 38 MHz (1.8V VVDCORE)
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EFC->EEFC_FMR = (1 << 8) ;
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// Configure PMC
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return BOARD_ConfigurePmc();
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}
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