refactor(h7): generic system init (#6172)
This commit is contained in:
Raphael Coeffic
@@ -566,6 +566,10 @@ link_libraries(firmware -lstdc++)
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add_dependencies(firmware ${RADIO_DEPENDENCIES})
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set_target_properties(firmware PROPERTIES EXCLUDE_FROM_ALL TRUE)
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if(ARCH STREQUAL ARM)
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target_link_libraries(firmware PRIVATE cmsis)
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endif()
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target_compile_definitions(board PUBLIC FREE_RTOS)
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target_compile_definitions(board_lib PUBLIC FREE_RTOS)
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target_compile_definitions(firmware PUBLIC FREE_RTOS)
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@@ -599,17 +603,15 @@ if (DEFINED TARGET_FLASH_SIZE)
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)
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endif()
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if (DEFINED TARGET_SDRAM_START)
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# message("TARGET_SDRAM_START = ${TARGET_SDRAM_START}")
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if (DEFINED TARGET_EXTRAM_START)
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target_link_options(firmware PRIVATE
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-Wl,--defsym=__sdram_start=${TARGET_SDRAM_START}
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-Wl,--defsym=__EXTRAM_START__=${TARGET_EXTRAM_START}
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)
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endif()
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if (DEFINED TARGET_SDRAM_SIZE)
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# message("TARGET_SDRAM_SIZE = ${TARGET_SDRAM_SIZE}")
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if (DEFINED TARGET_EXTRAM_SIZE)
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target_link_options(firmware PRIVATE
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-Wl,--defsym=__sdram_size=${TARGET_SDRAM_SIZE}
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-Wl,--defsym=__EXTRAM_SIZE__=${TARGET_EXTRAM_SIZE}
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)
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endif()
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@@ -623,7 +625,7 @@ endif()
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if(ACCESS_DENIED)
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add_subdirectory(thirdparty/AccessDenied)
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include_directories(thirdparty/AccessDenied)
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target_link_libraries(firmware AccessDenied)
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target_link_libraries(firmware PRIVATE AccessDenied)
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endif()
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if(FIRMWARE_STRIP_BOOTLOADER)
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@@ -18,6 +18,7 @@ SECTIONS
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} > REGION_ISR_VECT AT> REGION_TEXT_STORAGE
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_isr_load = LOADADDR(.isr_vector);
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g_pfnVectors = _isr_load;
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/* The program code and other data goes into FLASH */
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.text :
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@@ -8,6 +8,12 @@
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*(.eh_frame)
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*(.data.__global_locale)
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/* Init hooks table */
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. = ALIGN(4);
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__init_hook_array_start = .;
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KEEP (*(.init_hook))
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__init_hook_array_end = .;
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/*
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C++ Runtime: initializers for static variables.
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C Runtime: designated constructors
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@@ -12,11 +12,11 @@ BOOTLOADER_SIZE = 0x20000;
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MIN_HEAP_SIZE = 0;
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/* SDRAM definitions */
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SDRAM_START = DEFINED(__sdram_start) ? __sdram_start : 0xD0000000;
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SDRAM_SIZE = DEFINED(__sdram_size) ? __sdram_size : 8192K;
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EXTRAM_START = DEFINED(__EXTRAM_START__) ? __EXTRAM_START__ : 0xD0000000;
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EXTRAM_SIZE = DEFINED(__EXTRAM_SIZE__) ? __EXTRAM_SIZE__ : 8192K;
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/* Highest heap address */
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HEAP_ADDRESS = SDRAM_START + SDRAM_SIZE;
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HEAP_ADDRESS = EXTRAM_START + EXTRAM_SIZE;
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/* Specify the memory areas */
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MEMORY
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@@ -24,7 +24,7 @@ MEMORY
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K
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CCM (xrw) : ORIGIN = 0x10000000, LENGTH = 64K
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SDRAM(xrw) : ORIGIN = SDRAM_START, LENGTH = SDRAM_SIZE
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SDRAM(xrw) : ORIGIN = EXTRAM_START, LENGTH = EXTRAM_SIZE
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}
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REGION_ALIAS("REGION_BOOTLOADER", FLASH);
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@@ -1,9 +1,12 @@
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/* SDRAM definitions */
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SDRAM_START = DEFINED(__sdram_start) ? __sdram_start : 0xC0000000;
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SDRAM_SIZE = DEFINED(__sdram_size) ? __sdram_size : 8192K;
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EXTRAM_START = DEFINED(__EXTRAM_START__) ? __EXTRAM_START__ : 0xC0000000;
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EXTRAM_SIZE = DEFINED(__EXTRAM_SIZE__) ? __EXTRAM_SIZE__ : 8192K;
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NORFLASH_START = 0x90000000;
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NORFLASH_SIZE = 8M;
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/* Highest heap address */
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HEAP_ADDRESS = SDRAM_START + SDRAM_SIZE;
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HEAP_ADDRESS = EXTRAM_START + EXTRAM_SIZE;
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/* Highest address of the user mode stack */
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STACK_ADDRESS = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM) - 16; /* end of RAM */
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@@ -26,7 +29,7 @@ MEMORY
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RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
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RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
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RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
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SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_SIZE
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SDRAM (rwx) : ORIGIN = EXTRAM_START, LENGTH = EXTRAM_SIZE
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}
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REGION_ALIAS("REGION_TEXT_STORAGE", FLASH);
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@@ -46,6 +46,8 @@ _stext_iram = LOADADDR(.iram);
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_e_dram = .;
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} > RAM_D2
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_dram_addr = ADDR(.dram);
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.sdram (NOLOAD) :
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{
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. = ALIGN(4);
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@@ -1,9 +1,12 @@
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/* SDRAM definitions */
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SDRAM_START = DEFINED(__sdram_start) ? __sdram_start : 0xC0000000;
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SDRAM_SIZE = DEFINED(__sdram_size) ? __sdram_size : 8192K;
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EXTRAM_START = DEFINED(__EXTRAM_START__) ? __EXTRAM_START__ : 0xC0000000;
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EXTRAM_SIZE = DEFINED(__EXTRAM_SIZE__) ? __EXTRAM_SIZE__ : 8192K;
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NORFLASH_START = 0x90000000;
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NORFLASH_SIZE = 8M;
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/* Highest heap address */
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HEAP_ADDRESS = SDRAM_START + SDRAM_SIZE;
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HEAP_ADDRESS = EXTRAM_START + EXTRAM_SIZE;
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/* Highest address of the user mode stack */
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STACK_ADDRESS = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM); /* end of RAM */
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@@ -26,7 +29,7 @@ MEMORY
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RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
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RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
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RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
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SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_SIZE
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SDRAM (rwx) : ORIGIN = EXTRAM_START, LENGTH = EXTRAM_SIZE
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NORFLASH (rx) : ORIGIN = 0x90000000, LENGTH = 8M
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}
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@@ -1,12 +1,12 @@
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/* PSRAM definitions */
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PSRAM_START = DEFINED(__PSRAM_START__) ? __PSRAM_START__ : 0x90000000;
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PSRAM_SIZE = DEFINED(__PSRAM_SIZE__) ? __PSRAM_SIZE__ : 32678K;
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EXTRAM_START = DEFINED(__EXTRAM_START__) ? __EXTRAM_START__ : 0x90000000;
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EXTRAM_SIZE = DEFINED(__EXTRAM_SIZE__) ? __EXTRAM_SIZE__ : 32678K;
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NORFLASH_START = 0x70000000;
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NORFLASH_SIZE = 128M;
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/* Highest heap address */
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HEAP_ADDRESS = PSRAM_START + PSRAM_SIZE;
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HEAP_ADDRESS = EXTRAM_START + EXTRAM_SIZE;
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/* Highest address of the user mode stack */
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STACK_ADDRESS = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM) - 16; /* end of RAM */
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@@ -28,7 +28,7 @@ MEMORY
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DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
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RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 384K
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DMA (xrw) : ORIGIN = 0x24060000, LENGTH = 72K
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PSRAM (rwx) : ORIGIN = PSRAM_START, LENGTH = PSRAM_SIZE
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PSRAM (rwx) : ORIGIN = EXTRAM_START, LENGTH = EXTRAM_SIZE
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}
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REGION_ALIAS("REGION_TEXT_STORAGE", FLASH);
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@@ -1,12 +1,12 @@
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/* PSRAM definitions */
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PSRAM_START = DEFINED(__PSRAM_START__) ? __PSRAM_START__ : 0x90000000;
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PSRAM_SIZE = DEFINED(__PSRAM_SIZE__) ? __PSRAM_SIZE__ : 32678K;
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EXTRAM_START = DEFINED(__EXTRAM_START__) ? __EXTRAM_START__ : 0x90000000;
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EXTRAM_SIZE = DEFINED(__EXTRAM_SIZE__) ? __EXTRAM_SIZE__ : 32678K;
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NORFLASH_START = 0x70000000;
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NORFLASH_SIZE = 128M;
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/* Highest heap address */
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HEAP_ADDRESS = PSRAM_START + PSRAM_SIZE;
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HEAP_ADDRESS = EXTRAM_START + EXTRAM_SIZE;
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/* Highest address of the user mode stack */
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STACK_ADDRESS = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM);
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@@ -28,8 +28,8 @@ MEMORY
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DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K /* SRAM3 = 128K */
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RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 384K /* SRAM1 + SRAM2 + SRAM3 */
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DMA (xrw) : ORIGIN = 0x24060000, LENGTH = 72K /* SRAM4 */
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PSRAM (rwx) : ORIGIN = PSRAM_START, LENGTH = PSRAM_SIZE
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NORFLASH (rwx) : ORIGIN = 0x70000000, LENGTH = 128M
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PSRAM (rwx) : ORIGIN = EXTRAM_START, LENGTH = EXTRAM_SIZE
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NORFLASH (rx) : ORIGIN = NORFLASH_START, LENGTH = NORFLASH_SIZE
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}
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REGION_ALIAS("REGION_BOOTLOADER", FLASH);
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@@ -1,753 +0,0 @@
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/**
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******************************************************************************
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* @file startup_stm32h750xx.s
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* @author MCD Application Team
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* @brief STM32H750xx Devices vector table for GCC based toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m7
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr sp, =_estack /* set stack pointer */
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/* Call the clock system initialization function.*/
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bl SystemInit
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/* Copy the data segment initializers from flash to SRAM */
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ldr r0, =_sdata
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ldr r1, =_edata
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ldr r2, =_sidata
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movs r3, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r4, [r2, r3]
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str r4, [r0, r3]
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adds r3, r3, #4
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LoopCopyDataInit:
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adds r4, r0, r3
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cmp r4, r1
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bcc CopyDataInit
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/* Zero fill the bss segment. */
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ldr r2, =_sbss
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ldr r4, =_ebss
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movs r3, #0
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b LoopFillZerobss
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FillZerobss:
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str r3, [r2]
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adds r2, r2, #4
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LoopFillZerobss:
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cmp r2, r4
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bcc FillZerobss
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/* Call static constructors */
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bl __libc_init_array
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/* Call the application's entry point.*/
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bl main
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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* @param None
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* @retval None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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.size g_pfnVectors, .-g_pfnVectors
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/* External Interrupts */
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.word WWDG_IRQHandler /* Window WatchDog */
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.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
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.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
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.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
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.word FLASH_IRQHandler /* FLASH */
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.word RCC_IRQHandler /* RCC */
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.word EXTI0_IRQHandler /* EXTI Line0 */
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.word EXTI1_IRQHandler /* EXTI Line1 */
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.word EXTI2_IRQHandler /* EXTI Line2 */
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.word EXTI3_IRQHandler /* EXTI Line3 */
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.word EXTI4_IRQHandler /* EXTI Line4 */
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.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
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.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
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.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
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.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
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.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
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.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
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.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
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.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
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.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
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.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
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.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
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.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
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.word EXTI9_5_IRQHandler /* External Line[9:5]s */
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.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
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.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
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.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.word TIM2_IRQHandler /* TIM2 */
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.word TIM3_IRQHandler /* TIM3 */
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.word TIM4_IRQHandler /* TIM4 */
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.word I2C1_EV_IRQHandler /* I2C1 Event */
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.word I2C1_ER_IRQHandler /* I2C1 Error */
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.word I2C2_EV_IRQHandler /* I2C2 Event */
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.word I2C2_ER_IRQHandler /* I2C2 Error */
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.word SPI1_IRQHandler /* SPI1 */
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.word SPI2_IRQHandler /* SPI2 */
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.word USART1_IRQHandler /* USART1 */
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.word USART2_IRQHandler /* USART2 */
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.word USART3_IRQHandler /* USART3 */
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.word EXTI15_10_IRQHandler /* External Line[15:10]s */
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.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
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.word 0 /* Reserved */
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.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
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.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
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.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
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.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
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.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
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.word FMC_IRQHandler /* FMC */
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.word SDMMC1_IRQHandler /* SDMMC1 */
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.word TIM5_IRQHandler /* TIM5 */
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.word SPI3_IRQHandler /* SPI3 */
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.word UART4_IRQHandler /* UART4 */
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.word UART5_IRQHandler /* UART5 */
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.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
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.word TIM7_IRQHandler /* TIM7 */
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.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
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.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
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||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
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||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
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.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
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.word ETH_IRQHandler /* Ethernet */
|
||||
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word DCMI_IRQHandler /* DCMI */
|
||||
.word CRYP_IRQHandler /* Crypto */
|
||||
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word SAI1_IRQHandler /* SAI1 */
|
||||
.word LTDC_IRQHandler /* LTDC */
|
||||
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
.word SAI2_IRQHandler /* SAI2 */
|
||||
.word QUADSPI_IRQHandler /* QUADSPI */
|
||||
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||
.word CEC_IRQHandler /* HDMI_CEC */
|
||||
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
|
||||
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
|
||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
|
||||
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
|
||||
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
|
||||
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
|
||||
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
|
||||
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
|
||||
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
|
||||
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||
.word SAI3_IRQHandler /* SAI3 global Interrupt */
|
||||
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||
.word JPEG_IRQHandler /* JPEG global Interrupt */
|
||||
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word ADC3_IRQHandler /* ADC3 global Interrupt */
|
||||
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
|
||||
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
|
||||
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
|
||||
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
|
||||
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
|
||||
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
|
||||
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
|
||||
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
|
||||
.word COMP1_IRQHandler /* COMP1 global Interrupt */
|
||||
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
|
||||
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
|
||||
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_AVD_IRQHandler
|
||||
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN_CAL_IRQHandler
|
||||
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRYP_IRQHandler
|
||||
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_RNG_IRQHandler
|
||||
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_IRQHandler
|
||||
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_ER_IRQHandler
|
||||
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_Master_IRQHandler
|
||||
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMA_IRQHandler
|
||||
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMB_IRQHandler
|
||||
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMC_IRQHandler
|
||||
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMD_IRQHandler
|
||||
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIME_IRQHandler
|
||||
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_FLT_IRQHandler
|
||||
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT0_IRQHandler
|
||||
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT1_IRQHandler
|
||||
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT2_IRQHandler
|
||||
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT3_IRQHandler
|
||||
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI3_IRQHandler
|
||||
.thumb_set SAI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SWPMI1_IRQHandler
|
||||
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_WKUP_IRQHandler
|
||||
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
.weak JPEG_IRQHandler
|
||||
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDMA_IRQHandler
|
||||
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM1_IRQHandler
|
||||
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC3_IRQHandler
|
||||
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX2_OVR_IRQHandler
|
||||
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel0_IRQHandler
|
||||
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel1_IRQHandler
|
||||
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel2_IRQHandler
|
||||
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel3_IRQHandler
|
||||
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel4_IRQHandler
|
||||
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel5_IRQHandler
|
||||
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel6_IRQHandler
|
||||
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel7_IRQHandler
|
||||
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP1_IRQHandler
|
||||
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ECC_IRQHandler
|
||||
.thumb_set ECC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI4_IRQHandler
|
||||
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
@@ -1,780 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32h7s7xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32H7S7xx Devices vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m7
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32H7S7xx vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
/* External Interrupts */
|
||||
.word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
|
||||
.word 0 /* Reserved */
|
||||
.word DTS_IRQHandler /* Digital Temperature Sensor */
|
||||
.word IWDG_IRQHandler /* Internal Watchdog */
|
||||
.word WWDG_IRQHandler /* Window Watchdog */
|
||||
.word RCC_IRQHandler /* RCC global interrupts through EXTI Line detection */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word FLASH_IRQHandler /* FLASH interrupts */
|
||||
.word RAMECC_IRQHandler /* RAMECC interrupts */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word TAMP_IRQHandler /* Tamper and TimeStamp interrupts */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word EXTI5_IRQHandler /* EXTI Line5 */
|
||||
.word EXTI6_IRQHandler /* EXTI Line6 */
|
||||
.word EXTI7_IRQHandler /* EXTI Line7 */
|
||||
.word EXTI8_IRQHandler /* EXTI Line8 */
|
||||
.word EXTI9_IRQHandler /* EXTI Line9 */
|
||||
.word EXTI10_IRQHandler /* EXTI Line10 */
|
||||
.word EXTI11_IRQHandler /* EXTI Line11 */
|
||||
.word EXTI12_IRQHandler /* EXTI Line12 */
|
||||
.word EXTI13_IRQHandler /* EXTI Line13 */
|
||||
.word EXTI14_IRQHandler /* EXTI Line14 */
|
||||
.word EXTI15_IRQHandler /* EXTI Line15 */
|
||||
.word RTC_IRQHandler /* RTC wakeup and alarm interrupts */
|
||||
.word SAES_IRQHandler /* SAES */
|
||||
.word CRYP_IRQHandler /* CRYP */
|
||||
.word PKA_IRQHandler /* PKA */
|
||||
.word HASH_IRQHandler /* HASH */
|
||||
.word RNG_IRQHandler /* RNG */
|
||||
.word ADC1_2_IRQHandler /* ADC1 & ADC2 */
|
||||
.word GPDMA1_Channel0_IRQHandler /* GPDMA1 Channel 0 */
|
||||
.word GPDMA1_Channel1_IRQHandler /* GPDMA1 Channel 1 */
|
||||
.word GPDMA1_Channel2_IRQHandler /* GPDMA1 Channel 2 */
|
||||
.word GPDMA1_Channel3_IRQHandler /* GPDMA1 Channel 3 */
|
||||
.word GPDMA1_Channel4_IRQHandler /* GPDMA1 Channel 4 */
|
||||
.word GPDMA1_Channel5_IRQHandler /* GPDMA1 Channel 5 */
|
||||
.word GPDMA1_Channel6_IRQHandler /* GPDMA1 Channel 6 */
|
||||
.word GPDMA1_Channel7_IRQHandler /* GPDMA1 Channel 7 */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word TIM6_IRQHandler /* TIM6 */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word TIM9_IRQHandler /* TIM9 */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 */
|
||||
.word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 */
|
||||
.word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 */
|
||||
.word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 */
|
||||
.word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 */
|
||||
.word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 */
|
||||
.word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 */
|
||||
.word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 */
|
||||
.word SAI1_A_IRQHandler /* Serial Audio Interface 1 block A */
|
||||
.word SAI1_B_IRQHandler /* Serial Audio Interface 1 block B */
|
||||
.word SAI2_A_IRQHandler /* Serial Audio Interface 2 block A */
|
||||
.word SAI2_B_IRQHandler /* Serial Audio Interface 2 block B */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 Event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 Error */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word I3C1_EV_IRQHandler /* I3C1 Event */
|
||||
.word I3C1_ER_IRQHandler /* I3C1 Error */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word CORDIC_IRQHandler /* CORDIC */
|
||||
.word GFXTIM_IRQHandler /* GFXTIM */
|
||||
.word DCMIPP_IRQHandler /* DCMIPP */
|
||||
.word LTDC_IRQHandler /* LTDC */
|
||||
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
.word JPEG_IRQHandler /* JPEG */
|
||||
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||
.word I3C1_WKUP_IRQHandler /* I3C1 wakeup */
|
||||
.word MCE1_IRQHandler /* MCE1 */
|
||||
.word MCE2_IRQHandler /* MCE2 */
|
||||
.word MCE3_IRQHandler /* MCE3 */
|
||||
.word XSPI1_IRQHandler /* XSPI1 */
|
||||
.word XSPI2_IRQHandler /* XSPI2 */
|
||||
.word FMC_IRQHandler /* FMC */
|
||||
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||
.word SDMMC2_IRQHandler /* SDMMC2 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word TIM12_IRQHandler /* TIM12 */
|
||||
.word TIM13_IRQHandler /* TIM13 */
|
||||
.word TIM14_IRQHandler /* TIM14 */
|
||||
.word TIM15_IRQHandler /* TIM15 */
|
||||
.word TIM16_IRQHandler /* TIM16 */
|
||||
.word TIM17_IRQHandler /* TIM17 */
|
||||
.word LPTIM1_IRQHandler /* LP TIM1 */
|
||||
.word LPTIM2_IRQHandler /* LP TIM2 */
|
||||
.word LPTIM3_IRQHandler /* LP TIM3 */
|
||||
.word LPTIM4_IRQHandler /* LP TIM4 */
|
||||
.word LPTIM5_IRQHandler /* LP TIM5 */
|
||||
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||
.word MDIOS_IRQHandler /* MDIOS */
|
||||
.word ADF1_FLT0_IRQHandler /* ADF1 Filter 0 */
|
||||
.word CRS_IRQHandler /* CRS */
|
||||
.word UCPD1_IRQHandler /* UCPD1 */
|
||||
.word CEC_IRQHandler /* HDMI_CEC */
|
||||
.word PSSI_IRQHandler /* PSSI */
|
||||
.word LPUART1_IRQHandler /* LP UART1 */
|
||||
.word WAKEUP_PIN_IRQHandler /* Wake-up pins interrupt */
|
||||
.word GPDMA1_Channel8_IRQHandler /* GPDMA1 Channel 8 */
|
||||
.word GPDMA1_Channel9_IRQHandler /* GPDMA1 Channel 9 */
|
||||
.word GPDMA1_Channel10_IRQHandler /* GPDMA1 Channel 10 */
|
||||
.word GPDMA1_Channel11_IRQHandler /* GPDMA1 Channel 11 */
|
||||
.word GPDMA1_Channel12_IRQHandler /* GPDMA1 Channel 12 */
|
||||
.word GPDMA1_Channel13_IRQHandler /* GPDMA1 Channel 13 */
|
||||
.word GPDMA1_Channel14_IRQHandler /* GPDMA1 Channel 14 */
|
||||
.word GPDMA1_Channel15_IRQHandler /* GPDMA1 Channel 15 */
|
||||
.word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 */
|
||||
.word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 */
|
||||
.word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 */
|
||||
.word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 */
|
||||
.word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 */
|
||||
.word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 */
|
||||
.word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 */
|
||||
.word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 */
|
||||
.word GPU2D_IRQHandler /* GPU2D */
|
||||
.word GPU2D_ER_IRQHandler /* GPU2D error */
|
||||
.word ICACHE_IRQHandler /* ICACHE */
|
||||
.word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */
|
||||
.word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */
|
||||
.word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */
|
||||
.word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DTS_IRQHandler
|
||||
.thumb_set DTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak IWDG_IRQHandler
|
||||
.thumb_set IWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RAMECC_IRQHandler
|
||||
.thumb_set RAMECC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_IRQHandler
|
||||
.thumb_set TAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_IRQHandler
|
||||
.thumb_set EXTI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI6_IRQHandler
|
||||
.thumb_set EXTI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI7_IRQHandler
|
||||
.thumb_set EXTI7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI8_IRQHandler
|
||||
.thumb_set EXTI8_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_IRQHandler
|
||||
.thumb_set EXTI9_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_IRQHandler
|
||||
.thumb_set EXTI10_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI11_IRQHandler
|
||||
.thumb_set EXTI11_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI12_IRQHandler
|
||||
.thumb_set EXTI12_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI13_IRQHandler
|
||||
.thumb_set EXTI13_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI14_IRQHandler
|
||||
.thumb_set EXTI14_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_IRQHandler
|
||||
.thumb_set EXTI15_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAES_IRQHandler
|
||||
.thumb_set SAES_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRYP_IRQHandler
|
||||
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_IRQHandler
|
||||
.thumb_set HASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel0_IRQHandler
|
||||
.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel1_IRQHandler
|
||||
.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel2_IRQHandler
|
||||
.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel3_IRQHandler
|
||||
.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel4_IRQHandler
|
||||
.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel5_IRQHandler
|
||||
.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel6_IRQHandler
|
||||
.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel7_IRQHandler
|
||||
.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM9_IRQHandler
|
||||
.thumb_set TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel0_IRQHandler
|
||||
.thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel1_IRQHandler
|
||||
.thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel2_IRQHandler
|
||||
.thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel3_IRQHandler
|
||||
.thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel4_IRQHandler
|
||||
.thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel5_IRQHandler
|
||||
.thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel6_IRQHandler
|
||||
.thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel7_IRQHandler
|
||||
.thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_A_IRQHandler
|
||||
.thumb_set SAI1_A_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_B_IRQHandler
|
||||
.thumb_set SAI1_B_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_A_IRQHandler
|
||||
.thumb_set SAI2_A_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_B_IRQHandler
|
||||
.thumb_set SAI2_B_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_EV_IRQHandler
|
||||
.thumb_set I3C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_ER_IRQHandler
|
||||
.thumb_set I3C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak CORDIC_IRQHandler
|
||||
.thumb_set CORDIC_IRQHandler,Default_Handler
|
||||
|
||||
.weak GFXTIM_IRQHandler
|
||||
.thumb_set GFXTIM_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMIPP_IRQHandler
|
||||
.thumb_set DCMIPP_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_IRQHandler
|
||||
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_ER_IRQHandler
|
||||
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak JPEG_IRQHandler
|
||||
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||
|
||||
.weak GFXMMU_IRQHandler
|
||||
.thumb_set GFXMMU_IRQHandler,Default_Handler
|
||||
|
||||
.weak I3C1_WKUP_IRQHandler
|
||||
.thumb_set I3C1_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak MCE1_IRQHandler
|
||||
.thumb_set MCE1_IRQHandler,Default_Handler
|
||||
|
||||
.weak MCE2_IRQHandler
|
||||
.thumb_set MCE2_IRQHandler,Default_Handler
|
||||
|
||||
.weak MCE3_IRQHandler
|
||||
.thumb_set MCE3_IRQHandler,Default_Handler
|
||||
|
||||
.weak XSPI1_IRQHandler
|
||||
.thumb_set XSPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak XSPI2_IRQHandler
|
||||
.thumb_set XSPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM12_IRQHandler
|
||||
.thumb_set TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM13_IRQHandler
|
||||
.thumb_set TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM14_IRQHandler
|
||||
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADF1_FLT0_IRQHandler
|
||||
.thumb_set ADF1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak UCPD1_IRQHandler
|
||||
.thumb_set UCPD1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak PSSI_IRQHandler
|
||||
.thumb_set PSSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel8_IRQHandler
|
||||
.thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel9_IRQHandler
|
||||
.thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel10_IRQHandler
|
||||
.thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel11_IRQHandler
|
||||
.thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel12_IRQHandler
|
||||
.thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel13_IRQHandler
|
||||
.thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel14_IRQHandler
|
||||
.thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPDMA1_Channel15_IRQHandler
|
||||
.thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel8_IRQHandler
|
||||
.thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel9_IRQHandler
|
||||
.thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel10_IRQHandler
|
||||
.thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel11_IRQHandler
|
||||
.thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel12_IRQHandler
|
||||
.thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel13_IRQHandler
|
||||
.thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel14_IRQHandler
|
||||
.thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler
|
||||
|
||||
.weak HPDMA1_Channel15_IRQHandler
|
||||
.thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPU2D_IRQHandler
|
||||
.thumb_set GPU2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPU2D_ER_IRQHandler
|
||||
.thumb_set GPU2D_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak ICACHE_IRQHandler
|
||||
.thumb_set ICACHE_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit
|
||||
@@ -57,8 +57,12 @@ endif()
|
||||
add_executable(bootloader EXCLUDE_FROM_ALL ${BOOTLOADER_SRC})
|
||||
add_dependencies(bootloader ${BITMAPS_TARGET})
|
||||
|
||||
target_compile_definitions(bootloader PRIVATE BOOT)
|
||||
target_compile_definitions(board_bl PRIVATE BOOT)
|
||||
target_compile_definitions(bootloader PUBLIC BOOT)
|
||||
target_compile_definitions(board_bl PUBLIC BOOT)
|
||||
|
||||
if(ARCH STREQUAL ARM)
|
||||
target_link_libraries(bootloader PUBLIC cmsis)
|
||||
endif()
|
||||
|
||||
target_link_options(bootloader BEFORE PRIVATE
|
||||
-L${LINKER_DIR}/${TARGET_LINKER_DIR}/bootloader
|
||||
@@ -67,17 +71,15 @@ target_link_options(bootloader BEFORE PRIVATE
|
||||
-lm --specs=nano.specs
|
||||
)
|
||||
|
||||
if (DEFINED TARGET_SDRAM_START)
|
||||
# message("TARGET_SDRAM_START = ${TARGET_SDRAM_START}")
|
||||
if (DEFINED TARGET_EXTRAM_START)
|
||||
target_link_options(bootloader PRIVATE
|
||||
-Wl,--defsym=__sdram_start=${TARGET_SDRAM_START}
|
||||
-Wl,--defsym=__EXTRAM_START__=${TARGET_EXTRAM_START}
|
||||
)
|
||||
endif()
|
||||
|
||||
if (DEFINED TARGET_SDRAM_SIZE)
|
||||
# message("TARGET_SDRAM_SIZE = ${TARGET_SDRAM_SIZE}")
|
||||
if (DEFINED TARGET_EXTRAM_SIZE)
|
||||
target_link_options(bootloader PRIVATE
|
||||
-Wl,--defsym=__sdram_size=${TARGET_SDRAM_SIZE}
|
||||
-Wl,--defsym=__EXTRAM_SIZE__=${TARGET_EXTRAM_SIZE}
|
||||
)
|
||||
endif()
|
||||
|
||||
|
||||
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Copyright (C) EdgeTX
|
||||
*
|
||||
* Based on code named
|
||||
* opentx - https://github.com/opentx/opentx
|
||||
* th9x - http://code.google.com/p/th9x
|
||||
* er9x - http://code.google.com/p/er9x
|
||||
* gruvin9x - http://code.google.com/p/gruvin9x
|
||||
*
|
||||
* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "cortex_m_isr.h"
|
||||
#include "stm32_cmsis.h"
|
||||
|
||||
#define GET_VECTACTIVE() \
|
||||
((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos)
|
||||
|
||||
#define HARDFAULT_HANDLING_ASM(_x) \
|
||||
__asm volatile( \
|
||||
"tst lr, #4 \n" \
|
||||
"ite eq \n" \
|
||||
"mrseq r0, msp \n" \
|
||||
"mrsne r0, psp \n" \
|
||||
"b hard_fault_handler_c \n")
|
||||
|
||||
#define HALT_IF_DEBUGGING() \
|
||||
do { \
|
||||
if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) { \
|
||||
__asm("bkpt 1"); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
||||
__attribute__((optimize("O0")))
|
||||
void default_isr_handler()
|
||||
{
|
||||
/* Halt in debugger if connected */
|
||||
if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) {
|
||||
uint32_t active_irq = GET_VECTACTIVE();
|
||||
if (active_irq >= NVIC_USER_IRQ_OFFSET) {
|
||||
/* External interrupt: check IRQn_Type for number */
|
||||
active_irq -= NVIC_USER_IRQ_OFFSET;
|
||||
__asm__("bkpt 1");
|
||||
} else {
|
||||
/* Cortex-M Exception */
|
||||
__asm__("bkpt 2");
|
||||
}
|
||||
}
|
||||
while (1) {}
|
||||
}
|
||||
|
||||
typedef struct __attribute__((packed)) ContextStateFrame {
|
||||
uint32_t r0;
|
||||
uint32_t r1;
|
||||
uint32_t r2;
|
||||
uint32_t r3;
|
||||
uint32_t r12;
|
||||
uint32_t lr;
|
||||
uint32_t return_address;
|
||||
uint32_t xpsr;
|
||||
} sContextStateFrame;
|
||||
|
||||
__attribute__((optimize("O0")))
|
||||
void hard_fault_handler_c(sContextStateFrame *frame) {
|
||||
HALT_IF_DEBUGGING();
|
||||
}
|
||||
|
||||
void HardFault_Handler(void) {
|
||||
HARDFAULT_HANDLING_ASM();
|
||||
}
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) EdgeTX
|
||||
*
|
||||
* Based on code named
|
||||
* opentx - https://github.com/opentx/opentx
|
||||
* th9x - http://code.google.com/p/th9x
|
||||
* er9x - http://code.google.com/p/er9x
|
||||
* gruvin9x - http://code.google.com/p/gruvin9x
|
||||
*
|
||||
* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define WEAK_DEFAULT __attribute__((weak,alias("Default_Handler")))
|
||||
#define ISR_VECTOR __attribute__((section(".isr_vector")))
|
||||
|
||||
typedef void (*isr_t)(void);
|
||||
extern void* _estack;
|
||||
|
||||
extern void default_isr_handler();
|
||||
|
||||
@@ -53,13 +53,12 @@ include_directories(${STM32LIB_DIR}/CMSIS/Include)
|
||||
|
||||
add_definitions(-DSTM32F2)
|
||||
|
||||
add_library(stm32_stdperiph OBJECT EXCLUDE_FROM_ALL
|
||||
add_library(cmsis INTERFACE)
|
||||
|
||||
target_sources(cmsis INTERFACE
|
||||
targets/common/arm/stm32/f2/system_stm32f2xx.c
|
||||
boards/generic_stm32/startup/startup_stm32f205xx.s
|
||||
)
|
||||
|
||||
set(FIRMWARE_SRC ${FIRMWARE_SRC} $<TARGET_OBJECTS:stm32_stdperiph>)
|
||||
set(BOOTLOADER_SRC ${BOOTLOADER_SRC} $<TARGET_OBJECTS:stm32_stdperiph>)
|
||||
)
|
||||
|
||||
if(NOT NATIVE_BUILD)
|
||||
include_directories(targets/common/arm/stm32/f2)
|
||||
|
||||
@@ -21,6 +21,7 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#define __INIT_HOOK
|
||||
#define __CCMRAM
|
||||
#define __DMA
|
||||
#define __DMA_NO_CACHE
|
||||
|
||||
@@ -71,30 +71,26 @@ include_directories(${STM32LIB_DIR}/CMSIS/Include)
|
||||
|
||||
add_definitions(-DSTM32F4)
|
||||
|
||||
set(STM32_STDPERIPH_SRC
|
||||
targets/common/arm/stm32/f4/system_stm32f4xx.c
|
||||
)
|
||||
|
||||
if(CPU_TYPE_FULL STREQUAL STM32F429xI)
|
||||
set(STM32_STDPERIPH_SRC ${STM32_STDPERIPH_SRC}
|
||||
set(CMSIS_SRC ${CMSIS_SRC}
|
||||
boards/generic_stm32/startup/startup_stm32f42_43xxx.s
|
||||
)
|
||||
)
|
||||
elseif (CPU_TYPE_FULL STREQUAL STM32F413xG)
|
||||
set(STM32_STDPERIPH_SRC ${STM32_STDPERIPH_SRC}
|
||||
set(CMSIS_SRC ${CMSIS_SRC}
|
||||
boards/generic_stm32/startup/startup_stm32f413xx.s
|
||||
)
|
||||
else()
|
||||
set(STM32_STDPERIPH_SRC ${STM32_STDPERIPH_SRC}
|
||||
set(CMSIS_SRC ${CMSIS_SRC}
|
||||
boards/generic_stm32/startup/startup_stm32f40_41xxx.s
|
||||
)
|
||||
)
|
||||
endif()
|
||||
|
||||
add_library(stm32_stdperiph OBJECT EXCLUDE_FROM_ALL
|
||||
${STM32_STDPERIPH_SRC}
|
||||
)
|
||||
add_library(cmsis INTERFACE)
|
||||
|
||||
set(FIRMWARE_SRC ${FIRMWARE_SRC} $<TARGET_OBJECTS:stm32_stdperiph>)
|
||||
set(BOOTLOADER_SRC ${BOOTLOADER_SRC} $<TARGET_OBJECTS:stm32_stdperiph>)
|
||||
target_sources(cmsis INTERFACE
|
||||
targets/common/arm/stm32/f4/system_stm32f4xx.c
|
||||
${CMSIS_SRC}
|
||||
)
|
||||
|
||||
if(NOT NATIVE_BUILD)
|
||||
include_directories(targets/common/arm/stm32/f4)
|
||||
|
||||
@@ -21,6 +21,8 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#define __INIT_HOOK
|
||||
|
||||
#define __CCMRAM __attribute__((section(".ccm"), aligned(4)))
|
||||
#define __DMA __attribute__((section(".ram"), aligned(4)))
|
||||
#define __DMA_NO_CACHE __DMA
|
||||
|
||||
@@ -18,7 +18,6 @@ else()
|
||||
)
|
||||
endif()
|
||||
|
||||
|
||||
if(NOT NATIVE_BUILD)
|
||||
if(CPU_TYPE STREQUAL STM32H7RS)
|
||||
set(STM32CUBE_PREFIX stm32h7rsxx)
|
||||
@@ -123,27 +122,28 @@ endif()
|
||||
|
||||
if(CPU_TYPE_FULL STREQUAL STM32H750xB)
|
||||
set(CMSIS_SRC ${CMSIS_SRC}
|
||||
boards/generic_stm32/startup/startup_stm32h750xx.s
|
||||
targets/common/arm/stm32/h7/vectors_stm32h750xx.c
|
||||
)
|
||||
elseif(CPU_TYPE_FULL STREQUAL STM32H747Ix)
|
||||
set(CMSIS_SRC ${CMSIS_SRC}
|
||||
boards/generic_stm32/startup/startup_stm32h747xx.s
|
||||
targets/common/arm/stm32/h7/vectors_stm32h747xx.c
|
||||
)
|
||||
elseif(CPU_TYPE_FULL STREQUAL STM32H7S7xx)
|
||||
elseif(CPU_TYPE_FULL STREQUAL STM32H7S7xx OR CPU_TYPE_FULL STREQUAL STM32H7R7xx)
|
||||
set(CMSIS_SRC ${CMSIS_SRC}
|
||||
boards/generic_stm32/startup/startup_stm32h7s7xx.s
|
||||
targets/common/arm/stm32/h7/vectors_stm32h7s7xx.c
|
||||
)
|
||||
else()
|
||||
message(FATAL_ERROR "### ERROR ####: ${CPU_TYPE_FULL}")
|
||||
endif()
|
||||
|
||||
add_library(cmsis OBJECT EXCLUDE_FROM_ALL
|
||||
add_library(cmsis INTERFACE)
|
||||
|
||||
target_sources(cmsis INTERFACE
|
||||
targets/common/arm/stm32/system_init.c
|
||||
targets/common/arm/stm32/cortex_m_isr.c
|
||||
${CMSIS_SRC}
|
||||
)
|
||||
|
||||
set(FIRMWARE_SRC ${FIRMWARE_SRC} $<TARGET_OBJECTS:cmsis>)
|
||||
set(BOOTLOADER_SRC ${BOOTLOADER_SRC} $<TARGET_OBJECTS:cmsis>)
|
||||
|
||||
if(NOT NATIVE_BUILD)
|
||||
include_directories(targets/common/arm/stm32/h7)
|
||||
|
||||
|
||||
@@ -21,6 +21,8 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#define __INIT_HOOK __attribute__((section(".init_hook")))
|
||||
|
||||
#define __CCMRAM __attribute__((section(".ccm"), aligned(4)))
|
||||
#define __DMA __attribute__((section(".ram"), aligned(4)))
|
||||
#define __DMA_NO_CACHE __attribute__((section(".dram"), aligned(4)))
|
||||
|
||||
@@ -444,134 +444,6 @@ void SystemCoreClockUpdate (void)
|
||||
#endif /* DUAL_CORE && CORE_CM4 */
|
||||
}
|
||||
|
||||
// TODO: better exception handler
|
||||
void NMI_Handler(void){asm("BKPT");}
|
||||
void HardFault_Handler(void){asm("BKPT");}
|
||||
void MemManage_Handler(void){asm("BKPT");}
|
||||
void BusFault_Handler(void){asm("BKPT");}
|
||||
void UsageFault_Handler(void){asm("BKPT");}
|
||||
//void SVC_Handler(void){asm("BKPT");}
|
||||
void DebugMon_Handler(void){asm("BKPT");}
|
||||
//void PendSV_Handler(void){asm("BKPT");}
|
||||
//void SysTick_Handler(void){asm("BKPT");}
|
||||
void WWDG_IRQHandler(void){asm("BKPT");}
|
||||
void PVD_AVD_IRQHandler(void){asm("BKPT");}
|
||||
void TAMP_STAMP_IRQHandler(void){asm("BKPT");}
|
||||
void RTC_WKUP_IRQHandler(void){asm("BKPT");}
|
||||
void FLASH_IRQHandler(void){asm("BKPT");}
|
||||
void RCC_IRQHandler(void){asm("BKPT");}
|
||||
void EXTI0_IRQHandler(void){asm("BKPT");}
|
||||
void EXTI1_IRQHandler(void){asm("BKPT");}
|
||||
void DMA1_Stream1_IRQHandler(void){asm("BKPT");}
|
||||
void DMA1_Stream2_IRQHandler(void){asm("BKPT");}
|
||||
void DMA1_Stream3_IRQHandler(void){asm("BKPT");}
|
||||
void DMA1_Stream4_IRQHandler(void){asm("BKPT");}
|
||||
//void ADC_IRQHandler(void){asm("BKPT");}
|
||||
void FDCAN1_IT0_IRQHandler(void){asm("BKPT");}
|
||||
void FDCAN2_IT0_IRQHandler(void){asm("BKPT");}
|
||||
void FDCAN1_IT1_IRQHandler(void){asm("BKPT");}
|
||||
void FDCAN2_IT1_IRQHandler(void){asm("BKPT");}
|
||||
void TIM1_BRK_IRQHandler(void){asm("BKPT");}
|
||||
void TIM1_UP_IRQHandler(void){asm("BKPT");}
|
||||
void TIM1_TRG_COM_IRQHandler(void){asm("BKPT");}
|
||||
void TIM1_CC_IRQHandler(void){asm("BKPT");}
|
||||
void TIM2_IRQHandler(void){asm("BKPT");}
|
||||
void TIM3_IRQHandler(void){asm("BKPT");}
|
||||
// void TIM4_IRQHandler(void){asm("BKPT");}
|
||||
void I2C1_EV_IRQHandler(void){asm("BKPT");}
|
||||
void I2C1_ER_IRQHandler(void){asm("BKPT");}
|
||||
void I2C2_EV_IRQHandler(void){asm("BKPT");}
|
||||
void I2C2_ER_IRQHandler(void){asm("BKPT");}
|
||||
void SPI1_IRQHandler(void){asm("BKPT");}
|
||||
void SPI2_IRQHandler(void){asm("BKPT");}
|
||||
//void EXTI15_10_IRQHandler(void){asm("BKPT");}
|
||||
void RTC_Alarm_IRQHandler(void){asm("BKPT");}
|
||||
void TIM8_CC_IRQHandler(void){asm("BKPT");}
|
||||
//void DMA1_Stream7_IRQHandler(void){asm("BKPT");}
|
||||
void FMC_IRQHandler(void){asm("BKPT");}
|
||||
void TIM5_IRQHandler(void){asm("BKPT");}
|
||||
void SPI3_IRQHandler(void){asm("BKPT");}
|
||||
//void UART5_IRQHandler(void){asm("BKPT");}
|
||||
void TIM7_IRQHandler(void){asm("BKPT");}
|
||||
//void DMA2_Stream0_IRQHandler(void){asm("BKPT");}
|
||||
void DMA2_Stream2_IRQHandler(void){asm("BKPT");}
|
||||
void DMA2_Stream3_IRQHandler(void){asm("BKPT");}
|
||||
//void DMA2_Stream4_IRQHandler(void){asm("BKPT");}
|
||||
void ETH_IRQHandler(void){asm("BKPT");}
|
||||
//void ETH_WKUP_IRQHandler(void){asm("BKPT");}
|
||||
void FDCAN_CAL_IRQHandler(void){asm("BKPT");}
|
||||
void DMA2_Stream5_IRQHandler(void){asm("BKPT");}
|
||||
// void DMA2_Stream6_IRQHandler(void){asm("BKPT");}
|
||||
void DMA2_Stream7_IRQHandler(void){asm("BKPT");}
|
||||
void I2C3_EV_IRQHandler(void){asm("BKPT");}
|
||||
void I2C3_ER_IRQHandler(void){asm("BKPT");}
|
||||
void OTG_HS_EP1_OUT_IRQHandler(void){asm("BKPT");}
|
||||
void OTG_HS_EP1_IN_IRQHandler(void){asm("BKPT");}
|
||||
void OTG_HS_WKUP_IRQHandler(void){asm("BKPT");}
|
||||
void OTG_HS_IRQHandler(void){asm("BKPT");}
|
||||
void DCMI_IRQHandler(void){asm("BKPT");}
|
||||
void CRYP_IRQHandler(void){asm("BKPT");}
|
||||
void HASH_RNG_IRQHandler(void){asm("BKPT");}
|
||||
void FPU_IRQHandler(void){asm("BKPT");}
|
||||
//void UART8_IRQHandler(void){asm("BKPT");}
|
||||
void SPI4_IRQHandler(void){asm("BKPT");}
|
||||
void SPI5_IRQHandler(void){asm("BKPT");}
|
||||
void SPI6_IRQHandler(void){asm("BKPT");}
|
||||
void SAI1_IRQHandler(void){asm("BKPT");}
|
||||
void LTDC_ER_IRQHandler(void){asm("BKPT");}
|
||||
void DMA2D_IRQHandler(void){asm("BKPT");}
|
||||
void SAI2_IRQHandler(void){asm("BKPT");}
|
||||
void QUADSPI_IRQHandler(void){asm("BKPT");}
|
||||
void LPTIM1_IRQHandler(void){asm("BKPT");}
|
||||
void CEC_IRQHandler(void){asm("BKPT");}
|
||||
void I2C4_EV_IRQHandler(void){asm("BKPT");}
|
||||
void I2C4_ER_IRQHandler(void){asm("BKPT");}
|
||||
void SPDIF_RX_IRQHandler(void){asm("BKPT");}
|
||||
void OTG_FS_EP1_OUT_IRQHandler(void){asm("BKPT");}
|
||||
void OTG_FS_EP1_IN_IRQHandler(void){asm("BKPT");}
|
||||
void OTG_FS_WKUP_IRQHandler(void){asm("BKPT");}
|
||||
void DMAMUX1_OVR_IRQHandler(void){asm("BKPT");}
|
||||
void HRTIM1_Master_IRQHandler(void){asm("BKPT");}
|
||||
void HRTIM1_TIMA_IRQHandler(void){asm("BKPT");}
|
||||
void HRTIM1_TIMB_IRQHandler(void){asm("BKPT");}
|
||||
void HRTIM1_TIMC_IRQHandler(void){asm("BKPT");}
|
||||
void HRTIM1_TIMD_IRQHandler(void){asm("BKPT");}
|
||||
void HRTIM1_TIME_IRQHandler(void){asm("BKPT");}
|
||||
void HRTIM1_FLT_IRQHandler(void){asm("BKPT");}
|
||||
void DFSDM1_FLT0_IRQHandler(void){asm("BKPT");}
|
||||
void DFSDM1_FLT1_IRQHandler(void){asm("BKPT");}
|
||||
void DFSDM1_FLT2_IRQHandler(void){asm("BKPT");}
|
||||
void DFSDM1_FLT3_IRQHandler(void){asm("BKPT");}
|
||||
void SAI3_IRQHandler(void){asm("BKPT");}
|
||||
void SWPMI1_IRQHandler(void){asm("BKPT");}
|
||||
void TIM16_IRQHandler(void){asm("BKPT");}
|
||||
void MDIOS_WKUP_IRQHandler(void){asm("BKPT");}
|
||||
void MDIOS_IRQHandler(void){asm("BKPT");}
|
||||
void JPEG_IRQHandler(void){asm("BKPT");}
|
||||
void MDMA_IRQHandler(void){asm("BKPT");}
|
||||
void SDMMC2_IRQHandler(void){asm("BKPT");}
|
||||
void HSEM1_IRQHandler(void){asm("BKPT");}
|
||||
// void ADC3_IRQHandler(void){asm("BKPT");}
|
||||
void DMAMUX2_OVR_IRQHandler(void){asm("BKPT");}
|
||||
void BDMA_Channel0_IRQHandler(void){asm("BKPT");}
|
||||
void BDMA_Channel1_IRQHandler(void){asm("BKPT");}
|
||||
void BDMA_Channel2_IRQHandler(void){asm("BKPT");}
|
||||
void BDMA_Channel3_IRQHandler(void){asm("BKPT");}
|
||||
void BDMA_Channel4_IRQHandler(void){asm("BKPT");}
|
||||
void BDMA_Channel5_IRQHandler(void){asm("BKPT");}
|
||||
void BDMA_Channel6_IRQHandler(void){asm("BKPT");}
|
||||
void BDMA_Channel7_IRQHandler(void){asm("BKPT");}
|
||||
void COMP1_IRQHandler(void){asm("BKPT");}
|
||||
void LPTIM2_IRQHandler(void){asm("BKPT");}
|
||||
void LPTIM3_IRQHandler(void){asm("BKPT");}
|
||||
void LPTIM4_IRQHandler(void){asm("BKPT");}
|
||||
void LPTIM5_IRQHandler(void){asm("BKPT");}
|
||||
void LPUART1_IRQHandler(void){asm("BKPT");}
|
||||
void CRS_IRQHandler(void){asm("BKPT");}
|
||||
void ECC_IRQHandler(void){asm("BKPT");}
|
||||
void SAI4_IRQHandler(void){asm("BKPT");}
|
||||
void WAKEUP_PIN_IRQHandler(void){asm("BKPT");}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -0,0 +1,328 @@
|
||||
|
||||
#include "stm32h747xx.h"
|
||||
#include "cortex_m_isr.h"
|
||||
|
||||
void Default_Handler() { default_isr_handler(); }
|
||||
|
||||
/* stm32h747xx specific interrupt vectors */
|
||||
WEAK_DEFAULT void Reset_Handler();
|
||||
WEAK_DEFAULT void NMI_Handler();
|
||||
WEAK_DEFAULT void HardFault_Handler();
|
||||
WEAK_DEFAULT void MemManage_Handler();
|
||||
WEAK_DEFAULT void BusFault_Handler();
|
||||
WEAK_DEFAULT void UsageFault_Handler();
|
||||
WEAK_DEFAULT void SVC_Handler();
|
||||
WEAK_DEFAULT void DebugMon_Handler();
|
||||
WEAK_DEFAULT void PendSV_Handler();
|
||||
WEAK_DEFAULT void SysTick_Handler();
|
||||
WEAK_DEFAULT void WWDG_IRQHandler();
|
||||
WEAK_DEFAULT void PVD_AVD_IRQHandler();
|
||||
WEAK_DEFAULT void TAMP_STAMP_IRQHandler();
|
||||
WEAK_DEFAULT void RTC_WKUP_IRQHandler();
|
||||
WEAK_DEFAULT void FLASH_IRQHandler();
|
||||
WEAK_DEFAULT void RCC_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI0_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI1_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI2_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI3_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI4_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream0_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream1_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream2_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream3_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream4_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream5_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream6_IRQHandler();
|
||||
WEAK_DEFAULT void ADC_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN1_IT0_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN2_IT0_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN1_IT1_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN2_IT1_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI9_5_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_BRK_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_UP_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_TRG_COM_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_CC_IRQHandler();
|
||||
WEAK_DEFAULT void TIM2_IRQHandler();
|
||||
WEAK_DEFAULT void TIM3_IRQHandler();
|
||||
WEAK_DEFAULT void TIM4_IRQHandler();
|
||||
WEAK_DEFAULT void I2C1_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I2C1_ER_IRQHandler();
|
||||
WEAK_DEFAULT void I2C2_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I2C2_ER_IRQHandler();
|
||||
WEAK_DEFAULT void SPI1_IRQHandler();
|
||||
WEAK_DEFAULT void SPI2_IRQHandler();
|
||||
WEAK_DEFAULT void USART1_IRQHandler();
|
||||
WEAK_DEFAULT void USART2_IRQHandler();
|
||||
WEAK_DEFAULT void USART3_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI15_10_IRQHandler();
|
||||
WEAK_DEFAULT void RTC_Alarm_IRQHandler();
|
||||
WEAK_DEFAULT void TIM8_BRK_TIM12_IRQHandler();
|
||||
WEAK_DEFAULT void TIM8_UP_TIM13_IRQHandler();
|
||||
WEAK_DEFAULT void TIM8_TRG_COM_TIM14_IRQHandler();
|
||||
WEAK_DEFAULT void TIM8_CC_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream7_IRQHandler();
|
||||
WEAK_DEFAULT void FMC_IRQHandler();
|
||||
WEAK_DEFAULT void SDMMC1_IRQHandler();
|
||||
WEAK_DEFAULT void TIM5_IRQHandler();
|
||||
WEAK_DEFAULT void SPI3_IRQHandler();
|
||||
WEAK_DEFAULT void UART4_IRQHandler();
|
||||
WEAK_DEFAULT void UART5_IRQHandler();
|
||||
WEAK_DEFAULT void TIM6_DAC_IRQHandler();
|
||||
WEAK_DEFAULT void TIM7_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream0_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream1_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream2_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream3_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream4_IRQHandler();
|
||||
WEAK_DEFAULT void ETH_IRQHandler();
|
||||
WEAK_DEFAULT void ETH_WKUP_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN_CAL_IRQHandler();
|
||||
WEAK_DEFAULT void CM7_SEV_IRQHandler();
|
||||
WEAK_DEFAULT void CM4_SEV_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream5_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream6_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream7_IRQHandler();
|
||||
WEAK_DEFAULT void USART6_IRQHandler();
|
||||
WEAK_DEFAULT void I2C3_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I2C3_ER_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_HS_EP1_OUT_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_HS_EP1_IN_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_HS_WKUP_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_HS_IRQHandler();
|
||||
WEAK_DEFAULT void DCMI_IRQHandler();
|
||||
WEAK_DEFAULT void RNG_IRQHandler();
|
||||
WEAK_DEFAULT void FPU_IRQHandler();
|
||||
WEAK_DEFAULT void UART7_IRQHandler();
|
||||
WEAK_DEFAULT void UART8_IRQHandler();
|
||||
WEAK_DEFAULT void SPI4_IRQHandler();
|
||||
WEAK_DEFAULT void SPI5_IRQHandler();
|
||||
WEAK_DEFAULT void SPI6_IRQHandler();
|
||||
WEAK_DEFAULT void SAI1_IRQHandler();
|
||||
WEAK_DEFAULT void LTDC_IRQHandler();
|
||||
WEAK_DEFAULT void LTDC_ER_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2D_IRQHandler();
|
||||
WEAK_DEFAULT void SAI2_IRQHandler();
|
||||
WEAK_DEFAULT void QUADSPI_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM1_IRQHandler();
|
||||
WEAK_DEFAULT void CEC_IRQHandler();
|
||||
WEAK_DEFAULT void I2C4_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I2C4_ER_IRQHandler();
|
||||
WEAK_DEFAULT void SPDIF_RX_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_FS_EP1_OUT_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_FS_EP1_IN_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_FS_WKUP_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_FS_IRQHandler();
|
||||
WEAK_DEFAULT void DMAMUX1_OVR_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_Master_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_TIMA_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_TIMB_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_TIMC_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_TIMD_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_TIME_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_FLT_IRQHandler();
|
||||
WEAK_DEFAULT void DFSDM1_FLT0_IRQHandler();
|
||||
WEAK_DEFAULT void DFSDM1_FLT1_IRQHandler();
|
||||
WEAK_DEFAULT void DFSDM1_FLT2_IRQHandler();
|
||||
WEAK_DEFAULT void DFSDM1_FLT3_IRQHandler();
|
||||
WEAK_DEFAULT void SAI3_IRQHandler();
|
||||
WEAK_DEFAULT void SWPMI1_IRQHandler();
|
||||
WEAK_DEFAULT void TIM15_IRQHandler();
|
||||
WEAK_DEFAULT void TIM16_IRQHandler();
|
||||
WEAK_DEFAULT void TIM17_IRQHandler();
|
||||
WEAK_DEFAULT void MDIOS_WKUP_IRQHandler();
|
||||
WEAK_DEFAULT void MDIOS_IRQHandler();
|
||||
WEAK_DEFAULT void JPEG_IRQHandler();
|
||||
WEAK_DEFAULT void MDMA_IRQHandler();
|
||||
WEAK_DEFAULT void DSI_IRQHandler();
|
||||
WEAK_DEFAULT void SDMMC2_IRQHandler();
|
||||
WEAK_DEFAULT void HSEM1_IRQHandler();
|
||||
WEAK_DEFAULT void HSEM2_IRQHandler();
|
||||
WEAK_DEFAULT void ADC3_IRQHandler();
|
||||
WEAK_DEFAULT void DMAMUX2_OVR_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel0_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel1_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel2_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel3_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel4_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel5_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel6_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel7_IRQHandler();
|
||||
WEAK_DEFAULT void COMP_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM2_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM3_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM4_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM5_IRQHandler();
|
||||
WEAK_DEFAULT void LPUART1_IRQHandler();
|
||||
WEAK_DEFAULT void WWDG_RST_IRQHandler();
|
||||
WEAK_DEFAULT void CRS_IRQHandler();
|
||||
WEAK_DEFAULT void ECC_IRQHandler();
|
||||
WEAK_DEFAULT void SAI4_IRQHandler();
|
||||
WEAK_DEFAULT void HOLD_CORE_IRQHandler();
|
||||
WEAK_DEFAULT void WAKEUP_PIN_IRQHandler();
|
||||
|
||||
/* CPU specific interrupt vector table */
|
||||
const isr_t g_pnfVectors[] ISR_VECTOR = {
|
||||
[0] = (isr_t)&_estack,
|
||||
[1 ] = Reset_Handler,
|
||||
[2 ] = NMI_Handler,
|
||||
[3 ] = HardFault_Handler,
|
||||
[4 ] = MemManage_Handler,
|
||||
[5 ] = BusFault_Handler,
|
||||
[6 ] = UsageFault_Handler,
|
||||
[7 ] = 0,
|
||||
[8 ] = 0,
|
||||
[9 ] = 0,
|
||||
[10 ] = 0,
|
||||
[11 ] = SVC_Handler,
|
||||
[12 ] = DebugMon_Handler,
|
||||
[13 ] = 0,
|
||||
[14 ] = PendSV_Handler,
|
||||
[15 ] = SysTick_Handler,
|
||||
[WWDG_IRQn + 16 ] = WWDG_IRQHandler,
|
||||
[PVD_AVD_IRQn + 16 ] = PVD_AVD_IRQHandler,
|
||||
[TAMP_STAMP_IRQn + 16 ] = TAMP_STAMP_IRQHandler,
|
||||
[RTC_WKUP_IRQn + 16 ] = RTC_WKUP_IRQHandler,
|
||||
[FLASH_IRQn + 16 ] = FLASH_IRQHandler,
|
||||
[RCC_IRQn + 16 ] = RCC_IRQHandler,
|
||||
[EXTI0_IRQn + 16 ] = EXTI0_IRQHandler,
|
||||
[EXTI1_IRQn + 16 ] = EXTI1_IRQHandler,
|
||||
[EXTI2_IRQn + 16 ] = EXTI2_IRQHandler,
|
||||
[EXTI3_IRQn + 16 ] = EXTI3_IRQHandler,
|
||||
[EXTI4_IRQn + 16 ] = EXTI4_IRQHandler,
|
||||
[DMA1_Stream0_IRQn + 16 ] = DMA1_Stream0_IRQHandler,
|
||||
[DMA1_Stream1_IRQn + 16 ] = DMA1_Stream1_IRQHandler,
|
||||
[DMA1_Stream2_IRQn + 16 ] = DMA1_Stream2_IRQHandler,
|
||||
[DMA1_Stream3_IRQn + 16 ] = DMA1_Stream3_IRQHandler,
|
||||
[DMA1_Stream4_IRQn + 16 ] = DMA1_Stream4_IRQHandler,
|
||||
[DMA1_Stream5_IRQn + 16 ] = DMA1_Stream5_IRQHandler,
|
||||
[DMA1_Stream6_IRQn + 16 ] = DMA1_Stream6_IRQHandler,
|
||||
[ADC_IRQn + 16 ] = ADC_IRQHandler,
|
||||
[FDCAN1_IT0_IRQn + 16 ] = FDCAN1_IT0_IRQHandler,
|
||||
[FDCAN2_IT0_IRQn + 16 ] = FDCAN2_IT0_IRQHandler,
|
||||
[FDCAN1_IT1_IRQn + 16 ] = FDCAN1_IT1_IRQHandler,
|
||||
[FDCAN2_IT1_IRQn + 16 ] = FDCAN2_IT1_IRQHandler,
|
||||
[EXTI9_5_IRQn + 16 ] = EXTI9_5_IRQHandler,
|
||||
[TIM1_BRK_IRQn + 16 ] = TIM1_BRK_IRQHandler,
|
||||
[TIM1_UP_IRQn + 16 ] = TIM1_UP_IRQHandler,
|
||||
[TIM1_TRG_COM_IRQn + 16 ] = TIM1_TRG_COM_IRQHandler,
|
||||
[TIM1_CC_IRQn + 16 ] = TIM1_CC_IRQHandler,
|
||||
[TIM2_IRQn + 16 ] = TIM2_IRQHandler,
|
||||
[TIM3_IRQn + 16 ] = TIM3_IRQHandler,
|
||||
[TIM4_IRQn + 16 ] = TIM4_IRQHandler,
|
||||
[I2C1_EV_IRQn + 16 ] = I2C1_EV_IRQHandler,
|
||||
[I2C1_ER_IRQn + 16 ] = I2C1_ER_IRQHandler,
|
||||
[I2C2_EV_IRQn + 16 ] = I2C2_EV_IRQHandler,
|
||||
[I2C2_ER_IRQn + 16 ] = I2C2_ER_IRQHandler,
|
||||
[SPI1_IRQn + 16 ] = SPI1_IRQHandler,
|
||||
[SPI2_IRQn + 16 ] = SPI2_IRQHandler,
|
||||
[USART1_IRQn + 16 ] = USART1_IRQHandler,
|
||||
[USART2_IRQn + 16 ] = USART2_IRQHandler,
|
||||
[USART3_IRQn + 16 ] = USART3_IRQHandler,
|
||||
[EXTI15_10_IRQn + 16 ] = EXTI15_10_IRQHandler,
|
||||
[RTC_Alarm_IRQn + 16 ] = RTC_Alarm_IRQHandler,
|
||||
[TIM8_BRK_TIM12_IRQn + 16 ] = TIM8_BRK_TIM12_IRQHandler,
|
||||
[TIM8_UP_TIM13_IRQn + 16 ] = TIM8_UP_TIM13_IRQHandler,
|
||||
[TIM8_TRG_COM_TIM14_IRQn + 16 ] = TIM8_TRG_COM_TIM14_IRQHandler,
|
||||
[TIM8_CC_IRQn + 16 ] = TIM8_CC_IRQHandler,
|
||||
[DMA1_Stream7_IRQn + 16 ] = DMA1_Stream7_IRQHandler,
|
||||
[FMC_IRQn + 16 ] = FMC_IRQHandler,
|
||||
[SDMMC1_IRQn + 16 ] = SDMMC1_IRQHandler,
|
||||
[TIM5_IRQn + 16 ] = TIM5_IRQHandler,
|
||||
[SPI3_IRQn + 16 ] = SPI3_IRQHandler,
|
||||
[UART4_IRQn + 16 ] = UART4_IRQHandler,
|
||||
[UART5_IRQn + 16 ] = UART5_IRQHandler,
|
||||
[TIM6_DAC_IRQn + 16 ] = TIM6_DAC_IRQHandler,
|
||||
[TIM7_IRQn + 16 ] = TIM7_IRQHandler,
|
||||
[DMA2_Stream0_IRQn + 16 ] = DMA2_Stream0_IRQHandler,
|
||||
[DMA2_Stream1_IRQn + 16 ] = DMA2_Stream1_IRQHandler,
|
||||
[DMA2_Stream2_IRQn + 16 ] = DMA2_Stream2_IRQHandler,
|
||||
[DMA2_Stream3_IRQn + 16 ] = DMA2_Stream3_IRQHandler,
|
||||
[DMA2_Stream4_IRQn + 16 ] = DMA2_Stream4_IRQHandler,
|
||||
[ETH_IRQn + 16 ] = ETH_IRQHandler,
|
||||
[ETH_WKUP_IRQn + 16 ] = ETH_WKUP_IRQHandler,
|
||||
[FDCAN_CAL_IRQn + 16 ] = FDCAN_CAL_IRQHandler,
|
||||
[CM7_SEV_IRQn + 16 ] = CM7_SEV_IRQHandler,
|
||||
[CM4_SEV_IRQn + 16 ] = CM4_SEV_IRQHandler,
|
||||
[DMA2_Stream5_IRQn + 16 ] = DMA2_Stream5_IRQHandler,
|
||||
[DMA2_Stream6_IRQn + 16 ] = DMA2_Stream6_IRQHandler,
|
||||
[DMA2_Stream7_IRQn + 16 ] = DMA2_Stream7_IRQHandler,
|
||||
[USART6_IRQn + 16 ] = USART6_IRQHandler,
|
||||
[I2C3_EV_IRQn + 16 ] = I2C3_EV_IRQHandler,
|
||||
[I2C3_ER_IRQn + 16 ] = I2C3_ER_IRQHandler,
|
||||
[OTG_HS_EP1_OUT_IRQn + 16 ] = OTG_HS_EP1_OUT_IRQHandler,
|
||||
[OTG_HS_EP1_IN_IRQn + 16 ] = OTG_HS_EP1_IN_IRQHandler,
|
||||
[OTG_HS_WKUP_IRQn + 16 ] = OTG_HS_WKUP_IRQHandler,
|
||||
[OTG_HS_IRQn + 16 ] = OTG_HS_IRQHandler,
|
||||
[DCMI_IRQn + 16 ] = DCMI_IRQHandler,
|
||||
[RNG_IRQn + 16 ] = RNG_IRQHandler,
|
||||
[FPU_IRQn + 16 ] = FPU_IRQHandler,
|
||||
[UART7_IRQn + 16 ] = UART7_IRQHandler,
|
||||
[UART8_IRQn + 16 ] = UART8_IRQHandler,
|
||||
[SPI4_IRQn + 16 ] = SPI4_IRQHandler,
|
||||
[SPI5_IRQn + 16 ] = SPI5_IRQHandler,
|
||||
[SPI6_IRQn + 16 ] = SPI6_IRQHandler,
|
||||
[SAI1_IRQn + 16 ] = SAI1_IRQHandler,
|
||||
[LTDC_IRQn + 16 ] = LTDC_IRQHandler,
|
||||
[LTDC_ER_IRQn + 16 ] = LTDC_ER_IRQHandler,
|
||||
[DMA2D_IRQn + 16 ] = DMA2D_IRQHandler,
|
||||
[SAI2_IRQn + 16 ] = SAI2_IRQHandler,
|
||||
[QUADSPI_IRQn + 16 ] = QUADSPI_IRQHandler,
|
||||
[LPTIM1_IRQn + 16 ] = LPTIM1_IRQHandler,
|
||||
[CEC_IRQn + 16 ] = CEC_IRQHandler,
|
||||
[I2C4_EV_IRQn + 16 ] = I2C4_EV_IRQHandler,
|
||||
[I2C4_ER_IRQn + 16 ] = I2C4_ER_IRQHandler,
|
||||
[SPDIF_RX_IRQn + 16 ] = SPDIF_RX_IRQHandler,
|
||||
[OTG_FS_EP1_OUT_IRQn + 16 ] = OTG_FS_EP1_OUT_IRQHandler,
|
||||
[OTG_FS_EP1_IN_IRQn + 16 ] = OTG_FS_EP1_IN_IRQHandler,
|
||||
[OTG_FS_WKUP_IRQn + 16 ] = OTG_FS_WKUP_IRQHandler,
|
||||
[OTG_FS_IRQn + 16 ] = OTG_FS_IRQHandler,
|
||||
[DMAMUX1_OVR_IRQn + 16 ] = DMAMUX1_OVR_IRQHandler,
|
||||
[HRTIM1_Master_IRQn + 16 ] = HRTIM1_Master_IRQHandler,
|
||||
[HRTIM1_TIMA_IRQn + 16 ] = HRTIM1_TIMA_IRQHandler,
|
||||
[HRTIM1_TIMB_IRQn + 16 ] = HRTIM1_TIMB_IRQHandler,
|
||||
[HRTIM1_TIMC_IRQn + 16 ] = HRTIM1_TIMC_IRQHandler,
|
||||
[HRTIM1_TIMD_IRQn + 16 ] = HRTIM1_TIMD_IRQHandler,
|
||||
[HRTIM1_TIME_IRQn + 16 ] = HRTIM1_TIME_IRQHandler,
|
||||
[HRTIM1_FLT_IRQn + 16 ] = HRTIM1_FLT_IRQHandler,
|
||||
[DFSDM1_FLT0_IRQn + 16 ] = DFSDM1_FLT0_IRQHandler,
|
||||
[DFSDM1_FLT1_IRQn + 16 ] = DFSDM1_FLT1_IRQHandler,
|
||||
[DFSDM1_FLT2_IRQn + 16 ] = DFSDM1_FLT2_IRQHandler,
|
||||
[DFSDM1_FLT3_IRQn + 16 ] = DFSDM1_FLT3_IRQHandler,
|
||||
[SAI3_IRQn + 16 ] = SAI3_IRQHandler,
|
||||
[SWPMI1_IRQn + 16 ] = SWPMI1_IRQHandler,
|
||||
[TIM15_IRQn + 16 ] = TIM15_IRQHandler,
|
||||
[TIM16_IRQn + 16 ] = TIM16_IRQHandler,
|
||||
[TIM17_IRQn + 16 ] = TIM17_IRQHandler,
|
||||
[MDIOS_WKUP_IRQn + 16 ] = MDIOS_WKUP_IRQHandler,
|
||||
[MDIOS_IRQn + 16 ] = MDIOS_IRQHandler,
|
||||
[JPEG_IRQn + 16 ] = JPEG_IRQHandler,
|
||||
[MDMA_IRQn + 16 ] = MDMA_IRQHandler,
|
||||
[DSI_IRQn + 16 ] = DSI_IRQHandler,
|
||||
[SDMMC2_IRQn + 16 ] = SDMMC2_IRQHandler,
|
||||
[HSEM1_IRQn + 16 ] = HSEM1_IRQHandler,
|
||||
[HSEM2_IRQn + 16 ] = HSEM2_IRQHandler,
|
||||
[ADC3_IRQn + 16 ] = ADC3_IRQHandler,
|
||||
[DMAMUX2_OVR_IRQn + 16 ] = DMAMUX2_OVR_IRQHandler,
|
||||
[BDMA_Channel0_IRQn + 16 ] = BDMA_Channel0_IRQHandler,
|
||||
[BDMA_Channel1_IRQn + 16 ] = BDMA_Channel1_IRQHandler,
|
||||
[BDMA_Channel2_IRQn + 16 ] = BDMA_Channel2_IRQHandler,
|
||||
[BDMA_Channel3_IRQn + 16 ] = BDMA_Channel3_IRQHandler,
|
||||
[BDMA_Channel4_IRQn + 16 ] = BDMA_Channel4_IRQHandler,
|
||||
[BDMA_Channel5_IRQn + 16 ] = BDMA_Channel5_IRQHandler,
|
||||
[BDMA_Channel6_IRQn + 16 ] = BDMA_Channel6_IRQHandler,
|
||||
[BDMA_Channel7_IRQn + 16 ] = BDMA_Channel7_IRQHandler,
|
||||
[COMP_IRQn + 16 ] = COMP_IRQHandler,
|
||||
[LPTIM2_IRQn + 16 ] = LPTIM2_IRQHandler,
|
||||
[LPTIM3_IRQn + 16 ] = LPTIM3_IRQHandler,
|
||||
[LPTIM4_IRQn + 16 ] = LPTIM4_IRQHandler,
|
||||
[LPTIM5_IRQn + 16 ] = LPTIM5_IRQHandler,
|
||||
[LPUART1_IRQn + 16 ] = LPUART1_IRQHandler,
|
||||
[WWDG_RST_IRQn + 16 ] = WWDG_RST_IRQHandler,
|
||||
[CRS_IRQn + 16 ] = CRS_IRQHandler,
|
||||
[ECC_IRQn + 16 ] = ECC_IRQHandler,
|
||||
[SAI4_IRQn + 16 ] = SAI4_IRQHandler,
|
||||
[HOLD_CORE_IRQn + 16 ] = HOLD_CORE_IRQHandler,
|
||||
[WAKEUP_PIN_IRQn + 16 ] = WAKEUP_PIN_IRQHandler,
|
||||
};
|
||||
|
||||
@@ -0,0 +1,318 @@
|
||||
|
||||
#include "stm32h750xx.h"
|
||||
#include "cortex_m_isr.h"
|
||||
|
||||
void Default_Handler() { default_isr_handler(); }
|
||||
|
||||
/* stm32h750xx specific interrupt vectors */
|
||||
WEAK_DEFAULT void Reset_Handler();
|
||||
WEAK_DEFAULT void NMI_Handler();
|
||||
WEAK_DEFAULT void HardFault_Handler();
|
||||
WEAK_DEFAULT void MemManage_Handler();
|
||||
WEAK_DEFAULT void BusFault_Handler();
|
||||
WEAK_DEFAULT void UsageFault_Handler();
|
||||
WEAK_DEFAULT void SVC_Handler();
|
||||
WEAK_DEFAULT void DebugMon_Handler();
|
||||
WEAK_DEFAULT void PendSV_Handler();
|
||||
WEAK_DEFAULT void SysTick_Handler();
|
||||
WEAK_DEFAULT void WWDG_IRQHandler();
|
||||
WEAK_DEFAULT void PVD_AVD_IRQHandler();
|
||||
WEAK_DEFAULT void TAMP_STAMP_IRQHandler();
|
||||
WEAK_DEFAULT void RTC_WKUP_IRQHandler();
|
||||
WEAK_DEFAULT void FLASH_IRQHandler();
|
||||
WEAK_DEFAULT void RCC_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI0_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI1_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI2_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI3_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI4_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream0_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream1_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream2_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream3_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream4_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream5_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream6_IRQHandler();
|
||||
WEAK_DEFAULT void ADC_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN1_IT0_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN2_IT0_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN1_IT1_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN2_IT1_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI9_5_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_BRK_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_UP_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_TRG_COM_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_CC_IRQHandler();
|
||||
WEAK_DEFAULT void TIM2_IRQHandler();
|
||||
WEAK_DEFAULT void TIM3_IRQHandler();
|
||||
WEAK_DEFAULT void TIM4_IRQHandler();
|
||||
WEAK_DEFAULT void I2C1_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I2C1_ER_IRQHandler();
|
||||
WEAK_DEFAULT void I2C2_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I2C2_ER_IRQHandler();
|
||||
WEAK_DEFAULT void SPI1_IRQHandler();
|
||||
WEAK_DEFAULT void SPI2_IRQHandler();
|
||||
WEAK_DEFAULT void USART1_IRQHandler();
|
||||
WEAK_DEFAULT void USART2_IRQHandler();
|
||||
WEAK_DEFAULT void USART3_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI15_10_IRQHandler();
|
||||
WEAK_DEFAULT void RTC_Alarm_IRQHandler();
|
||||
WEAK_DEFAULT void TIM8_BRK_TIM12_IRQHandler();
|
||||
WEAK_DEFAULT void TIM8_UP_TIM13_IRQHandler();
|
||||
WEAK_DEFAULT void TIM8_TRG_COM_TIM14_IRQHandler();
|
||||
WEAK_DEFAULT void TIM8_CC_IRQHandler();
|
||||
WEAK_DEFAULT void DMA1_Stream7_IRQHandler();
|
||||
WEAK_DEFAULT void FMC_IRQHandler();
|
||||
WEAK_DEFAULT void SDMMC1_IRQHandler();
|
||||
WEAK_DEFAULT void TIM5_IRQHandler();
|
||||
WEAK_DEFAULT void SPI3_IRQHandler();
|
||||
WEAK_DEFAULT void UART4_IRQHandler();
|
||||
WEAK_DEFAULT void UART5_IRQHandler();
|
||||
WEAK_DEFAULT void TIM6_DAC_IRQHandler();
|
||||
WEAK_DEFAULT void TIM7_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream0_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream1_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream2_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream3_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream4_IRQHandler();
|
||||
WEAK_DEFAULT void ETH_IRQHandler();
|
||||
WEAK_DEFAULT void ETH_WKUP_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN_CAL_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream5_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream6_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2_Stream7_IRQHandler();
|
||||
WEAK_DEFAULT void USART6_IRQHandler();
|
||||
WEAK_DEFAULT void I2C3_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I2C3_ER_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_HS_EP1_OUT_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_HS_EP1_IN_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_HS_WKUP_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_HS_IRQHandler();
|
||||
WEAK_DEFAULT void DCMI_IRQHandler();
|
||||
WEAK_DEFAULT void CRYP_IRQHandler();
|
||||
WEAK_DEFAULT void HASH_RNG_IRQHandler();
|
||||
WEAK_DEFAULT void FPU_IRQHandler();
|
||||
WEAK_DEFAULT void UART7_IRQHandler();
|
||||
WEAK_DEFAULT void UART8_IRQHandler();
|
||||
WEAK_DEFAULT void SPI4_IRQHandler();
|
||||
WEAK_DEFAULT void SPI5_IRQHandler();
|
||||
WEAK_DEFAULT void SPI6_IRQHandler();
|
||||
WEAK_DEFAULT void SAI1_IRQHandler();
|
||||
WEAK_DEFAULT void LTDC_IRQHandler();
|
||||
WEAK_DEFAULT void LTDC_ER_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2D_IRQHandler();
|
||||
WEAK_DEFAULT void SAI2_IRQHandler();
|
||||
WEAK_DEFAULT void QUADSPI_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM1_IRQHandler();
|
||||
WEAK_DEFAULT void CEC_IRQHandler();
|
||||
WEAK_DEFAULT void I2C4_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I2C4_ER_IRQHandler();
|
||||
WEAK_DEFAULT void SPDIF_RX_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_FS_EP1_OUT_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_FS_EP1_IN_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_FS_WKUP_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_FS_IRQHandler();
|
||||
WEAK_DEFAULT void DMAMUX1_OVR_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_Master_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_TIMA_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_TIMB_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_TIMC_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_TIMD_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_TIME_IRQHandler();
|
||||
WEAK_DEFAULT void HRTIM1_FLT_IRQHandler();
|
||||
WEAK_DEFAULT void DFSDM1_FLT0_IRQHandler();
|
||||
WEAK_DEFAULT void DFSDM1_FLT1_IRQHandler();
|
||||
WEAK_DEFAULT void DFSDM1_FLT2_IRQHandler();
|
||||
WEAK_DEFAULT void DFSDM1_FLT3_IRQHandler();
|
||||
WEAK_DEFAULT void SAI3_IRQHandler();
|
||||
WEAK_DEFAULT void SWPMI1_IRQHandler();
|
||||
WEAK_DEFAULT void TIM15_IRQHandler();
|
||||
WEAK_DEFAULT void TIM16_IRQHandler();
|
||||
WEAK_DEFAULT void TIM17_IRQHandler();
|
||||
WEAK_DEFAULT void MDIOS_WKUP_IRQHandler();
|
||||
WEAK_DEFAULT void MDIOS_IRQHandler();
|
||||
WEAK_DEFAULT void JPEG_IRQHandler();
|
||||
WEAK_DEFAULT void MDMA_IRQHandler();
|
||||
WEAK_DEFAULT void SDMMC2_IRQHandler();
|
||||
WEAK_DEFAULT void HSEM1_IRQHandler();
|
||||
WEAK_DEFAULT void ADC3_IRQHandler();
|
||||
WEAK_DEFAULT void DMAMUX2_OVR_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel0_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel1_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel2_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel3_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel4_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel5_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel6_IRQHandler();
|
||||
WEAK_DEFAULT void BDMA_Channel7_IRQHandler();
|
||||
WEAK_DEFAULT void COMP_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM2_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM3_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM4_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM5_IRQHandler();
|
||||
WEAK_DEFAULT void LPUART1_IRQHandler();
|
||||
WEAK_DEFAULT void CRS_IRQHandler();
|
||||
WEAK_DEFAULT void ECC_IRQHandler();
|
||||
WEAK_DEFAULT void SAI4_IRQHandler();
|
||||
WEAK_DEFAULT void WAKEUP_PIN_IRQHandler();
|
||||
|
||||
/* CPU specific interrupt vector table */
|
||||
const isr_t g_pnfVectors[] ISR_VECTOR = {
|
||||
[0] = (isr_t)&_estack,
|
||||
[1 ] = Reset_Handler,
|
||||
[2 ] = NMI_Handler,
|
||||
[3 ] = HardFault_Handler,
|
||||
[4 ] = MemManage_Handler,
|
||||
[5 ] = BusFault_Handler,
|
||||
[6 ] = UsageFault_Handler,
|
||||
[7 ] = 0,
|
||||
[8 ] = 0,
|
||||
[9 ] = 0,
|
||||
[10 ] = 0,
|
||||
[11 ] = SVC_Handler,
|
||||
[12 ] = DebugMon_Handler,
|
||||
[13 ] = 0,
|
||||
[14 ] = PendSV_Handler,
|
||||
[15 ] = SysTick_Handler,
|
||||
[WWDG_IRQn + 16 ] = WWDG_IRQHandler,
|
||||
[PVD_AVD_IRQn + 16 ] = PVD_AVD_IRQHandler,
|
||||
[TAMP_STAMP_IRQn + 16 ] = TAMP_STAMP_IRQHandler,
|
||||
[RTC_WKUP_IRQn + 16 ] = RTC_WKUP_IRQHandler,
|
||||
[FLASH_IRQn + 16 ] = FLASH_IRQHandler,
|
||||
[RCC_IRQn + 16 ] = RCC_IRQHandler,
|
||||
[EXTI0_IRQn + 16 ] = EXTI0_IRQHandler,
|
||||
[EXTI1_IRQn + 16 ] = EXTI1_IRQHandler,
|
||||
[EXTI2_IRQn + 16 ] = EXTI2_IRQHandler,
|
||||
[EXTI3_IRQn + 16 ] = EXTI3_IRQHandler,
|
||||
[EXTI4_IRQn + 16 ] = EXTI4_IRQHandler,
|
||||
[DMA1_Stream0_IRQn + 16 ] = DMA1_Stream0_IRQHandler,
|
||||
[DMA1_Stream1_IRQn + 16 ] = DMA1_Stream1_IRQHandler,
|
||||
[DMA1_Stream2_IRQn + 16 ] = DMA1_Stream2_IRQHandler,
|
||||
[DMA1_Stream3_IRQn + 16 ] = DMA1_Stream3_IRQHandler,
|
||||
[DMA1_Stream4_IRQn + 16 ] = DMA1_Stream4_IRQHandler,
|
||||
[DMA1_Stream5_IRQn + 16 ] = DMA1_Stream5_IRQHandler,
|
||||
[DMA1_Stream6_IRQn + 16 ] = DMA1_Stream6_IRQHandler,
|
||||
[ADC_IRQn + 16 ] = ADC_IRQHandler,
|
||||
[FDCAN1_IT0_IRQn + 16 ] = FDCAN1_IT0_IRQHandler,
|
||||
[FDCAN2_IT0_IRQn + 16 ] = FDCAN2_IT0_IRQHandler,
|
||||
[FDCAN1_IT1_IRQn + 16 ] = FDCAN1_IT1_IRQHandler,
|
||||
[FDCAN2_IT1_IRQn + 16 ] = FDCAN2_IT1_IRQHandler,
|
||||
[EXTI9_5_IRQn + 16 ] = EXTI9_5_IRQHandler,
|
||||
[TIM1_BRK_IRQn + 16 ] = TIM1_BRK_IRQHandler,
|
||||
[TIM1_UP_IRQn + 16 ] = TIM1_UP_IRQHandler,
|
||||
[TIM1_TRG_COM_IRQn + 16 ] = TIM1_TRG_COM_IRQHandler,
|
||||
[TIM1_CC_IRQn + 16 ] = TIM1_CC_IRQHandler,
|
||||
[TIM2_IRQn + 16 ] = TIM2_IRQHandler,
|
||||
[TIM3_IRQn + 16 ] = TIM3_IRQHandler,
|
||||
[TIM4_IRQn + 16 ] = TIM4_IRQHandler,
|
||||
[I2C1_EV_IRQn + 16 ] = I2C1_EV_IRQHandler,
|
||||
[I2C1_ER_IRQn + 16 ] = I2C1_ER_IRQHandler,
|
||||
[I2C2_EV_IRQn + 16 ] = I2C2_EV_IRQHandler,
|
||||
[I2C2_ER_IRQn + 16 ] = I2C2_ER_IRQHandler,
|
||||
[SPI1_IRQn + 16 ] = SPI1_IRQHandler,
|
||||
[SPI2_IRQn + 16 ] = SPI2_IRQHandler,
|
||||
[USART1_IRQn + 16 ] = USART1_IRQHandler,
|
||||
[USART2_IRQn + 16 ] = USART2_IRQHandler,
|
||||
[USART3_IRQn + 16 ] = USART3_IRQHandler,
|
||||
[EXTI15_10_IRQn + 16 ] = EXTI15_10_IRQHandler,
|
||||
[RTC_Alarm_IRQn + 16 ] = RTC_Alarm_IRQHandler,
|
||||
[TIM8_BRK_TIM12_IRQn + 16 ] = TIM8_BRK_TIM12_IRQHandler,
|
||||
[TIM8_UP_TIM13_IRQn + 16 ] = TIM8_UP_TIM13_IRQHandler,
|
||||
[TIM8_TRG_COM_TIM14_IRQn + 16 ] = TIM8_TRG_COM_TIM14_IRQHandler,
|
||||
[TIM8_CC_IRQn + 16 ] = TIM8_CC_IRQHandler,
|
||||
[DMA1_Stream7_IRQn + 16 ] = DMA1_Stream7_IRQHandler,
|
||||
[FMC_IRQn + 16 ] = FMC_IRQHandler,
|
||||
[SDMMC1_IRQn + 16 ] = SDMMC1_IRQHandler,
|
||||
[TIM5_IRQn + 16 ] = TIM5_IRQHandler,
|
||||
[SPI3_IRQn + 16 ] = SPI3_IRQHandler,
|
||||
[UART4_IRQn + 16 ] = UART4_IRQHandler,
|
||||
[UART5_IRQn + 16 ] = UART5_IRQHandler,
|
||||
[TIM6_DAC_IRQn + 16 ] = TIM6_DAC_IRQHandler,
|
||||
[TIM7_IRQn + 16 ] = TIM7_IRQHandler,
|
||||
[DMA2_Stream0_IRQn + 16 ] = DMA2_Stream0_IRQHandler,
|
||||
[DMA2_Stream1_IRQn + 16 ] = DMA2_Stream1_IRQHandler,
|
||||
[DMA2_Stream2_IRQn + 16 ] = DMA2_Stream2_IRQHandler,
|
||||
[DMA2_Stream3_IRQn + 16 ] = DMA2_Stream3_IRQHandler,
|
||||
[DMA2_Stream4_IRQn + 16 ] = DMA2_Stream4_IRQHandler,
|
||||
[ETH_IRQn + 16 ] = ETH_IRQHandler,
|
||||
[ETH_WKUP_IRQn + 16 ] = ETH_WKUP_IRQHandler,
|
||||
[FDCAN_CAL_IRQn + 16 ] = FDCAN_CAL_IRQHandler,
|
||||
[DMA2_Stream5_IRQn + 16 ] = DMA2_Stream5_IRQHandler,
|
||||
[DMA2_Stream6_IRQn + 16 ] = DMA2_Stream6_IRQHandler,
|
||||
[DMA2_Stream7_IRQn + 16 ] = DMA2_Stream7_IRQHandler,
|
||||
[USART6_IRQn + 16 ] = USART6_IRQHandler,
|
||||
[I2C3_EV_IRQn + 16 ] = I2C3_EV_IRQHandler,
|
||||
[I2C3_ER_IRQn + 16 ] = I2C3_ER_IRQHandler,
|
||||
[OTG_HS_EP1_OUT_IRQn + 16 ] = OTG_HS_EP1_OUT_IRQHandler,
|
||||
[OTG_HS_EP1_IN_IRQn + 16 ] = OTG_HS_EP1_IN_IRQHandler,
|
||||
[OTG_HS_WKUP_IRQn + 16 ] = OTG_HS_WKUP_IRQHandler,
|
||||
[OTG_HS_IRQn + 16 ] = OTG_HS_IRQHandler,
|
||||
[DCMI_IRQn + 16 ] = DCMI_IRQHandler,
|
||||
[CRYP_IRQn + 16 ] = CRYP_IRQHandler,
|
||||
[HASH_RNG_IRQn + 16 ] = HASH_RNG_IRQHandler,
|
||||
[FPU_IRQn + 16 ] = FPU_IRQHandler,
|
||||
[UART7_IRQn + 16 ] = UART7_IRQHandler,
|
||||
[UART8_IRQn + 16 ] = UART8_IRQHandler,
|
||||
[SPI4_IRQn + 16 ] = SPI4_IRQHandler,
|
||||
[SPI5_IRQn + 16 ] = SPI5_IRQHandler,
|
||||
[SPI6_IRQn + 16 ] = SPI6_IRQHandler,
|
||||
[SAI1_IRQn + 16 ] = SAI1_IRQHandler,
|
||||
[LTDC_IRQn + 16 ] = LTDC_IRQHandler,
|
||||
[LTDC_ER_IRQn + 16 ] = LTDC_ER_IRQHandler,
|
||||
[DMA2D_IRQn + 16 ] = DMA2D_IRQHandler,
|
||||
[SAI2_IRQn + 16 ] = SAI2_IRQHandler,
|
||||
[QUADSPI_IRQn + 16 ] = QUADSPI_IRQHandler,
|
||||
[LPTIM1_IRQn + 16 ] = LPTIM1_IRQHandler,
|
||||
[CEC_IRQn + 16 ] = CEC_IRQHandler,
|
||||
[I2C4_EV_IRQn + 16 ] = I2C4_EV_IRQHandler,
|
||||
[I2C4_ER_IRQn + 16 ] = I2C4_ER_IRQHandler,
|
||||
[SPDIF_RX_IRQn + 16 ] = SPDIF_RX_IRQHandler,
|
||||
[OTG_FS_EP1_OUT_IRQn + 16 ] = OTG_FS_EP1_OUT_IRQHandler,
|
||||
[OTG_FS_EP1_IN_IRQn + 16 ] = OTG_FS_EP1_IN_IRQHandler,
|
||||
[OTG_FS_WKUP_IRQn + 16 ] = OTG_FS_WKUP_IRQHandler,
|
||||
[OTG_FS_IRQn + 16 ] = OTG_FS_IRQHandler,
|
||||
[DMAMUX1_OVR_IRQn + 16 ] = DMAMUX1_OVR_IRQHandler,
|
||||
[HRTIM1_Master_IRQn + 16 ] = HRTIM1_Master_IRQHandler,
|
||||
[HRTIM1_TIMA_IRQn + 16 ] = HRTIM1_TIMA_IRQHandler,
|
||||
[HRTIM1_TIMB_IRQn + 16 ] = HRTIM1_TIMB_IRQHandler,
|
||||
[HRTIM1_TIMC_IRQn + 16 ] = HRTIM1_TIMC_IRQHandler,
|
||||
[HRTIM1_TIMD_IRQn + 16 ] = HRTIM1_TIMD_IRQHandler,
|
||||
[HRTIM1_TIME_IRQn + 16 ] = HRTIM1_TIME_IRQHandler,
|
||||
[HRTIM1_FLT_IRQn + 16 ] = HRTIM1_FLT_IRQHandler,
|
||||
[DFSDM1_FLT0_IRQn + 16 ] = DFSDM1_FLT0_IRQHandler,
|
||||
[DFSDM1_FLT1_IRQn + 16 ] = DFSDM1_FLT1_IRQHandler,
|
||||
[DFSDM1_FLT2_IRQn + 16 ] = DFSDM1_FLT2_IRQHandler,
|
||||
[DFSDM1_FLT3_IRQn + 16 ] = DFSDM1_FLT3_IRQHandler,
|
||||
[SAI3_IRQn + 16 ] = SAI3_IRQHandler,
|
||||
[SWPMI1_IRQn + 16 ] = SWPMI1_IRQHandler,
|
||||
[TIM15_IRQn + 16 ] = TIM15_IRQHandler,
|
||||
[TIM16_IRQn + 16 ] = TIM16_IRQHandler,
|
||||
[TIM17_IRQn + 16 ] = TIM17_IRQHandler,
|
||||
[MDIOS_WKUP_IRQn + 16 ] = MDIOS_WKUP_IRQHandler,
|
||||
[MDIOS_IRQn + 16 ] = MDIOS_IRQHandler,
|
||||
[JPEG_IRQn + 16 ] = JPEG_IRQHandler,
|
||||
[MDMA_IRQn + 16 ] = MDMA_IRQHandler,
|
||||
[SDMMC2_IRQn + 16 ] = SDMMC2_IRQHandler,
|
||||
[HSEM1_IRQn + 16 ] = HSEM1_IRQHandler,
|
||||
[ADC3_IRQn + 16 ] = ADC3_IRQHandler,
|
||||
[DMAMUX2_OVR_IRQn + 16 ] = DMAMUX2_OVR_IRQHandler,
|
||||
[BDMA_Channel0_IRQn + 16 ] = BDMA_Channel0_IRQHandler,
|
||||
[BDMA_Channel1_IRQn + 16 ] = BDMA_Channel1_IRQHandler,
|
||||
[BDMA_Channel2_IRQn + 16 ] = BDMA_Channel2_IRQHandler,
|
||||
[BDMA_Channel3_IRQn + 16 ] = BDMA_Channel3_IRQHandler,
|
||||
[BDMA_Channel4_IRQn + 16 ] = BDMA_Channel4_IRQHandler,
|
||||
[BDMA_Channel5_IRQn + 16 ] = BDMA_Channel5_IRQHandler,
|
||||
[BDMA_Channel6_IRQn + 16 ] = BDMA_Channel6_IRQHandler,
|
||||
[BDMA_Channel7_IRQn + 16 ] = BDMA_Channel7_IRQHandler,
|
||||
[COMP_IRQn + 16 ] = COMP_IRQHandler,
|
||||
[LPTIM2_IRQn + 16 ] = LPTIM2_IRQHandler,
|
||||
[LPTIM3_IRQn + 16 ] = LPTIM3_IRQHandler,
|
||||
[LPTIM4_IRQn + 16 ] = LPTIM4_IRQHandler,
|
||||
[LPTIM5_IRQn + 16 ] = LPTIM5_IRQHandler,
|
||||
[LPUART1_IRQn + 16 ] = LPUART1_IRQHandler,
|
||||
[CRS_IRQn + 16 ] = CRS_IRQHandler,
|
||||
[ECC_IRQn + 16 ] = ECC_IRQHandler,
|
||||
[SAI4_IRQn + 16 ] = SAI4_IRQHandler,
|
||||
[WAKEUP_PIN_IRQn + 16 ] = WAKEUP_PIN_IRQHandler,
|
||||
};
|
||||
|
||||
@@ -0,0 +1,332 @@
|
||||
|
||||
#include "stm32h7s7xx.h"
|
||||
#include "cortex_m_isr.h"
|
||||
|
||||
void Default_Handler() { default_isr_handler(); }
|
||||
|
||||
/* stm32h7s7xx specific interrupt vectors */
|
||||
WEAK_DEFAULT void Reset_Handler();
|
||||
WEAK_DEFAULT void NMI_Handler();
|
||||
WEAK_DEFAULT void HardFault_Handler();
|
||||
WEAK_DEFAULT void MemManage_Handler();
|
||||
WEAK_DEFAULT void BusFault_Handler();
|
||||
WEAK_DEFAULT void UsageFault_Handler();
|
||||
WEAK_DEFAULT void SVC_Handler();
|
||||
WEAK_DEFAULT void DebugMon_Handler();
|
||||
WEAK_DEFAULT void PendSV_Handler();
|
||||
WEAK_DEFAULT void SysTick_Handler();
|
||||
WEAK_DEFAULT void PVD_PVM_IRQHandler();
|
||||
WEAK_DEFAULT void DTS_IRQHandler();
|
||||
WEAK_DEFAULT void IWDG_IRQHandler();
|
||||
WEAK_DEFAULT void WWDG_IRQHandler();
|
||||
WEAK_DEFAULT void RCC_IRQHandler();
|
||||
WEAK_DEFAULT void FLASH_IRQHandler();
|
||||
WEAK_DEFAULT void RAMECC_IRQHandler();
|
||||
WEAK_DEFAULT void FPU_IRQHandler();
|
||||
WEAK_DEFAULT void TAMP_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI0_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI1_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI2_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI3_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI4_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI5_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI6_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI7_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI8_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI9_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI10_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI11_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI12_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI13_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI14_IRQHandler();
|
||||
WEAK_DEFAULT void EXTI15_IRQHandler();
|
||||
WEAK_DEFAULT void RTC_IRQHandler();
|
||||
WEAK_DEFAULT void SAES_IRQHandler();
|
||||
WEAK_DEFAULT void CRYP_IRQHandler();
|
||||
WEAK_DEFAULT void PKA_IRQHandler();
|
||||
WEAK_DEFAULT void HASH_IRQHandler();
|
||||
WEAK_DEFAULT void RNG_IRQHandler();
|
||||
WEAK_DEFAULT void ADC1_2_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel0_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel1_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel2_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel3_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel4_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel5_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel6_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel7_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_BRK_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_UP_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_TRG_COM_IRQHandler();
|
||||
WEAK_DEFAULT void TIM1_CC_IRQHandler();
|
||||
WEAK_DEFAULT void TIM2_IRQHandler();
|
||||
WEAK_DEFAULT void TIM3_IRQHandler();
|
||||
WEAK_DEFAULT void TIM4_IRQHandler();
|
||||
WEAK_DEFAULT void TIM5_IRQHandler();
|
||||
WEAK_DEFAULT void TIM6_IRQHandler();
|
||||
WEAK_DEFAULT void TIM7_IRQHandler();
|
||||
WEAK_DEFAULT void TIM9_IRQHandler();
|
||||
WEAK_DEFAULT void SPI1_IRQHandler();
|
||||
WEAK_DEFAULT void SPI2_IRQHandler();
|
||||
WEAK_DEFAULT void SPI3_IRQHandler();
|
||||
WEAK_DEFAULT void SPI4_IRQHandler();
|
||||
WEAK_DEFAULT void SPI5_IRQHandler();
|
||||
WEAK_DEFAULT void SPI6_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel0_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel1_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel2_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel3_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel4_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel5_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel6_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel7_IRQHandler();
|
||||
WEAK_DEFAULT void SAI1_A_IRQHandler();
|
||||
WEAK_DEFAULT void SAI1_B_IRQHandler();
|
||||
WEAK_DEFAULT void SAI2_A_IRQHandler();
|
||||
WEAK_DEFAULT void SAI2_B_IRQHandler();
|
||||
WEAK_DEFAULT void I2C1_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I2C1_ER_IRQHandler();
|
||||
WEAK_DEFAULT void I2C2_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I2C2_ER_IRQHandler();
|
||||
WEAK_DEFAULT void I2C3_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I2C3_ER_IRQHandler();
|
||||
WEAK_DEFAULT void USART1_IRQHandler();
|
||||
WEAK_DEFAULT void USART2_IRQHandler();
|
||||
WEAK_DEFAULT void USART3_IRQHandler();
|
||||
WEAK_DEFAULT void UART4_IRQHandler();
|
||||
WEAK_DEFAULT void UART5_IRQHandler();
|
||||
WEAK_DEFAULT void UART7_IRQHandler();
|
||||
WEAK_DEFAULT void UART8_IRQHandler();
|
||||
WEAK_DEFAULT void I3C1_EV_IRQHandler();
|
||||
WEAK_DEFAULT void I3C1_ER_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_HS_IRQHandler();
|
||||
WEAK_DEFAULT void ETH_IRQHandler();
|
||||
WEAK_DEFAULT void CORDIC_IRQHandler();
|
||||
WEAK_DEFAULT void GFXTIM_IRQHandler();
|
||||
WEAK_DEFAULT void DCMIPP_IRQHandler();
|
||||
WEAK_DEFAULT void LTDC_IRQHandler();
|
||||
WEAK_DEFAULT void LTDC_ER_IRQHandler();
|
||||
WEAK_DEFAULT void DMA2D_IRQHandler();
|
||||
WEAK_DEFAULT void JPEG_IRQHandler();
|
||||
WEAK_DEFAULT void GFXMMU_IRQHandler();
|
||||
WEAK_DEFAULT void I3C1_WKUP_IRQHandler();
|
||||
WEAK_DEFAULT void MCE1_IRQHandler();
|
||||
WEAK_DEFAULT void MCE2_IRQHandler();
|
||||
WEAK_DEFAULT void MCE3_IRQHandler();
|
||||
WEAK_DEFAULT void XSPI1_IRQHandler();
|
||||
WEAK_DEFAULT void XSPI2_IRQHandler();
|
||||
WEAK_DEFAULT void FMC_IRQHandler();
|
||||
WEAK_DEFAULT void SDMMC1_IRQHandler();
|
||||
WEAK_DEFAULT void SDMMC2_IRQHandler();
|
||||
WEAK_DEFAULT void OTG_FS_IRQHandler();
|
||||
WEAK_DEFAULT void TIM12_IRQHandler();
|
||||
WEAK_DEFAULT void TIM13_IRQHandler();
|
||||
WEAK_DEFAULT void TIM14_IRQHandler();
|
||||
WEAK_DEFAULT void TIM15_IRQHandler();
|
||||
WEAK_DEFAULT void TIM16_IRQHandler();
|
||||
WEAK_DEFAULT void TIM17_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM1_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM2_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM3_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM4_IRQHandler();
|
||||
WEAK_DEFAULT void LPTIM5_IRQHandler();
|
||||
WEAK_DEFAULT void SPDIF_RX_IRQHandler();
|
||||
WEAK_DEFAULT void MDIOS_IRQHandler();
|
||||
WEAK_DEFAULT void ADF1_FLT0_IRQHandler();
|
||||
WEAK_DEFAULT void CRS_IRQHandler();
|
||||
WEAK_DEFAULT void UCPD1_IRQHandler();
|
||||
WEAK_DEFAULT void CEC_IRQHandler();
|
||||
WEAK_DEFAULT void PSSI_IRQHandler();
|
||||
WEAK_DEFAULT void LPUART1_IRQHandler();
|
||||
WEAK_DEFAULT void WAKEUP_PIN_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel8_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel9_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel10_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel11_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel12_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel13_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel14_IRQHandler();
|
||||
WEAK_DEFAULT void GPDMA1_Channel15_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel8_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel9_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel10_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel11_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel12_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel13_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel14_IRQHandler();
|
||||
WEAK_DEFAULT void HPDMA1_Channel15_IRQHandler();
|
||||
WEAK_DEFAULT void GPU2D_IRQHandler();
|
||||
WEAK_DEFAULT void GPU2D_ER_IRQHandler();
|
||||
WEAK_DEFAULT void ICACHE_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN1_IT0_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN1_IT1_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN2_IT0_IRQHandler();
|
||||
WEAK_DEFAULT void FDCAN2_IT1_IRQHandler();
|
||||
|
||||
/* CPU specific interrupt vector table */
|
||||
const isr_t _isr_vector[] ISR_VECTOR = {
|
||||
[0] = (isr_t)&_estack,
|
||||
[1 ] = Reset_Handler,
|
||||
[2 ] = NMI_Handler,
|
||||
[3 ] = HardFault_Handler,
|
||||
[4 ] = MemManage_Handler,
|
||||
[5 ] = BusFault_Handler,
|
||||
[6 ] = UsageFault_Handler,
|
||||
[7 ] = 0,
|
||||
[8 ] = 0,
|
||||
[9 ] = 0,
|
||||
[10 ] = 0,
|
||||
[11 ] = SVC_Handler,
|
||||
[12 ] = DebugMon_Handler,
|
||||
[13 ] = 0,
|
||||
[14 ] = PendSV_Handler,
|
||||
[15 ] = SysTick_Handler,
|
||||
[PVD_PVM_IRQn + 16 ] = PVD_PVM_IRQHandler,
|
||||
[DTS_IRQn + 16 ] = DTS_IRQHandler,
|
||||
[IWDG_IRQn + 16 ] = IWDG_IRQHandler,
|
||||
[WWDG_IRQn + 16 ] = WWDG_IRQHandler,
|
||||
[RCC_IRQn + 16 ] = RCC_IRQHandler,
|
||||
[FLASH_IRQn + 16 ] = FLASH_IRQHandler,
|
||||
[RAMECC_IRQn + 16 ] = RAMECC_IRQHandler,
|
||||
[FPU_IRQn + 16 ] = FPU_IRQHandler,
|
||||
[TAMP_IRQn + 16 ] = TAMP_IRQHandler,
|
||||
[EXTI0_IRQn + 16 ] = EXTI0_IRQHandler,
|
||||
[EXTI1_IRQn + 16 ] = EXTI1_IRQHandler,
|
||||
[EXTI2_IRQn + 16 ] = EXTI2_IRQHandler,
|
||||
[EXTI3_IRQn + 16 ] = EXTI3_IRQHandler,
|
||||
[EXTI4_IRQn + 16 ] = EXTI4_IRQHandler,
|
||||
[EXTI5_IRQn + 16 ] = EXTI5_IRQHandler,
|
||||
[EXTI6_IRQn + 16 ] = EXTI6_IRQHandler,
|
||||
[EXTI7_IRQn + 16 ] = EXTI7_IRQHandler,
|
||||
[EXTI8_IRQn + 16 ] = EXTI8_IRQHandler,
|
||||
[EXTI9_IRQn + 16 ] = EXTI9_IRQHandler,
|
||||
[EXTI10_IRQn + 16 ] = EXTI10_IRQHandler,
|
||||
[EXTI11_IRQn + 16 ] = EXTI11_IRQHandler,
|
||||
[EXTI12_IRQn + 16 ] = EXTI12_IRQHandler,
|
||||
[EXTI13_IRQn + 16 ] = EXTI13_IRQHandler,
|
||||
[EXTI14_IRQn + 16 ] = EXTI14_IRQHandler,
|
||||
[EXTI15_IRQn + 16 ] = EXTI15_IRQHandler,
|
||||
[RTC_IRQn + 16 ] = RTC_IRQHandler,
|
||||
[SAES_IRQn + 16 ] = SAES_IRQHandler,
|
||||
[CRYP_IRQn + 16 ] = CRYP_IRQHandler,
|
||||
[PKA_IRQn + 16 ] = PKA_IRQHandler,
|
||||
[HASH_IRQn + 16 ] = HASH_IRQHandler,
|
||||
[RNG_IRQn + 16 ] = RNG_IRQHandler,
|
||||
[ADC1_2_IRQn + 16 ] = ADC1_2_IRQHandler,
|
||||
[GPDMA1_Channel0_IRQn + 16 ] = GPDMA1_Channel0_IRQHandler,
|
||||
[GPDMA1_Channel1_IRQn + 16 ] = GPDMA1_Channel1_IRQHandler,
|
||||
[GPDMA1_Channel2_IRQn + 16 ] = GPDMA1_Channel2_IRQHandler,
|
||||
[GPDMA1_Channel3_IRQn + 16 ] = GPDMA1_Channel3_IRQHandler,
|
||||
[GPDMA1_Channel4_IRQn + 16 ] = GPDMA1_Channel4_IRQHandler,
|
||||
[GPDMA1_Channel5_IRQn + 16 ] = GPDMA1_Channel5_IRQHandler,
|
||||
[GPDMA1_Channel6_IRQn + 16 ] = GPDMA1_Channel6_IRQHandler,
|
||||
[GPDMA1_Channel7_IRQn + 16 ] = GPDMA1_Channel7_IRQHandler,
|
||||
[TIM1_BRK_IRQn + 16 ] = TIM1_BRK_IRQHandler,
|
||||
[TIM1_UP_IRQn + 16 ] = TIM1_UP_IRQHandler,
|
||||
[TIM1_TRG_COM_IRQn + 16 ] = TIM1_TRG_COM_IRQHandler,
|
||||
[TIM1_CC_IRQn + 16 ] = TIM1_CC_IRQHandler,
|
||||
[TIM2_IRQn + 16 ] = TIM2_IRQHandler,
|
||||
[TIM3_IRQn + 16 ] = TIM3_IRQHandler,
|
||||
[TIM4_IRQn + 16 ] = TIM4_IRQHandler,
|
||||
[TIM5_IRQn + 16 ] = TIM5_IRQHandler,
|
||||
[TIM6_IRQn + 16 ] = TIM6_IRQHandler,
|
||||
[TIM7_IRQn + 16 ] = TIM7_IRQHandler,
|
||||
[TIM9_IRQn + 16 ] = TIM9_IRQHandler,
|
||||
[SPI1_IRQn + 16 ] = SPI1_IRQHandler,
|
||||
[SPI2_IRQn + 16 ] = SPI2_IRQHandler,
|
||||
[SPI3_IRQn + 16 ] = SPI3_IRQHandler,
|
||||
[SPI4_IRQn + 16 ] = SPI4_IRQHandler,
|
||||
[SPI5_IRQn + 16 ] = SPI5_IRQHandler,
|
||||
[SPI6_IRQn + 16 ] = SPI6_IRQHandler,
|
||||
[HPDMA1_Channel0_IRQn + 16 ] = HPDMA1_Channel0_IRQHandler,
|
||||
[HPDMA1_Channel1_IRQn + 16 ] = HPDMA1_Channel1_IRQHandler,
|
||||
[HPDMA1_Channel2_IRQn + 16 ] = HPDMA1_Channel2_IRQHandler,
|
||||
[HPDMA1_Channel3_IRQn + 16 ] = HPDMA1_Channel3_IRQHandler,
|
||||
[HPDMA1_Channel4_IRQn + 16 ] = HPDMA1_Channel4_IRQHandler,
|
||||
[HPDMA1_Channel5_IRQn + 16 ] = HPDMA1_Channel5_IRQHandler,
|
||||
[HPDMA1_Channel6_IRQn + 16 ] = HPDMA1_Channel6_IRQHandler,
|
||||
[HPDMA1_Channel7_IRQn + 16 ] = HPDMA1_Channel7_IRQHandler,
|
||||
[SAI1_A_IRQn + 16 ] = SAI1_A_IRQHandler,
|
||||
[SAI1_B_IRQn + 16 ] = SAI1_B_IRQHandler,
|
||||
[SAI2_A_IRQn + 16 ] = SAI2_A_IRQHandler,
|
||||
[SAI2_B_IRQn + 16 ] = SAI2_B_IRQHandler,
|
||||
[I2C1_EV_IRQn + 16 ] = I2C1_EV_IRQHandler,
|
||||
[I2C1_ER_IRQn + 16 ] = I2C1_ER_IRQHandler,
|
||||
[I2C2_EV_IRQn + 16 ] = I2C2_EV_IRQHandler,
|
||||
[I2C2_ER_IRQn + 16 ] = I2C2_ER_IRQHandler,
|
||||
[I2C3_EV_IRQn + 16 ] = I2C3_EV_IRQHandler,
|
||||
[I2C3_ER_IRQn + 16 ] = I2C3_ER_IRQHandler,
|
||||
[USART1_IRQn + 16 ] = USART1_IRQHandler,
|
||||
[USART2_IRQn + 16 ] = USART2_IRQHandler,
|
||||
[USART3_IRQn + 16 ] = USART3_IRQHandler,
|
||||
[UART4_IRQn + 16 ] = UART4_IRQHandler,
|
||||
[UART5_IRQn + 16 ] = UART5_IRQHandler,
|
||||
[UART7_IRQn + 16 ] = UART7_IRQHandler,
|
||||
[UART8_IRQn + 16 ] = UART8_IRQHandler,
|
||||
[I3C1_EV_IRQn + 16 ] = I3C1_EV_IRQHandler,
|
||||
[I3C1_ER_IRQn + 16 ] = I3C1_ER_IRQHandler,
|
||||
[OTG_HS_IRQn + 16 ] = OTG_HS_IRQHandler,
|
||||
[ETH_IRQn + 16 ] = ETH_IRQHandler,
|
||||
[CORDIC_IRQn + 16 ] = CORDIC_IRQHandler,
|
||||
[GFXTIM_IRQn + 16 ] = GFXTIM_IRQHandler,
|
||||
[DCMIPP_IRQn + 16 ] = DCMIPP_IRQHandler,
|
||||
[LTDC_IRQn + 16 ] = LTDC_IRQHandler,
|
||||
[LTDC_ER_IRQn + 16 ] = LTDC_ER_IRQHandler,
|
||||
[DMA2D_IRQn + 16 ] = DMA2D_IRQHandler,
|
||||
[JPEG_IRQn + 16 ] = JPEG_IRQHandler,
|
||||
[GFXMMU_IRQn + 16 ] = GFXMMU_IRQHandler,
|
||||
[I3C1_WKUP_IRQn + 16 ] = I3C1_WKUP_IRQHandler,
|
||||
[MCE1_IRQn + 16 ] = MCE1_IRQHandler,
|
||||
[MCE2_IRQn + 16 ] = MCE2_IRQHandler,
|
||||
[MCE3_IRQn + 16 ] = MCE3_IRQHandler,
|
||||
[XSPI1_IRQn + 16 ] = XSPI1_IRQHandler,
|
||||
[XSPI2_IRQn + 16 ] = XSPI2_IRQHandler,
|
||||
[FMC_IRQn + 16 ] = FMC_IRQHandler,
|
||||
[SDMMC1_IRQn + 16 ] = SDMMC1_IRQHandler,
|
||||
[SDMMC2_IRQn + 16 ] = SDMMC2_IRQHandler,
|
||||
[OTG_FS_IRQn + 16 ] = OTG_FS_IRQHandler,
|
||||
[TIM12_IRQn + 16 ] = TIM12_IRQHandler,
|
||||
[TIM13_IRQn + 16 ] = TIM13_IRQHandler,
|
||||
[TIM14_IRQn + 16 ] = TIM14_IRQHandler,
|
||||
[TIM15_IRQn + 16 ] = TIM15_IRQHandler,
|
||||
[TIM16_IRQn + 16 ] = TIM16_IRQHandler,
|
||||
[TIM17_IRQn + 16 ] = TIM17_IRQHandler,
|
||||
[LPTIM1_IRQn + 16 ] = LPTIM1_IRQHandler,
|
||||
[LPTIM2_IRQn + 16 ] = LPTIM2_IRQHandler,
|
||||
[LPTIM3_IRQn + 16 ] = LPTIM3_IRQHandler,
|
||||
[LPTIM4_IRQn + 16 ] = LPTIM4_IRQHandler,
|
||||
[LPTIM5_IRQn + 16 ] = LPTIM5_IRQHandler,
|
||||
[SPDIF_RX_IRQn + 16 ] = SPDIF_RX_IRQHandler,
|
||||
[MDIOS_IRQn + 16 ] = MDIOS_IRQHandler,
|
||||
[ADF1_FLT0_IRQn + 16 ] = ADF1_FLT0_IRQHandler,
|
||||
[CRS_IRQn + 16 ] = CRS_IRQHandler,
|
||||
[UCPD1_IRQn + 16 ] = UCPD1_IRQHandler,
|
||||
[CEC_IRQn + 16 ] = CEC_IRQHandler,
|
||||
[PSSI_IRQn + 16 ] = PSSI_IRQHandler,
|
||||
[LPUART1_IRQn + 16 ] = LPUART1_IRQHandler,
|
||||
[WAKEUP_PIN_IRQn + 16 ] = WAKEUP_PIN_IRQHandler,
|
||||
[GPDMA1_Channel8_IRQn + 16 ] = GPDMA1_Channel8_IRQHandler,
|
||||
[GPDMA1_Channel9_IRQn + 16 ] = GPDMA1_Channel9_IRQHandler,
|
||||
[GPDMA1_Channel10_IRQn + 16 ] = GPDMA1_Channel10_IRQHandler,
|
||||
[GPDMA1_Channel11_IRQn + 16 ] = GPDMA1_Channel11_IRQHandler,
|
||||
[GPDMA1_Channel12_IRQn + 16 ] = GPDMA1_Channel12_IRQHandler,
|
||||
[GPDMA1_Channel13_IRQn + 16 ] = GPDMA1_Channel13_IRQHandler,
|
||||
[GPDMA1_Channel14_IRQn + 16 ] = GPDMA1_Channel14_IRQHandler,
|
||||
[GPDMA1_Channel15_IRQn + 16 ] = GPDMA1_Channel15_IRQHandler,
|
||||
[HPDMA1_Channel8_IRQn + 16 ] = HPDMA1_Channel8_IRQHandler,
|
||||
[HPDMA1_Channel9_IRQn + 16 ] = HPDMA1_Channel9_IRQHandler,
|
||||
[HPDMA1_Channel10_IRQn + 16 ] = HPDMA1_Channel10_IRQHandler,
|
||||
[HPDMA1_Channel11_IRQn + 16 ] = HPDMA1_Channel11_IRQHandler,
|
||||
[HPDMA1_Channel12_IRQn + 16 ] = HPDMA1_Channel12_IRQHandler,
|
||||
[HPDMA1_Channel13_IRQn + 16 ] = HPDMA1_Channel13_IRQHandler,
|
||||
[HPDMA1_Channel14_IRQn + 16 ] = HPDMA1_Channel14_IRQHandler,
|
||||
[HPDMA1_Channel15_IRQn + 16 ] = HPDMA1_Channel15_IRQHandler,
|
||||
[GPU2D_IRQn + 16 ] = GPU2D_IRQHandler,
|
||||
[GPU2D_ER_IRQn + 16 ] = GPU2D_ER_IRQHandler,
|
||||
[ICACHE_IRQn + 16 ] = ICACHE_IRQHandler,
|
||||
[FDCAN1_IT0_IRQn + 16 ] = FDCAN1_IT0_IRQHandler,
|
||||
[FDCAN1_IT1_IRQn + 16 ] = FDCAN1_IT1_IRQHandler,
|
||||
[FDCAN2_IT0_IRQn + 16 ] = FDCAN2_IT0_IRQHandler,
|
||||
[FDCAN2_IT1_IRQn + 16 ] = FDCAN2_IT1_IRQHandler,
|
||||
};
|
||||
|
||||
@@ -136,3 +136,9 @@ void pwrResetHandler()
|
||||
pwrOn();
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(BOOT)
|
||||
void* _pwr_init_hook[] __INIT_HOOK = {
|
||||
(void*)pwrResetHandler,
|
||||
};
|
||||
#endif
|
||||
|
||||
+110
-33
@@ -1,20 +1,50 @@
|
||||
#include <stdint.h>
|
||||
#include "stm32_cmsis.h"
|
||||
#include "system_clock.h"
|
||||
/*
|
||||
* Copyright (C) EdgeTX
|
||||
*
|
||||
* Based on code named
|
||||
* opentx - https://github.com/opentx/opentx
|
||||
* th9x - http://code.google.com/p/th9x
|
||||
* er9x - http://code.google.com/p/er9x
|
||||
* gruvin9x - http://code.google.com/p/gruvin9x
|
||||
*
|
||||
* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "stm32_cmsis.h"
|
||||
#include "stm32_hal.h"
|
||||
|
||||
|
||||
#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
|
||||
(defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
|
||||
#define USE_CACHE
|
||||
#endif
|
||||
|
||||
#if (defined (USE_CACHE) && defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U))
|
||||
#define REQUIRE_MPU_CONFIG
|
||||
#endif
|
||||
|
||||
#if defined(ITCM_BASE) /* H7RS */ || defined(D1_ITCMRAM_BASE) /* H7 */
|
||||
#define LOAD_FAST_CODE_RAM
|
||||
#endif
|
||||
|
||||
#define NAKED __attribute__((naked))
|
||||
#define BOOTSTRAP __attribute__((section(".bootstrap")))
|
||||
|
||||
// Linker script symbols
|
||||
extern uint32_t _sisr_vector;
|
||||
extern uint32_t _dram_addr;
|
||||
extern uint32_t PSRAM_START;
|
||||
extern uint32_t NORFLASH_START;
|
||||
|
||||
extern "C" NAKED BOOTSTRAP
|
||||
void Reset_Handler()
|
||||
NAKED BOOTSTRAP void Reset_Handler()
|
||||
{
|
||||
asm inline (
|
||||
"ldr sp, =_estack \n"
|
||||
@@ -22,12 +52,18 @@ void Reset_Handler()
|
||||
|
||||
#if defined(BOOT)
|
||||
asm inline (
|
||||
"bl SystemInit \n"
|
||||
"bl SystemClock_Config \n"
|
||||
);
|
||||
|
||||
#if defined(USE_CACHE)
|
||||
asm inline (
|
||||
"bl CPU_CACHE_Enable \n"
|
||||
);
|
||||
#endif
|
||||
#endif // USE_CACHE
|
||||
#endif // BOOT
|
||||
|
||||
// Copy code into normal RAM
|
||||
// Copy code into RAM
|
||||
asm inline (
|
||||
"ldr r0, =_stext \n"
|
||||
"ldr r1, =_etext \n"
|
||||
@@ -35,13 +71,12 @@ void Reset_Handler()
|
||||
"bl naked_copy \n"
|
||||
);
|
||||
|
||||
#if defined(BOOT)
|
||||
#if defined(BOOT) && defined(REQUIRE_MPU_CONFIG)
|
||||
asm inline (
|
||||
"bl SystemInit \n"
|
||||
"bl MPU_Init \n"
|
||||
"bl MPU_Config \n"
|
||||
);
|
||||
#endif
|
||||
|
||||
|
||||
// Copy / setup ISR vector
|
||||
asm inline (
|
||||
"ldr r0, =_sisr_vector \n"
|
||||
@@ -51,6 +86,7 @@ void Reset_Handler()
|
||||
"bl set_vtor \n"
|
||||
);
|
||||
|
||||
#if defined(LOAD_FAST_CODE_RAM)
|
||||
// Copy code into fast RAM
|
||||
asm inline (
|
||||
"ldr r0, =_siram \n"
|
||||
@@ -58,6 +94,7 @@ void Reset_Handler()
|
||||
"ldr r2, =_stext_iram \n"
|
||||
"bl naked_copy \n"
|
||||
);
|
||||
#endif
|
||||
|
||||
// Copy initialized data segment
|
||||
asm inline (
|
||||
@@ -66,6 +103,11 @@ void Reset_Handler()
|
||||
"ldr r2, =_sidata \n"
|
||||
"bl naked_copy \n"
|
||||
);
|
||||
|
||||
// Execute early hooks
|
||||
asm inline (
|
||||
"bl init_hooks \n"
|
||||
);
|
||||
|
||||
// Zero fill bss segment
|
||||
asm inline (
|
||||
@@ -83,10 +125,16 @@ void Reset_Handler()
|
||||
"bcc FillZerobss \n"
|
||||
);
|
||||
|
||||
#if defined(USE_CACHE)
|
||||
asm inline (
|
||||
"bl clean_dcache \n"
|
||||
);
|
||||
#endif
|
||||
|
||||
asm inline (
|
||||
// Call static constructors
|
||||
"bl __libc_init_array \n"
|
||||
// Update global clock speed variable
|
||||
"bl SystemCoreClockUpdate \n"
|
||||
// Call the application's entry point
|
||||
"bl main \n"
|
||||
@@ -94,11 +142,10 @@ void Reset_Handler()
|
||||
);
|
||||
}
|
||||
|
||||
extern "C" BOOTSTRAP void set_vtor() {
|
||||
SCB->VTOR = (intptr_t)&_sisr_vector;
|
||||
}
|
||||
BOOTSTRAP void set_vtor() { SCB->VTOR = (intptr_t)&_sisr_vector; }
|
||||
|
||||
extern "C" NAKED BOOTSTRAP void naked_copy() {
|
||||
NAKED BOOTSTRAP void naked_copy()
|
||||
{
|
||||
// r0: destination start
|
||||
// r1: destination end
|
||||
// r2: source start
|
||||
@@ -117,13 +164,31 @@ extern "C" NAKED BOOTSTRAP void naked_copy() {
|
||||
"adds r4, r0, r3 \n"
|
||||
"cmp r4, r1 \n"
|
||||
"bcc CopyInit \n"
|
||||
|
||||
"SkipCopy: \n"
|
||||
"bx lr \n"
|
||||
);
|
||||
}
|
||||
|
||||
extern "C" BOOTSTRAP
|
||||
void CPU_CACHE_Enable()
|
||||
void init_hooks()
|
||||
{
|
||||
extern uint32_t __init_hook_array_start;
|
||||
extern uint32_t __init_hook_array_end;
|
||||
|
||||
typedef void (*hook_fct_t)();
|
||||
|
||||
for (uint32_t hook = (uint32_t)&__init_hook_array_start;
|
||||
hook != (uint32_t)&__init_hook_array_end; hook += sizeof(void*)) {
|
||||
(*(hook_fct_t*)hook)();
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(USE_CACHE)
|
||||
// SCB_CleanDCache() is "forced inline"
|
||||
void clean_dcache() { SCB_CleanDCache(); }
|
||||
|
||||
#if defined(BOOT)
|
||||
BOOTSTRAP void CPU_CACHE_Enable()
|
||||
{
|
||||
/* Enable I-Cache */
|
||||
SCB_EnableICache();
|
||||
@@ -131,9 +196,23 @@ void CPU_CACHE_Enable()
|
||||
/* Enable D-Cache */
|
||||
SCB_EnableDCache();
|
||||
}
|
||||
#endif // BOOT
|
||||
#endif // USE_CACHE
|
||||
|
||||
extern "C" __attribute__((used))
|
||||
void MPU_Init()
|
||||
#if defined(BOOT) && defined(REQUIRE_MPU_CONFIG)
|
||||
// Linker script symbols
|
||||
extern uint32_t _dram_addr;
|
||||
extern uint32_t EXTRAM_START;
|
||||
extern uint32_t EXTRAM_SIZE;
|
||||
extern uint32_t NORFLASH_START;
|
||||
extern uint32_t NORFLASH_SIZE;
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t mpu_region_size(uint32_t size)
|
||||
{
|
||||
return 32 - __CLZ(size) - 1;
|
||||
}
|
||||
|
||||
void MPU_Config()
|
||||
{
|
||||
MPU_Region_InitTypeDef MPU_InitStruct = {0};
|
||||
|
||||
@@ -160,11 +239,11 @@ void MPU_Init()
|
||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
|
||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||
|
||||
/* Region 2: XSPI memory range, bank1 */
|
||||
/* Region 2: QSPI memory range, bank1 */
|
||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||
MPU_InitStruct.Number = MPU_REGION_NUMBER2;
|
||||
MPU_InitStruct.BaseAddress = (uint32_t)&NORFLASH_START;
|
||||
MPU_InitStruct.Size = MPU_REGION_SIZE_128MB;
|
||||
MPU_InitStruct.Size = mpu_region_size((uint32_t)&NORFLASH_SIZE);
|
||||
MPU_InitStruct.SubRegionDisable = 0x0;
|
||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
|
||||
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
||||
@@ -174,11 +253,11 @@ void MPU_Init()
|
||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
|
||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||
|
||||
/* Region 3: SDRAM memory range */
|
||||
/* Region 3: external RAM memory range */
|
||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||
MPU_InitStruct.Number = MPU_REGION_NUMBER3;
|
||||
MPU_InitStruct.BaseAddress = (uint32_t)&PSRAM_START;
|
||||
MPU_InitStruct.Size = MPU_REGION_SIZE_32MB;
|
||||
MPU_InitStruct.BaseAddress = (uint32_t)&EXTRAM_START;
|
||||
MPU_InitStruct.Size = mpu_region_size((uint32_t)&EXTRAM_SIZE);
|
||||
MPU_InitStruct.SubRegionDisable = 0x0;
|
||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
|
||||
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
||||
@@ -188,11 +267,11 @@ void MPU_Init()
|
||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
|
||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||
|
||||
/* Region 3: DMA memory range */
|
||||
/* Region 4: dedicated DMA buffers (cache disabled) */
|
||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||
MPU_InitStruct.Number = MPU_REGION_NUMBER4;
|
||||
MPU_InitStruct.BaseAddress = (uint32_t)&_dram_addr;
|
||||
MPU_InitStruct.Size = MPU_REGION_SIZE_64KB; // actually 72KB
|
||||
MPU_InitStruct.Size = MPU_REGION_SIZE_64KB; // FIXME
|
||||
MPU_InitStruct.SubRegionDisable = 0x0;
|
||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
|
||||
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
||||
@@ -202,12 +281,10 @@ void MPU_Init()
|
||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
|
||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||
|
||||
|
||||
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
|
||||
|
||||
/* Enable bus fault exception */
|
||||
SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
|
||||
}
|
||||
|
||||
extern "C" void clean_dcache() {
|
||||
SCB_CleanDCache();
|
||||
}
|
||||
#endif // REQUIRE_MPU_CONFIG
|
||||
@@ -24,7 +24,7 @@ set(PPM_LIMITS_SYMETRICAL YES)
|
||||
# for size report script
|
||||
set(CPU_TYPE_FULL STM32F429xI)
|
||||
set(TARGET_LINKER_DIR stm32f429_sdram)
|
||||
set(TARGET_SDRAM_START 0xC0000000)
|
||||
set(TARGET_EXTRAM_START 0xC0000000)
|
||||
|
||||
set(SIZE_TARGET_MEM_DEFINE "MEM_SIZE_SDRAM1=8192")
|
||||
|
||||
|
||||
@@ -25,7 +25,7 @@ set(HARDWARE_EXTERNAL_MODULE YES)
|
||||
# for size report script
|
||||
set(CPU_TYPE_FULL STM32F429xI)
|
||||
set(TARGET_LINKER_DIR stm32f429_sdram)
|
||||
set(TARGET_SDRAM_START 0xC0000000)
|
||||
set(TARGET_EXTRAM_START 0xC0000000)
|
||||
|
||||
set(SIZE_TARGET_MEM_DEFINE "MEM_SIZE_SDRAM1=8192")
|
||||
|
||||
|
||||
@@ -35,7 +35,8 @@ set(IMU ON)
|
||||
# for size report script
|
||||
set(CPU_TYPE_FULL STM32H750xB)
|
||||
set(TARGET_LINKER_DIR stm32h750_sdram)
|
||||
set(TARGET_SDRAM_START 0xC0000000)
|
||||
set(TARGET_EXTRAM_START 0xC0000000)
|
||||
|
||||
set(SIZE_TARGET_MEM_DEFINE "MEM_SIZE_SDRAM1=8192")
|
||||
set(FIRMWARE_STRIP_BOOTLOADER YES)
|
||||
|
||||
@@ -113,7 +114,6 @@ set(BOARD_COMMON_SRC
|
||||
${TARGET_SRC_DIR}/board.cpp
|
||||
${TARGET_SRC_DIR}/bsp_io.cpp
|
||||
${TARGET_SRC_DIR}/key_driver.cpp
|
||||
${TARGET_SRC_DIR}/system_init.cpp
|
||||
${TARGET_SRC_DIR}/lcd_driver.cpp
|
||||
${TARGET_SRC_DIR}/backlight_driver.cpp
|
||||
${TARGET_SRC_DIR}/haptic_driver.cpp
|
||||
@@ -132,7 +132,7 @@ set(BOARD_COMMON_SRC
|
||||
# Bootloader board library
|
||||
add_library(board_bl OBJECT EXCLUDE_FROM_ALL
|
||||
${BOARD_COMMON_SRC}
|
||||
${TARGET_SRC_DIR}/system_clock.cpp
|
||||
${TARGET_SRC_DIR}/system_clock.c
|
||||
${TARGET_SRC_DIR}/sdram_driver.cpp
|
||||
${TARGET_SRC_DIR}/bootloader/boot_menu.cpp
|
||||
targets/common/arm/stm32/stm32_qspi.cpp
|
||||
|
||||
@@ -26,8 +26,7 @@
|
||||
|
||||
#define BOOTSTRAP __attribute__((section(".bootstrap")))
|
||||
|
||||
extern "C" BOOTSTRAP
|
||||
void SystemClock_Config(void)
|
||||
BOOTSTRAP void SystemClock_Config(void)
|
||||
{
|
||||
/* Power Configuration */
|
||||
LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
|
||||
@@ -19,5 +19,5 @@
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
extern "C" void SystemClock_Config();
|
||||
void SystemClock_Config();
|
||||
|
||||
|
||||
@@ -1,222 +0,0 @@
|
||||
#include <stdint.h>
|
||||
#include "stm32_cmsis.h"
|
||||
#include "system_clock.h"
|
||||
|
||||
#include "stm32_hal.h"
|
||||
|
||||
#define NAKED __attribute__((naked))
|
||||
#define BOOTSTRAP __attribute__((section(".bootstrap")))
|
||||
|
||||
// Linker script symbols
|
||||
extern uint32_t _sisr_vector;
|
||||
extern uint32_t SDRAM_START;
|
||||
|
||||
extern "C" NAKED BOOTSTRAP
|
||||
void Reset_Handler()
|
||||
{
|
||||
asm inline (
|
||||
"ldr sp, =_estack \n"
|
||||
);
|
||||
|
||||
#if defined(BOOT)
|
||||
asm inline (
|
||||
"bl SystemInit \n"
|
||||
"bl SystemClock_Config \n"
|
||||
"bl CPU_CACHE_Enable \n"
|
||||
);
|
||||
#endif
|
||||
|
||||
// Copy code into normal RAM
|
||||
asm inline (
|
||||
"ldr r0, =_stext \n"
|
||||
"ldr r1, =_etext \n"
|
||||
"ldr r2, =_text_load \n"
|
||||
"bl naked_copy \n"
|
||||
);
|
||||
|
||||
#if defined(BOOT)
|
||||
asm inline (
|
||||
"bl MPU_Init \n"
|
||||
);
|
||||
#endif
|
||||
|
||||
// Copy / setup ISR vector
|
||||
asm inline (
|
||||
"ldr r0, =_sisr_vector \n"
|
||||
"ldr r1, =_eisr_vector \n"
|
||||
"ldr r2, =_isr_load \n"
|
||||
"bl naked_copy \n"
|
||||
"bl set_vtor \n"
|
||||
);
|
||||
|
||||
// Copy code into fast RAM
|
||||
asm inline (
|
||||
"ldr r0, =_siram \n"
|
||||
"ldr r1, =_eiram \n"
|
||||
"ldr r2, =_stext_iram \n"
|
||||
"bl naked_copy \n"
|
||||
);
|
||||
|
||||
// Copy initialized data segment
|
||||
asm inline (
|
||||
"ldr r0, =_sdata \n"
|
||||
"ldr r1, =_edata \n"
|
||||
"ldr r2, =_sidata \n"
|
||||
"bl naked_copy \n"
|
||||
);
|
||||
|
||||
#if defined(BOOT)
|
||||
asm inline (
|
||||
"bl pwrResetHandler \n"
|
||||
);
|
||||
#endif
|
||||
|
||||
// Zero fill bss segment
|
||||
asm inline (
|
||||
"ldr r2, =_sbss \n"
|
||||
"ldr r4, =_ebss \n"
|
||||
"movs r3, 0 \n"
|
||||
"b LoopFillZerobss \n"
|
||||
|
||||
"FillZerobss: \n"
|
||||
"str r3, [r2] \n"
|
||||
"adds r2, r2, 4 \n"
|
||||
|
||||
"LoopFillZerobss: \n"
|
||||
"cmp r2, r4 \n"
|
||||
"bcc FillZerobss \n"
|
||||
);
|
||||
|
||||
asm inline (
|
||||
"bl clean_dcache \n"
|
||||
// Call static constructors
|
||||
"bl __libc_init_array \n"
|
||||
"bl SystemCoreClockUpdate \n"
|
||||
// Call the application's entry point
|
||||
"bl main \n"
|
||||
"bx lr \n"
|
||||
);
|
||||
}
|
||||
|
||||
extern "C" BOOTSTRAP void set_vtor() {
|
||||
SCB->VTOR = (intptr_t)&_sisr_vector;
|
||||
}
|
||||
|
||||
extern "C" NAKED BOOTSTRAP void naked_copy() {
|
||||
// r0: destination start
|
||||
// r1: destination end
|
||||
// r2: source start
|
||||
asm inline (
|
||||
"cmp r0, r2 \n"
|
||||
"beq SkipCopy \n"
|
||||
"movs r3, 0 \n"
|
||||
"b LoopCopyInit \n"
|
||||
|
||||
"CopyInit: \n"
|
||||
"ldr r4, [r2, r3] \n"
|
||||
"str r4, [r0, r3] \n"
|
||||
"adds r3, r3, #4 \n"
|
||||
|
||||
"LoopCopyInit: \n"
|
||||
"adds r4, r0, r3 \n"
|
||||
"cmp r4, r1 \n"
|
||||
"bcc CopyInit \n"
|
||||
"SkipCopy: \n"
|
||||
"bx lr \n"
|
||||
);
|
||||
}
|
||||
|
||||
extern "C" BOOTSTRAP
|
||||
void CPU_CACHE_Enable()
|
||||
{
|
||||
/* Enable I-Cache */
|
||||
SCB_EnableICache();
|
||||
|
||||
/* Enable D-Cache */
|
||||
SCB_EnableDCache();
|
||||
}
|
||||
|
||||
extern "C" __attribute__((used))
|
||||
void MPU_Init()
|
||||
{
|
||||
MPU_Region_InitTypeDef MPU_InitStruct = {0};
|
||||
|
||||
/* Disables the MPU */
|
||||
HAL_MPU_Disable();
|
||||
|
||||
/*
|
||||
* Region 0: overwrite default setting to prevent speculative
|
||||
* read to unavailable memories.
|
||||
* Range: 0x60000000 to 0xE0000000
|
||||
*
|
||||
* Set as strongly ordered, code execution disabled
|
||||
*/
|
||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
|
||||
MPU_InitStruct.BaseAddress = 0;
|
||||
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
|
||||
MPU_InitStruct.SubRegionDisable = 0x87;
|
||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
|
||||
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
|
||||
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
|
||||
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
|
||||
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
|
||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
|
||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||
|
||||
#if defined(FIRMWARE_QSPI)
|
||||
/* Region 2: QSPI memory range, bank1 */
|
||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||
MPU_InitStruct.Number = MPU_REGION_NUMBER2;
|
||||
MPU_InitStruct.BaseAddress = 0x90000000;
|
||||
MPU_InitStruct.Size = MPU_REGION_SIZE_8MB;
|
||||
MPU_InitStruct.SubRegionDisable = 0x0;
|
||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
|
||||
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
||||
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
|
||||
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
|
||||
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
|
||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
|
||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||
#endif
|
||||
|
||||
#if defined(SDRAM)
|
||||
/* Region 3: SDRAM memory range */
|
||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||
MPU_InitStruct.Number = MPU_REGION_NUMBER3;
|
||||
MPU_InitStruct.BaseAddress = (uint32_t)&SDRAM_START;
|
||||
MPU_InitStruct.Size = MPU_REGION_SIZE_8MB;
|
||||
MPU_InitStruct.SubRegionDisable = 0x0;
|
||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
|
||||
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
||||
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
|
||||
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
|
||||
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
|
||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
|
||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||
#endif
|
||||
|
||||
/* Region 3: SRAM1 memory range */
|
||||
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
|
||||
MPU_InitStruct.Number = MPU_REGION_NUMBER4;
|
||||
MPU_InitStruct.BaseAddress = 0x30000000;
|
||||
MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
|
||||
MPU_InitStruct.SubRegionDisable = 0x0;
|
||||
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
|
||||
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
|
||||
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
|
||||
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
|
||||
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
|
||||
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
|
||||
HAL_MPU_ConfigRegion(&MPU_InitStruct);
|
||||
|
||||
|
||||
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
|
||||
|
||||
/* Enable bus fault exception */
|
||||
SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
|
||||
}
|
||||
|
||||
extern "C" void clean_dcache() {
|
||||
SCB_CleanDCache();
|
||||
}
|
||||
@@ -68,7 +68,6 @@ set(TARGET_SRC_DIR targets/${TARGET_DIR})
|
||||
|
||||
set(BOARD_COMMON_SRC
|
||||
${TARGET_SRC_DIR}/board.cpp
|
||||
${TARGET_SRC_DIR}/system_init.cpp
|
||||
${TARGET_SRC_DIR}/lcd_driver.cpp
|
||||
${TARGET_SRC_DIR}/backlight_driver.cpp
|
||||
# ${TARGET_SRC_DIR}/seesaw.cpp
|
||||
@@ -87,7 +86,7 @@ set(BOARD_COMMON_SRC
|
||||
# Bootloader board library
|
||||
add_library(board_bl OBJECT EXCLUDE_FROM_ALL
|
||||
${BOARD_COMMON_SRC}
|
||||
${TARGET_SRC_DIR}/system_clock.cpp
|
||||
${TARGET_SRC_DIR}/system_clock.c
|
||||
${TARGET_SRC_DIR}/extram_driver.cpp
|
||||
${TARGET_SRC_DIR}/bootloader/boot_menu.cpp
|
||||
)
|
||||
|
||||
+1
-2
@@ -48,8 +48,7 @@
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
extern "C" BOOTSTRAP
|
||||
void SystemClock_Config()
|
||||
BOOTSTRAP void SystemClock_Config()
|
||||
{
|
||||
/* Power Configuration */
|
||||
LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
|
||||
@@ -19,5 +19,5 @@
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
extern "C" void SystemClock_Config();
|
||||
void SystemClock_Config();
|
||||
|
||||
|
||||
@@ -0,0 +1,135 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
# Copyright (C) 2020 Inria
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
|
||||
"""Generate the vectors table for a given STM32 CPU line."""
|
||||
|
||||
import os
|
||||
import argparse
|
||||
import re
|
||||
|
||||
|
||||
VECTORS_FORMAT = """
|
||||
#include "{cpu_line}.h"
|
||||
#include "cortex_m_isr.h"
|
||||
|
||||
void Default_Handler() {{ default_isr_handler(); }}
|
||||
|
||||
/* {cpu_line} specific interrupt vectors */
|
||||
{isr_lines}
|
||||
|
||||
/* CPU specific interrupt vector table */
|
||||
const isr_t _isr_vector[] ISR_VECTOR = {{
|
||||
[0] = (isr_t)&_estack,
|
||||
{irq_lines}
|
||||
}};
|
||||
"""
|
||||
|
||||
|
||||
def parse_cmsis(cmsis_dir, cpu_line):
|
||||
"""Parse the CMSIS to get the list IRQs."""
|
||||
cpu_line_cmsis = os.path.join("{}/{}.h".format(cmsis_dir, cpu_line.lower()))
|
||||
|
||||
with open(cpu_line_cmsis, "rb") as cmsis:
|
||||
cmsis_content = cmsis.readlines()
|
||||
|
||||
irq_lines = []
|
||||
use_line = False
|
||||
for line in cmsis_content:
|
||||
try:
|
||||
line = line.decode()
|
||||
except UnicodeDecodeError:
|
||||
# skip line that contains non unicode characters
|
||||
continue
|
||||
|
||||
# start filling lines after interrupt Doxygen comment
|
||||
if "typedef enum" in line:
|
||||
irq_lines = [] # Cleanup any previous content
|
||||
use_line = True
|
||||
|
||||
# enum not yet detected: skip
|
||||
if not use_line:
|
||||
continue
|
||||
|
||||
# Stop at the end of the IRQn_Type enum definition
|
||||
if "IRQn_Type" in line:
|
||||
break
|
||||
|
||||
# use a regexp to get the available IRQs
|
||||
match = re.match(r"[ ]+([a-zA-Z0-9_]+_IRQn)[ ]+= \d+", line)
|
||||
|
||||
# Skip lines that don't match
|
||||
if match:
|
||||
irq_lines.append(match.group(1).strip())
|
||||
|
||||
isrs = [
|
||||
{"irq": irq + " + 16", "func": irq.rsplit("_", 1)[0] + "_IRQHandler"}
|
||||
for irq in irq_lines
|
||||
]
|
||||
return {"isrs": isrs, "cpu_line": cpu_line}
|
||||
|
||||
|
||||
def generate_vectors(context):
|
||||
"""Use vector template string to generate the vectors C file."""
|
||||
isr_line_format = "WEAK_DEFAULT void {func}();"
|
||||
irq_line_format = " [{irq:<35}] = {func},"
|
||||
|
||||
isr_lines = []
|
||||
irq_lines = []
|
||||
|
||||
cortex_m_irqs = [
|
||||
"Reset_Handler",
|
||||
"NMI_Handler",
|
||||
"HardFault_Handler",
|
||||
"MemManage_Handler",
|
||||
"BusFault_Handler",
|
||||
"UsageFault_Handler",
|
||||
"0",
|
||||
"0",
|
||||
"0",
|
||||
"0",
|
||||
"SVC_Handler",
|
||||
"DebugMon_Handler",
|
||||
"0",
|
||||
"PendSV_Handler",
|
||||
"SysTick_Handler",
|
||||
]
|
||||
|
||||
irqn = 1
|
||||
for isr in cortex_m_irqs:
|
||||
if isr != "0":
|
||||
isr_lines.append(isr_line_format.format(func=isr))
|
||||
irq_lines.append(irq_line_format.format(irq=irqn, func=isr))
|
||||
irqn += 1
|
||||
|
||||
for isr in context["isrs"]:
|
||||
isr_line = isr_line_format.format(**isr)
|
||||
if isr_line not in isr_lines:
|
||||
isr_lines.append(isr_line)
|
||||
irq_lines.append(irq_line_format.format(**isr))
|
||||
|
||||
vectors_content = VECTORS_FORMAT.format(
|
||||
cpu_line=context["cpu_line"],
|
||||
isr_lines="\n".join(isr_lines),
|
||||
irq_lines="\n".join(irq_lines),
|
||||
)
|
||||
|
||||
print(vectors_content)
|
||||
|
||||
|
||||
def main(args):
|
||||
"""Main function."""
|
||||
context = parse_cmsis(args.cmsis_dir, args.cpu_line)
|
||||
generate_vectors(context)
|
||||
|
||||
|
||||
PARSER = argparse.ArgumentParser()
|
||||
PARSER.add_argument("cmsis_dir", help="CMSIS directory")
|
||||
PARSER.add_argument("cpu_line", help="STM32 CPU line")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main(PARSER.parse_args())
|
||||
Reference in New Issue
Block a user