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refactor(h7): generic system init (#6172)

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This commit is contained in:
Raphael Coeffic
2025-05-08 22:38:01 +10:00
committed by GitHub
parent 9e20b7f2ee
commit 04a7e340d7
36 changed files with 1431 additions and 1993 deletions
Download Patch File Download Diff File Expand all files Collapse all files
radio/src/targets/common/arm/stm32/bootloader/CMakeLists.txt
+10 -8
View File
@@ -57,8 +57,12 @@ endif()
add_executable(bootloader EXCLUDE_FROM_ALL ${BOOTLOADER_SRC})
add_dependencies(bootloader ${BITMAPS_TARGET})
target_compile_definitions(bootloader PRIVATE BOOT)
target_compile_definitions(board_bl PRIVATE BOOT)
target_compile_definitions(bootloader PUBLIC BOOT)
target_compile_definitions(board_bl PUBLIC BOOT)
if(ARCH STREQUAL ARM)
target_link_libraries(bootloader PUBLIC cmsis)
endif()
target_link_options(bootloader BEFORE PRIVATE
-L${LINKER_DIR}/${TARGET_LINKER_DIR}/bootloader
@@ -67,17 +71,15 @@ target_link_options(bootloader BEFORE PRIVATE
-lm --specs=nano.specs
)
if (DEFINED TARGET_SDRAM_START)
# message("TARGET_SDRAM_START = ${TARGET_SDRAM_START}")
if (DEFINED TARGET_EXTRAM_START)
target_link_options(bootloader PRIVATE
-Wl,--defsym=__sdram_start=${TARGET_SDRAM_START}
-Wl,--defsym=__EXTRAM_START__=${TARGET_EXTRAM_START}
)
endif()
if (DEFINED TARGET_SDRAM_SIZE)
# message("TARGET_SDRAM_SIZE = ${TARGET_SDRAM_SIZE}")
if (DEFINED TARGET_EXTRAM_SIZE)
target_link_options(bootloader PRIVATE
-Wl,--defsym=__sdram_size=${TARGET_SDRAM_SIZE}
-Wl,--defsym=__EXTRAM_SIZE__=${TARGET_EXTRAM_SIZE}
)
endif()
radio/src/targets/common/arm/stm32/cortex_m_isr.c
+80
View File
@@ -0,0 +1,80 @@
/*
* Copyright (C) EdgeTX
*
* Based on code named
* opentx - https://github.com/opentx/opentx
* th9x - http://code.google.com/p/th9x
* er9x - http://code.google.com/p/er9x
* gruvin9x - http://code.google.com/p/gruvin9x
*
* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "cortex_m_isr.h"
#include "stm32_cmsis.h"
#define GET_VECTACTIVE() \
((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos)
#define HARDFAULT_HANDLING_ASM(_x) \
__asm volatile( \
"tst lr, #4 \n" \
"ite eq \n" \
"mrseq r0, msp \n" \
"mrsne r0, psp \n" \
"b hard_fault_handler_c \n")
#define HALT_IF_DEBUGGING() \
do { \
if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) { \
__asm("bkpt 1"); \
} \
} while (0)
__attribute__((optimize("O0")))
void default_isr_handler()
{
/* Halt in debugger if connected */
if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) {
uint32_t active_irq = GET_VECTACTIVE();
if (active_irq >= NVIC_USER_IRQ_OFFSET) {
/* External interrupt: check IRQn_Type for number */
active_irq -= NVIC_USER_IRQ_OFFSET;
__asm__("bkpt 1");
} else {
/* Cortex-M Exception */
__asm__("bkpt 2");
}
}
while (1) {}
}
typedef struct __attribute__((packed)) ContextStateFrame {
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r12;
uint32_t lr;
uint32_t return_address;
uint32_t xpsr;
} sContextStateFrame;
__attribute__((optimize("O0")))
void hard_fault_handler_c(sContextStateFrame *frame) {
HALT_IF_DEBUGGING();
}
void HardFault_Handler(void) {
HARDFAULT_HANDLING_ASM();
}
radio/src/targets/common/arm/stm32/cortex_m_isr.h
+29
View File
@@ -0,0 +1,29 @@
/*
* Copyright (C) EdgeTX
*
* Based on code named
* opentx - https://github.com/opentx/opentx
* th9x - http://code.google.com/p/th9x
* er9x - http://code.google.com/p/er9x
* gruvin9x - http://code.google.com/p/gruvin9x
*
* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define WEAK_DEFAULT __attribute__((weak,alias("Default_Handler")))
#define ISR_VECTOR __attribute__((section(".isr_vector")))
typedef void (*isr_t)(void);
extern void* _estack;
extern void default_isr_handler();
radio/src/targets/common/arm/stm32/f2/CMakeLists.txt
+4 -5
View File
@@ -53,13 +53,12 @@ include_directories(${STM32LIB_DIR}/CMSIS/Include)
add_definitions(-DSTM32F2)
add_library(stm32_stdperiph OBJECT EXCLUDE_FROM_ALL
add_library(cmsis INTERFACE)
target_sources(cmsis INTERFACE
targets/common/arm/stm32/f2/system_stm32f2xx.c
boards/generic_stm32/startup/startup_stm32f205xx.s
)
set(FIRMWARE_SRC ${FIRMWARE_SRC} $<TARGET_OBJECTS:stm32_stdperiph>)
set(BOOTLOADER_SRC ${BOOTLOADER_SRC} $<TARGET_OBJECTS:stm32_stdperiph>)
)
if(NOT NATIVE_BUILD)
include_directories(targets/common/arm/stm32/f2)
radio/src/targets/common/arm/stm32/f2/memory_sections.h
+1
View File
@@ -21,6 +21,7 @@
#pragma once
#define __INIT_HOOK
#define __CCMRAM
#define __DMA
#define __DMA_NO_CACHE
radio/src/targets/common/arm/stm32/f4/CMakeLists.txt
+10 -14
View File
@@ -71,30 +71,26 @@ include_directories(${STM32LIB_DIR}/CMSIS/Include)
add_definitions(-DSTM32F4)
set(STM32_STDPERIPH_SRC
targets/common/arm/stm32/f4/system_stm32f4xx.c
)
if(CPU_TYPE_FULL STREQUAL STM32F429xI)
set(STM32_STDPERIPH_SRC ${STM32_STDPERIPH_SRC}
set(CMSIS_SRC ${CMSIS_SRC}
boards/generic_stm32/startup/startup_stm32f42_43xxx.s
)
)
elseif (CPU_TYPE_FULL STREQUAL STM32F413xG)
set(STM32_STDPERIPH_SRC ${STM32_STDPERIPH_SRC}
set(CMSIS_SRC ${CMSIS_SRC}
boards/generic_stm32/startup/startup_stm32f413xx.s
)
else()
set(STM32_STDPERIPH_SRC ${STM32_STDPERIPH_SRC}
set(CMSIS_SRC ${CMSIS_SRC}
boards/generic_stm32/startup/startup_stm32f40_41xxx.s
)
)
endif()
add_library(stm32_stdperiph OBJECT EXCLUDE_FROM_ALL
${STM32_STDPERIPH_SRC}
)
add_library(cmsis INTERFACE)
set(FIRMWARE_SRC ${FIRMWARE_SRC} $<TARGET_OBJECTS:stm32_stdperiph>)
set(BOOTLOADER_SRC ${BOOTLOADER_SRC} $<TARGET_OBJECTS:stm32_stdperiph>)
target_sources(cmsis INTERFACE
targets/common/arm/stm32/f4/system_stm32f4xx.c
${CMSIS_SRC}
)
if(NOT NATIVE_BUILD)
include_directories(targets/common/arm/stm32/f4)
radio/src/targets/common/arm/stm32/f4/memory_sections.h
+2
View File
@@ -21,6 +21,8 @@
#pragma once
#define __INIT_HOOK
#define __CCMRAM __attribute__((section(".ccm"), aligned(4)))
#define __DMA __attribute__((section(".ram"), aligned(4)))
#define __DMA_NO_CACHE __DMA
radio/src/targets/common/arm/stm32/h7/CMakeLists.txt
+9 -9
View File
@@ -18,7 +18,6 @@ else()
)
endif()
if(NOT NATIVE_BUILD)
if(CPU_TYPE STREQUAL STM32H7RS)
set(STM32CUBE_PREFIX stm32h7rsxx)
@@ -123,27 +122,28 @@ endif()
if(CPU_TYPE_FULL STREQUAL STM32H750xB)
set(CMSIS_SRC ${CMSIS_SRC}
boards/generic_stm32/startup/startup_stm32h750xx.s
targets/common/arm/stm32/h7/vectors_stm32h750xx.c
)
elseif(CPU_TYPE_FULL STREQUAL STM32H747Ix)
set(CMSIS_SRC ${CMSIS_SRC}
boards/generic_stm32/startup/startup_stm32h747xx.s
targets/common/arm/stm32/h7/vectors_stm32h747xx.c
)
elseif(CPU_TYPE_FULL STREQUAL STM32H7S7xx)
elseif(CPU_TYPE_FULL STREQUAL STM32H7S7xx OR CPU_TYPE_FULL STREQUAL STM32H7R7xx)
set(CMSIS_SRC ${CMSIS_SRC}
boards/generic_stm32/startup/startup_stm32h7s7xx.s
targets/common/arm/stm32/h7/vectors_stm32h7s7xx.c
)
else()
message(FATAL_ERROR "### ERROR ####: ${CPU_TYPE_FULL}")
endif()
add_library(cmsis OBJECT EXCLUDE_FROM_ALL
add_library(cmsis INTERFACE)
target_sources(cmsis INTERFACE
targets/common/arm/stm32/system_init.c
targets/common/arm/stm32/cortex_m_isr.c
${CMSIS_SRC}
)
set(FIRMWARE_SRC ${FIRMWARE_SRC} $<TARGET_OBJECTS:cmsis>)
set(BOOTLOADER_SRC ${BOOTLOADER_SRC} $<TARGET_OBJECTS:cmsis>)
if(NOT NATIVE_BUILD)
include_directories(targets/common/arm/stm32/h7)
radio/src/targets/common/arm/stm32/h7/memory_sections.h
+2
View File
@@ -21,6 +21,8 @@
#pragma once
#define __INIT_HOOK __attribute__((section(".init_hook")))
#define __CCMRAM __attribute__((section(".ccm"), aligned(4)))
#define __DMA __attribute__((section(".ram"), aligned(4)))
#define __DMA_NO_CACHE __attribute__((section(".dram"), aligned(4)))
radio/src/targets/common/arm/stm32/h7/system_stm32h7xx.c
-128
View File
@@ -444,134 +444,6 @@ void SystemCoreClockUpdate (void)
#endif /* DUAL_CORE && CORE_CM4 */
}
// TODO: better exception handler
void NMI_Handler(void){asm("BKPT");}
void HardFault_Handler(void){asm("BKPT");}
void MemManage_Handler(void){asm("BKPT");}
void BusFault_Handler(void){asm("BKPT");}
void UsageFault_Handler(void){asm("BKPT");}
//void SVC_Handler(void){asm("BKPT");}
void DebugMon_Handler(void){asm("BKPT");}
//void PendSV_Handler(void){asm("BKPT");}
//void SysTick_Handler(void){asm("BKPT");}
void WWDG_IRQHandler(void){asm("BKPT");}
void PVD_AVD_IRQHandler(void){asm("BKPT");}
void TAMP_STAMP_IRQHandler(void){asm("BKPT");}
void RTC_WKUP_IRQHandler(void){asm("BKPT");}
void FLASH_IRQHandler(void){asm("BKPT");}
void RCC_IRQHandler(void){asm("BKPT");}
void EXTI0_IRQHandler(void){asm("BKPT");}
void EXTI1_IRQHandler(void){asm("BKPT");}
void DMA1_Stream1_IRQHandler(void){asm("BKPT");}
void DMA1_Stream2_IRQHandler(void){asm("BKPT");}
void DMA1_Stream3_IRQHandler(void){asm("BKPT");}
void DMA1_Stream4_IRQHandler(void){asm("BKPT");}
//void ADC_IRQHandler(void){asm("BKPT");}
void FDCAN1_IT0_IRQHandler(void){asm("BKPT");}
void FDCAN2_IT0_IRQHandler(void){asm("BKPT");}
void FDCAN1_IT1_IRQHandler(void){asm("BKPT");}
void FDCAN2_IT1_IRQHandler(void){asm("BKPT");}
void TIM1_BRK_IRQHandler(void){asm("BKPT");}
void TIM1_UP_IRQHandler(void){asm("BKPT");}
void TIM1_TRG_COM_IRQHandler(void){asm("BKPT");}
void TIM1_CC_IRQHandler(void){asm("BKPT");}
void TIM2_IRQHandler(void){asm("BKPT");}
void TIM3_IRQHandler(void){asm("BKPT");}
// void TIM4_IRQHandler(void){asm("BKPT");}
void I2C1_EV_IRQHandler(void){asm("BKPT");}
void I2C1_ER_IRQHandler(void){asm("BKPT");}
void I2C2_EV_IRQHandler(void){asm("BKPT");}
void I2C2_ER_IRQHandler(void){asm("BKPT");}
void SPI1_IRQHandler(void){asm("BKPT");}
void SPI2_IRQHandler(void){asm("BKPT");}
//void EXTI15_10_IRQHandler(void){asm("BKPT");}
void RTC_Alarm_IRQHandler(void){asm("BKPT");}
void TIM8_CC_IRQHandler(void){asm("BKPT");}
//void DMA1_Stream7_IRQHandler(void){asm("BKPT");}
void FMC_IRQHandler(void){asm("BKPT");}
void TIM5_IRQHandler(void){asm("BKPT");}
void SPI3_IRQHandler(void){asm("BKPT");}
//void UART5_IRQHandler(void){asm("BKPT");}
void TIM7_IRQHandler(void){asm("BKPT");}
//void DMA2_Stream0_IRQHandler(void){asm("BKPT");}
void DMA2_Stream2_IRQHandler(void){asm("BKPT");}
void DMA2_Stream3_IRQHandler(void){asm("BKPT");}
//void DMA2_Stream4_IRQHandler(void){asm("BKPT");}
void ETH_IRQHandler(void){asm("BKPT");}
//void ETH_WKUP_IRQHandler(void){asm("BKPT");}
void FDCAN_CAL_IRQHandler(void){asm("BKPT");}
void DMA2_Stream5_IRQHandler(void){asm("BKPT");}
// void DMA2_Stream6_IRQHandler(void){asm("BKPT");}
void DMA2_Stream7_IRQHandler(void){asm("BKPT");}
void I2C3_EV_IRQHandler(void){asm("BKPT");}
void I2C3_ER_IRQHandler(void){asm("BKPT");}
void OTG_HS_EP1_OUT_IRQHandler(void){asm("BKPT");}
void OTG_HS_EP1_IN_IRQHandler(void){asm("BKPT");}
void OTG_HS_WKUP_IRQHandler(void){asm("BKPT");}
void OTG_HS_IRQHandler(void){asm("BKPT");}
void DCMI_IRQHandler(void){asm("BKPT");}
void CRYP_IRQHandler(void){asm("BKPT");}
void HASH_RNG_IRQHandler(void){asm("BKPT");}
void FPU_IRQHandler(void){asm("BKPT");}
//void UART8_IRQHandler(void){asm("BKPT");}
void SPI4_IRQHandler(void){asm("BKPT");}
void SPI5_IRQHandler(void){asm("BKPT");}
void SPI6_IRQHandler(void){asm("BKPT");}
void SAI1_IRQHandler(void){asm("BKPT");}
void LTDC_ER_IRQHandler(void){asm("BKPT");}
void DMA2D_IRQHandler(void){asm("BKPT");}
void SAI2_IRQHandler(void){asm("BKPT");}
void QUADSPI_IRQHandler(void){asm("BKPT");}
void LPTIM1_IRQHandler(void){asm("BKPT");}
void CEC_IRQHandler(void){asm("BKPT");}
void I2C4_EV_IRQHandler(void){asm("BKPT");}
void I2C4_ER_IRQHandler(void){asm("BKPT");}
void SPDIF_RX_IRQHandler(void){asm("BKPT");}
void OTG_FS_EP1_OUT_IRQHandler(void){asm("BKPT");}
void OTG_FS_EP1_IN_IRQHandler(void){asm("BKPT");}
void OTG_FS_WKUP_IRQHandler(void){asm("BKPT");}
void DMAMUX1_OVR_IRQHandler(void){asm("BKPT");}
void HRTIM1_Master_IRQHandler(void){asm("BKPT");}
void HRTIM1_TIMA_IRQHandler(void){asm("BKPT");}
void HRTIM1_TIMB_IRQHandler(void){asm("BKPT");}
void HRTIM1_TIMC_IRQHandler(void){asm("BKPT");}
void HRTIM1_TIMD_IRQHandler(void){asm("BKPT");}
void HRTIM1_TIME_IRQHandler(void){asm("BKPT");}
void HRTIM1_FLT_IRQHandler(void){asm("BKPT");}
void DFSDM1_FLT0_IRQHandler(void){asm("BKPT");}
void DFSDM1_FLT1_IRQHandler(void){asm("BKPT");}
void DFSDM1_FLT2_IRQHandler(void){asm("BKPT");}
void DFSDM1_FLT3_IRQHandler(void){asm("BKPT");}
void SAI3_IRQHandler(void){asm("BKPT");}
void SWPMI1_IRQHandler(void){asm("BKPT");}
void TIM16_IRQHandler(void){asm("BKPT");}
void MDIOS_WKUP_IRQHandler(void){asm("BKPT");}
void MDIOS_IRQHandler(void){asm("BKPT");}
void JPEG_IRQHandler(void){asm("BKPT");}
void MDMA_IRQHandler(void){asm("BKPT");}
void SDMMC2_IRQHandler(void){asm("BKPT");}
void HSEM1_IRQHandler(void){asm("BKPT");}
// void ADC3_IRQHandler(void){asm("BKPT");}
void DMAMUX2_OVR_IRQHandler(void){asm("BKPT");}
void BDMA_Channel0_IRQHandler(void){asm("BKPT");}
void BDMA_Channel1_IRQHandler(void){asm("BKPT");}
void BDMA_Channel2_IRQHandler(void){asm("BKPT");}
void BDMA_Channel3_IRQHandler(void){asm("BKPT");}
void BDMA_Channel4_IRQHandler(void){asm("BKPT");}
void BDMA_Channel5_IRQHandler(void){asm("BKPT");}
void BDMA_Channel6_IRQHandler(void){asm("BKPT");}
void BDMA_Channel7_IRQHandler(void){asm("BKPT");}
void COMP1_IRQHandler(void){asm("BKPT");}
void LPTIM2_IRQHandler(void){asm("BKPT");}
void LPTIM3_IRQHandler(void){asm("BKPT");}
void LPTIM4_IRQHandler(void){asm("BKPT");}
void LPTIM5_IRQHandler(void){asm("BKPT");}
void LPUART1_IRQHandler(void){asm("BKPT");}
void CRS_IRQHandler(void){asm("BKPT");}
void ECC_IRQHandler(void){asm("BKPT");}
void SAI4_IRQHandler(void){asm("BKPT");}
void WAKEUP_PIN_IRQHandler(void){asm("BKPT");}
/**
* @}
*/
radio/src/targets/common/arm/stm32/h7/vectors_stm32h747xx.c
+328
View File
@@ -0,0 +1,328 @@
#include "stm32h747xx.h"
#include "cortex_m_isr.h"
void Default_Handler() { default_isr_handler(); }
/* stm32h747xx specific interrupt vectors */
WEAK_DEFAULT void Reset_Handler();
WEAK_DEFAULT void NMI_Handler();
WEAK_DEFAULT void HardFault_Handler();
WEAK_DEFAULT void MemManage_Handler();
WEAK_DEFAULT void BusFault_Handler();
WEAK_DEFAULT void UsageFault_Handler();
WEAK_DEFAULT void SVC_Handler();
WEAK_DEFAULT void DebugMon_Handler();
WEAK_DEFAULT void PendSV_Handler();
WEAK_DEFAULT void SysTick_Handler();
WEAK_DEFAULT void WWDG_IRQHandler();
WEAK_DEFAULT void PVD_AVD_IRQHandler();
WEAK_DEFAULT void TAMP_STAMP_IRQHandler();
WEAK_DEFAULT void RTC_WKUP_IRQHandler();
WEAK_DEFAULT void FLASH_IRQHandler();
WEAK_DEFAULT void RCC_IRQHandler();
WEAK_DEFAULT void EXTI0_IRQHandler();
WEAK_DEFAULT void EXTI1_IRQHandler();
WEAK_DEFAULT void EXTI2_IRQHandler();
WEAK_DEFAULT void EXTI3_IRQHandler();
WEAK_DEFAULT void EXTI4_IRQHandler();
WEAK_DEFAULT void DMA1_Stream0_IRQHandler();
WEAK_DEFAULT void DMA1_Stream1_IRQHandler();
WEAK_DEFAULT void DMA1_Stream2_IRQHandler();
WEAK_DEFAULT void DMA1_Stream3_IRQHandler();
WEAK_DEFAULT void DMA1_Stream4_IRQHandler();
WEAK_DEFAULT void DMA1_Stream5_IRQHandler();
WEAK_DEFAULT void DMA1_Stream6_IRQHandler();
WEAK_DEFAULT void ADC_IRQHandler();
WEAK_DEFAULT void FDCAN1_IT0_IRQHandler();
WEAK_DEFAULT void FDCAN2_IT0_IRQHandler();
WEAK_DEFAULT void FDCAN1_IT1_IRQHandler();
WEAK_DEFAULT void FDCAN2_IT1_IRQHandler();
WEAK_DEFAULT void EXTI9_5_IRQHandler();
WEAK_DEFAULT void TIM1_BRK_IRQHandler();
WEAK_DEFAULT void TIM1_UP_IRQHandler();
WEAK_DEFAULT void TIM1_TRG_COM_IRQHandler();
WEAK_DEFAULT void TIM1_CC_IRQHandler();
WEAK_DEFAULT void TIM2_IRQHandler();
WEAK_DEFAULT void TIM3_IRQHandler();
WEAK_DEFAULT void TIM4_IRQHandler();
WEAK_DEFAULT void I2C1_EV_IRQHandler();
WEAK_DEFAULT void I2C1_ER_IRQHandler();
WEAK_DEFAULT void I2C2_EV_IRQHandler();
WEAK_DEFAULT void I2C2_ER_IRQHandler();
WEAK_DEFAULT void SPI1_IRQHandler();
WEAK_DEFAULT void SPI2_IRQHandler();
WEAK_DEFAULT void USART1_IRQHandler();
WEAK_DEFAULT void USART2_IRQHandler();
WEAK_DEFAULT void USART3_IRQHandler();
WEAK_DEFAULT void EXTI15_10_IRQHandler();
WEAK_DEFAULT void RTC_Alarm_IRQHandler();
WEAK_DEFAULT void TIM8_BRK_TIM12_IRQHandler();
WEAK_DEFAULT void TIM8_UP_TIM13_IRQHandler();
WEAK_DEFAULT void TIM8_TRG_COM_TIM14_IRQHandler();
WEAK_DEFAULT void TIM8_CC_IRQHandler();
WEAK_DEFAULT void DMA1_Stream7_IRQHandler();
WEAK_DEFAULT void FMC_IRQHandler();
WEAK_DEFAULT void SDMMC1_IRQHandler();
WEAK_DEFAULT void TIM5_IRQHandler();
WEAK_DEFAULT void SPI3_IRQHandler();
WEAK_DEFAULT void UART4_IRQHandler();
WEAK_DEFAULT void UART5_IRQHandler();
WEAK_DEFAULT void TIM6_DAC_IRQHandler();
WEAK_DEFAULT void TIM7_IRQHandler();
WEAK_DEFAULT void DMA2_Stream0_IRQHandler();
WEAK_DEFAULT void DMA2_Stream1_IRQHandler();
WEAK_DEFAULT void DMA2_Stream2_IRQHandler();
WEAK_DEFAULT void DMA2_Stream3_IRQHandler();
WEAK_DEFAULT void DMA2_Stream4_IRQHandler();
WEAK_DEFAULT void ETH_IRQHandler();
WEAK_DEFAULT void ETH_WKUP_IRQHandler();
WEAK_DEFAULT void FDCAN_CAL_IRQHandler();
WEAK_DEFAULT void CM7_SEV_IRQHandler();
WEAK_DEFAULT void CM4_SEV_IRQHandler();
WEAK_DEFAULT void DMA2_Stream5_IRQHandler();
WEAK_DEFAULT void DMA2_Stream6_IRQHandler();
WEAK_DEFAULT void DMA2_Stream7_IRQHandler();
WEAK_DEFAULT void USART6_IRQHandler();
WEAK_DEFAULT void I2C3_EV_IRQHandler();
WEAK_DEFAULT void I2C3_ER_IRQHandler();
WEAK_DEFAULT void OTG_HS_EP1_OUT_IRQHandler();
WEAK_DEFAULT void OTG_HS_EP1_IN_IRQHandler();
WEAK_DEFAULT void OTG_HS_WKUP_IRQHandler();
WEAK_DEFAULT void OTG_HS_IRQHandler();
WEAK_DEFAULT void DCMI_IRQHandler();
WEAK_DEFAULT void RNG_IRQHandler();
WEAK_DEFAULT void FPU_IRQHandler();
WEAK_DEFAULT void UART7_IRQHandler();
WEAK_DEFAULT void UART8_IRQHandler();
WEAK_DEFAULT void SPI4_IRQHandler();
WEAK_DEFAULT void SPI5_IRQHandler();
WEAK_DEFAULT void SPI6_IRQHandler();
WEAK_DEFAULT void SAI1_IRQHandler();
WEAK_DEFAULT void LTDC_IRQHandler();
WEAK_DEFAULT void LTDC_ER_IRQHandler();
WEAK_DEFAULT void DMA2D_IRQHandler();
WEAK_DEFAULT void SAI2_IRQHandler();
WEAK_DEFAULT void QUADSPI_IRQHandler();
WEAK_DEFAULT void LPTIM1_IRQHandler();
WEAK_DEFAULT void CEC_IRQHandler();
WEAK_DEFAULT void I2C4_EV_IRQHandler();
WEAK_DEFAULT void I2C4_ER_IRQHandler();
WEAK_DEFAULT void SPDIF_RX_IRQHandler();
WEAK_DEFAULT void OTG_FS_EP1_OUT_IRQHandler();
WEAK_DEFAULT void OTG_FS_EP1_IN_IRQHandler();
WEAK_DEFAULT void OTG_FS_WKUP_IRQHandler();
WEAK_DEFAULT void OTG_FS_IRQHandler();
WEAK_DEFAULT void DMAMUX1_OVR_IRQHandler();
WEAK_DEFAULT void HRTIM1_Master_IRQHandler();
WEAK_DEFAULT void HRTIM1_TIMA_IRQHandler();
WEAK_DEFAULT void HRTIM1_TIMB_IRQHandler();
WEAK_DEFAULT void HRTIM1_TIMC_IRQHandler();
WEAK_DEFAULT void HRTIM1_TIMD_IRQHandler();
WEAK_DEFAULT void HRTIM1_TIME_IRQHandler();
WEAK_DEFAULT void HRTIM1_FLT_IRQHandler();
WEAK_DEFAULT void DFSDM1_FLT0_IRQHandler();
WEAK_DEFAULT void DFSDM1_FLT1_IRQHandler();
WEAK_DEFAULT void DFSDM1_FLT2_IRQHandler();
WEAK_DEFAULT void DFSDM1_FLT3_IRQHandler();
WEAK_DEFAULT void SAI3_IRQHandler();
WEAK_DEFAULT void SWPMI1_IRQHandler();
WEAK_DEFAULT void TIM15_IRQHandler();
WEAK_DEFAULT void TIM16_IRQHandler();
WEAK_DEFAULT void TIM17_IRQHandler();
WEAK_DEFAULT void MDIOS_WKUP_IRQHandler();
WEAK_DEFAULT void MDIOS_IRQHandler();
WEAK_DEFAULT void JPEG_IRQHandler();
WEAK_DEFAULT void MDMA_IRQHandler();
WEAK_DEFAULT void DSI_IRQHandler();
WEAK_DEFAULT void SDMMC2_IRQHandler();
WEAK_DEFAULT void HSEM1_IRQHandler();
WEAK_DEFAULT void HSEM2_IRQHandler();
WEAK_DEFAULT void ADC3_IRQHandler();
WEAK_DEFAULT void DMAMUX2_OVR_IRQHandler();
WEAK_DEFAULT void BDMA_Channel0_IRQHandler();
WEAK_DEFAULT void BDMA_Channel1_IRQHandler();
WEAK_DEFAULT void BDMA_Channel2_IRQHandler();
WEAK_DEFAULT void BDMA_Channel3_IRQHandler();
WEAK_DEFAULT void BDMA_Channel4_IRQHandler();
WEAK_DEFAULT void BDMA_Channel5_IRQHandler();
WEAK_DEFAULT void BDMA_Channel6_IRQHandler();
WEAK_DEFAULT void BDMA_Channel7_IRQHandler();
WEAK_DEFAULT void COMP_IRQHandler();
WEAK_DEFAULT void LPTIM2_IRQHandler();
WEAK_DEFAULT void LPTIM3_IRQHandler();
WEAK_DEFAULT void LPTIM4_IRQHandler();
WEAK_DEFAULT void LPTIM5_IRQHandler();
WEAK_DEFAULT void LPUART1_IRQHandler();
WEAK_DEFAULT void WWDG_RST_IRQHandler();
WEAK_DEFAULT void CRS_IRQHandler();
WEAK_DEFAULT void ECC_IRQHandler();
WEAK_DEFAULT void SAI4_IRQHandler();
WEAK_DEFAULT void HOLD_CORE_IRQHandler();
WEAK_DEFAULT void WAKEUP_PIN_IRQHandler();
/* CPU specific interrupt vector table */
const isr_t g_pnfVectors[] ISR_VECTOR = {
[0] = (isr_t)&_estack,
[1 ] = Reset_Handler,
[2 ] = NMI_Handler,
[3 ] = HardFault_Handler,
[4 ] = MemManage_Handler,
[5 ] = BusFault_Handler,
[6 ] = UsageFault_Handler,
[7 ] = 0,
[8 ] = 0,
[9 ] = 0,
[10 ] = 0,
[11 ] = SVC_Handler,
[12 ] = DebugMon_Handler,
[13 ] = 0,
[14 ] = PendSV_Handler,
[15 ] = SysTick_Handler,
[WWDG_IRQn + 16 ] = WWDG_IRQHandler,
[PVD_AVD_IRQn + 16 ] = PVD_AVD_IRQHandler,
[TAMP_STAMP_IRQn + 16 ] = TAMP_STAMP_IRQHandler,
[RTC_WKUP_IRQn + 16 ] = RTC_WKUP_IRQHandler,
[FLASH_IRQn + 16 ] = FLASH_IRQHandler,
[RCC_IRQn + 16 ] = RCC_IRQHandler,
[EXTI0_IRQn + 16 ] = EXTI0_IRQHandler,
[EXTI1_IRQn + 16 ] = EXTI1_IRQHandler,
[EXTI2_IRQn + 16 ] = EXTI2_IRQHandler,
[EXTI3_IRQn + 16 ] = EXTI3_IRQHandler,
[EXTI4_IRQn + 16 ] = EXTI4_IRQHandler,
[DMA1_Stream0_IRQn + 16 ] = DMA1_Stream0_IRQHandler,
[DMA1_Stream1_IRQn + 16 ] = DMA1_Stream1_IRQHandler,
[DMA1_Stream2_IRQn + 16 ] = DMA1_Stream2_IRQHandler,
[DMA1_Stream3_IRQn + 16 ] = DMA1_Stream3_IRQHandler,
[DMA1_Stream4_IRQn + 16 ] = DMA1_Stream4_IRQHandler,
[DMA1_Stream5_IRQn + 16 ] = DMA1_Stream5_IRQHandler,
[DMA1_Stream6_IRQn + 16 ] = DMA1_Stream6_IRQHandler,
[ADC_IRQn + 16 ] = ADC_IRQHandler,
[FDCAN1_IT0_IRQn + 16 ] = FDCAN1_IT0_IRQHandler,
[FDCAN2_IT0_IRQn + 16 ] = FDCAN2_IT0_IRQHandler,
[FDCAN1_IT1_IRQn + 16 ] = FDCAN1_IT1_IRQHandler,
[FDCAN2_IT1_IRQn + 16 ] = FDCAN2_IT1_IRQHandler,
[EXTI9_5_IRQn + 16 ] = EXTI9_5_IRQHandler,
[TIM1_BRK_IRQn + 16 ] = TIM1_BRK_IRQHandler,
[TIM1_UP_IRQn + 16 ] = TIM1_UP_IRQHandler,
[TIM1_TRG_COM_IRQn + 16 ] = TIM1_TRG_COM_IRQHandler,
[TIM1_CC_IRQn + 16 ] = TIM1_CC_IRQHandler,
[TIM2_IRQn + 16 ] = TIM2_IRQHandler,
[TIM3_IRQn + 16 ] = TIM3_IRQHandler,
[TIM4_IRQn + 16 ] = TIM4_IRQHandler,
[I2C1_EV_IRQn + 16 ] = I2C1_EV_IRQHandler,
[I2C1_ER_IRQn + 16 ] = I2C1_ER_IRQHandler,
[I2C2_EV_IRQn + 16 ] = I2C2_EV_IRQHandler,
[I2C2_ER_IRQn + 16 ] = I2C2_ER_IRQHandler,
[SPI1_IRQn + 16 ] = SPI1_IRQHandler,
[SPI2_IRQn + 16 ] = SPI2_IRQHandler,
[USART1_IRQn + 16 ] = USART1_IRQHandler,
[USART2_IRQn + 16 ] = USART2_IRQHandler,
[USART3_IRQn + 16 ] = USART3_IRQHandler,
[EXTI15_10_IRQn + 16 ] = EXTI15_10_IRQHandler,
[RTC_Alarm_IRQn + 16 ] = RTC_Alarm_IRQHandler,
[TIM8_BRK_TIM12_IRQn + 16 ] = TIM8_BRK_TIM12_IRQHandler,
[TIM8_UP_TIM13_IRQn + 16 ] = TIM8_UP_TIM13_IRQHandler,
[TIM8_TRG_COM_TIM14_IRQn + 16 ] = TIM8_TRG_COM_TIM14_IRQHandler,
[TIM8_CC_IRQn + 16 ] = TIM8_CC_IRQHandler,
[DMA1_Stream7_IRQn + 16 ] = DMA1_Stream7_IRQHandler,
[FMC_IRQn + 16 ] = FMC_IRQHandler,
[SDMMC1_IRQn + 16 ] = SDMMC1_IRQHandler,
[TIM5_IRQn + 16 ] = TIM5_IRQHandler,
[SPI3_IRQn + 16 ] = SPI3_IRQHandler,
[UART4_IRQn + 16 ] = UART4_IRQHandler,
[UART5_IRQn + 16 ] = UART5_IRQHandler,
[TIM6_DAC_IRQn + 16 ] = TIM6_DAC_IRQHandler,
[TIM7_IRQn + 16 ] = TIM7_IRQHandler,
[DMA2_Stream0_IRQn + 16 ] = DMA2_Stream0_IRQHandler,
[DMA2_Stream1_IRQn + 16 ] = DMA2_Stream1_IRQHandler,
[DMA2_Stream2_IRQn + 16 ] = DMA2_Stream2_IRQHandler,
[DMA2_Stream3_IRQn + 16 ] = DMA2_Stream3_IRQHandler,
[DMA2_Stream4_IRQn + 16 ] = DMA2_Stream4_IRQHandler,
[ETH_IRQn + 16 ] = ETH_IRQHandler,
[ETH_WKUP_IRQn + 16 ] = ETH_WKUP_IRQHandler,
[FDCAN_CAL_IRQn + 16 ] = FDCAN_CAL_IRQHandler,
[CM7_SEV_IRQn + 16 ] = CM7_SEV_IRQHandler,
[CM4_SEV_IRQn + 16 ] = CM4_SEV_IRQHandler,
[DMA2_Stream5_IRQn + 16 ] = DMA2_Stream5_IRQHandler,
[DMA2_Stream6_IRQn + 16 ] = DMA2_Stream6_IRQHandler,
[DMA2_Stream7_IRQn + 16 ] = DMA2_Stream7_IRQHandler,
[USART6_IRQn + 16 ] = USART6_IRQHandler,
[I2C3_EV_IRQn + 16 ] = I2C3_EV_IRQHandler,
[I2C3_ER_IRQn + 16 ] = I2C3_ER_IRQHandler,
[OTG_HS_EP1_OUT_IRQn + 16 ] = OTG_HS_EP1_OUT_IRQHandler,
[OTG_HS_EP1_IN_IRQn + 16 ] = OTG_HS_EP1_IN_IRQHandler,
[OTG_HS_WKUP_IRQn + 16 ] = OTG_HS_WKUP_IRQHandler,
[OTG_HS_IRQn + 16 ] = OTG_HS_IRQHandler,
[DCMI_IRQn + 16 ] = DCMI_IRQHandler,
[RNG_IRQn + 16 ] = RNG_IRQHandler,
[FPU_IRQn + 16 ] = FPU_IRQHandler,
[UART7_IRQn + 16 ] = UART7_IRQHandler,
[UART8_IRQn + 16 ] = UART8_IRQHandler,
[SPI4_IRQn + 16 ] = SPI4_IRQHandler,
[SPI5_IRQn + 16 ] = SPI5_IRQHandler,
[SPI6_IRQn + 16 ] = SPI6_IRQHandler,
[SAI1_IRQn + 16 ] = SAI1_IRQHandler,
[LTDC_IRQn + 16 ] = LTDC_IRQHandler,
[LTDC_ER_IRQn + 16 ] = LTDC_ER_IRQHandler,
[DMA2D_IRQn + 16 ] = DMA2D_IRQHandler,
[SAI2_IRQn + 16 ] = SAI2_IRQHandler,
[QUADSPI_IRQn + 16 ] = QUADSPI_IRQHandler,
[LPTIM1_IRQn + 16 ] = LPTIM1_IRQHandler,
[CEC_IRQn + 16 ] = CEC_IRQHandler,
[I2C4_EV_IRQn + 16 ] = I2C4_EV_IRQHandler,
[I2C4_ER_IRQn + 16 ] = I2C4_ER_IRQHandler,
[SPDIF_RX_IRQn + 16 ] = SPDIF_RX_IRQHandler,
[OTG_FS_EP1_OUT_IRQn + 16 ] = OTG_FS_EP1_OUT_IRQHandler,
[OTG_FS_EP1_IN_IRQn + 16 ] = OTG_FS_EP1_IN_IRQHandler,
[OTG_FS_WKUP_IRQn + 16 ] = OTG_FS_WKUP_IRQHandler,
[OTG_FS_IRQn + 16 ] = OTG_FS_IRQHandler,
[DMAMUX1_OVR_IRQn + 16 ] = DMAMUX1_OVR_IRQHandler,
[HRTIM1_Master_IRQn + 16 ] = HRTIM1_Master_IRQHandler,
[HRTIM1_TIMA_IRQn + 16 ] = HRTIM1_TIMA_IRQHandler,
[HRTIM1_TIMB_IRQn + 16 ] = HRTIM1_TIMB_IRQHandler,
[HRTIM1_TIMC_IRQn + 16 ] = HRTIM1_TIMC_IRQHandler,
[HRTIM1_TIMD_IRQn + 16 ] = HRTIM1_TIMD_IRQHandler,
[HRTIM1_TIME_IRQn + 16 ] = HRTIM1_TIME_IRQHandler,
[HRTIM1_FLT_IRQn + 16 ] = HRTIM1_FLT_IRQHandler,
[DFSDM1_FLT0_IRQn + 16 ] = DFSDM1_FLT0_IRQHandler,
[DFSDM1_FLT1_IRQn + 16 ] = DFSDM1_FLT1_IRQHandler,
[DFSDM1_FLT2_IRQn + 16 ] = DFSDM1_FLT2_IRQHandler,
[DFSDM1_FLT3_IRQn + 16 ] = DFSDM1_FLT3_IRQHandler,
[SAI3_IRQn + 16 ] = SAI3_IRQHandler,
[SWPMI1_IRQn + 16 ] = SWPMI1_IRQHandler,
[TIM15_IRQn + 16 ] = TIM15_IRQHandler,
[TIM16_IRQn + 16 ] = TIM16_IRQHandler,
[TIM17_IRQn + 16 ] = TIM17_IRQHandler,
[MDIOS_WKUP_IRQn + 16 ] = MDIOS_WKUP_IRQHandler,
[MDIOS_IRQn + 16 ] = MDIOS_IRQHandler,
[JPEG_IRQn + 16 ] = JPEG_IRQHandler,
[MDMA_IRQn + 16 ] = MDMA_IRQHandler,
[DSI_IRQn + 16 ] = DSI_IRQHandler,
[SDMMC2_IRQn + 16 ] = SDMMC2_IRQHandler,
[HSEM1_IRQn + 16 ] = HSEM1_IRQHandler,
[HSEM2_IRQn + 16 ] = HSEM2_IRQHandler,
[ADC3_IRQn + 16 ] = ADC3_IRQHandler,
[DMAMUX2_OVR_IRQn + 16 ] = DMAMUX2_OVR_IRQHandler,
[BDMA_Channel0_IRQn + 16 ] = BDMA_Channel0_IRQHandler,
[BDMA_Channel1_IRQn + 16 ] = BDMA_Channel1_IRQHandler,
[BDMA_Channel2_IRQn + 16 ] = BDMA_Channel2_IRQHandler,
[BDMA_Channel3_IRQn + 16 ] = BDMA_Channel3_IRQHandler,
[BDMA_Channel4_IRQn + 16 ] = BDMA_Channel4_IRQHandler,
[BDMA_Channel5_IRQn + 16 ] = BDMA_Channel5_IRQHandler,
[BDMA_Channel6_IRQn + 16 ] = BDMA_Channel6_IRQHandler,
[BDMA_Channel7_IRQn + 16 ] = BDMA_Channel7_IRQHandler,
[COMP_IRQn + 16 ] = COMP_IRQHandler,
[LPTIM2_IRQn + 16 ] = LPTIM2_IRQHandler,
[LPTIM3_IRQn + 16 ] = LPTIM3_IRQHandler,
[LPTIM4_IRQn + 16 ] = LPTIM4_IRQHandler,
[LPTIM5_IRQn + 16 ] = LPTIM5_IRQHandler,
[LPUART1_IRQn + 16 ] = LPUART1_IRQHandler,
[WWDG_RST_IRQn + 16 ] = WWDG_RST_IRQHandler,
[CRS_IRQn + 16 ] = CRS_IRQHandler,
[ECC_IRQn + 16 ] = ECC_IRQHandler,
[SAI4_IRQn + 16 ] = SAI4_IRQHandler,
[HOLD_CORE_IRQn + 16 ] = HOLD_CORE_IRQHandler,
[WAKEUP_PIN_IRQn + 16 ] = WAKEUP_PIN_IRQHandler,
};
radio/src/targets/common/arm/stm32/h7/vectors_stm32h750xx.c
+318
View File
@@ -0,0 +1,318 @@
#include "stm32h750xx.h"
#include "cortex_m_isr.h"
void Default_Handler() { default_isr_handler(); }
/* stm32h750xx specific interrupt vectors */
WEAK_DEFAULT void Reset_Handler();
WEAK_DEFAULT void NMI_Handler();
WEAK_DEFAULT void HardFault_Handler();
WEAK_DEFAULT void MemManage_Handler();
WEAK_DEFAULT void BusFault_Handler();
WEAK_DEFAULT void UsageFault_Handler();
WEAK_DEFAULT void SVC_Handler();
WEAK_DEFAULT void DebugMon_Handler();
WEAK_DEFAULT void PendSV_Handler();
WEAK_DEFAULT void SysTick_Handler();
WEAK_DEFAULT void WWDG_IRQHandler();
WEAK_DEFAULT void PVD_AVD_IRQHandler();
WEAK_DEFAULT void TAMP_STAMP_IRQHandler();
WEAK_DEFAULT void RTC_WKUP_IRQHandler();
WEAK_DEFAULT void FLASH_IRQHandler();
WEAK_DEFAULT void RCC_IRQHandler();
WEAK_DEFAULT void EXTI0_IRQHandler();
WEAK_DEFAULT void EXTI1_IRQHandler();
WEAK_DEFAULT void EXTI2_IRQHandler();
WEAK_DEFAULT void EXTI3_IRQHandler();
WEAK_DEFAULT void EXTI4_IRQHandler();
WEAK_DEFAULT void DMA1_Stream0_IRQHandler();
WEAK_DEFAULT void DMA1_Stream1_IRQHandler();
WEAK_DEFAULT void DMA1_Stream2_IRQHandler();
WEAK_DEFAULT void DMA1_Stream3_IRQHandler();
WEAK_DEFAULT void DMA1_Stream4_IRQHandler();
WEAK_DEFAULT void DMA1_Stream5_IRQHandler();
WEAK_DEFAULT void DMA1_Stream6_IRQHandler();
WEAK_DEFAULT void ADC_IRQHandler();
WEAK_DEFAULT void FDCAN1_IT0_IRQHandler();
WEAK_DEFAULT void FDCAN2_IT0_IRQHandler();
WEAK_DEFAULT void FDCAN1_IT1_IRQHandler();
WEAK_DEFAULT void FDCAN2_IT1_IRQHandler();
WEAK_DEFAULT void EXTI9_5_IRQHandler();
WEAK_DEFAULT void TIM1_BRK_IRQHandler();
WEAK_DEFAULT void TIM1_UP_IRQHandler();
WEAK_DEFAULT void TIM1_TRG_COM_IRQHandler();
WEAK_DEFAULT void TIM1_CC_IRQHandler();
WEAK_DEFAULT void TIM2_IRQHandler();
WEAK_DEFAULT void TIM3_IRQHandler();
WEAK_DEFAULT void TIM4_IRQHandler();
WEAK_DEFAULT void I2C1_EV_IRQHandler();
WEAK_DEFAULT void I2C1_ER_IRQHandler();
WEAK_DEFAULT void I2C2_EV_IRQHandler();
WEAK_DEFAULT void I2C2_ER_IRQHandler();
WEAK_DEFAULT void SPI1_IRQHandler();
WEAK_DEFAULT void SPI2_IRQHandler();
WEAK_DEFAULT void USART1_IRQHandler();
WEAK_DEFAULT void USART2_IRQHandler();
WEAK_DEFAULT void USART3_IRQHandler();
WEAK_DEFAULT void EXTI15_10_IRQHandler();
WEAK_DEFAULT void RTC_Alarm_IRQHandler();
WEAK_DEFAULT void TIM8_BRK_TIM12_IRQHandler();
WEAK_DEFAULT void TIM8_UP_TIM13_IRQHandler();
WEAK_DEFAULT void TIM8_TRG_COM_TIM14_IRQHandler();
WEAK_DEFAULT void TIM8_CC_IRQHandler();
WEAK_DEFAULT void DMA1_Stream7_IRQHandler();
WEAK_DEFAULT void FMC_IRQHandler();
WEAK_DEFAULT void SDMMC1_IRQHandler();
WEAK_DEFAULT void TIM5_IRQHandler();
WEAK_DEFAULT void SPI3_IRQHandler();
WEAK_DEFAULT void UART4_IRQHandler();
WEAK_DEFAULT void UART5_IRQHandler();
WEAK_DEFAULT void TIM6_DAC_IRQHandler();
WEAK_DEFAULT void TIM7_IRQHandler();
WEAK_DEFAULT void DMA2_Stream0_IRQHandler();
WEAK_DEFAULT void DMA2_Stream1_IRQHandler();
WEAK_DEFAULT void DMA2_Stream2_IRQHandler();
WEAK_DEFAULT void DMA2_Stream3_IRQHandler();
WEAK_DEFAULT void DMA2_Stream4_IRQHandler();
WEAK_DEFAULT void ETH_IRQHandler();
WEAK_DEFAULT void ETH_WKUP_IRQHandler();
WEAK_DEFAULT void FDCAN_CAL_IRQHandler();
WEAK_DEFAULT void DMA2_Stream5_IRQHandler();
WEAK_DEFAULT void DMA2_Stream6_IRQHandler();
WEAK_DEFAULT void DMA2_Stream7_IRQHandler();
WEAK_DEFAULT void USART6_IRQHandler();
WEAK_DEFAULT void I2C3_EV_IRQHandler();
WEAK_DEFAULT void I2C3_ER_IRQHandler();
WEAK_DEFAULT void OTG_HS_EP1_OUT_IRQHandler();
WEAK_DEFAULT void OTG_HS_EP1_IN_IRQHandler();
WEAK_DEFAULT void OTG_HS_WKUP_IRQHandler();
WEAK_DEFAULT void OTG_HS_IRQHandler();
WEAK_DEFAULT void DCMI_IRQHandler();
WEAK_DEFAULT void CRYP_IRQHandler();
WEAK_DEFAULT void HASH_RNG_IRQHandler();
WEAK_DEFAULT void FPU_IRQHandler();
WEAK_DEFAULT void UART7_IRQHandler();
WEAK_DEFAULT void UART8_IRQHandler();
WEAK_DEFAULT void SPI4_IRQHandler();
WEAK_DEFAULT void SPI5_IRQHandler();
WEAK_DEFAULT void SPI6_IRQHandler();
WEAK_DEFAULT void SAI1_IRQHandler();
WEAK_DEFAULT void LTDC_IRQHandler();
WEAK_DEFAULT void LTDC_ER_IRQHandler();
WEAK_DEFAULT void DMA2D_IRQHandler();
WEAK_DEFAULT void SAI2_IRQHandler();
WEAK_DEFAULT void QUADSPI_IRQHandler();
WEAK_DEFAULT void LPTIM1_IRQHandler();
WEAK_DEFAULT void CEC_IRQHandler();
WEAK_DEFAULT void I2C4_EV_IRQHandler();
WEAK_DEFAULT void I2C4_ER_IRQHandler();
WEAK_DEFAULT void SPDIF_RX_IRQHandler();
WEAK_DEFAULT void OTG_FS_EP1_OUT_IRQHandler();
WEAK_DEFAULT void OTG_FS_EP1_IN_IRQHandler();
WEAK_DEFAULT void OTG_FS_WKUP_IRQHandler();
WEAK_DEFAULT void OTG_FS_IRQHandler();
WEAK_DEFAULT void DMAMUX1_OVR_IRQHandler();
WEAK_DEFAULT void HRTIM1_Master_IRQHandler();
WEAK_DEFAULT void HRTIM1_TIMA_IRQHandler();
WEAK_DEFAULT void HRTIM1_TIMB_IRQHandler();
WEAK_DEFAULT void HRTIM1_TIMC_IRQHandler();
WEAK_DEFAULT void HRTIM1_TIMD_IRQHandler();
WEAK_DEFAULT void HRTIM1_TIME_IRQHandler();
WEAK_DEFAULT void HRTIM1_FLT_IRQHandler();
WEAK_DEFAULT void DFSDM1_FLT0_IRQHandler();
WEAK_DEFAULT void DFSDM1_FLT1_IRQHandler();
WEAK_DEFAULT void DFSDM1_FLT2_IRQHandler();
WEAK_DEFAULT void DFSDM1_FLT3_IRQHandler();
WEAK_DEFAULT void SAI3_IRQHandler();
WEAK_DEFAULT void SWPMI1_IRQHandler();
WEAK_DEFAULT void TIM15_IRQHandler();
WEAK_DEFAULT void TIM16_IRQHandler();
WEAK_DEFAULT void TIM17_IRQHandler();
WEAK_DEFAULT void MDIOS_WKUP_IRQHandler();
WEAK_DEFAULT void MDIOS_IRQHandler();
WEAK_DEFAULT void JPEG_IRQHandler();
WEAK_DEFAULT void MDMA_IRQHandler();
WEAK_DEFAULT void SDMMC2_IRQHandler();
WEAK_DEFAULT void HSEM1_IRQHandler();
WEAK_DEFAULT void ADC3_IRQHandler();
WEAK_DEFAULT void DMAMUX2_OVR_IRQHandler();
WEAK_DEFAULT void BDMA_Channel0_IRQHandler();
WEAK_DEFAULT void BDMA_Channel1_IRQHandler();
WEAK_DEFAULT void BDMA_Channel2_IRQHandler();
WEAK_DEFAULT void BDMA_Channel3_IRQHandler();
WEAK_DEFAULT void BDMA_Channel4_IRQHandler();
WEAK_DEFAULT void BDMA_Channel5_IRQHandler();
WEAK_DEFAULT void BDMA_Channel6_IRQHandler();
WEAK_DEFAULT void BDMA_Channel7_IRQHandler();
WEAK_DEFAULT void COMP_IRQHandler();
WEAK_DEFAULT void LPTIM2_IRQHandler();
WEAK_DEFAULT void LPTIM3_IRQHandler();
WEAK_DEFAULT void LPTIM4_IRQHandler();
WEAK_DEFAULT void LPTIM5_IRQHandler();
WEAK_DEFAULT void LPUART1_IRQHandler();
WEAK_DEFAULT void CRS_IRQHandler();
WEAK_DEFAULT void ECC_IRQHandler();
WEAK_DEFAULT void SAI4_IRQHandler();
WEAK_DEFAULT void WAKEUP_PIN_IRQHandler();
/* CPU specific interrupt vector table */
const isr_t g_pnfVectors[] ISR_VECTOR = {
[0] = (isr_t)&_estack,
[1 ] = Reset_Handler,
[2 ] = NMI_Handler,
[3 ] = HardFault_Handler,
[4 ] = MemManage_Handler,
[5 ] = BusFault_Handler,
[6 ] = UsageFault_Handler,
[7 ] = 0,
[8 ] = 0,
[9 ] = 0,
[10 ] = 0,
[11 ] = SVC_Handler,
[12 ] = DebugMon_Handler,
[13 ] = 0,
[14 ] = PendSV_Handler,
[15 ] = SysTick_Handler,
[WWDG_IRQn + 16 ] = WWDG_IRQHandler,
[PVD_AVD_IRQn + 16 ] = PVD_AVD_IRQHandler,
[TAMP_STAMP_IRQn + 16 ] = TAMP_STAMP_IRQHandler,
[RTC_WKUP_IRQn + 16 ] = RTC_WKUP_IRQHandler,
[FLASH_IRQn + 16 ] = FLASH_IRQHandler,
[RCC_IRQn + 16 ] = RCC_IRQHandler,
[EXTI0_IRQn + 16 ] = EXTI0_IRQHandler,
[EXTI1_IRQn + 16 ] = EXTI1_IRQHandler,
[EXTI2_IRQn + 16 ] = EXTI2_IRQHandler,
[EXTI3_IRQn + 16 ] = EXTI3_IRQHandler,
[EXTI4_IRQn + 16 ] = EXTI4_IRQHandler,
[DMA1_Stream0_IRQn + 16 ] = DMA1_Stream0_IRQHandler,
[DMA1_Stream1_IRQn + 16 ] = DMA1_Stream1_IRQHandler,
[DMA1_Stream2_IRQn + 16 ] = DMA1_Stream2_IRQHandler,
[DMA1_Stream3_IRQn + 16 ] = DMA1_Stream3_IRQHandler,
[DMA1_Stream4_IRQn + 16 ] = DMA1_Stream4_IRQHandler,
[DMA1_Stream5_IRQn + 16 ] = DMA1_Stream5_IRQHandler,
[DMA1_Stream6_IRQn + 16 ] = DMA1_Stream6_IRQHandler,
[ADC_IRQn + 16 ] = ADC_IRQHandler,
[FDCAN1_IT0_IRQn + 16 ] = FDCAN1_IT0_IRQHandler,
[FDCAN2_IT0_IRQn + 16 ] = FDCAN2_IT0_IRQHandler,
[FDCAN1_IT1_IRQn + 16 ] = FDCAN1_IT1_IRQHandler,
[FDCAN2_IT1_IRQn + 16 ] = FDCAN2_IT1_IRQHandler,
[EXTI9_5_IRQn + 16 ] = EXTI9_5_IRQHandler,
[TIM1_BRK_IRQn + 16 ] = TIM1_BRK_IRQHandler,
[TIM1_UP_IRQn + 16 ] = TIM1_UP_IRQHandler,
[TIM1_TRG_COM_IRQn + 16 ] = TIM1_TRG_COM_IRQHandler,
[TIM1_CC_IRQn + 16 ] = TIM1_CC_IRQHandler,
[TIM2_IRQn + 16 ] = TIM2_IRQHandler,
[TIM3_IRQn + 16 ] = TIM3_IRQHandler,
[TIM4_IRQn + 16 ] = TIM4_IRQHandler,
[I2C1_EV_IRQn + 16 ] = I2C1_EV_IRQHandler,
[I2C1_ER_IRQn + 16 ] = I2C1_ER_IRQHandler,
[I2C2_EV_IRQn + 16 ] = I2C2_EV_IRQHandler,
[I2C2_ER_IRQn + 16 ] = I2C2_ER_IRQHandler,
[SPI1_IRQn + 16 ] = SPI1_IRQHandler,
[SPI2_IRQn + 16 ] = SPI2_IRQHandler,
[USART1_IRQn + 16 ] = USART1_IRQHandler,
[USART2_IRQn + 16 ] = USART2_IRQHandler,
[USART3_IRQn + 16 ] = USART3_IRQHandler,
[EXTI15_10_IRQn + 16 ] = EXTI15_10_IRQHandler,
[RTC_Alarm_IRQn + 16 ] = RTC_Alarm_IRQHandler,
[TIM8_BRK_TIM12_IRQn + 16 ] = TIM8_BRK_TIM12_IRQHandler,
[TIM8_UP_TIM13_IRQn + 16 ] = TIM8_UP_TIM13_IRQHandler,
[TIM8_TRG_COM_TIM14_IRQn + 16 ] = TIM8_TRG_COM_TIM14_IRQHandler,
[TIM8_CC_IRQn + 16 ] = TIM8_CC_IRQHandler,
[DMA1_Stream7_IRQn + 16 ] = DMA1_Stream7_IRQHandler,
[FMC_IRQn + 16 ] = FMC_IRQHandler,
[SDMMC1_IRQn + 16 ] = SDMMC1_IRQHandler,
[TIM5_IRQn + 16 ] = TIM5_IRQHandler,
[SPI3_IRQn + 16 ] = SPI3_IRQHandler,
[UART4_IRQn + 16 ] = UART4_IRQHandler,
[UART5_IRQn + 16 ] = UART5_IRQHandler,
[TIM6_DAC_IRQn + 16 ] = TIM6_DAC_IRQHandler,
[TIM7_IRQn + 16 ] = TIM7_IRQHandler,
[DMA2_Stream0_IRQn + 16 ] = DMA2_Stream0_IRQHandler,
[DMA2_Stream1_IRQn + 16 ] = DMA2_Stream1_IRQHandler,
[DMA2_Stream2_IRQn + 16 ] = DMA2_Stream2_IRQHandler,
[DMA2_Stream3_IRQn + 16 ] = DMA2_Stream3_IRQHandler,
[DMA2_Stream4_IRQn + 16 ] = DMA2_Stream4_IRQHandler,
[ETH_IRQn + 16 ] = ETH_IRQHandler,
[ETH_WKUP_IRQn + 16 ] = ETH_WKUP_IRQHandler,
[FDCAN_CAL_IRQn + 16 ] = FDCAN_CAL_IRQHandler,
[DMA2_Stream5_IRQn + 16 ] = DMA2_Stream5_IRQHandler,
[DMA2_Stream6_IRQn + 16 ] = DMA2_Stream6_IRQHandler,
[DMA2_Stream7_IRQn + 16 ] = DMA2_Stream7_IRQHandler,
[USART6_IRQn + 16 ] = USART6_IRQHandler,
[I2C3_EV_IRQn + 16 ] = I2C3_EV_IRQHandler,
[I2C3_ER_IRQn + 16 ] = I2C3_ER_IRQHandler,
[OTG_HS_EP1_OUT_IRQn + 16 ] = OTG_HS_EP1_OUT_IRQHandler,
[OTG_HS_EP1_IN_IRQn + 16 ] = OTG_HS_EP1_IN_IRQHandler,
[OTG_HS_WKUP_IRQn + 16 ] = OTG_HS_WKUP_IRQHandler,
[OTG_HS_IRQn + 16 ] = OTG_HS_IRQHandler,
[DCMI_IRQn + 16 ] = DCMI_IRQHandler,
[CRYP_IRQn + 16 ] = CRYP_IRQHandler,
[HASH_RNG_IRQn + 16 ] = HASH_RNG_IRQHandler,
[FPU_IRQn + 16 ] = FPU_IRQHandler,
[UART7_IRQn + 16 ] = UART7_IRQHandler,
[UART8_IRQn + 16 ] = UART8_IRQHandler,
[SPI4_IRQn + 16 ] = SPI4_IRQHandler,
[SPI5_IRQn + 16 ] = SPI5_IRQHandler,
[SPI6_IRQn + 16 ] = SPI6_IRQHandler,
[SAI1_IRQn + 16 ] = SAI1_IRQHandler,
[LTDC_IRQn + 16 ] = LTDC_IRQHandler,
[LTDC_ER_IRQn + 16 ] = LTDC_ER_IRQHandler,
[DMA2D_IRQn + 16 ] = DMA2D_IRQHandler,
[SAI2_IRQn + 16 ] = SAI2_IRQHandler,
[QUADSPI_IRQn + 16 ] = QUADSPI_IRQHandler,
[LPTIM1_IRQn + 16 ] = LPTIM1_IRQHandler,
[CEC_IRQn + 16 ] = CEC_IRQHandler,
[I2C4_EV_IRQn + 16 ] = I2C4_EV_IRQHandler,
[I2C4_ER_IRQn + 16 ] = I2C4_ER_IRQHandler,
[SPDIF_RX_IRQn + 16 ] = SPDIF_RX_IRQHandler,
[OTG_FS_EP1_OUT_IRQn + 16 ] = OTG_FS_EP1_OUT_IRQHandler,
[OTG_FS_EP1_IN_IRQn + 16 ] = OTG_FS_EP1_IN_IRQHandler,
[OTG_FS_WKUP_IRQn + 16 ] = OTG_FS_WKUP_IRQHandler,
[OTG_FS_IRQn + 16 ] = OTG_FS_IRQHandler,
[DMAMUX1_OVR_IRQn + 16 ] = DMAMUX1_OVR_IRQHandler,
[HRTIM1_Master_IRQn + 16 ] = HRTIM1_Master_IRQHandler,
[HRTIM1_TIMA_IRQn + 16 ] = HRTIM1_TIMA_IRQHandler,
[HRTIM1_TIMB_IRQn + 16 ] = HRTIM1_TIMB_IRQHandler,
[HRTIM1_TIMC_IRQn + 16 ] = HRTIM1_TIMC_IRQHandler,
[HRTIM1_TIMD_IRQn + 16 ] = HRTIM1_TIMD_IRQHandler,
[HRTIM1_TIME_IRQn + 16 ] = HRTIM1_TIME_IRQHandler,
[HRTIM1_FLT_IRQn + 16 ] = HRTIM1_FLT_IRQHandler,
[DFSDM1_FLT0_IRQn + 16 ] = DFSDM1_FLT0_IRQHandler,
[DFSDM1_FLT1_IRQn + 16 ] = DFSDM1_FLT1_IRQHandler,
[DFSDM1_FLT2_IRQn + 16 ] = DFSDM1_FLT2_IRQHandler,
[DFSDM1_FLT3_IRQn + 16 ] = DFSDM1_FLT3_IRQHandler,
[SAI3_IRQn + 16 ] = SAI3_IRQHandler,
[SWPMI1_IRQn + 16 ] = SWPMI1_IRQHandler,
[TIM15_IRQn + 16 ] = TIM15_IRQHandler,
[TIM16_IRQn + 16 ] = TIM16_IRQHandler,
[TIM17_IRQn + 16 ] = TIM17_IRQHandler,
[MDIOS_WKUP_IRQn + 16 ] = MDIOS_WKUP_IRQHandler,
[MDIOS_IRQn + 16 ] = MDIOS_IRQHandler,
[JPEG_IRQn + 16 ] = JPEG_IRQHandler,
[MDMA_IRQn + 16 ] = MDMA_IRQHandler,
[SDMMC2_IRQn + 16 ] = SDMMC2_IRQHandler,
[HSEM1_IRQn + 16 ] = HSEM1_IRQHandler,
[ADC3_IRQn + 16 ] = ADC3_IRQHandler,
[DMAMUX2_OVR_IRQn + 16 ] = DMAMUX2_OVR_IRQHandler,
[BDMA_Channel0_IRQn + 16 ] = BDMA_Channel0_IRQHandler,
[BDMA_Channel1_IRQn + 16 ] = BDMA_Channel1_IRQHandler,
[BDMA_Channel2_IRQn + 16 ] = BDMA_Channel2_IRQHandler,
[BDMA_Channel3_IRQn + 16 ] = BDMA_Channel3_IRQHandler,
[BDMA_Channel4_IRQn + 16 ] = BDMA_Channel4_IRQHandler,
[BDMA_Channel5_IRQn + 16 ] = BDMA_Channel5_IRQHandler,
[BDMA_Channel6_IRQn + 16 ] = BDMA_Channel6_IRQHandler,
[BDMA_Channel7_IRQn + 16 ] = BDMA_Channel7_IRQHandler,
[COMP_IRQn + 16 ] = COMP_IRQHandler,
[LPTIM2_IRQn + 16 ] = LPTIM2_IRQHandler,
[LPTIM3_IRQn + 16 ] = LPTIM3_IRQHandler,
[LPTIM4_IRQn + 16 ] = LPTIM4_IRQHandler,
[LPTIM5_IRQn + 16 ] = LPTIM5_IRQHandler,
[LPUART1_IRQn + 16 ] = LPUART1_IRQHandler,
[CRS_IRQn + 16 ] = CRS_IRQHandler,
[ECC_IRQn + 16 ] = ECC_IRQHandler,
[SAI4_IRQn + 16 ] = SAI4_IRQHandler,
[WAKEUP_PIN_IRQn + 16 ] = WAKEUP_PIN_IRQHandler,
};
radio/src/targets/common/arm/stm32/h7/vectors_stm32h7s7xx.c
+332
View File
@@ -0,0 +1,332 @@
#include "stm32h7s7xx.h"
#include "cortex_m_isr.h"
void Default_Handler() { default_isr_handler(); }
/* stm32h7s7xx specific interrupt vectors */
WEAK_DEFAULT void Reset_Handler();
WEAK_DEFAULT void NMI_Handler();
WEAK_DEFAULT void HardFault_Handler();
WEAK_DEFAULT void MemManage_Handler();
WEAK_DEFAULT void BusFault_Handler();
WEAK_DEFAULT void UsageFault_Handler();
WEAK_DEFAULT void SVC_Handler();
WEAK_DEFAULT void DebugMon_Handler();
WEAK_DEFAULT void PendSV_Handler();
WEAK_DEFAULT void SysTick_Handler();
WEAK_DEFAULT void PVD_PVM_IRQHandler();
WEAK_DEFAULT void DTS_IRQHandler();
WEAK_DEFAULT void IWDG_IRQHandler();
WEAK_DEFAULT void WWDG_IRQHandler();
WEAK_DEFAULT void RCC_IRQHandler();
WEAK_DEFAULT void FLASH_IRQHandler();
WEAK_DEFAULT void RAMECC_IRQHandler();
WEAK_DEFAULT void FPU_IRQHandler();
WEAK_DEFAULT void TAMP_IRQHandler();
WEAK_DEFAULT void EXTI0_IRQHandler();
WEAK_DEFAULT void EXTI1_IRQHandler();
WEAK_DEFAULT void EXTI2_IRQHandler();
WEAK_DEFAULT void EXTI3_IRQHandler();
WEAK_DEFAULT void EXTI4_IRQHandler();
WEAK_DEFAULT void EXTI5_IRQHandler();
WEAK_DEFAULT void EXTI6_IRQHandler();
WEAK_DEFAULT void EXTI7_IRQHandler();
WEAK_DEFAULT void EXTI8_IRQHandler();
WEAK_DEFAULT void EXTI9_IRQHandler();
WEAK_DEFAULT void EXTI10_IRQHandler();
WEAK_DEFAULT void EXTI11_IRQHandler();
WEAK_DEFAULT void EXTI12_IRQHandler();
WEAK_DEFAULT void EXTI13_IRQHandler();
WEAK_DEFAULT void EXTI14_IRQHandler();
WEAK_DEFAULT void EXTI15_IRQHandler();
WEAK_DEFAULT void RTC_IRQHandler();
WEAK_DEFAULT void SAES_IRQHandler();
WEAK_DEFAULT void CRYP_IRQHandler();
WEAK_DEFAULT void PKA_IRQHandler();
WEAK_DEFAULT void HASH_IRQHandler();
WEAK_DEFAULT void RNG_IRQHandler();
WEAK_DEFAULT void ADC1_2_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel0_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel1_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel2_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel3_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel4_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel5_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel6_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel7_IRQHandler();
WEAK_DEFAULT void TIM1_BRK_IRQHandler();
WEAK_DEFAULT void TIM1_UP_IRQHandler();
WEAK_DEFAULT void TIM1_TRG_COM_IRQHandler();
WEAK_DEFAULT void TIM1_CC_IRQHandler();
WEAK_DEFAULT void TIM2_IRQHandler();
WEAK_DEFAULT void TIM3_IRQHandler();
WEAK_DEFAULT void TIM4_IRQHandler();
WEAK_DEFAULT void TIM5_IRQHandler();
WEAK_DEFAULT void TIM6_IRQHandler();
WEAK_DEFAULT void TIM7_IRQHandler();
WEAK_DEFAULT void TIM9_IRQHandler();
WEAK_DEFAULT void SPI1_IRQHandler();
WEAK_DEFAULT void SPI2_IRQHandler();
WEAK_DEFAULT void SPI3_IRQHandler();
WEAK_DEFAULT void SPI4_IRQHandler();
WEAK_DEFAULT void SPI5_IRQHandler();
WEAK_DEFAULT void SPI6_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel0_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel1_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel2_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel3_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel4_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel5_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel6_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel7_IRQHandler();
WEAK_DEFAULT void SAI1_A_IRQHandler();
WEAK_DEFAULT void SAI1_B_IRQHandler();
WEAK_DEFAULT void SAI2_A_IRQHandler();
WEAK_DEFAULT void SAI2_B_IRQHandler();
WEAK_DEFAULT void I2C1_EV_IRQHandler();
WEAK_DEFAULT void I2C1_ER_IRQHandler();
WEAK_DEFAULT void I2C2_EV_IRQHandler();
WEAK_DEFAULT void I2C2_ER_IRQHandler();
WEAK_DEFAULT void I2C3_EV_IRQHandler();
WEAK_DEFAULT void I2C3_ER_IRQHandler();
WEAK_DEFAULT void USART1_IRQHandler();
WEAK_DEFAULT void USART2_IRQHandler();
WEAK_DEFAULT void USART3_IRQHandler();
WEAK_DEFAULT void UART4_IRQHandler();
WEAK_DEFAULT void UART5_IRQHandler();
WEAK_DEFAULT void UART7_IRQHandler();
WEAK_DEFAULT void UART8_IRQHandler();
WEAK_DEFAULT void I3C1_EV_IRQHandler();
WEAK_DEFAULT void I3C1_ER_IRQHandler();
WEAK_DEFAULT void OTG_HS_IRQHandler();
WEAK_DEFAULT void ETH_IRQHandler();
WEAK_DEFAULT void CORDIC_IRQHandler();
WEAK_DEFAULT void GFXTIM_IRQHandler();
WEAK_DEFAULT void DCMIPP_IRQHandler();
WEAK_DEFAULT void LTDC_IRQHandler();
WEAK_DEFAULT void LTDC_ER_IRQHandler();
WEAK_DEFAULT void DMA2D_IRQHandler();
WEAK_DEFAULT void JPEG_IRQHandler();
WEAK_DEFAULT void GFXMMU_IRQHandler();
WEAK_DEFAULT void I3C1_WKUP_IRQHandler();
WEAK_DEFAULT void MCE1_IRQHandler();
WEAK_DEFAULT void MCE2_IRQHandler();
WEAK_DEFAULT void MCE3_IRQHandler();
WEAK_DEFAULT void XSPI1_IRQHandler();
WEAK_DEFAULT void XSPI2_IRQHandler();
WEAK_DEFAULT void FMC_IRQHandler();
WEAK_DEFAULT void SDMMC1_IRQHandler();
WEAK_DEFAULT void SDMMC2_IRQHandler();
WEAK_DEFAULT void OTG_FS_IRQHandler();
WEAK_DEFAULT void TIM12_IRQHandler();
WEAK_DEFAULT void TIM13_IRQHandler();
WEAK_DEFAULT void TIM14_IRQHandler();
WEAK_DEFAULT void TIM15_IRQHandler();
WEAK_DEFAULT void TIM16_IRQHandler();
WEAK_DEFAULT void TIM17_IRQHandler();
WEAK_DEFAULT void LPTIM1_IRQHandler();
WEAK_DEFAULT void LPTIM2_IRQHandler();
WEAK_DEFAULT void LPTIM3_IRQHandler();
WEAK_DEFAULT void LPTIM4_IRQHandler();
WEAK_DEFAULT void LPTIM5_IRQHandler();
WEAK_DEFAULT void SPDIF_RX_IRQHandler();
WEAK_DEFAULT void MDIOS_IRQHandler();
WEAK_DEFAULT void ADF1_FLT0_IRQHandler();
WEAK_DEFAULT void CRS_IRQHandler();
WEAK_DEFAULT void UCPD1_IRQHandler();
WEAK_DEFAULT void CEC_IRQHandler();
WEAK_DEFAULT void PSSI_IRQHandler();
WEAK_DEFAULT void LPUART1_IRQHandler();
WEAK_DEFAULT void WAKEUP_PIN_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel8_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel9_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel10_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel11_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel12_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel13_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel14_IRQHandler();
WEAK_DEFAULT void GPDMA1_Channel15_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel8_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel9_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel10_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel11_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel12_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel13_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel14_IRQHandler();
WEAK_DEFAULT void HPDMA1_Channel15_IRQHandler();
WEAK_DEFAULT void GPU2D_IRQHandler();
WEAK_DEFAULT void GPU2D_ER_IRQHandler();
WEAK_DEFAULT void ICACHE_IRQHandler();
WEAK_DEFAULT void FDCAN1_IT0_IRQHandler();
WEAK_DEFAULT void FDCAN1_IT1_IRQHandler();
WEAK_DEFAULT void FDCAN2_IT0_IRQHandler();
WEAK_DEFAULT void FDCAN2_IT1_IRQHandler();
/* CPU specific interrupt vector table */
const isr_t _isr_vector[] ISR_VECTOR = {
[0] = (isr_t)&_estack,
[1 ] = Reset_Handler,
[2 ] = NMI_Handler,
[3 ] = HardFault_Handler,
[4 ] = MemManage_Handler,
[5 ] = BusFault_Handler,
[6 ] = UsageFault_Handler,
[7 ] = 0,
[8 ] = 0,
[9 ] = 0,
[10 ] = 0,
[11 ] = SVC_Handler,
[12 ] = DebugMon_Handler,
[13 ] = 0,
[14 ] = PendSV_Handler,
[15 ] = SysTick_Handler,
[PVD_PVM_IRQn + 16 ] = PVD_PVM_IRQHandler,
[DTS_IRQn + 16 ] = DTS_IRQHandler,
[IWDG_IRQn + 16 ] = IWDG_IRQHandler,
[WWDG_IRQn + 16 ] = WWDG_IRQHandler,
[RCC_IRQn + 16 ] = RCC_IRQHandler,
[FLASH_IRQn + 16 ] = FLASH_IRQHandler,
[RAMECC_IRQn + 16 ] = RAMECC_IRQHandler,
[FPU_IRQn + 16 ] = FPU_IRQHandler,
[TAMP_IRQn + 16 ] = TAMP_IRQHandler,
[EXTI0_IRQn + 16 ] = EXTI0_IRQHandler,
[EXTI1_IRQn + 16 ] = EXTI1_IRQHandler,
[EXTI2_IRQn + 16 ] = EXTI2_IRQHandler,
[EXTI3_IRQn + 16 ] = EXTI3_IRQHandler,
[EXTI4_IRQn + 16 ] = EXTI4_IRQHandler,
[EXTI5_IRQn + 16 ] = EXTI5_IRQHandler,
[EXTI6_IRQn + 16 ] = EXTI6_IRQHandler,
[EXTI7_IRQn + 16 ] = EXTI7_IRQHandler,
[EXTI8_IRQn + 16 ] = EXTI8_IRQHandler,
[EXTI9_IRQn + 16 ] = EXTI9_IRQHandler,
[EXTI10_IRQn + 16 ] = EXTI10_IRQHandler,
[EXTI11_IRQn + 16 ] = EXTI11_IRQHandler,
[EXTI12_IRQn + 16 ] = EXTI12_IRQHandler,
[EXTI13_IRQn + 16 ] = EXTI13_IRQHandler,
[EXTI14_IRQn + 16 ] = EXTI14_IRQHandler,
[EXTI15_IRQn + 16 ] = EXTI15_IRQHandler,
[RTC_IRQn + 16 ] = RTC_IRQHandler,
[SAES_IRQn + 16 ] = SAES_IRQHandler,
[CRYP_IRQn + 16 ] = CRYP_IRQHandler,
[PKA_IRQn + 16 ] = PKA_IRQHandler,
[HASH_IRQn + 16 ] = HASH_IRQHandler,
[RNG_IRQn + 16 ] = RNG_IRQHandler,
[ADC1_2_IRQn + 16 ] = ADC1_2_IRQHandler,
[GPDMA1_Channel0_IRQn + 16 ] = GPDMA1_Channel0_IRQHandler,
[GPDMA1_Channel1_IRQn + 16 ] = GPDMA1_Channel1_IRQHandler,
[GPDMA1_Channel2_IRQn + 16 ] = GPDMA1_Channel2_IRQHandler,
[GPDMA1_Channel3_IRQn + 16 ] = GPDMA1_Channel3_IRQHandler,
[GPDMA1_Channel4_IRQn + 16 ] = GPDMA1_Channel4_IRQHandler,
[GPDMA1_Channel5_IRQn + 16 ] = GPDMA1_Channel5_IRQHandler,
[GPDMA1_Channel6_IRQn + 16 ] = GPDMA1_Channel6_IRQHandler,
[GPDMA1_Channel7_IRQn + 16 ] = GPDMA1_Channel7_IRQHandler,
[TIM1_BRK_IRQn + 16 ] = TIM1_BRK_IRQHandler,
[TIM1_UP_IRQn + 16 ] = TIM1_UP_IRQHandler,
[TIM1_TRG_COM_IRQn + 16 ] = TIM1_TRG_COM_IRQHandler,
[TIM1_CC_IRQn + 16 ] = TIM1_CC_IRQHandler,
[TIM2_IRQn + 16 ] = TIM2_IRQHandler,
[TIM3_IRQn + 16 ] = TIM3_IRQHandler,
[TIM4_IRQn + 16 ] = TIM4_IRQHandler,
[TIM5_IRQn + 16 ] = TIM5_IRQHandler,
[TIM6_IRQn + 16 ] = TIM6_IRQHandler,
[TIM7_IRQn + 16 ] = TIM7_IRQHandler,
[TIM9_IRQn + 16 ] = TIM9_IRQHandler,
[SPI1_IRQn + 16 ] = SPI1_IRQHandler,
[SPI2_IRQn + 16 ] = SPI2_IRQHandler,
[SPI3_IRQn + 16 ] = SPI3_IRQHandler,
[SPI4_IRQn + 16 ] = SPI4_IRQHandler,
[SPI5_IRQn + 16 ] = SPI5_IRQHandler,
[SPI6_IRQn + 16 ] = SPI6_IRQHandler,
[HPDMA1_Channel0_IRQn + 16 ] = HPDMA1_Channel0_IRQHandler,
[HPDMA1_Channel1_IRQn + 16 ] = HPDMA1_Channel1_IRQHandler,
[HPDMA1_Channel2_IRQn + 16 ] = HPDMA1_Channel2_IRQHandler,
[HPDMA1_Channel3_IRQn + 16 ] = HPDMA1_Channel3_IRQHandler,
[HPDMA1_Channel4_IRQn + 16 ] = HPDMA1_Channel4_IRQHandler,
[HPDMA1_Channel5_IRQn + 16 ] = HPDMA1_Channel5_IRQHandler,
[HPDMA1_Channel6_IRQn + 16 ] = HPDMA1_Channel6_IRQHandler,
[HPDMA1_Channel7_IRQn + 16 ] = HPDMA1_Channel7_IRQHandler,
[SAI1_A_IRQn + 16 ] = SAI1_A_IRQHandler,
[SAI1_B_IRQn + 16 ] = SAI1_B_IRQHandler,
[SAI2_A_IRQn + 16 ] = SAI2_A_IRQHandler,
[SAI2_B_IRQn + 16 ] = SAI2_B_IRQHandler,
[I2C1_EV_IRQn + 16 ] = I2C1_EV_IRQHandler,
[I2C1_ER_IRQn + 16 ] = I2C1_ER_IRQHandler,
[I2C2_EV_IRQn + 16 ] = I2C2_EV_IRQHandler,
[I2C2_ER_IRQn + 16 ] = I2C2_ER_IRQHandler,
[I2C3_EV_IRQn + 16 ] = I2C3_EV_IRQHandler,
[I2C3_ER_IRQn + 16 ] = I2C3_ER_IRQHandler,
[USART1_IRQn + 16 ] = USART1_IRQHandler,
[USART2_IRQn + 16 ] = USART2_IRQHandler,
[USART3_IRQn + 16 ] = USART3_IRQHandler,
[UART4_IRQn + 16 ] = UART4_IRQHandler,
[UART5_IRQn + 16 ] = UART5_IRQHandler,
[UART7_IRQn + 16 ] = UART7_IRQHandler,
[UART8_IRQn + 16 ] = UART8_IRQHandler,
[I3C1_EV_IRQn + 16 ] = I3C1_EV_IRQHandler,
[I3C1_ER_IRQn + 16 ] = I3C1_ER_IRQHandler,
[OTG_HS_IRQn + 16 ] = OTG_HS_IRQHandler,
[ETH_IRQn + 16 ] = ETH_IRQHandler,
[CORDIC_IRQn + 16 ] = CORDIC_IRQHandler,
[GFXTIM_IRQn + 16 ] = GFXTIM_IRQHandler,
[DCMIPP_IRQn + 16 ] = DCMIPP_IRQHandler,
[LTDC_IRQn + 16 ] = LTDC_IRQHandler,
[LTDC_ER_IRQn + 16 ] = LTDC_ER_IRQHandler,
[DMA2D_IRQn + 16 ] = DMA2D_IRQHandler,
[JPEG_IRQn + 16 ] = JPEG_IRQHandler,
[GFXMMU_IRQn + 16 ] = GFXMMU_IRQHandler,
[I3C1_WKUP_IRQn + 16 ] = I3C1_WKUP_IRQHandler,
[MCE1_IRQn + 16 ] = MCE1_IRQHandler,
[MCE2_IRQn + 16 ] = MCE2_IRQHandler,
[MCE3_IRQn + 16 ] = MCE3_IRQHandler,
[XSPI1_IRQn + 16 ] = XSPI1_IRQHandler,
[XSPI2_IRQn + 16 ] = XSPI2_IRQHandler,
[FMC_IRQn + 16 ] = FMC_IRQHandler,
[SDMMC1_IRQn + 16 ] = SDMMC1_IRQHandler,
[SDMMC2_IRQn + 16 ] = SDMMC2_IRQHandler,
[OTG_FS_IRQn + 16 ] = OTG_FS_IRQHandler,
[TIM12_IRQn + 16 ] = TIM12_IRQHandler,
[TIM13_IRQn + 16 ] = TIM13_IRQHandler,
[TIM14_IRQn + 16 ] = TIM14_IRQHandler,
[TIM15_IRQn + 16 ] = TIM15_IRQHandler,
[TIM16_IRQn + 16 ] = TIM16_IRQHandler,
[TIM17_IRQn + 16 ] = TIM17_IRQHandler,
[LPTIM1_IRQn + 16 ] = LPTIM1_IRQHandler,
[LPTIM2_IRQn + 16 ] = LPTIM2_IRQHandler,
[LPTIM3_IRQn + 16 ] = LPTIM3_IRQHandler,
[LPTIM4_IRQn + 16 ] = LPTIM4_IRQHandler,
[LPTIM5_IRQn + 16 ] = LPTIM5_IRQHandler,
[SPDIF_RX_IRQn + 16 ] = SPDIF_RX_IRQHandler,
[MDIOS_IRQn + 16 ] = MDIOS_IRQHandler,
[ADF1_FLT0_IRQn + 16 ] = ADF1_FLT0_IRQHandler,
[CRS_IRQn + 16 ] = CRS_IRQHandler,
[UCPD1_IRQn + 16 ] = UCPD1_IRQHandler,
[CEC_IRQn + 16 ] = CEC_IRQHandler,
[PSSI_IRQn + 16 ] = PSSI_IRQHandler,
[LPUART1_IRQn + 16 ] = LPUART1_IRQHandler,
[WAKEUP_PIN_IRQn + 16 ] = WAKEUP_PIN_IRQHandler,
[GPDMA1_Channel8_IRQn + 16 ] = GPDMA1_Channel8_IRQHandler,
[GPDMA1_Channel9_IRQn + 16 ] = GPDMA1_Channel9_IRQHandler,
[GPDMA1_Channel10_IRQn + 16 ] = GPDMA1_Channel10_IRQHandler,
[GPDMA1_Channel11_IRQn + 16 ] = GPDMA1_Channel11_IRQHandler,
[GPDMA1_Channel12_IRQn + 16 ] = GPDMA1_Channel12_IRQHandler,
[GPDMA1_Channel13_IRQn + 16 ] = GPDMA1_Channel13_IRQHandler,
[GPDMA1_Channel14_IRQn + 16 ] = GPDMA1_Channel14_IRQHandler,
[GPDMA1_Channel15_IRQn + 16 ] = GPDMA1_Channel15_IRQHandler,
[HPDMA1_Channel8_IRQn + 16 ] = HPDMA1_Channel8_IRQHandler,
[HPDMA1_Channel9_IRQn + 16 ] = HPDMA1_Channel9_IRQHandler,
[HPDMA1_Channel10_IRQn + 16 ] = HPDMA1_Channel10_IRQHandler,
[HPDMA1_Channel11_IRQn + 16 ] = HPDMA1_Channel11_IRQHandler,
[HPDMA1_Channel12_IRQn + 16 ] = HPDMA1_Channel12_IRQHandler,
[HPDMA1_Channel13_IRQn + 16 ] = HPDMA1_Channel13_IRQHandler,
[HPDMA1_Channel14_IRQn + 16 ] = HPDMA1_Channel14_IRQHandler,
[HPDMA1_Channel15_IRQn + 16 ] = HPDMA1_Channel15_IRQHandler,
[GPU2D_IRQn + 16 ] = GPU2D_IRQHandler,
[GPU2D_ER_IRQn + 16 ] = GPU2D_ER_IRQHandler,
[ICACHE_IRQn + 16 ] = ICACHE_IRQHandler,
[FDCAN1_IT0_IRQn + 16 ] = FDCAN1_IT0_IRQHandler,
[FDCAN1_IT1_IRQn + 16 ] = FDCAN1_IT1_IRQHandler,
[FDCAN2_IT0_IRQn + 16 ] = FDCAN2_IT0_IRQHandler,
[FDCAN2_IT1_IRQn + 16 ] = FDCAN2_IT1_IRQHandler,
};
radio/src/targets/common/arm/stm32/pwr_driver.cpp
+6
View File
@@ -136,3 +136,9 @@ void pwrResetHandler()
pwrOn();
}
}
#if defined(BOOT)
void* _pwr_init_hook[] __INIT_HOOK = {
(void*)pwrResetHandler,
};
#endif
radio/src/targets/common/arm/stm32/system_init.c
+290
View File
@@ -0,0 +1,290 @@
/*
* Copyright (C) EdgeTX
*
* Based on code named
* opentx - https://github.com/opentx/opentx
* th9x - http://code.google.com/p/th9x
* er9x - http://code.google.com/p/er9x
* gruvin9x - http://code.google.com/p/gruvin9x
*
* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include "stm32_cmsis.h"
#include "stm32_hal.h"
#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
(defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
#define USE_CACHE
#endif
#if (defined (USE_CACHE) && defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U))
#define REQUIRE_MPU_CONFIG
#endif
#if defined(ITCM_BASE) /* H7RS */ || defined(D1_ITCMRAM_BASE) /* H7 */
#define LOAD_FAST_CODE_RAM
#endif
#define NAKED __attribute__((naked))
#define BOOTSTRAP __attribute__((section(".bootstrap")))
// Linker script symbols
extern uint32_t _sisr_vector;
NAKED BOOTSTRAP void Reset_Handler()
{
asm inline (
"ldr sp, =_estack \n"
);
#if defined(BOOT)
asm inline (
"bl SystemInit \n"
"bl SystemClock_Config \n"
);
#if defined(USE_CACHE)
asm inline (
"bl CPU_CACHE_Enable \n"
);
#endif // USE_CACHE
#endif // BOOT
// Copy code into RAM
asm inline (
"ldr r0, =_stext \n"
"ldr r1, =_etext \n"
"ldr r2, =_text_load \n"
"bl naked_copy \n"
);
#if defined(BOOT) && defined(REQUIRE_MPU_CONFIG)
asm inline (
"bl MPU_Config \n"
);
#endif
// Copy / setup ISR vector
asm inline (
"ldr r0, =_sisr_vector \n"
"ldr r1, =_eisr_vector \n"
"ldr r2, =_isr_load \n"
"bl naked_copy \n"
"bl set_vtor \n"
);
#if defined(LOAD_FAST_CODE_RAM)
// Copy code into fast RAM
asm inline (
"ldr r0, =_siram \n"
"ldr r1, =_eiram \n"
"ldr r2, =_stext_iram \n"
"bl naked_copy \n"
);
#endif
// Copy initialized data segment
asm inline (
"ldr r0, =_sdata \n"
"ldr r1, =_edata \n"
"ldr r2, =_sidata \n"
"bl naked_copy \n"
);
// Execute early hooks
asm inline (
"bl init_hooks \n"
);
// Zero fill bss segment
asm inline (
"ldr r2, =_sbss \n"
"ldr r4, =_ebss \n"
"movs r3, 0 \n"
"b LoopFillZerobss \n"
"FillZerobss: \n"
"str r3, [r2] \n"
"adds r2, r2, 4 \n"
"LoopFillZerobss: \n"
"cmp r2, r4 \n"
"bcc FillZerobss \n"
);
#if defined(USE_CACHE)
asm inline (
"bl clean_dcache \n"
);
#endif
asm inline (
// Call static constructors
"bl __libc_init_array \n"
// Update global clock speed variable
"bl SystemCoreClockUpdate \n"
// Call the application's entry point
"bl main \n"
"bx lr \n"
);
}
BOOTSTRAP void set_vtor() { SCB->VTOR = (intptr_t)&_sisr_vector; }
NAKED BOOTSTRAP void naked_copy()
{
// r0: destination start
// r1: destination end
// r2: source start
asm inline (
"cmp r0, r2 \n"
"beq SkipCopy \n"
"movs r3, 0 \n"
"b LoopCopyInit \n"
"CopyInit: \n"
"ldr r4, [r2, r3] \n"
"str r4, [r0, r3] \n"
"adds r3, r3, #4 \n"
"LoopCopyInit: \n"
"adds r4, r0, r3 \n"
"cmp r4, r1 \n"
"bcc CopyInit \n"
"SkipCopy: \n"
"bx lr \n"
);
}
void init_hooks()
{
extern uint32_t __init_hook_array_start;
extern uint32_t __init_hook_array_end;
typedef void (*hook_fct_t)();
for (uint32_t hook = (uint32_t)&__init_hook_array_start;
hook != (uint32_t)&__init_hook_array_end; hook += sizeof(void*)) {
(*(hook_fct_t*)hook)();
}
}
#if defined(USE_CACHE)
// SCB_CleanDCache() is "forced inline"
void clean_dcache() { SCB_CleanDCache(); }
#if defined(BOOT)
BOOTSTRAP void CPU_CACHE_Enable()
{
/* Enable I-Cache */
SCB_EnableICache();
/* Enable D-Cache */
SCB_EnableDCache();
}
#endif // BOOT
#endif // USE_CACHE
#if defined(BOOT) && defined(REQUIRE_MPU_CONFIG)
// Linker script symbols
extern uint32_t _dram_addr;
extern uint32_t EXTRAM_START;
extern uint32_t EXTRAM_SIZE;
extern uint32_t NORFLASH_START;
extern uint32_t NORFLASH_SIZE;
__STATIC_FORCEINLINE uint32_t mpu_region_size(uint32_t size)
{
return 32 - __CLZ(size) - 1;
}
void MPU_Config()
{
MPU_Region_InitTypeDef MPU_InitStruct = {0};
/* Disables the MPU */
HAL_MPU_Disable();
/*
* Region 0: overwrite default setting to prevent speculative
* read to unavailable memories.
* Range: 0x60000000 to 0xE0000000
*
* Set as strongly ordered, code execution disabled
*/
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.BaseAddress = 0;
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
MPU_InitStruct.SubRegionDisable = 0x87;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* Region 2: QSPI memory range, bank1 */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER2;
MPU_InitStruct.BaseAddress = (uint32_t)&NORFLASH_START;
MPU_InitStruct.Size = mpu_region_size((uint32_t)&NORFLASH_SIZE);
MPU_InitStruct.SubRegionDisable = 0x0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* Region 3: external RAM memory range */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER3;
MPU_InitStruct.BaseAddress = (uint32_t)&EXTRAM_START;
MPU_InitStruct.Size = mpu_region_size((uint32_t)&EXTRAM_SIZE);
MPU_InitStruct.SubRegionDisable = 0x0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* Region 4: dedicated DMA buffers (cache disabled) */
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER4;
MPU_InitStruct.BaseAddress = (uint32_t)&_dram_addr;
MPU_InitStruct.Size = MPU_REGION_SIZE_64KB; // FIXME
MPU_InitStruct.SubRegionDisable = 0x0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
/* Enable bus fault exception */
SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
}
#endif // REQUIRE_MPU_CONFIG