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[Horus/Taranis] Pulses cosmetics

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This commit is contained in:
Bertrand Songis
2016-06-10 23:37:26 +02:00
parent 575eb3d0d1
commit 17ab2c83aa
9 changed files with 26 additions and 50 deletions
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radio/src/pulses/dsm2_arm.cpp
+7 -7
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@@ -48,23 +48,23 @@ void _send_1(uint8_t v)
modulePulsesData[EXTERNAL_MODULE].dsm2.rest -= v;
}
void sendByteDsm2(uint8_t b) //max 10 changes 0 10 10 10 10 1
void sendByteDsm2(uint8_t b) // max 10 changes 0 10 10 10 10 1
{
bool lev = 0;
uint8_t len = BITLEN_DSM2; //max val: 9*16 < 256
for (uint8_t i=0; i<=8; i++) { //8Bits + Stop=1
bool nlev = b & 1; //lsb first
uint8_t len = BITLEN_DSM2; // max val: 9*16 < 256
for (uint8_t i=0; i<=8; i++) { // 8Bits + Stop=1
bool nlev = b & 1; // lsb first
if (lev == nlev) {
len += BITLEN_DSM2;
}
else {
_send_1(len); // _send_1(nlev ? len-5 : len+3);
_send_1(len);
len = BITLEN_DSM2;
lev = nlev;
}
b = (b>>1) | 0x80; //shift in stop bit
b = (b>>1) | 0x80; // shift in stop bit
}
_send_1(len+BITLEN_DSM2); // _send_1(len+BITLEN_DSM2+3); // 2 stop bits
_send_1(len+BITLEN_DSM2); // stop bit
}
void putDsm2Flush()
radio/src/pulses/ppm_arm.cpp
+1 -2
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@@ -50,8 +50,7 @@ void setupPulsesPPM(uint8_t port, PpmPulsesData<T> * ppmPulsesData)
*ptr++ = v; /* as Pat MacKenzie suggests */
#endif
}
if (rest > 65535) rest = 65535; /* prevents overflows */
if (rest < 9000) rest = 9000; /* avoids that CCR2 is bigger than ARR which would cause reboot */
rest = limit<int32_t>(9000, rest, 65535); /* avoids that CCR2 is bigger than ARR which would cause reboot */
#if defined(CPUSTM32)
*ppmPulsesData->ptr++ = rest;
#else
radio/src/pulses/pxx_arm.cpp
+1
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@@ -141,6 +141,7 @@ void pxxPutPcmPart(uint8_t port, uint8_t value)
void pxxPutPcmTail(uint8_t port)
{
// rest min value is 18000 - 200 * 48 = 8400 (4.2ms)
*(modulePulsesData[port].pxx.ptr-1) += modulePulsesData[port].pxx.rest;
}
#endif
radio/src/targets/horus/extmodule_driver.cpp
+1
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@@ -253,6 +253,7 @@ extern "C" void EXTMODULE_DMA_IRQHandler()
DMA_ClearITPendingBit(EXTMODULE_DMA_STREAM, EXTMODULE_DMA_FLAG_TC);
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
}
radio/src/targets/horus/pulses_driver.cpp
+1 -1
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@@ -224,7 +224,7 @@ extern "C" void INTMODULE_TIMER_CC_IRQHandler()
DEBUG_INTERRUPT(INT_TIM1CC);
DEBUG_TIMER_SAMPLE(debugTimerIntPulses);
DEBUG_TIMER_START(debugTimerIntPulsesDuration);
// INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // stop this interrupt
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag
setupPulses(INTERNAL_MODULE);
radio/src/targets/horus/trainer_driver.cpp
+3 -10
View File
@@ -102,6 +102,7 @@ void trainerSendNextFrame()
{
TRAINER_TIMER->CCR2 = GET_PPM_DELAY(TRAINER_MODULE)*2;
TRAINER_TIMER->CCER = TIM_CCER_CC2E | (g_model.moduleData[TRAINER_MODULE].ppm.pulsePol ? 0 : TIM_CCER_CC2P);
TRAINER_TIMER->CCR1 = *(trainerPulsesData.ppm.ptr - 1) - 4000; // 2mS in advance
TRAINER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA
TRAINER_DMA_STREAM->CR |= TRAINER_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1;
@@ -118,16 +119,8 @@ extern "C" void TRAINER_DMA_IRQHandler()
DMA_ClearITPendingBit(TRAINER_DMA_STREAM, TRAINER_DMA_FLAG_TC);
uint32_t arr = TRAINER_TIMER->ARR;
if (arr > 5000) {
TRAINER_TIMER->CCR1 = arr - 4000; // 2mS in advance
TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag
TRAINER_TIMER->DIER |= TIM_DIER_CC1IE; // Enable this interrupt
}
else {
setupPulsesPPMTrainer();
trainerSendNextFrame();
}
TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag
TRAINER_TIMER->DIER |= TIM_DIER_CC1IE; // Enable this interrupt
}
extern "C" void TRAINER_TIMER_IRQHandler()
radio/src/targets/taranis/extmodule_driver.cpp
+5 -10
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@@ -203,6 +203,7 @@ void extmoduleSendNextFrame()
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
EXTMODULE_TIMER->CCR1 = GET_PPM_DELAY(EXTERNAL_MODULE)*2;
EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | (GET_PPM_POLARITY(EXTERNAL_MODULE) ? TIM_CCER_CC1NP : 0); // // we are using complementary output so logic has to be reversed here
EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance
EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA
EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1;
EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR);
@@ -211,6 +212,7 @@ void extmoduleSendNextFrame()
EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA
}
else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) {
EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].pxx.ptr - 1) - 4000; // 2mS in advance
EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA
EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1;
EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR);
@@ -219,6 +221,7 @@ void extmoduleSendNextFrame()
EXTMODULE_DMA_STREAM->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE; // Enable DMA
}
else if (IS_DSM2_PROTOCOL(s_current_protocol[EXTERNAL_MODULE]) || IS_MULTIMODULE_PROTOCOL(s_current_protocol[EXTERNAL_MODULE])) {
EXTMODULE_TIMER->CCR2 = *(modulePulsesData[EXTERNAL_MODULE].dsm2.ptr - 1) - 4000; // 2mS in advance
EXTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA
EXTMODULE_DMA_STREAM->CR |= EXTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1;
EXTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->ARR);
@@ -238,16 +241,8 @@ extern "C" void EXTMODULE_DMA_IRQHandler()
DMA_ClearITPendingBit(EXTMODULE_DMA_STREAM, EXTMODULE_DMA_FLAG_TC);
uint32_t arr = EXTMODULE_TIMER->ARR;
if (arr > 5000) {
EXTMODULE_TIMER->CCR2 = arr - 4000; // 2mS in advance
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
}
else {
setupPulses(EXTERNAL_MODULE);
extmoduleSendNextFrame();
}
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
}
extern "C" void EXTMODULE_TIMER_CC_IRQHandler()
radio/src/targets/taranis/pulses_driver.cpp
+4 -10
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@@ -233,6 +233,7 @@ void intmodulePpmStart()
void intmoduleSendNextFrame()
{
if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
INTMODULE_TIMER->CCR2 = *(modulePulsesData[INTERNAL_MODULE].pxx.ptr - 1) - 4000; // 2mS in advance
INTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA
INTMODULE_DMA_STREAM->CR |= INTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1;
INTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&INTMODULE_TIMER->ARR);
@@ -244,6 +245,7 @@ void intmoduleSendNextFrame()
else if (s_current_protocol[INTERNAL_MODULE] == PROTO_PPM) {
INTMODULE_TIMER->CCR3 = GET_PPM_DEAY(INTERNAL_MODULE)*2;
INTMODULE_TIMER->CCER = TIM_CCER_CC3E | (GET_PPM_POLARITY(INTERNAL_MODULE) ? 0 : TIM_CCER_CC3P);
INTMODULE_TIMER->CCR2 = *(modulePulsesData[INTERNAL_MODULE].ppm.ptr - 1) - 4000; // 2mS in advance
INTMODULE_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA
INTMODULE_DMA_STREAM->CR |= INTMODULE_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1;
INTMODULE_DMA_STREAM->PAR = CONVERT_PTR_UINT(&INTMODULE_TIMER->ARR);
@@ -264,16 +266,8 @@ extern "C" void INTMODULE_DMA_IRQHandler()
DMA_ClearITPendingBit(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC);
uint32_t arr = INTMODULE_TIMER->ARR;
if (arr > 5000) {
INTMODULE_TIMER->CCR2 = arr - 4000; // 2mS in advance
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
}
else {
setupPulses(INTERNAL_MODULE);
intmoduleSendNextFrame();
}
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
}
extern "C" void INTMODULE_TIMER_CC_IRQHandler()
radio/src/targets/taranis/trainer_driver.cpp
+3 -10
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@@ -101,6 +101,7 @@ void trainerSendNextFrame()
{
TRAINER_TIMER->CCR4 = GET_PPM_DELAY(TRAINER_MODULE)*2;
TRAINER_TIMER->CCER = TIM_CCER_CC4E | (GET_PPM_POLARITY(TRAINER_MODULE) ? 0 : TIM_CCER_CC4P);
TRAINER_TIMER->CCR1 = *(trainerPulsesData.ppm.ptr - 1) - 4000; // 2mS in advance
TRAINER_DMA_STREAM->CR &= ~DMA_SxCR_EN; // Disable DMA
TRAINER_DMA_STREAM->CR |= TRAINER_DMA_CHANNEL | DMA_SxCR_DIR_0 | DMA_SxCR_MINC | DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PL_0 | DMA_SxCR_PL_1;
@@ -117,16 +118,8 @@ extern "C" void TRAINER_DMA_IRQHandler()
DMA_ClearITPendingBit(TRAINER_DMA_STREAM, TRAINER_DMA_FLAG_TC);
uint32_t arr = TRAINER_TIMER->ARR;
if (arr > 5000) {
TRAINER_TIMER->CCR1 = arr - 4000; // 2mS in advance
TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag
TRAINER_TIMER->DIER |= TIM_DIER_CC1IE; // Enable this interrupt
}
else {
setupPulsesPPMTrainer();
trainerSendNextFrame();
}
TRAINER_TIMER->SR &= ~TIM_SR_CC1IF; // Clear flag
TRAINER_TIMER->DIER |= TIM_DIER_CC1IE; // Enable this interrupt
}
extern "C" void TRAINER_TIMER_IRQHandler()