Companion9x 64bits compilation
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@@ -76,7 +76,7 @@ void init_pxx()
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DMA2_Stream1->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
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| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
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DMA2_Stream1->PAR = (uint32_t) &TIM1->DMAR ;
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DMA2_Stream1->M0AR = (uint32_t) &pxxStream[1] ;
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DMA2_Stream1->M0AR = CONVERT_PTR(&pxxStream[1]);
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// DMA2_Stream1->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
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// DMA2_Stream1->NDTR = 100 ;
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DMA2_Stream1->CR |= DMA_SxCR_EN ; // Enable DMA
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@@ -156,7 +156,7 @@ extern "C" void TIM1_CC_IRQHandler()
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{
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DMA2_Stream1->CR &= ~DMA_SxCR_EN ; // Disable DMA
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DMA2->LIFCR = DMA_LIFCR_CTCIF1 | DMA_LIFCR_CHTIF1 | DMA_LIFCR_CTEIF1 | DMA_LIFCR_CDMEIF1 | DMA_LIFCR_CFEIF1 ; // Write ones to clear bits
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DMA2_Stream1->M0AR = (uint32_t) &pxxStream[1] ;
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DMA2_Stream1->M0AR = CONVERT_PTR(&pxxStream[1]);
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DMA2_Stream1->CR |= DMA_SxCR_EN ; // Enable DMA
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TIM1->CCR1 = pxxStream[0] ;
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TIM1->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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