Configurable IRQ prio and read first in ISR

This commit is contained in:
Raphael Coeffic
2022-03-20 16:22:14 +01:00
parent fa3389447c
commit 5c21dee2fa
6 changed files with 23 additions and 13 deletions
@@ -67,6 +67,7 @@ static const stm32_usart_t extmoduleUSART = {
.GPIOx = EXTMODULE_TX_GPIO,
.pinInit = &extmoduleUSART_PinDef,
.IRQn = EXTMODULE_USART_IRQn,
.IRQ_Prio = EXTMODULE_USART_IRQ_PRIORITY,
.DMAx = EXTMODULE_USART_TX_DMA,
.DMA_Stream = EXTMODULE_USART_TX_DMA_STREAM_LL,
.DMA_Channel = EXTMODULE_USART_TX_DMA_CHANNEL,
@@ -24,6 +24,8 @@
#include <stdint.h>
#include "hal/serial_driver.h"
#define EXTMODULE_USART_IRQ_PRIORITY 6
// Callbacks using intmoduleFifo
void extmoduleFifoReceive(uint8_t data);
void extmoduleFifoError();
@@ -78,6 +78,7 @@ static const stm32_usart_t intmoduleUSART = {
.GPIOx = INTMODULE_GPIO,
.pinInit = &intmoduleUSART_PinDef,
.IRQn = INTMODULE_USART_IRQn,
.IRQ_Prio = INTMODULE_USART_IRQ_PRIORITY,
.DMAx = INTMODULE_DMA,
.DMA_Stream = INTMODULE_DMA_STREAM_LL,
.DMA_Channel = INTMODULE_DMA_CHANNEL,
@@ -24,6 +24,8 @@
#include <stdint.h>
#include "hal/serial_driver.h"
#define INTMODULE_USART_IRQ_PRIORITY 6
// Callbacks using intmoduleFifo
void intmoduleFifoReceive(uint8_t data);
void intmoduleFifoError();
@@ -82,7 +82,7 @@ void stm32_usart_init(const stm32_usart_t* usart, const etx_serial_init* params)
if (!usart->DMAx || params->rx_enable) {
// TODO: configurable priority ???
NVIC_SetPriority(usart->IRQn, 6);
NVIC_SetPriority(usart->IRQn, usart->IRQ_Prio);
NVIC_EnableIRQ(usart->IRQn);
}
}
@@ -107,6 +107,7 @@ void stm32_usart_deinit(const stm32_usart_t* usart)
void stm32_usart_send_byte(const stm32_usart_t* usart, uint8_t byte)
{
// TODO: split into 2 steps to avoid blocking on send
while (!LL_USART_IsActiveFlag_TXE(usart->USARTx));
LL_USART_TransmitData8(usart->USARTx, byte);
}
@@ -177,18 +178,7 @@ void stm32_usart_isr(const stm32_usart_t* usart, etx_serial_callbacks_t* cb)
{
uint32_t status = LL_USART_ReadReg(usart->USARTx, SR);
// IRQ based send: TXE IRQ is enabled only during transfer
if (LL_USART_IsEnabledIT_TXE(usart->USARTx) && (status & LL_USART_SR_TXE)) {
uint8_t data;
if (cb->on_send && cb->on_send(data)) {
LL_USART_TransmitData8(usart->USARTx, data);
} else {
LL_USART_DisableIT_TXE(usart->USARTx);
}
}
// Receive
// Receive: do it first as it is more time critical
if (LL_USART_IsEnabledIT_TXE(usart->USARTx)) {
// Drain RX
@@ -209,4 +199,15 @@ void stm32_usart_isr(const stm32_usart_t* usart, etx_serial_callbacks_t* cb)
status = LL_USART_ReadReg(usart->USARTx, SR);
}
}
// IRQ based send: TXE IRQ is enabled only during transfer
if (LL_USART_IsEnabledIT_TXE(usart->USARTx) && (status & LL_USART_SR_TXE)) {
uint8_t data;
if (cb->on_send && cb->on_send(data)) {
LL_USART_TransmitData8(usart->USARTx, data);
} else {
LL_USART_DisableIT_TXE(usart->USARTx);
}
}
}
@@ -31,7 +31,10 @@ struct stm32_usart_t {
USART_TypeDef* USARTx;
GPIO_TypeDef* GPIOx;
const LL_GPIO_InitTypeDef* pinInit;
// USART IRQ
IRQn_Type IRQn;
uint8_t IRQ_Prio;
// TX DMA defs
DMA_TypeDef* DMAx;