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[Taranis] Crossfire period now 4ms. S.PORT TX didn't wait end of serial transfer before going to RX mode

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This commit is contained in:
Bertrand Songis
2016-04-10 10:34:04 +02:00
parent 834092879c
commit 5d171b3761
5 changed files with 225 additions and 213 deletions
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radio/src/pulses/crossfire.cpp
+1 -1
View File
@@ -42,5 +42,5 @@ void createCrossfireFrame(uint8_t * frame, int16_t * pulses)
bitsavailable -= 8;
}
}
*buf = crc8(&frame[2], 24);
*buf = crc8(&frame[2], 23);
}
radio/src/pulses/pulses_arm.cpp
+1 -1
View File
@@ -196,7 +196,7 @@ void setupPulses(unsigned int port)
uint8_t * crossfire = modulePulsesData[port].crossfire.pulses;
createCrossfireFrame(crossfire, &channelOutputs[g_model.moduleData[port].channelsStart]);
sportSendBuffer(crossfire, CROSSFIRE_FRAME_LEN);
// TODO scheduleNextMixerCalculation()
scheduleNextMixerCalculation(port, CROSSFIRE_FRAME_PERIOD);
}
break;
}
radio/src/pulses/pulses_arm.h
+1
View File
@@ -69,6 +69,7 @@ PACK(struct Dsm2PulsesData {
#endif
#define CROSSFIRE_BAUDRATE 400000
#define CROSSFIRE_FRAME_PERIOD 4 // 4ms
#define CROSSFIRE_FRAME_LEN (3+22+1)
#define CROSSFIRE_CHANNELS_COUNT 16
PACK(struct CrossfirePulsesData {
radio/src/targets/taranis/pulses_driver.cpp
+210 -210
View File
@@ -24,44 +24,44 @@ void setupPulses(unsigned int port);
void setupPulsesPPM(unsigned int port);
void setupPulsesPXX(unsigned int port);
static void intmodulePxxStart( void ) ;
static void intmodulePxxStop( void ) ;
static void intmodulePxxStart(void);
static void intmodulePxxStop(void);
#if defined(TARANIS_INTERNAL_PPM)
static void intmodulePpmStart( void ) ;
static void intmodulePpmStop( void ) ;
static void intmodulePpmStart(void);
static void intmodulePpmStop(void);
#endif
static void extmodulePxxStart( void ) ;
static void extmodulePxxStop( void ) ;
#if defined(DSM2) || defined(MULTIMODULE)
static void extmoduleDsm2Start( void ) ;
static void extmoduleDsm2Stop( void ) ;
static void extmodulePxxStart(void);
static void extmodulePxxStop(void);
#if defined(DSM2) || defined(MULTIMODULE)
static void extmoduleDsm2Start(void);
static void extmoduleDsm2Stop(void);
#endif
static void extmodulePpmStart( void ) ;
static void extmodulePpmStop( void ) ;
static void intmoduleNoneStart( void ) ;
static void intmoduleNoneStop( void ) ;
static void extmoduleNoneStart( void ) ;
static void extmoduleNoneStop( void ) ;
static void extmoduleCrossfireStart( void ) ;
static void extmoduleCrossfireStop( void ) ;
static void extmodulePpmStart(void);
static void extmodulePpmStop(void);
static void intmoduleNoneStart(void);
static void intmoduleNoneStop(void);
static void extmoduleNoneStart(void);
static void extmoduleNoneStop(void);
static void extmoduleCrossfireStart(void);
static void extmoduleCrossfireStop(void);
void init_pxx(uint32_t port)
{
if (port == INTERNAL_MODULE)
intmodulePxxStart() ;
intmodulePxxStart();
else
extmodulePxxStart() ;
extmodulePxxStart();
}
void disable_pxx(uint32_t port)
{
if (port == INTERNAL_MODULE)
intmodulePxxStop() ;
intmodulePxxStop();
else
extmodulePxxStop() ;
extmodulePxxStop();
}
#if defined(DSM2) || defined(MULTIMODULE)
#if defined(DSM2) || defined(MULTIMODULE)
void init_dsm2(uint32_t port)
{
if (port == EXTERNAL_MODULE) {
@@ -154,37 +154,37 @@ static void intmoduleNoneStart()
// Timer1, channel 3
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Pin = INTMODULE_PPM_GPIO_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT ;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(INTMODULE_PPM_GPIO, &GPIO_InitStructure);
GPIO_SetBits(INTMODULE_PPM_GPIO, INTMODULE_PPM_GPIO_PIN) ; // Set high
GPIO_SetBits(INTMODULE_PPM_GPIO, INTMODULE_PPM_GPIO_PIN); // Set high
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
INTMODULE_TIMER->ARR = 36000 ; // 18mS
INTMODULE_TIMER->CCR2 = 32000 ; // Update time
INTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
INTMODULE_TIMER->ARR = 36000; // 18mS
INTMODULE_TIMER->CCR2 = 32000; // Update time
INTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1; // 0.5uS from 30MHz
INTMODULE_TIMER->CCER = TIM_CCER_CC3E ;
INTMODULE_TIMER->CCER = TIM_CCER_CC3E;
INTMODULE_TIMER->CCMR2 = 0 ;
INTMODULE_TIMER->EGR = 1 ; // Restart
INTMODULE_TIMER->CCMR2 = 0;
INTMODULE_TIMER->EGR = 1; // Restart
INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
INTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
NVIC_EnableIRQ(INTMODULE_TIMER_IRQn) ;
INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
INTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
NVIC_EnableIRQ(INTMODULE_TIMER_IRQn);
NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
}
static void intmoduleNoneStop()
{
NVIC_DisableIRQ(INTMODULE_TIMER_IRQn) ;
INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
NVIC_DisableIRQ(INTMODULE_TIMER_IRQn);
INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE;
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
}
static void extmoduleNoneStart()
@@ -195,34 +195,34 @@ static void extmoduleNoneStart()
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT ;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
EXTMODULE_TIMER->ARR = 36000 ; // 18mS
EXTMODULE_TIMER->CCR2 = 32000 ; // Update time
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
EXTMODULE_TIMER->ARR = 36000; // 18mS
EXTMODULE_TIMER->CCR2 = 32000; // Update time
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1; // 0.5uS from 30MHz
EXTMODULE_TIMER->CCMR2 = 0 ;
EXTMODULE_TIMER->EGR = 1 ; // Restart
EXTMODULE_TIMER->CCMR2 = 0;
EXTMODULE_TIMER->EGR = 1; // Restart
EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn);
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
}
static void extmoduleNoneStop()
{
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn);
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE;
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
}
static void extmoduleCrossfireStart()
@@ -231,34 +231,34 @@ static void extmoduleCrossfireStart()
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT ;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
EXTMODULE_TIMER->ARR = 5000 ; // 2.5mS
EXTMODULE_TIMER->CCR2 = 32000 ; // Update time
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
EXTMODULE_TIMER->ARR = (2000 * CROSSFIRE_FRAME_PERIOD);
EXTMODULE_TIMER->CCR2 = 32000; // Update time
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1; // 0.5uS from 30MHz
EXTMODULE_TIMER->CCMR2 = 0 ;
EXTMODULE_TIMER->EGR = 1 ; // Restart
EXTMODULE_TIMER->CCMR2 = 0;
EXTMODULE_TIMER->EGR = 1; // Restart
EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn);
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
}
static void extmoduleCrossfireStop()
{
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn);
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE;
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
if (!IS_TRAINER_EXTERNAL_MODULE()) {
EXTERNAL_MODULE_OFF();
@@ -270,7 +270,7 @@ static void intmodulePxxStart()
INTERNAL_MODULE_ON();
// Timer1, channel 3
setupPulsesPXX(INTERNAL_MODULE) ; // TODO not here!
setupPulsesPXX(INTERNAL_MODULE); // TODO not here!
GPIO_InitTypeDef GPIO_InitStructure;
@@ -282,42 +282,42 @@ static void intmodulePxxStart()
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(INTMODULE_PPM_GPIO, &GPIO_InitStructure);
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
INTMODULE_TIMER->ARR = 18000 ; // 9mS
INTMODULE_TIMER->CCR2 = 15000 ; // Update time
INTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
INTMODULE_TIMER->CCER = TIM_CCER_CC3E ;
INTMODULE_TIMER->CR2 = TIM_CR2_OIS3 ; // O/P idle high
INTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
INTMODULE_TIMER->ARR = 18000; // 9mS
INTMODULE_TIMER->CCR2 = 15000; // Update time
INTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1; // 0.5uS from 30MHz
INTMODULE_TIMER->CCER = TIM_CCER_CC3E;
INTMODULE_TIMER->CR2 = TIM_CR2_OIS3; // O/P idle high
INTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs
INTMODULE_TIMER->CCR3 = modulePulsesData[INTERNAL_MODULE].pxx.pulses[0];
INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0 ; // Force O/P high
INTMODULE_TIMER->EGR = 1 ; // Restart
INTMODULE_TIMER->DIER |= TIM_DIER_CC3DE ; // Enable DMA on CC3 match
INTMODULE_TIMER->DCR = 15 ; // DMA to CC1
INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_0; // Force O/P high
INTMODULE_TIMER->EGR = 1; // Restart
INTMODULE_TIMER->DIER |= TIM_DIER_CC3DE; // Enable DMA on CC3 match
INTMODULE_TIMER->DCR = 15; // DMA to CC1
// Enable the DMA channel here, DMA2 stream 6, channel 6
DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6 ; // Write ones to clear bits
DMA2_Stream6->CR &= ~DMA_SxCR_EN; // Disable DMA
DMA2->HIFCR = DMA_HIFCR_CTCIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6 | DMA_HIFCR_CFEIF6; // Write ones to clear bits
DMA2_Stream6->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL;
DMA2_Stream6->PAR = CONVERT_PTR_UINT(&INTMODULE_TIMER->DMAR);
DMA2_Stream6->M0AR = CONVERT_PTR_UINT(&modulePulsesData[INTERNAL_MODULE].pxx.pulses[1]);
DMA2_Stream6->CR |= DMA_SxCR_EN ; // Enable DMA
DMA2_Stream6->CR |= DMA_SxCR_EN; // Enable DMA
INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
INTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
INTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
NVIC_EnableIRQ(INTMODULE_TIMER_IRQn);
NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
}
static void intmodulePxxStop()
{
DMA2_Stream6->CR &= ~DMA_SxCR_EN ; // Disable DMA
NVIC_DisableIRQ(INTMODULE_TIMER_IRQn) ;
INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
DMA2_Stream6->CR &= ~DMA_SxCR_EN; // Disable DMA
NVIC_DisableIRQ(INTMODULE_TIMER_IRQn);
INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE;
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
INTERNAL_MODULE_OFF();
}
@@ -332,41 +332,41 @@ static void intmodulePpmStart()
// Timer1
configure_pins(INTMODULE_PPM_GPIO_PIN, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25);
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
// setupPulsesPPM() is also configuring registers,
// so it has to be called after the peripheral is enabled
setupPulsesPPM(INTERNAL_MODULE) ;
setupPulsesPPM(INTERNAL_MODULE);
INTMODULE_TIMER->ARR = *modulePulsesData[INTERNAL_MODULE].ppm.ptr++ ;
INTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
INTMODULE_TIMER->ARR = *modulePulsesData[INTERNAL_MODULE].ppm.ptr++;
INTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1; // 0.5uS from 30MHz
INTMODULE_TIMER->CCER = TIM_CCER_CC3E ;
INTMODULE_TIMER->CCER = TIM_CCER_CC3E;
INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 ; // PWM mode 1
INTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC2PE ; // PWM mode 1
INTMODULE_TIMER->BDTR = TIM_BDTR_MOE ;
INTMODULE_TIMER->EGR = 1 ;
INTMODULE_TIMER->DIER = TIM_DIER_UDE ;
INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2; // PWM mode 1
INTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC2PE; // PWM mode 1
INTMODULE_TIMER->BDTR = TIM_BDTR_MOE;
INTMODULE_TIMER->EGR = 1;
INTMODULE_TIMER->DIER = TIM_DIER_UDE;
INTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear flag
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ;
INTMODULE_TIMER->DIER |= TIM_DIER_UIE ;
INTMODULE_TIMER->SR &= ~TIM_SR_UIF; // Clear flag
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE;
INTMODULE_TIMER->DIER |= TIM_DIER_UIE;
INTMODULE_TIMER->CR1 = TIM_CR1_CEN ;
NVIC_EnableIRQ(INTMODULE_TIMER_IRQn) ;
INTMODULE_TIMER->CR1 = TIM_CR1_CEN;
NVIC_EnableIRQ(INTMODULE_TIMER_IRQn);
NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn) ;
NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 7);
}
static void intmodulePpmStop()
{
NVIC_DisableIRQ(INTMODULE_TIMER_IRQn) ;
NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn) ;
INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE & ~TIM_DIER_UIE ;
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
NVIC_DisableIRQ(INTMODULE_TIMER_IRQn);
NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);
INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE & ~TIM_DIER_UIE;
INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
INTERNAL_MODULE_OFF();
}
@@ -404,12 +404,12 @@ extern "C" void TIM1_CC_IRQHandler()
extern "C" void TIM1_UP_TIM10_IRQHandler()
{
DEBUG_INTERRUPT(INT_TIM1);
INTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear flag
INTMODULE_TIMER->SR &= ~TIM_SR_UIF; // Clear flag
INTMODULE_TIMER->ARR = *modulePulsesData[INTERNAL_MODULE].ppm.ptr++ ;
INTMODULE_TIMER->ARR = *modulePulsesData[INTERNAL_MODULE].ppm.ptr++;
if (*modulePulsesData[INTERNAL_MODULE].ppm.ptr == 0) {
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear this flag
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear this flag
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
}
}
#endif
@@ -429,49 +429,49 @@ void extmodulePxxStart()
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
EXTMODULE_TIMER->ARR = 18000 ; // 9mS
EXTMODULE_TIMER->CCR2 = 15000 ; // Update time
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE ;
EXTMODULE_TIMER->CR2 = TIM_CR2_OIS1 ; // O/P idle high
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
EXTMODULE_TIMER->ARR = 18000; // 9mS
EXTMODULE_TIMER->CCR2 = 15000; // Update time
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1; // 0.5uS from 30MHz
EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE;
EXTMODULE_TIMER->CR2 = TIM_CR2_OIS1; // O/P idle high
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0];
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
EXTMODULE_TIMER->EGR = 1 ; // Restart
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high
EXTMODULE_TIMER->EGR = 1; // Restart
EXTMODULE_TIMER->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
EXTMODULE_TIMER->DCR = 13 ; // DMA to CC1
EXTMODULE_TIMER->DIER |= TIM_DIER_CC1DE; // Enable DMA on CC1 match
EXTMODULE_TIMER->DCR = 13; // DMA to CC1
// Enable the DMA channel here, DMA2 stream 2, channel 7
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->CR &= ~DMA_SxCR_EN; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2; // Write ones to clear bits
DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL;
DMA2_Stream2->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->DMAR);
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
DMA2_Stream2->CR |= DMA_SxCR_EN; // Enable DMA
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0; // Toggle CC1 o/p
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn);
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
}
static void extmodulePxxStop()
{
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
DMA2_Stream2->CR &= ~DMA_SxCR_EN; // Disable DMA
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn);
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE;
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
if (!IS_TRAINER_EXTERNAL_MODULE()) {
EXTERNAL_MODULE_OFF();
}
}
#if defined(DSM2) || defined(MULTIMODULE)
#if defined(DSM2) || defined(MULTIMODULE)
static void extmoduleDsm2Start()
{
EXTERNAL_MODULE_ON();
@@ -487,45 +487,45 @@ static void extmoduleDsm2Start()
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
EXTMODULE_TIMER->ARR = 44000 ; // 22mS
EXTMODULE_TIMER->CCR2 = 40000 ; // Update time
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ;
EXTMODULE_TIMER->CR2 = TIM_CR2_OIS1 ; // O/P idle high
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
EXTMODULE_TIMER->ARR = 44000; // 22mS
EXTMODULE_TIMER->CCR2 = 40000; // Update time
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1; // 0.5uS from 30MHz
EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP;
EXTMODULE_TIMER->CR2 = TIM_CR2_OIS1; // O/P idle high
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE; // Enable outputs
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[0];
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
EXTMODULE_TIMER->EGR = 1 ; // Restart
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0; // Force O/P high
EXTMODULE_TIMER->EGR = 1; // Restart
EXTMODULE_TIMER->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
EXTMODULE_TIMER->DCR = 13 ; // DMA to CC1
EXTMODULE_TIMER->DIER |= TIM_DIER_CC1DE; // Enable DMA on CC1 match
EXTMODULE_TIMER->DCR = 13; // DMA to CC1
// Enable the DMA channel here, DMA2 stream 2, channel 7
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->CR &= ~DMA_SxCR_EN; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2; // Write ones to clear bits
DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL;
DMA2_Stream2->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->DMAR);
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[1]);
// DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
// DMA2_Stream2->NDTR = 100 ;
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
// DMA2_Stream2->FCR = 0x05; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0;
// DMA2_Stream2->NDTR = 100;
DMA2_Stream2->CR |= DMA_SxCR_EN; // Enable DMA
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0; // Toggle CC1 o/p
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn);
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
}
static void extmoduleDsm2Stop()
{
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
DMA2_Stream2->CR &= ~DMA_SxCR_EN; // Disable DMA
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn);
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE;
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
if (!IS_TRAINER_EXTERNAL_MODULE()) {
EXTERNAL_MODULE_OFF();
}
@@ -537,38 +537,38 @@ static void extmodulePpmStart()
EXTERNAL_MODULE_ON();
configure_pins(EXTMODULE_PPM_GPIO_PIN, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_3 | PIN_OS25);
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
// setupPulsesPPM() is also configuring registers,
// so it has to be called after the peripheral is enabled
setupPulsesPPM(EXTERNAL_MODULE) ;
setupPulsesPPM(EXTERNAL_MODULE);
EXTMODULE_TIMER->ARR = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++ ;
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz
EXTMODULE_TIMER->ARR = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++;
EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1; // 0.5uS from 30MHz
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE ; // PWM mode 1
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE ;
EXTMODULE_TIMER->EGR = 1 ;
EXTMODULE_TIMER->DIER = TIM_DIER_UDE ;
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE; // PWM mode 1
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE;
EXTMODULE_TIMER->EGR = 1;
EXTMODULE_TIMER->DIER = TIM_DIER_UDE;
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear flag
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ;
EXTMODULE_TIMER->DIER |= TIM_DIER_UIE ;
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF; // Clear flag
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE;
EXTMODULE_TIMER->DIER |= TIM_DIER_UIE;
EXTMODULE_TIMER->CR1 = TIM_CR1_CEN ;
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
EXTMODULE_TIMER->CR1 = TIM_CR1_CEN;
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn);
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn) ;
NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn);
NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 7);
}
static void extmodulePpmStop()
{
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
NVIC_DisableIRQ(TIM8_UP_TIM13_IRQn) ;
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE & ~TIM_DIER_UIE ;
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn);
NVIC_DisableIRQ(TIM8_UP_TIM13_IRQn);
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE & ~TIM_DIER_UIE;
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
if (!IS_TRAINER_EXTERNAL_MODULE()) {
EXTERNAL_MODULE_OFF();
}
@@ -577,50 +577,50 @@ static void extmodulePpmStop()
#if !defined(SIMU)
extern "C" void TIM8_CC_IRQHandler()
{
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ; // stop this interrupt
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // stop this interrupt
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
setupPulses(EXTERNAL_MODULE) ;
setupPulses(EXTERNAL_MODULE);
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) {
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
DMA2_Stream2->CR &= ~DMA_SxCR_EN; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
DMA2_Stream2->CR |= DMA_SxCR_EN; // Enable DMA
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0];
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
}
#if defined(DSM2)
else if ((s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) || IS_MULTIMODULE_PROTOCOL (s_current_protocol[EXTERNAL_MODULE]))
{
DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits
else if ((s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) || IS_MULTIMODULE_PROTOCOL (s_current_protocol[EXTERNAL_MODULE]))
{
DMA2_Stream2->CR &= ~DMA_SxCR_EN; // Disable DMA
DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2; // Write ones to clear bits
DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[1]);
DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA
DMA2_Stream2->CR |= DMA_SxCR_EN; // Enable DMA
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[0];
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
}
#endif
else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
EXTMODULE_TIMER->DIER |= TIM_DIER_UDE ;
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear this flag
EXTMODULE_TIMER->DIER |= TIM_DIER_UIE ; // Enable this interrupt
EXTMODULE_TIMER->DIER |= TIM_DIER_UDE;
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF; // Clear this flag
EXTMODULE_TIMER->DIER |= TIM_DIER_UIE; // Enable this interrupt
}
else {
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
}
}
extern "C" void TIM8_UP_TIM13_IRQHandler()
{
DEBUG_INTERRUPT(INT_TIM8);
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear flag
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF; // Clear flag
EXTMODULE_TIMER->ARR = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++ ;
EXTMODULE_TIMER->ARR = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++;
if (*modulePulsesData[EXTERNAL_MODULE].ppm.ptr == 0) {
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear this flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear this flag
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
}
}
#endif
radio/src/targets/taranis/telemetry_driver.cpp
+12 -1
View File
@@ -117,15 +117,26 @@ extern "C" void TELEMETRY_DMA_TX_IRQHandler(void)
DEBUG_INTERRUPT(INT_TELEM_DMA);
if (DMA_GetITStatus(TELEMETRY_DMA_Stream_TX, TELEMETRY_DMA_TX_FLAG_TC)) {
DMA_ClearITPendingBit(TELEMETRY_DMA_Stream_TX, TELEMETRY_DMA_TX_FLAG_TC);
telemetryPortSetDirectionInput();
TELEMETRY_USART->CR1 |= USART_CR1_TCIE;
}
}
#define USART_FLAG_ERRORS (USART_FLAG_ORE | USART_FLAG_NE | USART_FLAG_FE | USART_FLAG_PE)
extern "C" void TELEMETRY_USART_IRQHandler(void)
{
DEBUG_INTERRUPT(INT_TELEM_USART);
uint32_t status = TELEMETRY_USART->SR;
if ((status & USART_SR_TC) && (TELEMETRY_USART->CR1 & USART_CR1_TCIE)) {
TELEMETRY_USART->CR1 &= ~USART_CR1_TCIE;
telemetryPortSetDirectionInput();
while (status & (USART_FLAG_RXNE)) {
status = TELEMETRY_USART->DR;
status = TELEMETRY_USART->SR;
}
}
while (status & (USART_FLAG_RXNE | USART_FLAG_ERRORS)) {
uint8_t data = TELEMETRY_USART->DR;
if (status & USART_FLAG_ERRORS) {