[Taranis] DSM2 now ok on the logic analyser. I cannot test with a module, as I don't have a module ready for...

This commit is contained in:
bsongis
2013-11-03 14:17:54 +00:00
parent 0592960262
commit 82f111d249
3 changed files with 18 additions and 15 deletions
+16 -13
View File
@@ -59,20 +59,18 @@ uint8_t dsm2SerialBitCount;
uint8_t dsm2Index = 0;
void _send_1(uint8_t v)
{
dsm2Value += v;
if (dsm2Index == 0)
v -= 2;
else
v += 2;
if (dsm2Index == 0) {
*(dsm2StreamPtr+1) = dsm2Value;
dsm2Index = 1;
}
else {
*dsm2StreamPtr = dsm2Value;
dsm2Index = 0;
dsm2StreamPtr += 2;
}
dsm2Value += v;
*dsm2StreamPtr++ = dsm2Value;
dsm2Index = (dsm2Index+1) % 2;
}
void sendByteDsm2(uint8_t b) //max 10changes 0 10 10 10 10 1
void sendByteDsm2(uint8_t b) //max 10 changes 0 10 10 10 10 1
{
bool lev = 0;
uint8_t len = BITLEN_DSM2; //max val: 9*16 < 256
@@ -92,7 +90,7 @@ void sendByteDsm2(uint8_t b) //max 10changes 0 10 10 10 10 1
}
void putDsm2Flush()
{
// dsm2StreamPtr--; //remove last stopbits and
dsm2StreamPtr--; //remove last stopbits and
*dsm2StreamPtr++ = 44010; // Past the 44000 of the ARR
}
#else
@@ -139,11 +137,16 @@ void setupPulsesDSM2(unsigned int port)
dsm2SerialBitCount = 0 ;
#else
dsm2Value = 0;
dsm2Index = 0;
dsm2Index = 1;
#endif
dsm2StreamPtr = dsm2Stream;
#if defined(PCBTARANIS)
dsm2Value = 100;
*dsm2StreamPtr++ = dsm2Value;
#endif
switch(s_current_protocol[port]) {
case PROTO_DSM2_LP45:
dsmDat[0] = 0x00;
+1 -1
View File
@@ -52,7 +52,7 @@ uint8_t s_pulses_paused = 0;
uint16_t B3_comp_value;
#ifdef DSM2_SERIAL
#if defined(DSM2_SERIAL)
inline void DSM2_EnableTXD(void)
{
UCSR0B |= (1 << TXEN0); // enable TX
+1 -1
View File
@@ -471,7 +471,7 @@ static void init_pa7_dsm2()
#if defined(REV3)
TIM8->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P ;
#else
TIM8->CCER = TIM_CCER_CC1NE ;
TIM8->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ;
#endif
TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high
TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs