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Add Support for the DS3231 RTC and enable it for AR9X, refs #3531 (#3555)

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* Add Support for the DS3231 RTC and enable it for AR9X, refs #3531

* fix compile for PCB=sky9x

* rtc ds3231: Add missing OpenTX headers
This commit is contained in:
reichi
2016-06-09 17:58:42 +02:00
committed by Bertrand Songis
parent 0c66f520a2
commit 8606e75f45
9 changed files with 1425 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
radio/src/CMakeLists.txt
+12 -4
View File
@@ -226,16 +226,20 @@ elseif(PCB STREQUAL SKY9X OR PCB STREQUAL 9XRPRO OR PCB STREQUAL AR9X)
add_definitions(-Dat91sam3s8 -DREVX)
set(FLAVOUR 9xrpro)
set(LINKER_SCRIPT targets/sky9x/sam3s8c_flash.ld)
set(TARGET_SRC ${TARGET_SRC} rtc_driver.cpp)
set(BOOTLOADER bootflash8.lbm)
elseif(PCB STREQUAL AR9X)
add_definitions(-Dat91sam3s8 -DAR9X)
set(FLAVOUR ar9x)
include_directories(${THIRDPARTY_DIR}/xdk-asf-3.31.0/sam/drivers/twi)
set(SRC ${SRC} ${THIRDPARTY_DIR}/xdk-asf-3.31.0/sam/drivers/twi/twi.c)
set(TARGET_SRC ${TARGET_SRC} i2c_driver.cpp rtc_ds3231_driver.cpp)
set(LINKER_SCRIPT targets/sky9x/sam3s8c_flash.ld)
set(BOOTLOADER bootflash8.lbm)
else()
set(FLAVOUR sky9x)
option(PCBREV "PCB Revision" REVC)
set(TARGET_SRC ${TARGET_SRC} coproc_driver.cpp rotenc_driver.cpp)
set(TARGET_SRC ${TARGET_SRC} coproc_driver.cpp rotenc_driver.cpp rtc_driver.cpp)
add_definitions(-DROTARY_ENCODERS=1)
set(BOOTLOADER bootflash4.lbm)
if(PCBREV STREQUAL REVA)
@@ -271,7 +275,6 @@ elseif(PCB STREQUAL SKY9X OR PCB STREQUAL 9XRPRO OR PCB STREQUAL AR9X)
)
set(TARGET_SRC
${TARGET_SRC}
rtc_driver.cpp
board_sky9x.cpp
telemetry_driver.cpp
serial2_driver.cpp
@@ -279,8 +282,13 @@ elseif(PCB STREQUAL SKY9X OR PCB STREQUAL 9XRPRO OR PCB STREQUAL AR9X)
adc_driver.cpp
eeprom_driver.cpp
pulses_driver.cpp
keys_driver.cpp audio_driver.cpp buzzer_driver.cpp haptic_driver.cpp sdcard_driver.cpp massstorage.cpp
)
keys_driver.cpp
audio_driver.cpp
buzzer_driver.cpp
haptic_driver.cpp
sdcard_driver.cpp
massstorage.cpp
)
set(SRC ${SRC} debug.cpp)
set(FIRMWARE_SRC ${FIRMWARE_SRC} loadboot.cpp)
elseif(PCB STREQUAL 9X OR PCB STREQUAL 9XR OR PCB STREQUAL 9X128 OR PCB STREQUAL 9XR128)
radio/src/targets/sky9x/AT91SAM3S4.h
+21 -7
View File
@@ -5324,17 +5324,31 @@ typedef struct {
#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */
#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */
#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos)
#define TWI_MMR_IADRSZ_Pos 8
#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */
#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */
#define TWI_MMR_DADR_Pos 16
#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */
#define TWI_SMR_SADR_Pos 16
#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */
#define TWI_IADR_IADR_Pos 0
#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */
#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */
#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */
#define TWI_CWGR_CLDIV_Pos 0
#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
#define TWI_CWGR_CHDIV_Pos 8
#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
#define TWI_CWGR_CKDIV_Pos 16
#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
radio/src/targets/sky9x/audio_driver.cpp
+2
View File
@@ -165,10 +165,12 @@ void setScaledVolume(uint8_t volume)
{
#if !defined(NO_HARDWARE_VOLUME)
volumeRequired = volumeScale[min<uint8_t>(volume, VOLUME_LEVEL_MAX)];
#ifndef AR9X
__disable_irq() ;
i2cCheck() ;
__enable_irq() ;
#endif
#endif
}
#endif // #if !defined(SIMU)
radio/src/targets/sky9x/board_sky9x.cpp
+5
View File
@@ -19,6 +19,9 @@
*/
#include "../../opentx.h"
#ifdef AR9X
#include "i2c_driver.h"
#endif
uint16_t ResetReason;
uint32_t Master_frequency ;
@@ -367,6 +370,7 @@ void opentxBootloader();
// Set up for volume control (TWI0)
// Need PA3 and PA4 set to peripheral A
#ifndef AR9X
void i2cInit()
{
register Pio *pioptr;
@@ -392,6 +396,7 @@ void i2cInit()
TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing
NVIC_EnableIRQ(TWI0_IRQn) ;
}
#endif
void boardInit()
{
radio/src/targets/sky9x/i2c_driver.cpp
+83
View File
@@ -0,0 +1,83 @@
/*
* Copyright (C) OpenTX
*
* Based on code named
* th9x - http://code.google.com/p/th9x
* er9x - http://code.google.com/p/er9x
* gruvin9x - http://code.google.com/p/gruvin9x
*
* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "i2c_driver.h"
#include "twi.h"
#include "board.h"
#include "stdlib.h"
#define I2C_CLK_FAST 400000
uint32_t fromBCD(uint8_t bcd_value)
{
return (((bcd_value & 0xF0) * 10) >> 4) + (bcd_value & 0x0F);
}
uint8_t toBCD(uint32_t value)
{
div_t qr = div(value, 10);
return (qr.quot << 4) + qr.rem;
}
twi_packet getPacket(uint8_t chip, uint8_t* addr, uint8_t addr_len, uint8_t *buffer, uint32_t length)
{
twi_packet packet;
packet.chip = chip;
for (uint8_t i = 0; i < addr_len; ++i)
packet.addr[i] = addr[i];
packet.addr_length = addr_len;
packet.buffer = buffer;
packet.length = length;
return packet;
}
bool i2cInit()
{
//Enable Peripheral Clock
PMC->PMC_PCER0 |= 0x00080000L;
//Enable TWI PIOs
register Pio *pioptr;
pioptr = PIOA;
pioptr->PIO_ABCDSR[0] &= ~0x00000018; // Peripheral A
pioptr->PIO_ABCDSR[1] &= ~0x00000018; // Peripheral A
pioptr->PIO_PDR = 0x00000018; // Assign to peripheral
twi_enable_master_mode(TWI0);
twi_options_t opt;
opt.master_clk = Master_frequency;
opt.speed = I2C_CLK_FAST;
return twi_master_init(TWI0, &opt) == TWI_SUCCESS;
}
void i2cCheck()
{
}
uint32_t i2cReadBuffer(uint8_t chip, uint8_t* addr, uint8_t addr_len, uint8_t *buffer, uint32_t length)
{
twi_packet packet(getPacket(chip, addr, addr_len, buffer, length));
return twi_master_read(TWI0, &packet);
}
uint32_t i2cWriteBuffer(uint8_t chip, uint8_t* addr, uint8_t addr_len, uint8_t *buffer, uint32_t length)
{
twi_packet packet(getPacket(chip, addr, addr_len, buffer, length));
return twi_master_write(TWI0, &packet);
}
radio/src/targets/sky9x/i2c_driver.h
+33
View File
@@ -0,0 +1,33 @@
/*
* Copyright (C) OpenTX
*
* Based on code named
* th9x - http://code.google.com/p/th9x
* er9x - http://code.google.com/p/er9x
* gruvin9x - http://code.google.com/p/gruvin9x
*
* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _I2C_DRIVER_H_
#define _I2C_DRIVER_H_
#include "stdint.h"
uint32_t fromBCD(uint8_t bcd_value);
uint8_t toBCD(uint32_t value);
bool i2cInit();
uint32_t i2cReadBuffer(uint8_t chip, uint8_t addr[3], uint8_t addr_len, uint8_t *buffer, uint32_t length);
uint32_t i2cWriteBuffer(uint8_t chip, uint8_t addr[3], uint8_t addr_len, uint8_t *buffer, uint32_t length);
#endif
radio/src/targets/sky9x/rtc_ds3231_driver.cpp
+69
View File
@@ -0,0 +1,69 @@
/*
* Copyright (C) OpenTX
*
* Based on code named
* th9x - http://code.google.com/p/th9x
* er9x - http://code.google.com/p/er9x
* gruvin9x - http://code.google.com/p/gruvin9x
*
* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "rtc.h"
#include "i2c_driver.h"
#define DS3231_I2C_ADDR 0x68
void readRtc()
{
uint8_t buffer[7];
gtm utm;
int res = i2cReadBuffer(DS3231_I2C_ADDR, 0, 2, buffer, 7);
if (res != 0)
return;
// Set the date and time
utm.tm_sec = fromBCD(buffer[0] & 0x7F);
utm.tm_min = fromBCD(buffer[1] & 0x7F);
utm.tm_hour = fromBCD(buffer[2] & 0x3F);
utm.tm_mday = fromBCD(buffer[4] & 0x3F);
utm.tm_mon = fromBCD(buffer[5] & 0x1F) - 1;
utm.tm_year = fromBCD(buffer[6]) + 100;
g_rtcTime = gmktime(&utm);
}
void writeRtc(gtm* ptr)
{
g_rtcTime = gmktime(ptr);
g_ms100 = 0; // start of next second begins now
uint8_t buffer[7];
buffer[0] = toBCD(ptr->tm_sec);
buffer[1] = toBCD(ptr->tm_min);
buffer[2] = toBCD(ptr->tm_hour);
buffer[3] = toBCD(ptr->tm_wday);
buffer[4] = toBCD(ptr->tm_mday);
buffer[5] = toBCD(ptr->tm_mon + 1);
uint8_t offset = ptr->tm_year >= 100 ? 100 : 0;
buffer[6] = toBCD(ptr->tm_year - offset);
i2cWriteBuffer(DS3231_I2C_ADDR, 0, 1, buffer, 7);
}
void rtcSetTime(struct gtm * t)
{
writeRtc(t);
}
void rtcInit()
{
readRtc();
}
radio/src/thirdparty/xdk-asf-3.31.0/sam/drivers/twi/twi.c
Vendored
+749
View File
@@ -0,0 +1,749 @@
/**
* \file
*
* \brief Two-Wire Interface (TWI) driver for SAM.
*
* Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
extern "C" {
#endif
/**INDENT-ON**/
/// @endcond
/**
* \defgroup sam_drivers_twi_group Two-Wire Interface (TWI)
*
* Driver for the TWI (Two-Wire Interface). This driver provides access to the main
* features of the TWI controller.
* The TWI interconnects components on a unique two-wire bus.
* The TWI is programmable as a master or a slave with sequential or single-byte access.
* Multiple master capability is supported.
*
* \par Usage
*
* -# Enable the TWI peripheral clock in the PMC.
* -# Enable the required TWI PIOs (see pio.h).
* -# Enable TWI master mode by calling twi_enable_master_mode if it is a master on the I2C bus.
* -# Configure the TWI in master mode by calling twi_master_init.
* -# Send data to a slave device on the I2C bus by calling twi_master_write.
* -# Receive data from a slave device on the I2C bus by calling the twi_master_read.
* -# Enable TWI slave mode by calling twi_enable_slave_mode if it is a slave on the I2C bus.
* -# Configure the TWI in slave mode by calling twi_slave_init.
*
* @{
*/
#include "twi.h"
#include "stddef.h"
#define I2C_FAST_MODE_SPEED 400000
#define TWI_CLK_DIVIDER 2
#if SAMG55
#define TWI_CLK_CALC_ARGU 3
#else
#define TWI_CLK_CALC_ARGU 4
#endif
#define TWI_CLK_DIV_MAX 0xFF
#define TWI_CLK_DIV_MIN 7
#define TWI_WP_KEY_VALUE TWI_WPMR_WPKEY_PASSWD
/**
* \brief Enable TWI master mode.
*
* \param p_twi Pointer to a TWI instance.
*/
void twi_enable_master_mode(Twi *p_twi)
{
/* Set Master Disable bit and Slave Disable bit */
p_twi->TWI_CR = TWI_CR_MSDIS;
p_twi->TWI_CR = TWI_CR_SVDIS;
/* Set Master Enable bit */
p_twi->TWI_CR = TWI_CR_MSEN;
}
/**
* \brief Disable TWI master mode.
*
* \param p_twi Pointer to a TWI instance.
*/
void twi_disable_master_mode(Twi *p_twi)
{
/* Set Master Disable bit */
p_twi->TWI_CR = TWI_CR_MSDIS;
}
/**
* \brief Initialize TWI master mode.
*
* \param p_twi Pointer to a TWI instance.
* \param p_opt Options for initializing the TWI module (see \ref twi_options_t).
*
* \return TWI_SUCCESS if initialization is complete, error code otherwise.
*/
uint32_t twi_master_init(Twi *p_twi, const twi_options_t *p_opt)
{
uint32_t status = TWI_SUCCESS;
/* Disable TWI interrupts */
p_twi->TWI_IDR = ~0UL;
/* Dummy read in status register */
p_twi->TWI_SR;
/* Reset TWI peripheral */
twi_reset(p_twi);
twi_enable_master_mode(p_twi);
/* Select the speed */
if (twi_set_speed(p_twi, p_opt->speed, p_opt->master_clk) == FAIL) {
/* The desired speed setting is rejected */
status = TWI_INVALID_ARGUMENT;
}
if (p_opt->smbus == 1) {
p_twi->TWI_CR = TWI_CR_QUICK;
}
return status;
}
/**
* \brief Set the I2C bus speed in conjunction with the clock frequency.
*
* \param p_twi Pointer to a TWI instance.
* \param ul_speed The desired I2C bus speed (in Hz).
* \param ul_mck Main clock of the device (in Hz).
*
* \retval PASS New speed setting is accepted.
* \retval FAIL New speed setting is rejected.
*/
uint32_t twi_set_speed(Twi *p_twi, uint32_t ul_speed, uint32_t ul_mck)
{
uint32_t ckdiv = 0;
uint32_t c_lh_div;
if (ul_speed > I2C_FAST_MODE_SPEED) {
return FAIL;
}
c_lh_div = ul_mck / (ul_speed * TWI_CLK_DIVIDER) - TWI_CLK_CALC_ARGU;
/* cldiv must fit in 8 bits, ckdiv must fit in 3 bits */
while ((c_lh_div > TWI_CLK_DIV_MAX) && (ckdiv < TWI_CLK_DIV_MIN)) {
/* Increase clock divider */
ckdiv++;
/* Divide cldiv value */
c_lh_div /= TWI_CLK_DIVIDER;
}
/* set clock waveform generator register */
p_twi->TWI_CWGR =
TWI_CWGR_CLDIV(c_lh_div) | TWI_CWGR_CHDIV(c_lh_div) |
TWI_CWGR_CKDIV(ckdiv);
return PASS;
}
/**
* \brief Test if a chip answers a given I2C address.
*
* \param p_twi Pointer to a TWI instance.
* \param uc_slave_addr Address of the remote chip to search for.
*
* \return TWI_SUCCESS if a chip was found, error code otherwise.
*/
uint32_t twi_probe(Twi *p_twi, uint8_t uc_slave_addr)
{
twi_packet_t packet;
uint8_t data = 0;
/* Data to send */
packet.buffer = &data;
/* Data length */
packet.length = 1;
/* Slave chip address */
packet.chip = (uint32_t) uc_slave_addr;
/* Internal chip address */
packet.addr[0] = 0;
/* Address length */
packet.addr_length = 0;
/* Perform a master write access */
return (twi_master_write(p_twi, &packet));
}
/**
* \internal
* \brief Construct the TWI module address register field
*
* The TWI module address register is sent out MSB first. And the size controls
* which byte is the MSB to start with.
*
* Please see the device datasheet for details on this.
*/
uint32_t twi_mk_addr(const uint8_t *addr, int len)
{
uint32_t val;
if (len == 0)
return 0;
val = addr[0];
if (len > 1) {
val <<= 8;
val |= addr[1];
}
if (len > 2) {
val <<= 8;
val |= addr[2];
}
return val;
}
/**
* \brief Read multiple bytes from a TWI compatible slave device.
*
* \note This function will NOT return until all data has been read or error occurs.
*
* \param p_twi Pointer to a TWI instance.
* \param p_packet Packet information and data (see \ref twi_packet_t).
*
* \return TWI_SUCCESS if all bytes were read, error code otherwise.
*/
uint32_t twi_master_read(Twi *p_twi, twi_packet_t *p_packet)
{
uint32_t status;
uint32_t cnt = p_packet->length;
uint8_t *buffer = p_packet->buffer;
uint8_t stop_sent = 0;
uint32_t timeout = TWI_TIMEOUT;;
/* Check argument */
if (cnt == 0) {
return TWI_INVALID_ARGUMENT;
}
/* Set read mode, slave address and 3 internal address byte lengths */
p_twi->TWI_MMR = 0;
p_twi->TWI_MMR = TWI_MMR_MREAD | TWI_MMR_DADR(p_packet->chip) |
((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) &
TWI_MMR_IADRSZ_Msk);
/* Set internal address for remote chip */
p_twi->TWI_IADR = 0;
p_twi->TWI_IADR = twi_mk_addr(p_packet->addr, p_packet->addr_length);
/* Send a START condition */
if (cnt == 1) {
p_twi->TWI_CR = TWI_CR_START | TWI_CR_STOP;
stop_sent = 1;
} else {
p_twi->TWI_CR = TWI_CR_START;
stop_sent = 0;
}
while (cnt > 0) {
status = p_twi->TWI_SR;
if (status & TWI_SR_NACK) {
return TWI_RECEIVE_NACK;
}
if (!timeout--) {
return TWI_ERROR_TIMEOUT;
}
/* Last byte ? */
if (cnt == 1 && !stop_sent) {
p_twi->TWI_CR = TWI_CR_STOP;
stop_sent = 1;
}
if (!(status & TWI_SR_RXRDY)) {
continue;
}
*buffer++ = p_twi->TWI_RHR;
cnt--;
timeout = TWI_TIMEOUT;
}
while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) {
}
p_twi->TWI_SR;
return TWI_SUCCESS;
}
/**
* \brief Write multiple bytes to a TWI compatible slave device.
*
* \note This function will NOT return until all data has been written or error occurred.
*
* \param p_twi Pointer to a TWI instance.
* \param p_packet Packet information and data (see \ref twi_packet_t).
*
* \return TWI_SUCCESS if all bytes were written, error code otherwise.
*/
uint32_t twi_master_write(Twi *p_twi, twi_packet_t *p_packet)
{
uint32_t status;
uint32_t cnt = p_packet->length;
uint8_t *buffer = p_packet->buffer;
/* Check argument */
if (cnt == 0) {
return TWI_INVALID_ARGUMENT;
}
/* Set write mode, slave address and 3 internal address byte lengths */
p_twi->TWI_MMR = 0;
p_twi->TWI_MMR = TWI_MMR_DADR(p_packet->chip) |
((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) &
TWI_MMR_IADRSZ_Msk);
/* Set internal address for remote chip */
p_twi->TWI_IADR = 0;
p_twi->TWI_IADR = twi_mk_addr(p_packet->addr, p_packet->addr_length);
/* Send all bytes */
while (cnt > 0) {
status = p_twi->TWI_SR;
if (status & TWI_SR_NACK) {
return TWI_RECEIVE_NACK;
}
if (!(status & TWI_SR_TXRDY)) {
continue;
}
p_twi->TWI_THR = *buffer++;
cnt--;
}
while (1) {
status = p_twi->TWI_SR;
if (status & TWI_SR_NACK) {
return TWI_RECEIVE_NACK;
}
if (status & TWI_SR_TXRDY) {
break;
}
}
p_twi->TWI_CR = TWI_CR_STOP;
while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) {
}
return TWI_SUCCESS;
}
/**
* \brief Enable TWI interrupts.
*
* \param p_twi Pointer to a TWI instance.
* \param ul_sources Interrupts to be enabled.
*/
void twi_enable_interrupt(Twi *p_twi, uint32_t ul_sources)
{
/* Enable the specified interrupts */
p_twi->TWI_IER = ul_sources;
}
/**
* \brief Disable TWI interrupts.
*
* \param p_twi Pointer to a TWI instance.
* \param ul_sources Interrupts to be disabled.
*/
void twi_disable_interrupt(Twi *p_twi, uint32_t ul_sources)
{
/* Disable the specified interrupts */
p_twi->TWI_IDR = ul_sources;
/* Dummy read */
p_twi->TWI_SR;
}
/**
* \brief Get TWI interrupt status.
*
* \param p_twi Pointer to a TWI instance.
*
* \retval TWI interrupt status.
*/
uint32_t twi_get_interrupt_status(Twi *p_twi)
{
return p_twi->TWI_SR;
}
/**
* \brief Read TWI interrupt mask.
*
* \param p_twi Pointer to a TWI instance.
*
* \return The interrupt mask value.
*/
uint32_t twi_get_interrupt_mask(Twi *p_twi)
{
return p_twi->TWI_IMR;
}
/**
* \brief Reads a byte from the TWI bus.
*
* \param p_twi Pointer to a TWI instance.
*
* \return The byte read.
*/
uint8_t twi_read_byte(Twi *p_twi)
{
return p_twi->TWI_RHR;
}
/**
* \brief Sends a byte of data to one of the TWI slaves on the bus.
*
* \param p_twi Pointer to a TWI instance.
* \param byte The byte to send.
*/
void twi_write_byte(Twi *p_twi, uint8_t uc_byte)
{
p_twi->TWI_THR = uc_byte;
}
/**
* \brief Enable TWI slave mode.
*
* \param p_twi Pointer to a TWI instance.
*/
void twi_enable_slave_mode(Twi *p_twi)
{
/* Set Master Disable bit and Slave Disable bit */
p_twi->TWI_CR = TWI_CR_MSDIS;
p_twi->TWI_CR = TWI_CR_SVDIS;
/* Set Slave Enable bit */
p_twi->TWI_CR = TWI_CR_SVEN;
}
/**
* \brief Disable TWI slave mode.
*
* \param p_twi Pointer to a TWI instance.
*/
void twi_disable_slave_mode(Twi *p_twi)
{
/* Set Slave Disable bit */
p_twi->TWI_CR = TWI_CR_SVDIS;
}
/**
* \brief Initialize TWI slave mode.
*
* \param p_twi Pointer to a TWI instance.
* \param ul_device_addr Device address of the SAM slave device on the I2C bus.
*/
void twi_slave_init(Twi *p_twi, uint32_t ul_device_addr)
{
/* Disable TWI interrupts */
p_twi->TWI_IDR = ~0UL;
p_twi->TWI_SR;
/* Reset TWI */
twi_reset(p_twi);
/* Set slave address in slave mode */
p_twi->TWI_SMR = TWI_SMR_SADR(ul_device_addr);
/* Enable slave mode */
twi_enable_slave_mode(p_twi);
}
/**
* \brief Set TWI slave address.
*
* \param p_twi Pointer to a TWI instance.
* \param ul_device_addr Device address of the SAM slave device on the I2C bus.
*/
void twi_set_slave_addr(Twi *p_twi, uint32_t ul_device_addr)
{
/* Set slave address */
p_twi->TWI_SMR = TWI_SMR_SADR(ul_device_addr);
}
/**
* \brief Read data from master.
*
* \note This function will NOT return until master sends a STOP condition.
*
* \param p_twi Pointer to a TWI instance.
* \param p_data Pointer to the data buffer where data received will be stored.
*
* \return Number of bytes read.
*/
uint32_t twi_slave_read(Twi *p_twi, uint8_t *p_data)
{
uint32_t status, cnt = 0;
do {
status = p_twi->TWI_SR;
if (status & TWI_SR_SVACC) {
if (!(status & TWI_SR_GACC) &&
((status & (TWI_SR_SVREAD | TWI_SR_RXRDY))
== (TWI_SR_SVREAD | TWI_SR_RXRDY))) {
*p_data++ = (uint8_t) p_twi->TWI_RHR;
cnt++;
}
} else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP))
== (TWI_SR_EOSACC | TWI_SR_TXCOMP)) {
break;
}
} while (1);
return cnt;
}
/**
* \brief Write data to TWI bus.
*
* \note This function will NOT return until master sends a STOP condition.
*
* \param p_twi Pointer to a TWI instance.
* \param p_data Pointer to the data buffer to be sent.
*
* \return Number of bytes written.
*/
uint32_t twi_slave_write(Twi *p_twi, uint8_t *p_data)
{
uint32_t status, cnt = 0;
do {
status = p_twi->TWI_SR;
if (status & TWI_SR_SVACC) {
if (!(status & (TWI_SR_GACC | TWI_SR_SVREAD)) &&
(status & TWI_SR_TXRDY)) {
p_twi->TWI_THR = *p_data++;
cnt++;
}
} else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP))
== (TWI_SR_EOSACC | TWI_SR_TXCOMP)) {
break;
}
} while (1);
return cnt;
}
/**
* \brief Reset TWI.
*
* \param p_twi Pointer to a TWI instance.
*/
void twi_reset(Twi *p_twi)
{
/* Set SWRST bit to reset TWI peripheral */
p_twi->TWI_CR = TWI_CR_SWRST;
p_twi->TWI_RHR;
}
/**
* \brief Get TWI PDC base address.
*
* \param p_twi Pointer to a TWI instance.
*
* \return TWI PDC registers base for PDC driver to access.
*/
Pdc *twi_get_pdc_base(Twi *p_twi)
{
Pdc *p_pdc_base = NULL;
#if !SAMG
if (p_twi == TWI0) {
p_pdc_base = PDC_TWI0;
} else
#endif
#ifdef PDC_TWI1
if (p_twi == TWI1) {
p_pdc_base = PDC_TWI1;
} else
#endif
#ifdef PDC_TWI2
if (p_twi == TWI2) {
p_pdc_base = PDC_TWI2;
} else
#endif
{
Assert(false);
}
return p_pdc_base;
}
#if (SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM)
/**
* \brief Enables/Disables write protection mode.
*
* \param p_twi Pointer to a TWI instance.
* \param flag ture for enable, false for disable.
*/
void twi_set_write_protection(Twi *p_twi, bool flag)
{
p_twi->TWI_WPMR = (flag ? TWI_WPMR_WPEN : 0) | TWI_WP_KEY_VALUE;
}
/**
* \brief Read the write protection status.
*
* \param p_twi Pointer to a TWI instance.
* \param p_status Pointer to save the status.
*/
void twi_read_write_protection_status(Twi *p_twi, uint32_t *p_status)
{
*p_status = p_twi->TWI_WPSR;
}
#endif
#if SAMG55
/**
* \brief Set the prescaler, TLOW:SEXT, TLOW:MEXT and clock high max cycles for SMBUS mode.
*
* \param p_twi Base address of the TWI instance.
* \param ul_timing Parameter for prescaler, TLOW:SEXT, TLOW:MEXT and clock high max cycles.
*/
void twi_smbus_set_timing(Twi *p_twi, uint32_t ul_timing)
{
p_twi->TWI_SMBTR = ul_timing;;
}
/**
* \brief Set length/direction/PEC for alternative command mode.
*
* \param p_twi Base address of the TWI instance.
* \param ul_alt_cmd Alternative command parameters.
*/
void twi_set_alternative_command(Twi *p_twi, uint32_t ul_alt_cmd)
{
p_twi->TWI_ACR = ul_alt_cmd;;
}
/**
* \brief Set the filter for TWI.
*
* \param p_twi Base address of the TWI instance.
* \param ul_filter Filter value.
*/
void twi_set_filter(Twi *p_twi, uint32_t ul_filter)
{
p_twi->TWI_FILTR = ul_filter;;
}
/**
* \brief A mask can be applied on the slave device address in slave mode in order to allow multiple
* address answer. For each bit of the MASK field set to one the corresponding SADR bit will be masked.
*
* \param p_twi Base address of the TWI instance.
* \param ul_mask Mask value.
*/
void twi_mask_slave_addr(Twi *p_twi, uint32_t ul_mask)
{
p_twi->TWI_SMR |= TWI_SMR_MASK(ul_mask);
}
/**
* \brief Set sleepwalking match mode.
*
* \param p_twi Pointer to a TWI instance.
* \param ul_matching_addr1 Address 1 value.
* \param ul_matching_addr2 Address 2 value.
* \param ul_matching_addr3 Address 3 value.
* \param ul_matching_data Data value.
* \param flag1 ture for set, false for no.
* \param flag2 ture for set, false for no.
* \param flag3 ture for set, false for no.
* \param flag ture for set, false for no.
*/
void twi_set_sleepwalking(Twi *p_twi,
uint32_t ul_matching_addr1, bool flag1,
uint32_t ul_matching_addr2, bool flag2,
uint32_t ul_matching_addr3, bool flag3,
uint32_t ul_matching_data, bool flag)
{
uint32_t temp = 0;
if (flag1) {
temp |= TWI_SWMR_SADR1(ul_matching_addr1);
}
if (flag2) {
temp |= TWI_SWMR_SADR2(ul_matching_addr2);
}
if (flag3) {
temp |= TWI_SWMR_SADR3(ul_matching_addr3);
}
if (flag) {
temp |= TWI_SWMR_DATAM(ul_matching_data);
}
p_twi->TWI_SWMR = temp;
}
#endif
//@}
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
}
#endif
/**INDENT-ON**/
/// @endcond
radio/src/thirdparty/xdk-asf-3.31.0/sam/drivers/twi/twi.h
Vendored
+451
View File
@@ -0,0 +1,451 @@
/**
* \file
*
* \brief Two-Wire Interface (TWI) driver for SAM.
*
* Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef TWI_H_INCLUDED
#define TWI_H_INCLUDED
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
extern "C" {
#endif
/**INDENT-ON**/
/// @endcond
#define FAIL 1
#define PASS 0
#define Assert(expr) ((void) 0)
#include "board.h"
/** Time-out value (number of attempts). */
#define TWI_TIMEOUT 15000
/**
* \brief Return codes for TWI APIs.
* @{
*/
#define TWI_SUCCESS 0
#define TWI_INVALID_ARGUMENT 1
#define TWI_ARBITRATION_LOST 2
#define TWI_NO_CHIP_FOUND 3
#define TWI_RECEIVE_OVERRUN 4
#define TWI_RECEIVE_NACK 5
#define TWI_SEND_OVERRUN 6
#define TWI_SEND_NACK 7
#define TWI_BUSY 8
#define TWI_ERROR_TIMEOUT 9
/**
* @}
*/
/**
* \brief Input parameters when initializing the TWI module mode.
*/
typedef struct twi_options {
//! MCK for TWI.
uint32_t master_clk;
//! The baud rate of the TWI bus.
uint32_t speed;
//! The desired address.
uint8_t chip;
//! SMBUS mode (set 1 to use SMBUS quick command, otherwise don't).
uint8_t smbus;
} twi_options_t;
/**
* \brief Information concerning the data transmission.
*/
typedef struct twi_packet {
//! TWI address/commands to issue to the other chip (node).
uint8_t addr[3];
//! Length of the TWI data address segment (1-3 bytes).
uint32_t addr_length;
//! Where to find the data to be transferred.
void *buffer;
//! How many bytes do we want to transfer.
uint32_t length;
//! TWI chip address to communicate with.
uint8_t chip;
} twi_packet_t;
#if SAMG55
enum twi_source_clock {
TWI_SOURCE_PERIPH_CLK = TWI_CWGR_BRSRCCLK_PERIPH_CLK,
TWI_SOURCE_PCK_CLK = TWI_CWGR_BRSRCCLK_PMC_PCK,
};
#endif
void twi_enable_master_mode(Twi *p_twi);
void twi_disable_master_mode(Twi *p_twi);
uint32_t twi_master_init(Twi *p_twi, const twi_options_t *p_opt);
uint32_t twi_set_speed(Twi *p_twi, uint32_t ul_speed, uint32_t ul_mck);
uint32_t twi_probe(Twi *p_twi, uint8_t uc_slave_addr);
uint32_t twi_master_read(Twi *p_twi, twi_packet_t *p_packet);
uint32_t twi_master_write(Twi *p_twi, twi_packet_t *p_packet);
void twi_enable_interrupt(Twi *p_twi, uint32_t ul_sources);
void twi_disable_interrupt(Twi *p_twi, uint32_t ul_sources);
uint32_t twi_get_interrupt_status(Twi *p_twi);
uint32_t twi_get_interrupt_mask(Twi *p_twi);
uint8_t twi_read_byte(Twi *p_twi);
void twi_write_byte(Twi *p_twi, uint8_t uc_byte);
void twi_enable_slave_mode(Twi *p_twi);
void twi_disable_slave_mode(Twi *p_twi);
void twi_slave_init(Twi *p_twi, uint32_t ul_device_addr);
void twi_set_slave_addr(Twi *p_twi, uint32_t ul_device_addr);
uint32_t twi_slave_read(Twi *p_twi, uint8_t *p_data);
uint32_t twi_slave_write(Twi *p_twi, uint8_t *p_data);
void twi_reset(Twi *p_twi);
uint32_t twi_mk_addr(const uint8_t *addr, int len);
Pdc *twi_get_pdc_base(Twi *p_twi);
#if (SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM)
void twi_set_write_protection(Twi *p_twi, bool flag);
void twi_read_write_protection_status(Twi *p_twi, uint32_t *p_status);
#endif
#if SAMG55
void twi_smbus_set_timing(Twi *p_twi, uint32_t ul_timing);
void twi_set_alternative_command(Twi *p_twi, uint32_t ul_alt_cmd);
void twi_set_filter(Twi *p_twi, uint32_t ul_filter);
void twi_mask_slave_addr(Twi *p_twi, uint32_t ul_mask);
void twi_set_sleepwalking(Twi *p_twi,
uint32_t ul_matching_addr1, bool flag1,
uint32_t ul_matching_addr2, bool flag2,
uint32_t ul_matching_addr3, bool flag3,
uint32_t ul_matching_data, bool flag);
/**
* \brief Enable high speed mode.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_enable_highspeed(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_HSEN;
}
/**
* \brief Disable high speed mode.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_highspeed(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_HSDIS;
}
/**
* \brief Enable SMBus mode.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_enable_smbus(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_SMBEN;
}
/**
* \brief Disable SMBus mode.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_smbus(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_SMBDIS;
}
/**
* \brief Enable packet error checking.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_enable_pec(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_PECEN;
}
/**
* \brief Disable packet error checking.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_pec(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_PECDIS;
}
/**
* \brief Request a packet error checking.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_request_pec(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_PECRQ;
}
/**
* \brief If master mode is enabled, send a bus clear command.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_send_clear(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_CLEAR;
}
/**
* \brief Enable alternative command mode.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_enable_alternative_command(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_ACMEN;
}
/**
* \brief Enable alternative command mode.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_alternative_command(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_ACMDIS;
}
/**
* \brief Clear the Transmit Holding Register and set TXRDY, TXCOMP flags.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_thr_clear(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_THRCLR;
}
/**
* \brief Clear the TWI FSM lock.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_lock_clear(Twi *p_twi)
{
p_twi->TWI_CR = TWI_CR_LOCKCLR;
}
/**
* \brief Normal value to be returned in the ACK cycle of the data phase in slave receiver mode.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_slave_nack(Twi *p_twi)
{
p_twi->TWI_SMR &= ~TWI_SMR_NACKEN;
}
/**
* \brief NACK value to be returned in the ACK cycle of the data phase in slave receiver mode.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_enable_slave_nack(Twi *p_twi)
{
p_twi->TWI_SMR |= TWI_SMR_NACKEN;
}
/**
* \brief Acknowledge of the SMBus Default Address disabled.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_slave_default_addr(Twi *p_twi)
{
p_twi->TWI_SMR &= ~TWI_SMR_SMDA;
}
/**
* \brief Acknowledge of the SMBus Default Address enabled.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_enable_slave_default_addr(Twi *p_twi)
{
p_twi->TWI_SMR |= TWI_SMR_SMDA;
}
/**
* \brief Acknowledge of the SMBus Host Header disabled.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_smbus_host_header(Twi *p_twi)
{
p_twi->TWI_SMR &= ~TWI_SMR_SMHH;
}
/**
* \brief Acknowledge of the SMBus Host Header enabled.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_enable_smbus_host_header(Twi *p_twi)
{
p_twi->TWI_SMR |= TWI_SMR_SMHH;
}
/**
* \brief Clock stretching disabled in slave mode, OVRE and UNRE will indicate overrun and underrun.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_clock_wait_state(Twi *p_twi)
{
p_twi->TWI_SMR |= TWI_SMR_SCLWSDIS;
}
/**
* \brief Clear clock wait state disable mode.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_clear_disable_clock_wait_state(Twi *p_twi)
{
p_twi->TWI_SMR &= ~TWI_SMR_SCLWSDIS;
}
/**
* \brief Slave Address 1 matching disabled.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_slave_addr1_matching(Twi *p_twi)
{
p_twi->TWI_SMR &= ~TWI_SMR_SADR1EN;
}
/**
* \brief Slave Address 1 matching enabled.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_enable_slave_addr1_matching(Twi *p_twi)
{
p_twi->TWI_SMR |= TWI_SMR_SADR1EN;
}
/**
* \brief Slave Address 2 matching disabled.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_slave_addr2_matching(Twi *p_twi)
{
p_twi->TWI_SMR &= ~TWI_SMR_SADR2EN;
}
/**
* \brief Slave Address 2 matching enabled.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_enable_slave_addr2_matching(Twi *p_twi)
{
p_twi->TWI_SMR |= TWI_SMR_SADR2EN;
}
/**
* \brief Slave Address 3 matching disabled.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_slave_addr3_matching(Twi *p_twi)
{
p_twi->TWI_SMR &= ~TWI_SMR_SADR3EN;
}
/**
* \brief Slave Address 3 matching enabled.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_enable_slave_addr3_matching(Twi *p_twi)
{
p_twi->TWI_SMR |= TWI_SMR_SADR3EN;
}
/**
* \brief First received data matching disabled.
*
* \param p_twi Base address of the TWI instance.
*/
static inline void twi_disable_slave_data_matching(Twi *p_twi)
{
p_twi->TWI_SMR &= ~TWI_SMR_DATAMEN;
}
/**
* \brief Select the souce clock for the bit rate generation.
*
* \param p_twi Base address of the TWI instance.
* \param src_clk Source clock.
*/
static inline void twi_select_source_clock(Twi *p_twi, enum twi_source_clock src_clk)
{
p_twi->TWI_CWGR &= ~TWI_CWGR_BRSRCCLK;
p_twi->TWI_CWGR |= src_clk;
}
#endif
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
}
#endif
/**INDENT-ON**/
/// @endcond
#endif /* TWI_H_INCLUDED */