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[X9D] SD Card and clocks sorted hopefully for good.

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This commit is contained in:
bernet.andre@gmail.com
2013-01-09 13:24:49 +00:00
parent 78ed555f6e
commit 8abf660e2b
10 changed files with 60 additions and 68 deletions
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src/CoOS/kernel/OsConfig.h
+5 -1
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@@ -42,7 +42,11 @@ Idle task stack size(word).
/*!<
System frequency (Hz).
*/
#define CFG_CPU_FREQ (36000000)
#if defined(PCBX9D)
#define CFG_CPU_FREQ (60000000)
#else
#define CFG_CPU_FREQ (36000000) // TODO check if really correct for sky9x?
#endif
/*!<
systick frequency (Hz).
src/model_menus.cpp
+1 -1
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@@ -2164,7 +2164,7 @@ void menuModelExpoMix(uint8_t expo, uint8_t event)
uint8_t attr = ((s_copyMode || sub != cur) ? 0 : INVERS);
if (expo) {
#if defined(PCBX9D)
uint32_t allattr = isMixActive(i) ? 0 : GREY2;
uint32_t allattr = isMixActive(i) ? 0 : GREY1;
#endif
ed->weight = gvarMenuItem(EXPO_LINE_WEIGHT_POS, y, ed->weight, 0, 100, attr | expoweightattr, event);
src/sdcard.h
+1 -1
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@@ -49,7 +49,7 @@
#define LOGS_PATH "/9XLOGS" // no trailing slash = important
#define SOUNDS_PATH "/9XSOUNDS" // no trailing slash = important
#define SYSTEM_SOUNDS_PATH SOUNDS_PATH "/SYSTEM" // no trailing slash = important
#define BITMAPS_PATH MODELS_PATH
#define BITMAPS_PATH "/9XBMP"
#endif
#define MODELS_EXT ".bin"
src/x9d/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c
+35 -48
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@@ -2,12 +2,12 @@
******************************************************************************
* @file system_stm32f2xx.c
* @author MCD Application Team
* @version V1.1.3
* @date 05-March-2012
* @version V1.1.0
* @date 09-January-2013
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F2xx devices,
* and is generated by the clock configuration tool
* "STM32f2xx_Clock_Configuration_V1.0.0.xls"
* STM32f2xx_Clock_Configuration_V1.1.0.xls
*
* 1. This file provides two functions and one global variable to be called from
* user application:
@@ -46,23 +46,23 @@
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 120000000
* SYSCLK(Hz) | 60000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 120000000
* HCLK(Hz) | 60000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
* APB1 Prescaler | 2
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
* HSE Frequency(Hz) | 12000000
*-----------------------------------------------------------------------------
* PLL_M | 25
* PLL_M | 12
*-----------------------------------------------------------------------------
* PLL_N | 240
*-----------------------------------------------------------------------------
* PLL_P | 2
* PLL_P | 4
*-----------------------------------------------------------------------------
* PLL_Q | 5
*-----------------------------------------------------------------------------
@@ -74,7 +74,7 @@
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 3
* Flash Latency(WS) | 2
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
@@ -86,23 +86,17 @@
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -137,7 +131,7 @@
*/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM322xG_EVAL board as data memory */
on STM322xG_EVALboard as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
@@ -148,12 +142,11 @@
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
// Gives 60MHz
#define PLL_M 12
#define PLL_N 120
#define PLL_N 240
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
#define PLL_P 4
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 5
@@ -174,7 +167,7 @@
* @{
*/
uint32_t SystemCoreClock = 120000000;
uint32_t SystemCoreClock = 60000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
@@ -186,10 +179,6 @@
* @{
*/
extern uint32_t Master_frequency ;
uint32_t Peri1_frequency ;
uint32_t Peri2_frequency ;
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
@@ -248,7 +237,7 @@ void SystemInit(void)
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
@@ -370,11 +359,11 @@ static void SetSysClock(void)
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK2 = HCLK / 1*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* PCLK1 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
@@ -389,7 +378,7 @@ static void SetSysClock(void)
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
@@ -405,17 +394,14 @@ static void SetSysClock(void)
configuration. User can add here some code to deal with this error */
}
Master_frequency = 60000000 ;
Peri1_frequency = 30000000 ;
Peri2_frequency = 15000000 ;
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
* before jump to __main
* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
* before jump to __main
* @param None
* @retval None
*/
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
@@ -546,5 +532,6 @@ void SystemInit_ExtMemCtl(void)
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
src/x9d/board_x9d.cpp
+4 -3
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@@ -38,8 +38,9 @@ uint8_t temperature = 0; // Raw temp reading
uint8_t maxTemperature = 0 ; // Raw temp reading
volatile uint32_t Tenms ; // TODO to remove everywhere / use a #define
// TODO why not here the Peri1_frequency ... (to avoid modifications in system_stm32f2xx.c)
uint32_t Master_frequency ;
uint32_t Peri1_frequency = 30000000;
uint32_t Peri2_frequency = 30000000;
uint32_t Timer_mult = 2;
#define PIN_MODE_MASK 0x0003
#define PIN_INPUT 0x0000
@@ -124,7 +125,7 @@ void init5msTimer()
// Timer14
RCC->APB1ENR |= RCC_APB1ENR_TIM14EN ; // Enable clock
TIM14->ARR = 4999 ; // 5mS
TIM14->PSC = Peri1_frequency / 1000000 ; // 1uS from 30MHz
TIM14->PSC = (Peri1_frequency * Timer_mult) / 1000000 - 1 ; // 1uS from 30MHz
TIM14->CCER = 0 ;
TIM14->CCMR1 = 0 ;
TIM14->EGR = 0 ;
src/x9d/board_x9d.h
+4 -2
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@@ -47,8 +47,10 @@
#include "audio_driver.h"
#include "delays.h"
extern uint32_t Peri1_frequency ;
extern uint32_t Peri2_frequency ;
extern uint32_t SystemCoreClock;
extern uint32_t Peri1_frequency;
extern uint32_t Peri2_frequency;
extern uint32_t Timer_mult;
// TODO elsewhere
#if !defined(SIMU)
src/x9d/delays.cpp
+6 -6
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@@ -37,19 +37,19 @@ void delaysInit(void)
{
// Timer13
RCC->APB1ENR |= RCC_APB1ENR_TIM13EN; // Enable clock
TIM13->PSC = Peri1_frequency / 100000; // 0.1uS from 30MHz
TIM13->PSC = (Peri1_frequency * Timer_mult) / 10000000 - 1; // 0.1uS
TIM13->CCER = 0;
TIM13->CCMR1 = 0;
TIM13->EGR = 0;
TIM13->CR1 = 0x03;
TIM13->CR1 = 0x02;
TIM13->DIER = 0;
}
void delay_01us(uint16_t nb)
{
TIM13->EGR = 1;
TIM13->CNT = 0;
TIM13->EGR = 1;
while(((uint16_t)TIM13->CNT) < nb);
TIM13->EGR = 0;
TIM13->CR1 = 0x03;
while(TIM13->CNT < nb);
TIM13->CR1 = 0x02;
}
src/x9d/diskio.cpp
+2 -4
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@@ -132,10 +132,10 @@ static void interface_speed( enum speed_setting speed )
tmp = SPI_SD->CR1;
if ( speed == INTERFACE_SLOW ) {
/* Set slow clock (100k-400k) */
tmp = ( tmp | SPI_BaudRatePrescaler_256 );
tmp = ( tmp | SPI_BaudRatePrescaler_128 );
} else {
/* Set fast clock (depends on the CSD) */
tmp = ( tmp & ~SPI_BaudRatePrescaler_256 ) | SPI_BaudRatePrescaler_SPI_SD;
tmp = ( tmp & ~SPI_BaudRatePrescaler_128 ) | SPI_BaudRatePrescaler_SPI_SD;
}
SPI_SD->CR1 = tmp;
}
@@ -345,7 +345,6 @@ void power_on (void)
{
SPI_InitTypeDef SPI_InitStructure;
GPIO_InitTypeDef GPIO_InitStructure;
volatile BYTE dummyread;
/* Enable GPIO clock for CS */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_CS, ENABLE);
@@ -533,7 +532,6 @@ BYTE send_cmd (
}
/* Select the card and wait for ready */
DESELECT();
SELECT();
if (wait_ready() != 0xFF) {
return 0xFF;
src/x9d/hal.h
+1 -1
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@@ -185,7 +185,7 @@
#define SOCKET_WP_CONNECTED (0)
#define SOCKET_CP_CONNECTED (0)
#define SPI_BaudRatePrescaler_SPI_SD SPI_BaudRatePrescaler_4 // - for SPI1 and full-speed APB2: 60MHz/4 =15MHZ < 20MHZ
#define SPI_BaudRatePrescaler_SPI_SD SPI_BaudRatePrescaler_2 // - for SPI2 and full-speed APB1: 30MHz/2 =15MHZ < 20MHZ
// Selectable
// DMA
src/x9d/i2c_ee.c
+1 -1
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@@ -12,7 +12,7 @@
#include "../open9x.h"
#define I2C_delay() delay_01us(15);
#define I2C_delay() delay_01us(100);
/**
* @brief Configure the used I/O ports pin