More Sky9x bootloader files removed
This commit is contained in:
bsongis
@@ -1,558 +0,0 @@
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/* ----------------------------------------------------------------------------
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* ATMEL Microcontroller Software Support
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* ----------------------------------------------------------------------------
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* Copyright (c) 2008, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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//------------------------------------------------------------------------------
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// Headers
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//------------------------------------------------------------------------------
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#include <string.h>
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#include "Media.h"
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#include "debug.h"
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#include "board.h"
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#include "diskio.h"
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//------------------------------------------------------------------------------
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// Constants
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//------------------------------------------------------------------------------
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/// Number of SD Slots
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#define NUM_SD_SLOTS 1
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#define SD_BLOCK_SIZE 512
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//------------------------------------------------------------------------------
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/// Checks if the device is write protected.
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/// \return 1 if protected.
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//------------------------------------------------------------------------------
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#if 0
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static unsigned char CardIsProtected(unsigned char slot)
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{
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if (slot == 0) {
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#ifdef BOARD_SD_PIN_WP
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PIO_Configure(&pinMciWriteProtect, 1);
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return (PIO_Get(&pinMciWriteProtect) != 0);
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#else
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return 0;
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#endif
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}
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if (slot == 1) {
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#ifdef BOARD_SD_MCI1_PIN_WP
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PIO_Configure(&pinMciWriteProtect1, 1);
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return (PIO_Get(&pinMciWriteProtect1) != 0);
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#else
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return 0;
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#endif
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}
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return 0;
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}
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#endif
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//------------------------------------------------------------------------------
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/// Configure the PIO for SD
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//------------------------------------------------------------------------------
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#if 0
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static void ConfigurePIO(unsigned char mciID)
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{
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#ifdef BOARD_SD_PINS
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const Pin pinSd0[] = {BOARD_SD_PINS};
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#endif
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#ifdef BOARD_SD_MCI1_PINS
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const Pin pinSd1[] = {BOARD_SD_MCI1_PINS};
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#endif
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if(mciID == 0) {
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#ifdef BOARD_SD_PINS
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PIO_Configure(pinSd0, PIO_LISTSIZE(pinSd0));
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#endif
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} else {
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#ifdef BOARD_SD_MCI1_PINS
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PIO_Configure(pinSd1, PIO_LISTSIZE(pinSd1));
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#endif
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}
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}
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#endif
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//------------------------------------------------------------------------------
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//! \brief Reads a specified amount of data from a SDCARD memory
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//! \param media Pointer to a Media instance
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//! \param address Address of the data to read
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//! \param data Pointer to the buffer in which to store the retrieved
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//! data
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//! \param length Length of the buffer
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//! \param callback Optional pointer to a callback function to invoke when
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//! the operation is finished
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//! \param argument Optional pointer to an argument for the callback
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//! \return Operation result code
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//------------------------------------------------------------------------------
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static unsigned char MEDSdcard_Read(Media *media,
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unsigned int address,
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void *data,
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unsigned int length,
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MediaCallback callback,
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void *argument)
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{
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TRACE_DEBUG("MEDSdcard_Read(address=%d length=%d)\n\r", address, length);
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// Check that the media is ready
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if (media->state != MED_STATE_READY) {
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TRACE_INFO("Media busy\n\r");
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return MED_STATUS_BUSY;
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}
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// Check that the data to read is not too big
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if ((length + address) > media->size) {
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TRACE_WARNING("MEDSdcard_Read: Data too big: %d, %d\n\r",
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(int)length, (int)address);
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return MED_STATUS_ERROR;
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}
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// Enter Busy state
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media->state = MED_STATE_BUSY;
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disk_read (0, data, address, length);
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// Leave the Busy state
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media->state = MED_STATE_READY;
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// Invoke callback
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if (callback != 0) {
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callback(argument, MED_STATUS_SUCCESS, 0, 0);
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}
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return MED_STATUS_SUCCESS;
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}
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static unsigned char Eeprom_Read(Media *media,
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unsigned int address,
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void *data,
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unsigned int length,
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MediaCallback callback,
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void *argument)
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{
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if (media->state != MED_STATE_READY) {
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TRACE_INFO("Media busy\n\r");
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return MED_STATUS_BUSY;
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}
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// Check that the data to read is not too big
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if ((length + address) > media->size) {
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TRACE_WARNING("Eeprom_Read: Data too big: %d, %d\n\r",
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(int)length, (int)address);
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return MED_STATUS_ERROR;
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}
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// Enter Busy state
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media->state = MED_STATE_BUSY;
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disk_read (1, data, address, length);
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// Leave the Busy state
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media->state = MED_STATE_READY;
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// Invoke callback
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if (callback != 0) {
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callback(argument, MED_STATUS_SUCCESS, 0, 0);
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}
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return MED_STATUS_SUCCESS;
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}
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//------------------------------------------------------------------------------
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//! \brief Writes data on a SDRAM media
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//! \param media Pointer to a Media instance
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//! \param address Address at which to write
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//! \param data Pointer to the data to write
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//! \param length Size of the data buffer
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//! \param callback Optional pointer to a callback function to invoke when
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//! the write operation terminates
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//! \param argument Optional argument for the callback function
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//! \return Operation result code
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//! \see Media
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//! \see MediaCallback
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//------------------------------------------------------------------------------
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static unsigned char MEDSdcard_Write(Media *media,
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unsigned int address,
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void *data,
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unsigned int length,
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MediaCallback callback,
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void *argument)
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{
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TRACE_DEBUG("MEDSdcard_Write(address=%d length=%d)\n\r", address, length);
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// Check that the media if ready
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if (media->state != MED_STATE_READY) {
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TRACE_WARNING("MEDSdcard_Write: Media is busy\n\r");
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return MED_STATUS_BUSY;
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}
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// Check that the data to write is not too big
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if ((length + address) > media->size) {
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TRACE_WARNING("MEDSdcard_Write: Data too big\n\r");
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return MED_STATUS_ERROR;
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}
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// Put the media in Busy state
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media->state = MED_STATE_BUSY;
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disk_write(0, data, address, length);
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// Leave the Busy state
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media->state = MED_STATE_READY;
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// Invoke the callback if it exists
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if (callback != 0) {
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callback(argument, MED_STATUS_SUCCESS, 0, 0);
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}
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return MED_STATUS_SUCCESS;
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}
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static unsigned char Eeprom_Write(Media *media,
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unsigned int address,
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void *data,
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unsigned int length,
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MediaCallback callback,
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void *argument)
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{
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TRACE_DEBUG("Eeprom_Write(address=%d length=%d)\n\r", address, length);
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// Check that the media if ready
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if (media->state != MED_STATE_READY) {
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TRACE_WARNING("Eeprom_Write: Media is busy\n\r");
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return MED_STATUS_BUSY;
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}
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// Check that the data to write is not too big
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if ((length + address) > media->size) {
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TRACE_WARNING("Eeprom_Write: Data too big\n\r");
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return MED_STATUS_ERROR;
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}
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// Put the media in Busy state
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media->state = MED_STATE_BUSY;
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disk_write(1, data, address, length);
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// Leave the Busy state
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media->state = MED_STATE_READY;
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// Invoke the callback if it exists
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if (callback != 0) {
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callback(argument, MED_STATUS_SUCCESS, 0, 0);
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}
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return MED_STATUS_SUCCESS;
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}
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//------------------------------------------------------------------------------
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/// Initializes a Media instance and the associated physical interface
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/// \param media Pointer to the Media instance to initialize
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/// \return 1 if success.
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//------------------------------------------------------------------------------
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unsigned char MEDSdcard_Initialize(Media *media, unsigned char mciID)
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{
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TRACE_INFO("MEDSdcard init\n\r");
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// Initialize SDcard
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//--------------------------------------------------------------------------
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if ( !CardIsConnected( ) )
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{
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return 0;
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}
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// Configure SDcard pins
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// ConfigurePIO(mciID);
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#if defined(MCI2_INTERFACE)
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// DMAD_Initialize(BOARD_MCI_DMA_CHANNEL, DMAD_NO_DEFAULT_IT);
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#endif
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#if 0
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// Initialize the MCI driver
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if ( mciID == 0 )
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{
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IRQ_ConfigureIT(BOARD_SD_MCI_ID, 1, MCI0_IrqHandler);
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MCI_Init(mciDrv, BOARD_SD_MCI_BASE, BOARD_SD_MCI_ID, BOARD_SD_SLOT, BOARD_MCK );
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IRQ_EnableIT(BOARD_SD_MCI_ID);
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}
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else
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{
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#ifdef BOARD_SD_MCI1_ID
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IRQ_ConfigureIT(BOARD_SD_MCI1_ID, 1, MCI0_IrqHandler);
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MCI_Init(mciDrv, BOARD_SD_MCI1_BASE, BOARD_SD_MCI1_ID, BOARD_SD_MCI1_SLOT, BOARD_MCK );
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IRQ_EnableIT(BOARD_SD_MCI1_ID);
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#else
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TRACE_ERROR("SD/MMC card initialization failed (MCI1 not supported)\n\r");
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#endif
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}
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#if MCI_BUSY_CHECK_FIX && defined(BOARD_SD_DAT0)
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MCI_SetBusyFix(mciDrv, &pinSdDAT0);
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#endif
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// Initialize the SD card driver
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if (SD_Init(sdDrv, (SdDriver *)mciDrv))
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{
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TRACE_ERROR("SD/MMC card initialization failed\n\r");
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||||
return 0;
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||||
}
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else
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{
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||||
//SD_DisplayRegisterCSD(&sdDrv);
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TRACE_INFO("SD/MMC card initialization successful\n\r");
|
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TRACE_INFO("Card size: %d MB\n\r", (int)(MMC_GetTotalSizeKB(sdDrv)/1024));
|
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}
|
||||
MCI_SetSpeed(mciDrv, sdDrv->transSpeed, sdDrv->transSpeed, BOARD_MCK);
|
||||
#endif
|
||||
|
||||
|
||||
media->write = MEDSdcard_Write;
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media->read = MEDSdcard_Read;
|
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media->lock = 0;
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media->unlock = 0;
|
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media->handler = 0;
|
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media->flush = 0;
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|
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media->blockSize = SD_BLOCK_SIZE;
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media->baseAddress = 0;
|
||||
|
||||
media->size = SD_GET_BLOCKNR();
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||||
|
||||
media->mappedRD = 0;
|
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media->mappedWR = 0;
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||||
media->protected = 0; // TODO BSS CardIsProtected(mciID);
|
||||
media->removable = 1;
|
||||
|
||||
media->state = MED_STATE_READY;
|
||||
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||||
media->transfer.data = 0;
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media->transfer.address = 0;
|
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media->transfer.length = 0;
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media->transfer.callback = 0;
|
||||
media->transfer.argument = 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
unsigned char EEPROM_Initialize(Media *media, unsigned char mciID)
|
||||
{
|
||||
media->write = Eeprom_Write;
|
||||
media->read = Eeprom_Read;
|
||||
media->lock = 0;
|
||||
media->unlock = 0;
|
||||
media->handler = 0;
|
||||
media->flush = 0;
|
||||
|
||||
media->blockSize = 512 ;
|
||||
media->baseAddress = 0;
|
||||
|
||||
#ifdef REVX
|
||||
media->size = 2051 ;
|
||||
#else
|
||||
media->size = 1539 ;
|
||||
#endif
|
||||
|
||||
media->mappedRD = 0;
|
||||
media->mappedWR = 0;
|
||||
media->protected = 0; // TODO BSS CardIsProtected(mciID);
|
||||
media->removable = 1;
|
||||
|
||||
media->state = MED_STATE_READY;
|
||||
|
||||
media->transfer.data = 0;
|
||||
media->transfer.address = 0;
|
||||
media->transfer.length = 0;
|
||||
media->transfer.callback = 0;
|
||||
media->transfer.argument = 0;
|
||||
|
||||
return 1;
|
||||
|
||||
}
|
||||
|
||||
#if 0
|
||||
//------------------------------------------------------------------------------
|
||||
/// Initializes a Media instance and the associated physical interface
|
||||
/// \param media Pointer to the Media instance to initialize
|
||||
/// \return 1 if success.
|
||||
//------------------------------------------------------------------------------
|
||||
unsigned char MEDSdusb_Initialize(Media *media, unsigned char mciID)
|
||||
{
|
||||
TRACE_INFO("MEDSdusb init\n\r");
|
||||
|
||||
// Initialize SDcard
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
if (!CardIsConnected()) return 0;
|
||||
#if 0
|
||||
// Configure SDcard pins
|
||||
ConfigurePIO(mciID);
|
||||
|
||||
#if defined(MCI2_INTERFACE)
|
||||
DMAD_Initialize(BOARD_MCI_DMA_CHANNEL, DMAD_NO_DEFAULT_IT);
|
||||
#endif
|
||||
// Initialize the MCI driver
|
||||
if ( mciID == 0 )
|
||||
{
|
||||
IRQ_ConfigureIT(BOARD_SD_MCI_ID, 1, MCI0_IrqHandler);
|
||||
MCI_Init(mciDrv, BOARD_SD_MCI_BASE, BOARD_SD_MCI_ID, BOARD_SD_SLOT, BOARD_MCK );
|
||||
IRQ_EnableIT(BOARD_SD_MCI_ID);
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef BOARD_SD_MCI1_ID
|
||||
IRQ_ConfigureIT(BOARD_SD_MCI1_ID, 1, MCI0_IrqHandler);
|
||||
MCI_Init(mciDrv, BOARD_SD_MCI1_BASE, BOARD_SD_MCI1_ID, BOARD_SD_SLOT, BOARD_MCK );
|
||||
IRQ_EnableIT(BOARD_SD_MCI1_ID);
|
||||
#else
|
||||
TRACE_ERROR("SD/MMC card initialization failed (MCI1 not supported)\n\r");
|
||||
#endif
|
||||
}
|
||||
#if MCI_BUSY_CHECK_FIX && defined(BOARD_SD_DAT0)
|
||||
MCI_SetBusyFix(mciDrv, &pinSdDAT0);
|
||||
#endif
|
||||
|
||||
// Initialize the SD card driver
|
||||
if (SD_Init(sdDrv, (SdDriver *)mciDrv))
|
||||
{
|
||||
TRACE_ERROR("SD/MMC card initialization failed\n\r");
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
TRACE_INFO("SD/MMC card initialization successful\n\r");
|
||||
TRACE_INFO("Card size: %d MB\n\r", (int)(MMC_GetTotalSizeKB(sdDrv)/1024));
|
||||
}
|
||||
MCI_SetSpeed(mciDrv, sdDrv->transSpeed, sdDrv->transSpeed, BOARD_MCK);
|
||||
#endif
|
||||
// Initialize media fields
|
||||
//--------------------------------------------------------------------------
|
||||
//media->interface = sdDrv;
|
||||
media->write = MEDSdusb_Write;
|
||||
media->read = MEDSdusb_Read;
|
||||
media->lock = 0;
|
||||
media->unlock = 0;
|
||||
media->handler = 0;
|
||||
media->flush = 0;
|
||||
|
||||
media->blockSize = SD_BLOCK_SIZE;
|
||||
media->baseAddress = 0;
|
||||
media->size = 1024*1024; // TODO BSS SD_TOTAL_BLOCK(sdDrv);
|
||||
|
||||
media->mappedRD = 0;
|
||||
media->mappedWR = 0;
|
||||
media->protectedd = false; // TODO BSS CardIsProtected(mciID);
|
||||
media->removable = 1;
|
||||
|
||||
media->state = MED_STATE_READY;
|
||||
|
||||
media->transfer.data = 0;
|
||||
media->transfer.address = 0;
|
||||
media->transfer.length = 0;
|
||||
media->transfer.callback = 0;
|
||||
media->transfer.argument = 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
//------------------------------------------------------------------------------
|
||||
/// erase all the Sdcard
|
||||
/// \param media Pointer to the Media instance to initialize
|
||||
//------------------------------------------------------------------------------
|
||||
void MEDSdcard_EraseAll(Media *media)
|
||||
{
|
||||
unsigned char buffer[SD_BLOCK_SIZE];
|
||||
unsigned int block;
|
||||
unsigned int multiBlock = 1; // change buffer size for multiblocks
|
||||
unsigned char error;
|
||||
|
||||
TRACE_INFO("MEDSdcard Erase All ...\n\r");
|
||||
|
||||
// Clear the block buffer
|
||||
memset(buffer, 0, media->blockSize * multiBlock);
|
||||
|
||||
for (block=0;
|
||||
block < (SD_TOTAL_BLOCK((SdCard*)media->interface)-multiBlock);
|
||||
block += multiBlock)
|
||||
{
|
||||
// TODO BSS error = SD_WriteBlock((SdCard*)media->interface, block, multiBlock, buffer);
|
||||
assert( !error ); /* "\n\r-F- Failed to write block (%d) #%u\n\r", error, block */
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
/// erase block
|
||||
/// \param media Pointer to the Media instance to initialize
|
||||
/// \param block to erase
|
||||
//------------------------------------------------------------------------------
|
||||
#if 0
|
||||
void MEDSdcard_EraseBlock(Media *media, unsigned int block)
|
||||
{
|
||||
unsigned char buffer[SD_BLOCK_SIZE];
|
||||
unsigned char error;
|
||||
|
||||
// Clear the block buffer
|
||||
memset(buffer, 0, media->blockSize);
|
||||
|
||||
// TODO BSS error = SD_WriteBlock((SdCard*)media->interface, block, 1, buffer);
|
||||
assert( !error ) ; /* "\n\r-F- Failed to write block (%d) #%u\n\r", error, block */
|
||||
}
|
||||
#endif
|
||||
//------------------------------------------------------------------------------
|
||||
/// Get driver pointer
|
||||
//------------------------------------------------------------------------------
|
||||
#if 0
|
||||
SdCard* MEDSdcard_GetDriver( unsigned int slot )
|
||||
{
|
||||
if (slot >= NUM_SD_SLOTS)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
return &sdDrv[slot];
|
||||
}
|
||||
#endif
|
||||
@@ -1,273 +0,0 @@
|
||||
/* ----------------------------------------------------------------------------
|
||||
* ATMEL Microcontroller Software Support
|
||||
* ----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008, Atmel Corporation
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Atmel's name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* Provides the low-level initialization function that gets called on chip startup.
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Headers
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#include "board.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Local definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
/** Define clock timeout */
|
||||
#define CLOCK_TIMEOUT 5000
|
||||
/** Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.*/
|
||||
#define PMC_PLLA_SET_BIT29 (0x1 << 29)
|
||||
/** Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.*/
|
||||
#define PMC_PLLA_COUNT (0xBF << 8)
|
||||
/** The PLLA Clock frequency is the PLLA input frequency multiplied by 8*/
|
||||
#define PMC_PLLA_MULTIPIER (0x07 << 16)
|
||||
/** PLLA Divider is bypassed.*/
|
||||
#define PMC_PLLA_DIV (0x01)
|
||||
|
||||
void revert_osc( void ) ;
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Local functions
|
||||
* returns master_frequency
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
// *** WARNING, this is called BEFORE .data and .bss have been initialised
|
||||
// *** GLOBAL variables are NOT useable
|
||||
|
||||
static uint32_t BOARD_ConfigurePmc(void)
|
||||
{
|
||||
/* TODO: configurate PLL in new way */
|
||||
//#if 0
|
||||
// uint32_t timeout = 0;
|
||||
// /** 1: Checking the Main Oscillator Frequency (Optional) and Initialize main oscillator */
|
||||
// /** 1.1 Initialize main oscillator */
|
||||
// // TODO:
|
||||
|
||||
// /** 2. Setting PLL and Divider*/
|
||||
// /** 2.1 Initialize PLLA*/
|
||||
// PMC->CKGR_PLLAR = ( PMC_PLLA_SET_BIT29 |
|
||||
// PMC_PLLA_MULTIPIER |
|
||||
// PMC_PLLA_COUNT |
|
||||
// PMC_PLLA_DIV
|
||||
// );
|
||||
// timeout = 0;
|
||||
// /** 2.2 Wait for the LOCKA bit to be set by polling the status register.*/
|
||||
// while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT));
|
||||
// /** 2.3 wait for the MCKRDY bit to be set by polling the status register*/
|
||||
// timeout = 0;
|
||||
// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
|
||||
|
||||
// /** 3. Selection of Master Clock and Processor Clock*/
|
||||
// PMC->PMC_MCKR |= PMC_MCKR_PRES_CLK_2;
|
||||
|
||||
// /** 3.1 wait for the MCKRDY bit to be set by polling the status register*/
|
||||
// timeout = 0;
|
||||
// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
|
||||
|
||||
// /** 3.2 PLLA Clock is selected */
|
||||
// PMC->PMC_MCKR = PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK;
|
||||
|
||||
// /** 3.3 wait for the MCKRDY bit to be set by polling the status register*/
|
||||
// timeout = 0;
|
||||
// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
|
||||
//#endif
|
||||
|
||||
#if 1 // old as sam3u
|
||||
#define AT91C_CKGR_MUL_SHIFT 16
|
||||
//#define AT91C_CKGR_OUT_SHIFT 14
|
||||
#define AT91C_CKGR_PLLCOUNT_SHIFT 8
|
||||
#define AT91C_CKGR_DIV_SHIFT 0
|
||||
|
||||
// Settings at 72MHz/2 = 36MHz
|
||||
#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST & (0x8 << 8))
|
||||
#define BOARD_PLLR ((1 << 29) | (0x5 << AT91C_CKGR_MUL_SHIFT) \
|
||||
| (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x2 << AT91C_CKGR_DIV_SHIFT))
|
||||
#define BOARD_MCKR (PMC_MCKR_CSS_PLLA_CLK)
|
||||
|
||||
// Define clock timeout
|
||||
#undef CLOCK_TIMEOUT
|
||||
#define CLOCK_TIMEOUT 0xFFFFFFFF
|
||||
|
||||
register uint32_t timeout = 0 ;
|
||||
register Pmc *pmcptr ;
|
||||
|
||||
pmcptr = PMC ;
|
||||
|
||||
/* Enable NRST reset
|
||||
************************************/
|
||||
//AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN;
|
||||
|
||||
/* Select external slow clock
|
||||
****************************/
|
||||
|
||||
|
||||
// if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST) {
|
||||
// SUPC->SUPC_CR = SUPC_CR_XTALSEL_CRYSTAL_SEL | ((uint32_t)0xA5 << 24);
|
||||
// timeout = 0;
|
||||
// while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST) );
|
||||
// }
|
||||
|
||||
|
||||
/* Initialize main oscillator
|
||||
****************************/
|
||||
if(!(pmcptr->CKGR_MOR & CKGR_MOR_MOSCSEL))
|
||||
{
|
||||
|
||||
pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
||||
timeout = 0;
|
||||
while (!(pmcptr->PMC_SR & PMC_SR_MOSCXTS) && (++timeout < CLOCK_TIMEOUT));
|
||||
|
||||
}
|
||||
|
||||
/* Switch to 3-20MHz Xtal oscillator */
|
||||
pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
||||
timeout = 0;
|
||||
while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT));
|
||||
|
||||
pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
timeout = 0;
|
||||
while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT));
|
||||
|
||||
/* Initialize PLLA 72 MHz */
|
||||
pmcptr->CKGR_PLLAR = BOARD_PLLR;
|
||||
timeout = 0;
|
||||
while (!(pmcptr->PMC_SR & PMC_SR_LOCKA) && (++timeout < CLOCK_TIMEOUT));
|
||||
|
||||
|
||||
/* Initialize UTMI for USB usage, can be disabled if not using USB for the sake of saving power*/
|
||||
//AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN;
|
||||
//timeout = 0;
|
||||
//while (!(PMC->PMC_SR & AT91C_PMC_LOCKU) && (timeout++ < CLOCK_TIMEOUT));
|
||||
|
||||
/* Switch to fast clock
|
||||
**********************/
|
||||
// PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
// timeout = 0;
|
||||
// while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
|
||||
|
||||
// Switch to PLLA as main clock 36MHz
|
||||
PMC->PMC_MCKR = BOARD_MCKR;
|
||||
timeout = 0;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT));
|
||||
|
||||
#endif
|
||||
return 36000000L ; // Master_frequency
|
||||
}
|
||||
|
||||
#ifndef BOOT
|
||||
void revert_osc()
|
||||
{
|
||||
register uint32_t timeout = 0 ;
|
||||
register Pmc *pmcptr ;
|
||||
|
||||
pmcptr = PMC ;
|
||||
|
||||
|
||||
// Switch back to the internal oscillator
|
||||
pmcptr->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN ;
|
||||
timeout = 0;
|
||||
while (!(pmcptr->PMC_SR & PMC_SR_MOSCSELS) && (++timeout < CLOCK_TIMEOUT));
|
||||
|
||||
pmcptr->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_SLOW_CLK;
|
||||
timeout = 0;
|
||||
while (!(pmcptr->PMC_SR & PMC_SR_MCKRDY) && (++timeout < CLOCK_TIMEOUT));
|
||||
|
||||
|
||||
pmcptr->CKGR_PLLAR = 1 << 29 ; // Stop PLLA
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BOOT
|
||||
|
||||
extern void sam_bootx( void ) ;
|
||||
extern void dispUSB( void ) ;
|
||||
extern uint32_t initReadTrims( void ) ;
|
||||
extern void run_application( void ) ;
|
||||
|
||||
static void lowLevelUsbCheck( void )
|
||||
{
|
||||
PMC->PMC_PCER0 = (1<<ID_PIOC) ; // Enable clock to PIOC
|
||||
PIOC->PIO_PER = PIO_PC25 ; // Enable bit C25 (USB-detect)
|
||||
|
||||
uint32_t i ;
|
||||
for ( i = 0 ; i < 50 ; i += 1 )
|
||||
{
|
||||
__asm("nop") ;
|
||||
}
|
||||
|
||||
for ( i = 0 ; i < 10 ; i += 1 )
|
||||
{
|
||||
if ( PIOC->PIO_PDSR & 0x02000000 )
|
||||
{
|
||||
PMC->PMC_PCDR0 = (1<<ID_PIOC) ; // Disable clock to PIOC
|
||||
dispUSB() ;
|
||||
sam_bootx() ;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t x = initReadTrims() ;
|
||||
if ( ( x & 0x42 ) != 0x42 )
|
||||
{
|
||||
run_application() ;
|
||||
// loadAndRunBoot() ;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Exported functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* \brief Performs the low-level initialization of the chip. This includes EFC,
|
||||
* master clock and watchdog configuration.
|
||||
*/
|
||||
/*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemInit (void)
|
||||
{
|
||||
#ifdef BOOT
|
||||
lowLevelUsbCheck() ;
|
||||
#endif
|
||||
/** Set 2 cycle (1 WS) for Embedded Flash Access */
|
||||
// Max clock is 38 MHz (1.8V VVDCORE)
|
||||
EFC->EEFC_FMR = (1 << 8) ;
|
||||
|
||||
/** Configure PMC */
|
||||
return BOARD_ConfigurePmc();
|
||||
}
|
||||
|
||||
|
||||
@@ -1,604 +0,0 @@
|
||||
/****************************************************************************
|
||||
* Copyright (c) 2014 by Michael Blandford. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the author nor the names of its contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************
|
||||
* Other Authors:
|
||||
* - Andre Bernet
|
||||
* - Bertrand Songis
|
||||
* - Bryan J. Rentoul (Gruvin)
|
||||
* - Cameron Weeks
|
||||
* - Erez Raviv
|
||||
* - Jean-Pierre Parisy
|
||||
* - Karl Szmutny
|
||||
* - Michal Hlavinka
|
||||
* - Pat Mackenzie
|
||||
* - Philip Moss
|
||||
* - Rob Thomson
|
||||
* - Romolo Manfredini
|
||||
* - Thomas Husterer
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Headers
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include "AT91SAM3S4.h"
|
||||
|
||||
|
||||
uint8_t Eblock_buffer[4096] ;
|
||||
uint8_t Eblock_current[4096] ; // For erased checking
|
||||
int32_t EblockAddress ;
|
||||
|
||||
uint8_t Spi_tx_buf[24] ;
|
||||
uint8_t Spi_rx_buf[24] ;
|
||||
uint32_t Spi_init_done = 0 ;
|
||||
|
||||
uint32_t EepromBlocked = 1 ;
|
||||
extern uint8_t EE_timer ;
|
||||
|
||||
// Test for EEPROM file
|
||||
uint32_t isEepromStart( uint8_t *p )
|
||||
{
|
||||
uint32_t csum ;
|
||||
uint32_t size = 7 ;
|
||||
|
||||
csum = 0 ;
|
||||
while( size )
|
||||
{
|
||||
csum += *p++ ;
|
||||
size -= 1 ;
|
||||
}
|
||||
if ( csum == *p )
|
||||
{
|
||||
return 1 ;
|
||||
}
|
||||
return 0 ;
|
||||
}
|
||||
|
||||
|
||||
uint32_t eeprom_write_one( uint8_t byte, uint8_t count ) ;
|
||||
uint32_t eeprom_read_status( void ) ;
|
||||
void eeprom_write_enable( void ) ;
|
||||
void eeprom_wait_busy( void ) ;
|
||||
uint32_t spi_operation( register uint8_t *tx, register uint8_t *rx, register uint32_t count ) ;
|
||||
void init_spi( void ) ;
|
||||
uint32_t unprotect_eeprom( void ) ;
|
||||
uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count ) ;
|
||||
void AT25D_Read( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset) ;
|
||||
void AT25D_Write( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset ) ;
|
||||
uint32_t AT25D_EraseBlock( uint32_t memoryOffset ) ;
|
||||
void writeBlock( void ) ;
|
||||
|
||||
|
||||
uint32_t eeprom_write_one( uint8_t byte, uint8_t count )
|
||||
{
|
||||
register Spi *spiptr ;
|
||||
register uint32_t result ;
|
||||
|
||||
spiptr = SPI ;
|
||||
spiptr->SPI_CR = 1 ; // Enable
|
||||
(void) spiptr->SPI_RDR ; // Dump any rx data
|
||||
|
||||
spiptr->SPI_TDR = byte ;
|
||||
|
||||
result = 0 ;
|
||||
while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 )
|
||||
{
|
||||
// wait for received
|
||||
if ( ++result > 10000 )
|
||||
{
|
||||
break ;
|
||||
}
|
||||
}
|
||||
if ( count == 0 )
|
||||
{
|
||||
spiptr->SPI_CR = 2 ; // Disable
|
||||
return spiptr->SPI_RDR ;
|
||||
}
|
||||
(void) spiptr->SPI_RDR ; // Dump the rx data
|
||||
spiptr->SPI_TDR = 0 ;
|
||||
result = 0 ;
|
||||
while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 )
|
||||
{
|
||||
// wait for received
|
||||
if ( ++result > 10000 )
|
||||
{
|
||||
break ;
|
||||
}
|
||||
}
|
||||
spiptr->SPI_CR = 2 ; // Disable
|
||||
return spiptr->SPI_RDR ;
|
||||
}
|
||||
|
||||
|
||||
uint32_t eeprom_read_status()
|
||||
{
|
||||
return eeprom_write_one( 5, 1 ) ;
|
||||
}
|
||||
|
||||
|
||||
void eeprom_write_enable()
|
||||
{
|
||||
eeprom_write_one( 6, 0 ) ;
|
||||
}
|
||||
|
||||
void eeprom_wait_busy()
|
||||
{
|
||||
register uint32_t x ;
|
||||
register uint32_t y ;
|
||||
|
||||
y = 0 ;
|
||||
do
|
||||
{
|
||||
y += 1 ;
|
||||
if ( y > 1000000 )
|
||||
{
|
||||
break ;
|
||||
}
|
||||
x = eeprom_read_status() ;
|
||||
} while ( x & 1 ) ;
|
||||
|
||||
}
|
||||
|
||||
uint32_t spi_operation( register uint8_t *tx, register uint8_t *rx, register uint32_t count )
|
||||
{
|
||||
register Spi *spiptr ;
|
||||
register uint32_t result ;
|
||||
|
||||
// PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI
|
||||
|
||||
result = 0 ;
|
||||
spiptr = SPI ;
|
||||
spiptr->SPI_CR = 1 ; // Enable
|
||||
(void) spiptr->SPI_RDR ; // Dump any rx data
|
||||
while( count )
|
||||
{
|
||||
result = 0 ;
|
||||
while( ( spiptr->SPI_SR & SPI_SR_TXEMPTY ) == 0 )
|
||||
{
|
||||
// wait
|
||||
if ( ++result > 10000 )
|
||||
{
|
||||
result = 0xFFFF ;
|
||||
break ;
|
||||
}
|
||||
}
|
||||
if ( result > 10000 )
|
||||
{
|
||||
break ;
|
||||
}
|
||||
// if ( count == 1 )
|
||||
// {
|
||||
// spiptr->SPI_CR = SPI_CR_LASTXFER ; // LastXfer bit
|
||||
// }
|
||||
spiptr->SPI_TDR = *tx++ ;
|
||||
result = 0 ;
|
||||
while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 )
|
||||
{
|
||||
// wait for received
|
||||
if ( ++result > 10000 )
|
||||
{
|
||||
result = 0x2FFFF ;
|
||||
break ;
|
||||
}
|
||||
}
|
||||
if ( result > 10000 )
|
||||
{
|
||||
break ;
|
||||
}
|
||||
*rx++ = spiptr->SPI_RDR ;
|
||||
count -= 1 ;
|
||||
}
|
||||
if ( result <= 10000 )
|
||||
{
|
||||
result = 0 ;
|
||||
}
|
||||
spiptr->SPI_CR = 2 ; // Disable
|
||||
|
||||
// Power save
|
||||
// PMC->PMC_PCER0 &= ~0x00200000L ; // Disable peripheral clock to SPI
|
||||
|
||||
return result ;
|
||||
}
|
||||
|
||||
uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count )
|
||||
{
|
||||
register Spi *spiptr ;
|
||||
// register uint32_t result ;
|
||||
register uint32_t condition ;
|
||||
static uint8_t discard_rx_command[4] ;
|
||||
|
||||
// PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI
|
||||
|
||||
// Spi_complete = 0 ;
|
||||
if ( comlen > 4 )
|
||||
{
|
||||
// Spi_complete = 1 ;
|
||||
return 0x4FFFF ;
|
||||
}
|
||||
condition = SPI_SR_TXEMPTY ;
|
||||
spiptr = SPI ;
|
||||
spiptr->SPI_CR = 1 ; // Enable
|
||||
(void) spiptr->SPI_RDR ; // Dump any rx data
|
||||
(void) spiptr->SPI_SR ; // Clear error flags
|
||||
spiptr->SPI_RPR = (uint32_t)discard_rx_command ;
|
||||
spiptr->SPI_RCR = comlen ;
|
||||
if ( rx )
|
||||
{
|
||||
spiptr->SPI_RNPR = (uint32_t)rx ;
|
||||
spiptr->SPI_RNCR = count ;
|
||||
condition = SPI_SR_RXBUFF ;
|
||||
}
|
||||
spiptr->SPI_TPR = (uint32_t)command ;
|
||||
spiptr->SPI_TCR = comlen ;
|
||||
if ( tx )
|
||||
{
|
||||
spiptr->SPI_TNPR = (uint32_t)tx ;
|
||||
}
|
||||
else
|
||||
{
|
||||
spiptr->SPI_TNPR = (uint32_t)rx ;
|
||||
}
|
||||
spiptr->SPI_TNCR = count ;
|
||||
|
||||
spiptr->SPI_PTCR = SPI_PTCR_RXTEN | SPI_PTCR_TXTEN ; // Start transfers
|
||||
|
||||
// Wait for things to get started, avoids early interrupt
|
||||
for ( count = 0 ; count < 1000 ; count += 1 )
|
||||
{
|
||||
if ( ( spiptr->SPI_SR & SPI_SR_TXEMPTY ) == 0 )
|
||||
{
|
||||
break ;
|
||||
}
|
||||
}
|
||||
|
||||
count = 0 ;
|
||||
while( ( spiptr->SPI_SR & condition ) == 0 )
|
||||
{
|
||||
if ( ++count > 1000000 )
|
||||
{
|
||||
break ;
|
||||
}
|
||||
}
|
||||
|
||||
spiptr->SPI_CR = 2 ; // Disable
|
||||
(void) spiptr->SPI_RDR ; // Dump any rx data
|
||||
(void) spiptr->SPI_SR ; // Clear error flags
|
||||
spiptr->SPI_PTCR = SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS ; // Stop tramsfers
|
||||
|
||||
if ( count > 1000000 )
|
||||
{
|
||||
return 1 ;
|
||||
}
|
||||
return 0 ;
|
||||
}
|
||||
|
||||
|
||||
uint32_t unprotect_eeprom()
|
||||
{
|
||||
register uint8_t *p ;
|
||||
|
||||
eeprom_write_enable() ;
|
||||
|
||||
p = Spi_tx_buf ;
|
||||
*p = 0x39 ; // Unprotect sector command
|
||||
*(p+1) = 0 ;
|
||||
*(p+2) = 0 ;
|
||||
*(p+3) = 0 ; // 3 bytes address
|
||||
|
||||
return spi_operation( p, Spi_rx_buf, 4 ) ;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void init_spi()
|
||||
{
|
||||
register Pio *pioptr ;
|
||||
register Spi *spiptr ;
|
||||
register uint32_t timer ;
|
||||
register uint8_t *p ;
|
||||
uint8_t spi_buf[4] ;
|
||||
|
||||
if ( !Spi_init_done)
|
||||
{
|
||||
PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI
|
||||
/* Configure PIO */
|
||||
pioptr = PIOA ;
|
||||
pioptr->PIO_ABCDSR[0] &= ~0x00007800 ; // Peripheral A bits 14,13,12,11
|
||||
pioptr->PIO_ABCDSR[1] &= ~0x00007800 ; // Peripheral A
|
||||
pioptr->PIO_PDR = 0x00007800 ; // Assign to peripheral
|
||||
|
||||
spiptr = SPI ;
|
||||
timer = ( 64000000 / 3000000 ) << 8 ;
|
||||
spiptr->SPI_MR = 0x14000011 ; // 0001 0100 0000 0000 0000 0000 0001 0001 Master
|
||||
spiptr->SPI_CSR[0] = 0x01180009 | timer ; // 0000 0001 0001 1000 xxxx xxxx 0000 1001
|
||||
// NVIC_EnableIRQ(SPI_IRQn) ;
|
||||
|
||||
p = spi_buf ;
|
||||
|
||||
// *p = 0x39 ; // Unprotect sector command
|
||||
// *(p+1) = 0 ;
|
||||
// *(p+2) = 0 ;
|
||||
// *(p+3) = 0 ; // 3 bytes address
|
||||
|
||||
// spi_operation( p, spi_buf, 4 ) ;
|
||||
|
||||
eeprom_write_enable() ;
|
||||
|
||||
*p = 1 ; // Write status register command
|
||||
*(p+1) = 0 ;
|
||||
spi_operation( p, spi_buf, 2 ) ;
|
||||
Spi_init_done = 1 ;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
void AT25D_Read( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset)
|
||||
{
|
||||
register uint8_t *p ;
|
||||
|
||||
p = Spi_tx_buf ;
|
||||
*p = 3 ; // Read command
|
||||
*(p+1) = memoryOffset >> 16 ;
|
||||
*(p+2) = memoryOffset >> 8 ;
|
||||
*(p+3) = memoryOffset ; // 3 bytes address
|
||||
|
||||
spi_PDC_action( p, 0, BufferAddr, 4, size ) ;
|
||||
}
|
||||
|
||||
|
||||
uint32_t ee32_read_512( uint32_t sector, uint8_t *buffer )
|
||||
{
|
||||
AT25D_Read( buffer, 512, sector * 512 ) ;
|
||||
return 1 ;
|
||||
}
|
||||
|
||||
void AT25D_Write( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset )
|
||||
{
|
||||
register uint8_t *p ;
|
||||
|
||||
eeprom_write_enable() ;
|
||||
|
||||
p = Spi_tx_buf ;
|
||||
*p = 2 ; // Write command
|
||||
*(p+1) = memoryOffset >> 16 ;
|
||||
*(p+2) = memoryOffset >> 8 ;
|
||||
*(p+3) = memoryOffset ; // 3 bytes address
|
||||
|
||||
spi_PDC_action( p, BufferAddr, 0, 4, size ) ;
|
||||
|
||||
eeprom_wait_busy() ;
|
||||
|
||||
}
|
||||
|
||||
uint32_t eeprom_block_erased( register uint8_t *p)
|
||||
{
|
||||
register uint32_t x ;
|
||||
register uint32_t result ;
|
||||
|
||||
result = 1 ;
|
||||
|
||||
for ( x = 0 ; x < 4096 ; x += 1 )
|
||||
{
|
||||
if ( *p++ != 0xFF )
|
||||
{
|
||||
result = 0 ;
|
||||
break ;
|
||||
}
|
||||
}
|
||||
return result ;
|
||||
}
|
||||
|
||||
uint32_t eeprom_page_erased( register uint8_t *p)
|
||||
{
|
||||
register uint32_t x ;
|
||||
register uint32_t result ;
|
||||
|
||||
result = 1 ;
|
||||
|
||||
for ( x = 0 ; x < 256 ; x += 1 )
|
||||
{
|
||||
if ( *p++ != 0xFF )
|
||||
{
|
||||
result = 0 ;
|
||||
break ;
|
||||
}
|
||||
}
|
||||
return result ;
|
||||
}
|
||||
|
||||
void writeBlock()
|
||||
{
|
||||
uint32_t x ;
|
||||
uint32_t address ;
|
||||
uint32_t i ;
|
||||
uint8_t *s ;
|
||||
|
||||
x = eeprom_block_erased( Eblock_current ) ; // EEPROM block blanked?
|
||||
if ( x == 0 )
|
||||
{
|
||||
AT25D_EraseBlock( EblockAddress ) ;
|
||||
memset( Eblock_current, 0xFF, 4096 ) ; // Now erased
|
||||
}
|
||||
|
||||
s = Eblock_buffer ;
|
||||
address = EblockAddress ;
|
||||
for ( i = 0 ; i < 16 ; i += 1 ) // pages in block
|
||||
{
|
||||
x = eeprom_page_erased( s ) ;
|
||||
if ( x == 0 ) // Not blank
|
||||
{
|
||||
//EeWriteCount += 1 ;
|
||||
AT25D_Write( s, 256, address ) ;
|
||||
}
|
||||
s += 256 ;
|
||||
address += 256 ;
|
||||
}
|
||||
EblockAddress = -1 ;
|
||||
EE_timer = 0 ;
|
||||
}
|
||||
|
||||
|
||||
void readBlock( uint32_t block_address )
|
||||
{
|
||||
AT25D_Read( Eblock_buffer, 4096, block_address ) ; // read block to write to
|
||||
memcpy( Eblock_current, Eblock_buffer, 4096 ) ; // Copy for erase checking
|
||||
|
||||
EblockAddress = block_address ;
|
||||
}
|
||||
|
||||
uint32_t ee32_write( const uint8_t *buffer, uint32_t sector, uint32_t count )
|
||||
{
|
||||
// EEPROM write
|
||||
uint32_t startMemoryOffset ;
|
||||
uint32_t memoryOffset ;
|
||||
uint32_t bytesToWrite ;
|
||||
uint8_t *pBuffer ;
|
||||
int32_t block_address ;
|
||||
|
||||
if ( sector == 0 )
|
||||
{
|
||||
if ( isEepromStart( (uint8_t *) buffer ) )
|
||||
{
|
||||
EepromBlocked = 0 ;
|
||||
}
|
||||
else
|
||||
{
|
||||
EepromBlocked = 1 ;
|
||||
}
|
||||
}
|
||||
|
||||
if ( EepromBlocked )
|
||||
{
|
||||
return 1 ;
|
||||
}
|
||||
|
||||
startMemoryOffset = sector ;
|
||||
startMemoryOffset *= 512 ; // Byte address into EEPROM
|
||||
memoryOffset = startMemoryOffset;
|
||||
|
||||
bytesToWrite = count * 512 ;
|
||||
|
||||
unprotect_eeprom() ;
|
||||
|
||||
pBuffer = (uint8_t *) buffer ;
|
||||
|
||||
block_address = memoryOffset &0xFFFFF000 ; // 4k boundary
|
||||
|
||||
if ( EblockAddress != -1 )
|
||||
{
|
||||
// Ram copy is dirty
|
||||
if ( EblockAddress != block_address )
|
||||
{
|
||||
// flush buffer
|
||||
writeBlock() ;
|
||||
}
|
||||
}
|
||||
|
||||
// Now check for pre-read
|
||||
if ( EblockAddress != block_address )
|
||||
{
|
||||
readBlock( block_address ) ;
|
||||
|
||||
// // Check to see if it is blank
|
||||
// x = eeprom_block_erased( Eblock_buffer ) ;
|
||||
// if ( x == 0 )
|
||||
// {
|
||||
// AT25D_EraseBlock( block_address ) ;
|
||||
// }
|
||||
}
|
||||
|
||||
while (bytesToWrite)
|
||||
{
|
||||
uint32_t bytes_to_copy ;
|
||||
uint32_t i ;
|
||||
uint8_t *s ;
|
||||
uint8_t *dest ;
|
||||
|
||||
if ( EblockAddress != block_address )
|
||||
{
|
||||
readBlock( block_address ) ;
|
||||
}
|
||||
|
||||
dest = Eblock_buffer + (memoryOffset & 0x0FFF ) ;
|
||||
s = pBuffer ;
|
||||
bytes_to_copy = 4096 - ( memoryOffset - block_address ) ;
|
||||
if ( bytes_to_copy > bytesToWrite )
|
||||
{
|
||||
bytes_to_copy = bytesToWrite ;
|
||||
}
|
||||
for ( i = 0 ; i < bytes_to_copy ; i += 1 )
|
||||
{
|
||||
*dest++ = *s++ ;
|
||||
}
|
||||
memoryOffset += bytes_to_copy ;
|
||||
bytesToWrite -= bytes_to_copy ;
|
||||
|
||||
if ( dest > &Eblock_buffer[4095] )
|
||||
{
|
||||
// copied data past end
|
||||
writeBlock() ;
|
||||
}
|
||||
else
|
||||
{
|
||||
EE_timer = 30 ; // Write dirty block in 0.3 secs
|
||||
}
|
||||
}
|
||||
return 1 ;
|
||||
}
|
||||
|
||||
uint32_t AT25D_EraseBlock( uint32_t memoryOffset )
|
||||
{
|
||||
register uint8_t *p ;
|
||||
register uint32_t x ;
|
||||
|
||||
// EeEraseCount += 1 ;
|
||||
|
||||
eeprom_write_enable() ;
|
||||
p = Spi_tx_buf ;
|
||||
*p = 0x20 ; // Block Erase command
|
||||
*(p+1) = memoryOffset >> 16 ;
|
||||
*(p+2) = memoryOffset >> 8 ;
|
||||
*(p+3) = memoryOffset ; // 3 bytes address
|
||||
x = spi_operation( p, Spi_rx_buf, 4 ) ;
|
||||
|
||||
eeprom_wait_busy() ;
|
||||
return x ;
|
||||
}
|
||||
|
||||
|
||||
@@ -1,880 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm3.c
|
||||
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
|
||||
* @version V1.30
|
||||
* @date 30. October 2009
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* define compiler specific symbols */
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
|
||||
#endif
|
||||
|
||||
uint32_t __get_PSP(void) ;
|
||||
void __set_PSP(uint32_t topOfProcStack) ;
|
||||
uint32_t __get_MSP(void) ;
|
||||
void __set_MSP(uint32_t mainStackPointer) ;
|
||||
uint32_t __REV16(uint16_t value) ;
|
||||
int32_t __REVSH(int16_t value) ;
|
||||
uint32_t __RBIT(uint32_t value) ;
|
||||
uint8_t __LDREXB(uint8_t *addr) ;
|
||||
uint16_t __LDREXH(uint16_t *addr) ;
|
||||
uint32_t __LDREXW(uint32_t *addr) ;
|
||||
uint32_t __STREXB(uint8_t value, uint8_t *addr) ;
|
||||
uint32_t __STREXH(uint16_t value, uint16_t *addr) ;
|
||||
uint32_t __STREXW(uint32_t value, uint32_t *addr) ;
|
||||
|
||||
uint32_t __get_BASEPRI(void) ;
|
||||
void __set_BASEPRI(uint32_t basePri) ;
|
||||
uint32_t __get_PRIMASK(void) ;
|
||||
void __set_PRIMASK(uint32_t priMask) ;
|
||||
uint32_t __get_FAULTMASK(void) ;
|
||||
void __set_FAULTMASK(uint32_t faultMask) ;
|
||||
uint32_t __get_CONTROL(void) ;
|
||||
void __set_CONTROL(uint32_t control) ;
|
||||
uint32_t __REV(uint32_t value) ;
|
||||
|
||||
void revert_osc( void ) ;
|
||||
void sam_boot( void ) ;
|
||||
void sam_bootx( void ) ;
|
||||
void run_application( void ) ;
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/**
|
||||
* @brief Return the Process Stack Pointer
|
||||
*
|
||||
* @return ProcessStackPointer
|
||||
*
|
||||
* Return the actual process stack pointer
|
||||
*/
|
||||
__ASM uint32_t __get_PSP(void)
|
||||
{
|
||||
mrs r0, psp
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Process Stack Pointer
|
||||
*
|
||||
* @param topOfProcStack Process Stack Pointer
|
||||
*
|
||||
* Assign the value ProcessStackPointer to the MSP
|
||||
* (process stack pointer) Cortex processor register
|
||||
*/
|
||||
__ASM void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
msr psp, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Main Stack Pointer
|
||||
*
|
||||
* @return Main Stack Pointer
|
||||
*
|
||||
* Return the current value of the MSP (main stack pointer)
|
||||
* Cortex processor register
|
||||
*/
|
||||
__ASM uint32_t __get_MSP(void)
|
||||
{
|
||||
mrs r0, msp
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Main Stack Pointer
|
||||
*
|
||||
* @param topOfMainStack Main Stack Pointer
|
||||
*
|
||||
* Assign the value mainStackPointer to the MSP
|
||||
* (main stack pointer) Cortex processor register
|
||||
*/
|
||||
__ASM void __set_MSP(uint32_t mainStackPointer)
|
||||
{
|
||||
msr msp, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in unsigned short value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in unsigned short value
|
||||
*/
|
||||
__ASM uint32_t __REV16(uint16_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in signed short value with sign extension to integer
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in signed short value with sign extension to integer
|
||||
*/
|
||||
__ASM int32_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
|
||||
/**
|
||||
* @brief Remove the exclusive lock created by ldrex
|
||||
*
|
||||
* Removes the exclusive lock which is created by ldrex.
|
||||
*/
|
||||
__ASM void __CLREX(void)
|
||||
{
|
||||
clrex
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Base Priority value
|
||||
*
|
||||
* @return BasePriority
|
||||
*
|
||||
* Return the content of the base priority register
|
||||
*/
|
||||
__ASM uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
mrs r0, basepri
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Base Priority value
|
||||
*
|
||||
* @param basePri BasePriority
|
||||
*
|
||||
* Set the base priority register
|
||||
*/
|
||||
__ASM void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
msr basepri, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Priority Mask value
|
||||
*
|
||||
* @return PriMask
|
||||
*
|
||||
* Return state of the priority mask bit from the priority mask register
|
||||
*/
|
||||
__ASM uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
mrs r0, primask
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Priority Mask value
|
||||
*
|
||||
* @param priMask PriMask
|
||||
*
|
||||
* Set the priority mask bit in the priority mask register
|
||||
*/
|
||||
__ASM void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
msr primask, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Fault Mask value
|
||||
*
|
||||
* @return FaultMask
|
||||
*
|
||||
* Return the content of the fault mask register
|
||||
*/
|
||||
__ASM uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
mrs r0, faultmask
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Fault Mask value
|
||||
*
|
||||
* @param faultMask faultMask value
|
||||
*
|
||||
* Set the fault mask register
|
||||
*/
|
||||
__ASM void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
msr faultmask, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Control Register value
|
||||
*
|
||||
* @return Control value
|
||||
*
|
||||
* Return the content of the control register
|
||||
*/
|
||||
__ASM uint32_t __get_CONTROL(void)
|
||||
{
|
||||
mrs r0, control
|
||||
bx lr
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Control Register value
|
||||
*
|
||||
* @param control Control value
|
||||
*
|
||||
* Set the control register
|
||||
*/
|
||||
__ASM void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
msr control, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
#endif /* __ARMCC_VERSION */
|
||||
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
#pragma diag_suppress=Pe940
|
||||
|
||||
/**
|
||||
* @brief Return the Process Stack Pointer
|
||||
*
|
||||
* @return ProcessStackPointer
|
||||
*
|
||||
* Return the actual process stack pointer
|
||||
*/
|
||||
uint32_t __get_PSP(void)
|
||||
{
|
||||
__ASM("mrs r0, psp");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Process Stack Pointer
|
||||
*
|
||||
* @param topOfProcStack Process Stack Pointer
|
||||
*
|
||||
* Assign the value ProcessStackPointer to the MSP
|
||||
* (process stack pointer) Cortex processor register
|
||||
*/
|
||||
void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM("msr psp, r0");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Main Stack Pointer
|
||||
*
|
||||
* @return Main Stack Pointer
|
||||
*
|
||||
* Return the current value of the MSP (main stack pointer)
|
||||
* Cortex processor register
|
||||
*/
|
||||
uint32_t __get_MSP(void)
|
||||
{
|
||||
__ASM("mrs r0, msp");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Main Stack Pointer
|
||||
*
|
||||
* @param topOfMainStack Main Stack Pointer
|
||||
*
|
||||
* Assign the value mainStackPointer to the MSP
|
||||
* (main stack pointer) Cortex processor register
|
||||
*/
|
||||
void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM("msr msp, r0");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in unsigned short value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in unsigned short value
|
||||
*/
|
||||
uint32_t __REV16(uint16_t value)
|
||||
{
|
||||
__ASM("rev16 r0, r0");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse bit order of value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse bit order of value
|
||||
*/
|
||||
uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
__ASM("rbit r0, r0");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (8 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 8 bit values)
|
||||
*/
|
||||
uint8_t __LDREXB(uint8_t *addr)
|
||||
{
|
||||
__ASM("ldrexb r0, [r0]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (16 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 16 bit values
|
||||
*/
|
||||
uint16_t __LDREXH(uint16_t *addr)
|
||||
{
|
||||
__ASM("ldrexh r0, [r0]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (32 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 32 bit values
|
||||
*/
|
||||
uint32_t __LDREXW(uint32_t *addr)
|
||||
{
|
||||
__ASM("ldrex r0, [r0]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (8 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 8 bit values
|
||||
*/
|
||||
uint32_t __STREXB(uint8_t value, uint8_t *addr)
|
||||
{
|
||||
__ASM("strexb r0, r0, [r1]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (16 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 16 bit values
|
||||
*/
|
||||
uint32_t __STREXH(uint16_t value, uint16_t *addr)
|
||||
{
|
||||
__ASM("strexh r0, r0, [r1]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (32 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 32 bit values
|
||||
*/
|
||||
uint32_t __STREXW(uint32_t value, uint32_t *addr)
|
||||
{
|
||||
__ASM("strex r0, r0, [r1]");
|
||||
__ASM("bx lr");
|
||||
}
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
#ifndef BOOT
|
||||
/**
|
||||
* @brief Return the Process Stack Pointer
|
||||
*
|
||||
* @return ProcessStackPointer
|
||||
*
|
||||
* Return the actual process stack pointer
|
||||
*/
|
||||
/*extern uint32_t __get_PSP(void) __attribute__( ( naked ) ); */
|
||||
uint32_t __get_PSP(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n\t"
|
||||
"MOV r0, %0 \n\t"
|
||||
"BX lr \n\t" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Process Stack Pointer
|
||||
*
|
||||
* @param topOfProcStack Process Stack Pointer
|
||||
*
|
||||
* Assign the value ProcessStackPointer to the MSP
|
||||
* (process stack pointer) Cortex processor register
|
||||
*/
|
||||
/*void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); */
|
||||
void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n\t"
|
||||
"BX lr \n\t" : : "r" (topOfProcStack) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Main Stack Pointer
|
||||
*
|
||||
* @return Main Stack Pointer
|
||||
*
|
||||
* Return the current value of the MSP (main stack pointer)
|
||||
* Cortex processor register
|
||||
*/
|
||||
/*uint32_t __get_MSP(void) __attribute__( ( naked ) ); */
|
||||
uint32_t __get_MSP(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n\t"
|
||||
"MOV r0, %0 \n\t"
|
||||
"BX lr \n\t" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Main Stack Pointer
|
||||
*
|
||||
* @param topOfMainStack Main Stack Pointer
|
||||
*
|
||||
* Assign the value mainStackPointer to the MSP
|
||||
* (main stack pointer) Cortex processor register
|
||||
*/
|
||||
/*void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); */
|
||||
void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n\t"
|
||||
"BX lr \n\t" : : "r" (topOfMainStack) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Base Priority value
|
||||
*
|
||||
* @return BasePriority
|
||||
*
|
||||
* Return the content of the base priority register
|
||||
*/
|
||||
uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Base Priority value
|
||||
*
|
||||
* @param basePri BasePriority
|
||||
*
|
||||
* Set the base priority register
|
||||
*/
|
||||
void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Priority Mask value
|
||||
*
|
||||
* @return PriMask
|
||||
*
|
||||
* Return state of the priority mask bit from the priority mask register
|
||||
*/
|
||||
uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Priority Mask value
|
||||
*
|
||||
* @param priMask PriMask
|
||||
*
|
||||
* Set the priority mask bit in the priority mask register
|
||||
*/
|
||||
void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Fault Mask value
|
||||
*
|
||||
* @return FaultMask
|
||||
*
|
||||
* Return the content of the fault mask register
|
||||
*/
|
||||
uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Fault Mask value
|
||||
*
|
||||
* @param faultMask faultMask value
|
||||
*
|
||||
* Set the fault mask register
|
||||
*/
|
||||
void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Control Register value
|
||||
*
|
||||
* @return Control value
|
||||
*
|
||||
* Return the content of the control register
|
||||
*/
|
||||
uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Control Register value
|
||||
*
|
||||
* @param control Control value
|
||||
*
|
||||
* Set the control register
|
||||
*/
|
||||
void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in integer value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in integer value
|
||||
*/
|
||||
uint32_t __REV(uint32_t value)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#ifndef BOOT
|
||||
/**
|
||||
* @brief Reverse byte order in unsigned short value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in unsigned short value
|
||||
*/
|
||||
uint32_t __REV16(uint16_t value)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in signed short value with sign extension to integer
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse byte order in signed short value with sign extension to integer
|
||||
*/
|
||||
int32_t __REVSH(int16_t value)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reverse bit order of value
|
||||
*
|
||||
* @param value value to reverse
|
||||
* @return reversed value
|
||||
*
|
||||
* Reverse bit order of value
|
||||
*/
|
||||
uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (8 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 8 bit value
|
||||
*/
|
||||
uint8_t __LDREXB(uint8_t *addr)
|
||||
{
|
||||
uint8_t result=0;
|
||||
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (16 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 16 bit values
|
||||
*/
|
||||
uint16_t __LDREXH(uint16_t *addr)
|
||||
{
|
||||
uint16_t result=0;
|
||||
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (32 bit)
|
||||
*
|
||||
* @param *addr address pointer
|
||||
* @return value of (*address)
|
||||
*
|
||||
* Exclusive LDR command for 32 bit values
|
||||
*/
|
||||
uint32_t __LDREXW(uint32_t *addr)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (8 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 8 bit values
|
||||
*/
|
||||
uint32_t __STREXB(uint8_t value, uint8_t *addr)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (16 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 16 bit values
|
||||
*/
|
||||
uint32_t __STREXH(uint16_t value, uint16_t *addr)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STR Exclusive (32 bit)
|
||||
*
|
||||
* @param value value to store
|
||||
* @param *addr address pointer
|
||||
* @return successful / failed
|
||||
*
|
||||
* Exclusive STR command for 32 bit values
|
||||
*/
|
||||
uint32_t __STREXW(uint32_t value, uint32_t *addr)
|
||||
{
|
||||
uint32_t result=0;
|
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BOOT
|
||||
void run_application()
|
||||
{
|
||||
__ASM(" mov.w r1, #4227072"); // 0x408000
|
||||
__ASM(" movw r0, #60680"); // 0xED08
|
||||
__ASM(" movt r0, #57344"); // 0xE000
|
||||
__ASM(" str r1, [r0, #0]"); // Set the VTOR
|
||||
|
||||
// __ASM("mov.w r3, #0"); // 0x0000
|
||||
// __ASM("movt r3, #128"); // 0x0080
|
||||
__ASM("ldr r0, [r1, #0]"); // Stack pointer value
|
||||
__ASM("msr msp, r0"); // Set it
|
||||
__ASM("ldr r0, [r1, #4]"); // Reset address
|
||||
__ASM("mov.w r1, #1");
|
||||
__ASM("orr r0, r1"); // Set lsbit
|
||||
__ASM("bx r0"); // Execute application
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef BOOT
|
||||
|
||||
void sam_boot()
|
||||
{
|
||||
revert_osc() ;
|
||||
|
||||
__ASM(" mov.w r1, #8388608");
|
||||
__ASM(" movw r0, #60680");
|
||||
__ASM(" movt r0, #57344");
|
||||
__ASM(" str r1, [r0, #0]"); // Set the VTOR
|
||||
|
||||
__ASM("mov.w r3, #0");
|
||||
__ASM("movt r3, #128");
|
||||
__ASM("ldr r0, [r3, #0]");
|
||||
__ASM("msr msp, r0");
|
||||
__ASM("ldr r0, [r3, #4]");
|
||||
__ASM("mov.w r3, #1");
|
||||
__ASM("orr r0, r3");
|
||||
__ASM("bx r0");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BOOT
|
||||
|
||||
void sam_bootx()
|
||||
{
|
||||
__ASM(" mov.w r1, #8388608");
|
||||
__ASM(" movw r0, #60680");
|
||||
__ASM(" movt r0, #57344");
|
||||
__ASM(" str r1, [r0, #0]"); // Set the VTOR
|
||||
|
||||
__ASM("mov.w r3, #0");
|
||||
__ASM("movt r3, #128");
|
||||
__ASM("ldr r0, [r3, #0]");
|
||||
__ASM("msr msp, r0");
|
||||
__ASM("ldr r0, [r3, #4]");
|
||||
__ASM("mov.w r3, #1");
|
||||
__ASM("orr r0, r3");
|
||||
__ASM("bx r0");
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
@@ -1,147 +0,0 @@
|
||||
/****************************************************************************
|
||||
* Copyright (c) 2011 by Michael Fischer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the author nor the names of its contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************
|
||||
* History:
|
||||
*
|
||||
* 09.04.2011 mifi First Version
|
||||
* 29.04.2011 mifi Call SystemInit, and set the Vector Table Offset
|
||||
* before copy of data and bss segment.
|
||||
****************************************************************************/
|
||||
#define __CRT_C__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*=========================================================================*/
|
||||
/* DEFINE: All extern Data */
|
||||
/*=========================================================================*/
|
||||
/*
|
||||
* The next data are defined by the linker script.
|
||||
*/
|
||||
extern unsigned long _stext;
|
||||
extern unsigned long _etext;
|
||||
extern unsigned long _sdata;
|
||||
extern unsigned long _edata;
|
||||
extern unsigned long _sbss;
|
||||
extern unsigned long _ebss;
|
||||
extern unsigned long _estack;
|
||||
|
||||
/* This is the main */
|
||||
extern int main (void);
|
||||
|
||||
/*=========================================================================*/
|
||||
/* DEFINE: Prototypes */
|
||||
/*=========================================================================*/
|
||||
extern uint32_t SystemInit (void) ; // __attribute__((weak));
|
||||
|
||||
/*=========================================================================*/
|
||||
/* DEFINE: All code exported */
|
||||
/*=========================================================================*/
|
||||
|
||||
/***************************************************************************/
|
||||
/* SystemInit */
|
||||
/* */
|
||||
/* SystemInit is a function which is provided by the CMSIS interface. */
|
||||
/* If this function is not available, we need a function here to prevent */
|
||||
/* an error of the linker. Therefore this function is declared as weak. */
|
||||
/***************************************************************************/
|
||||
//uint32_t SystemInit (void)
|
||||
//{
|
||||
|
||||
//} /* SystemInit */
|
||||
|
||||
extern uint32_t Master_frequency ;
|
||||
|
||||
/***************************************************************************/
|
||||
/* ResetHandler */
|
||||
/* */
|
||||
/* This function is used for the C runtime initialisation, */
|
||||
/* for handling the .data and .bss segments. */
|
||||
/***************************************************************************/
|
||||
void ResetHandler (void)
|
||||
{
|
||||
{
|
||||
register uint32_t *pSrc;
|
||||
register uint32_t *pDest;
|
||||
register uint32_t m_freq ;
|
||||
|
||||
/*
|
||||
* Call the SystemInit code from CMSIS interface if available.
|
||||
* SystemInit is a week function which can be override
|
||||
* by an external function.
|
||||
*/
|
||||
m_freq = SystemInit();
|
||||
|
||||
/*
|
||||
* Set the "Vector Table Offset Register". From the ARM
|
||||
* documentation, we got the following information:
|
||||
*
|
||||
* Use the Vector Table Offset Register to determine:
|
||||
* - if the vector table is in RAM or code memory
|
||||
* - the vector table offset.
|
||||
*/
|
||||
*((uint32_t*)0xE000ED08) = (uint32_t)&_stext;
|
||||
|
||||
/*
|
||||
* Copy the initialized data of the ".data" segment
|
||||
* from the flash to the are in the ram.
|
||||
*/
|
||||
pSrc = &_etext;
|
||||
pDest = &_sdata;
|
||||
while(pDest < &_edata)
|
||||
{
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
|
||||
/*
|
||||
* Clear the ".bss" segment.
|
||||
*/
|
||||
pDest = &_sbss;
|
||||
while(pDest < &_ebss)
|
||||
{
|
||||
*pDest++ = 0;
|
||||
}
|
||||
Master_frequency = m_freq ;
|
||||
}
|
||||
|
||||
/*
|
||||
* And now the main function can be called.
|
||||
* Scotty, energie...
|
||||
*/
|
||||
main();
|
||||
|
||||
/*
|
||||
* In case there are problems with the
|
||||
* "warp drive", stop here.
|
||||
*/
|
||||
while(1) {};
|
||||
|
||||
} /* ResetHandler */
|
||||
|
||||
/*** EOF ***/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,144 +0,0 @@
|
||||
/****************************************************************************
|
||||
* Copyright (c) 2011 by Michael Fischer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the author nor the names of its contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************
|
||||
* History:
|
||||
*
|
||||
* 22.05.2011 mifi First Version
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* In this linker script there is no heap available.
|
||||
* The stack start at the end of the ram segment.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Take a look in the "The GNU linker" manual, here you get
|
||||
* the following information about the "MEMORY":
|
||||
*
|
||||
* "The MEMORY command describes the location and size of
|
||||
* blocks of memory in the target."
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 256K
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 48K
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* And the "SECTION" is used for:
|
||||
*
|
||||
* "The SECTIONS command tells the linker how to map input
|
||||
* sections into output sections, and how to place the output
|
||||
* sections in memory.
|
||||
*/
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/*
|
||||
* The ".text" section is used for the code, and
|
||||
* read only (.rodata) data. Even the vectors (.vectors)
|
||||
* MUST be saved at the start of this section.
|
||||
*/
|
||||
.text :
|
||||
{
|
||||
_stext = .; /* Provide the name for the start of this section */
|
||||
|
||||
CREATE_OBJECT_SYMBOLS
|
||||
KEEP(*(.vectors))
|
||||
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
|
||||
. = ALIGN(4); /* Align the start of the exidx part */
|
||||
*(.ARM.exidx)
|
||||
*(.ARM.exidx.*)
|
||||
|
||||
. = ALIGN(4); /* Align the start of the rodata part */
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
|
||||
. = ALIGN(4); /* Align the end of the section */
|
||||
} > FLASH
|
||||
_etext = .; /* Provide the name for the end of this section */
|
||||
|
||||
|
||||
/*
|
||||
* The ".data" section is used for initialized data
|
||||
* and for functions (.fastrun) which should be copied
|
||||
* from flash to ram. This functions will later be
|
||||
* executed from ram instead of flash.
|
||||
*/
|
||||
.data : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4); /* Align the start of the section */
|
||||
_sdata = .; /* Provide the name for the start of this section */
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
|
||||
. = ALIGN(4); /* Align the start of the fastrun part */
|
||||
*(.fastrun)
|
||||
*(.fastrun.*)
|
||||
|
||||
. = ALIGN(4); /* Align the end of the section */
|
||||
} > RAM
|
||||
_edata = .; /* Provide the name for the end of this section */
|
||||
|
||||
|
||||
/*
|
||||
* The ".bss" section is used for uninitialized data.
|
||||
* This section will be cleared by the startup code.
|
||||
*/
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4); /* Align the start of the section */
|
||||
_sbss = .; /* Provide the name for the start of this section */
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
|
||||
. = ALIGN(4); /* Align the end of the section */
|
||||
} > RAM = 0
|
||||
_ebss = .; /* Provide the name for the end of this section */
|
||||
|
||||
|
||||
/*
|
||||
* The ".stack" section is our stack.
|
||||
* Here this section starts at the end of the ram segment.
|
||||
*/
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
}
|
||||
|
||||
/*** EOF **/
|
||||
|
||||
@@ -1,144 +0,0 @@
|
||||
/****************************************************************************
|
||||
* Copyright (c) 2011 by Michael Fischer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the author nor the names of its contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************
|
||||
* History:
|
||||
*
|
||||
* 22.05.2011 mifi First Version
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* In this linker script there is no heap available.
|
||||
* The stack start at the end of the ram segment.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Take a look in the "The GNU linker" manual, here you get
|
||||
* the following information about the "MEMORY":
|
||||
*
|
||||
* "The MEMORY command describes the location and size of
|
||||
* blocks of memory in the target."
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00400000, LENGTH = 512K
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 48K
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* And the "SECTION" is used for:
|
||||
*
|
||||
* "The SECTIONS command tells the linker how to map input
|
||||
* sections into output sections, and how to place the output
|
||||
* sections in memory.
|
||||
*/
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/*
|
||||
* The ".text" section is used for the code, and
|
||||
* read only (.rodata) data. Even the vectors (.vectors)
|
||||
* MUST be saved at the start of this section.
|
||||
*/
|
||||
.text :
|
||||
{
|
||||
_stext = .; /* Provide the name for the start of this section */
|
||||
|
||||
CREATE_OBJECT_SYMBOLS
|
||||
KEEP(*(.vectors))
|
||||
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
|
||||
. = ALIGN(4); /* Align the start of the exidx part */
|
||||
*(.ARM.exidx)
|
||||
*(.ARM.exidx.*)
|
||||
|
||||
. = ALIGN(4); /* Align the start of the rodata part */
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
|
||||
. = ALIGN(4); /* Align the end of the section */
|
||||
} > FLASH
|
||||
_etext = .; /* Provide the name for the end of this section */
|
||||
|
||||
|
||||
/*
|
||||
* The ".data" section is used for initialized data
|
||||
* and for functions (.fastrun) which should be copied
|
||||
* from flash to ram. This functions will later be
|
||||
* executed from ram instead of flash.
|
||||
*/
|
||||
.data : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4); /* Align the start of the section */
|
||||
_sdata = .; /* Provide the name for the start of this section */
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
|
||||
. = ALIGN(4); /* Align the start of the fastrun part */
|
||||
*(.fastrun)
|
||||
*(.fastrun.*)
|
||||
|
||||
. = ALIGN(4); /* Align the end of the section */
|
||||
} > RAM
|
||||
_edata = .; /* Provide the name for the end of this section */
|
||||
|
||||
|
||||
/*
|
||||
* The ".bss" section is used for uninitialized data.
|
||||
* This section will be cleared by the startup code.
|
||||
*/
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4); /* Align the start of the section */
|
||||
_sbss = .; /* Provide the name for the start of this section */
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
|
||||
. = ALIGN(4); /* Align the end of the section */
|
||||
} > RAM = 0
|
||||
_ebss = .; /* Provide the name for the end of this section */
|
||||
|
||||
|
||||
/*
|
||||
* The ".stack" section is our stack.
|
||||
* Here this section starts at the end of the ram segment.
|
||||
*/
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
}
|
||||
|
||||
/*** EOF **/
|
||||
|
||||
@@ -1,198 +0,0 @@
|
||||
/****************************************************************************
|
||||
* Copyright (c) 2011 by Michael Fischer. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the author nor the names of its contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************
|
||||
* History:
|
||||
*
|
||||
* 22.05.2011 mifi First Version for the SAM3S4C
|
||||
****************************************************************************/
|
||||
#define __VECTORS_SAM3S_C__
|
||||
|
||||
/*=========================================================================*/
|
||||
/* DEFINE: All extern Data */
|
||||
/*=========================================================================*/
|
||||
extern unsigned long _estack;
|
||||
|
||||
/*=========================================================================*/
|
||||
/* DEFINE: Prototypes */
|
||||
/*=========================================================================*/
|
||||
void ResetHandler(void);
|
||||
|
||||
void NMI_Handler (void) __attribute__((weak));
|
||||
void HardFault_Handler (void) __attribute__((weak));
|
||||
void MemManage_Handler (void) __attribute__((weak));
|
||||
void BusFault_Handler (void) __attribute__((weak));
|
||||
void UsageFault_Handler (void) __attribute__((weak));
|
||||
void SVC_Handler (void) __attribute__((weak));
|
||||
void DebugMon_Handler (void) __attribute__((weak));
|
||||
void PendSV_Handler (void) __attribute__((weak));
|
||||
void SysTick_Handler (void) __attribute__((weak));
|
||||
|
||||
void SUPC_IRQHandler (void) __attribute__((weak));
|
||||
void RSTC_IRQHandler (void) __attribute__((weak));
|
||||
void RTC_IRQHandler (void) __attribute__((weak));
|
||||
void RTT_IRQHandler (void) __attribute__((weak));
|
||||
void WDT_IRQHandler (void) __attribute__((weak));
|
||||
void PMC_IRQHandler (void) __attribute__((weak));
|
||||
void EEFC_IRQHandler (void) __attribute__((weak));
|
||||
void UART0_IRQHandler (void) __attribute__((weak));
|
||||
void UART1_IRQHandler (void) __attribute__((weak));
|
||||
void SMC_IRQHandler (void) __attribute__((weak));
|
||||
void PIOA_IRQHandler (void) __attribute__((weak));
|
||||
void PIOB_IRQHandler (void) __attribute__((weak));
|
||||
void PIOC_IRQHandler (void) __attribute__((weak));
|
||||
void USART0_IRQHandler (void) __attribute__((weak));
|
||||
void USART1_IRQHandler (void) __attribute__((weak));
|
||||
void MCI_IRQHandler (void) __attribute__((weak));
|
||||
void TWI0_IRQHandler (void) __attribute__((weak));
|
||||
void TWI1_IRQHandler (void) __attribute__((weak));
|
||||
void SPI_IRQHandler (void) __attribute__((weak));
|
||||
void SSC_IRQHandler (void) __attribute__((weak));
|
||||
void TC0_IRQHandler (void) __attribute__((weak));
|
||||
void TC1_IRQHandler (void) __attribute__((weak));
|
||||
void TC2_IRQHandler (void) __attribute__((weak));
|
||||
void TC3_IRQHandler (void) __attribute__((weak));
|
||||
void TC4_IRQHandler (void) __attribute__((weak));
|
||||
void TC5_IRQHandler (void) __attribute__((weak));
|
||||
void ADC_IRQHandler (void) __attribute__((weak));
|
||||
void DAC_IRQHandler (void) __attribute__((weak));
|
||||
void PWM_IRQHandler (void) __attribute__((weak));
|
||||
void CRCCU_IRQHandler (void) __attribute__((weak));
|
||||
void ACC_IRQHandler (void) __attribute__((weak));
|
||||
void USBD_IRQHandler (void) __attribute__((weak));
|
||||
|
||||
/*=========================================================================*/
|
||||
/* DEFINE: All code exported */
|
||||
/*=========================================================================*/
|
||||
/*
|
||||
* This is our vector table.
|
||||
*/
|
||||
__attribute__ ((section(".vectors"), used))
|
||||
void (* const gVectors[])(void) =
|
||||
{
|
||||
(void (*)(void))((unsigned long)&_estack),
|
||||
ResetHandler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0,
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0,
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
|
||||
SUPC_IRQHandler, /* 0 SUPPLY CONTROLLER */
|
||||
RSTC_IRQHandler, /* 1 RESET CONTROLLER */
|
||||
RTC_IRQHandler, /* 2 REAL TIME CLOCK */
|
||||
RTT_IRQHandler, /* 3 REAL TIME TIMER */
|
||||
WDT_IRQHandler, /* 4 WATCHDOG TIMER */
|
||||
PMC_IRQHandler, /* 5 PMC */
|
||||
EEFC_IRQHandler, /* 6 EEFC */
|
||||
0, /* 7 Reserved */
|
||||
UART0_IRQHandler, /* 8 UART0 */
|
||||
UART1_IRQHandler, /* 9 UART1 */
|
||||
SMC_IRQHandler, /* 10 SMC */
|
||||
PIOA_IRQHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IRQHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IRQHandler, /* 13 Parallel IO Controller C */
|
||||
USART0_IRQHandler, /* 14 USART 0 */
|
||||
USART1_IRQHandler, /* 15 USART 1 */
|
||||
0, /* 16 Reserved */
|
||||
0, /* 17 Reserved */
|
||||
MCI_IRQHandler, /* 18 MCI */
|
||||
TWI0_IRQHandler, /* 19 TWI 0 */
|
||||
TWI1_IRQHandler, /* 20 TWI 1 */
|
||||
SPI_IRQHandler, /* 21 SPI */
|
||||
SSC_IRQHandler, /* 22 SSC */
|
||||
TC0_IRQHandler, /* 23 Timer Counter 0 */
|
||||
TC1_IRQHandler, /* 24 Timer Counter 1 */
|
||||
TC2_IRQHandler, /* 25 Timer Counter 2 */
|
||||
TC3_IRQHandler, /* 26 Timer Counter 3 */
|
||||
TC4_IRQHandler, /* 27 Timer Counter 4 */
|
||||
TC5_IRQHandler, /* 28 Timer Counter 5 */
|
||||
ADC_IRQHandler, /* 29 ADC controller */
|
||||
DAC_IRQHandler, /* 30 DAC controller */
|
||||
PWM_IRQHandler, /* 31 PWM */
|
||||
CRCCU_IRQHandler, /* 32 CRC Calculation Unit */
|
||||
ACC_IRQHandler, /* 33 Analog Comparator */
|
||||
USBD_IRQHandler, /* 34 USB Device Port */
|
||||
0 /* 35 not used */
|
||||
}; /* gVectors */
|
||||
|
||||
/*
|
||||
* And here are the weak interrupt handlers.
|
||||
*/
|
||||
void NMI_Handler (void) { while(1); }
|
||||
void HardFault_Handler (void) { while(1); }
|
||||
void MemManage_Handler (void) { while(1); }
|
||||
void BusFault_Handler (void) { while(1); }
|
||||
void UsageFault_Handler (void) { while(1); }
|
||||
void SVC_Handler (void) { while(1); }
|
||||
void DebugMon_Handler (void) { while(1); }
|
||||
void PendSV_Handler (void) { while(1); }
|
||||
void SysTick_Handler (void) { while(1); }
|
||||
|
||||
void SUPC_IRQHandler (void) { while(1); }
|
||||
void RSTC_IRQHandler (void) { while(1); }
|
||||
void RTC_IRQHandler (void) { while(1); }
|
||||
void RTT_IRQHandler (void) { while(1); }
|
||||
void WDT_IRQHandler (void) { while(1); }
|
||||
void PMC_IRQHandler (void) { while(1); }
|
||||
void EEFC_IRQHandler (void) { while(1); }
|
||||
void UART0_IRQHandler (void) { while(1); }
|
||||
void UART1_IRQHandler (void) { while(1); }
|
||||
void SMC_IRQHandler (void) { while(1); }
|
||||
void PIOA_IRQHandler (void) { while(1); }
|
||||
void PIOB_IRQHandler (void) { while(1); }
|
||||
void PIOC_IRQHandler (void) { while(1); }
|
||||
void USART0_IRQHandler (void) { while(1); }
|
||||
void USART1_IRQHandler (void) { while(1); }
|
||||
void MCI_IRQHandler (void) { while(1); }
|
||||
void TWI0_IRQHandler (void) { while(1); }
|
||||
void TWI1_IRQHandler (void) { while(1); }
|
||||
void SPI_IRQHandler (void) { while(1); }
|
||||
void SSC_IRQHandler (void) { while(1); }
|
||||
void TC0_IRQHandler (void) { while(1); }
|
||||
void TC1_IRQHandler (void) { while(1); }
|
||||
void TC2_IRQHandler (void) { while(1); }
|
||||
void TC3_IRQHandler (void) { while(1); }
|
||||
void TC4_IRQHandler (void) { while(1); }
|
||||
void TC5_IRQHandler (void) { while(1); }
|
||||
void ADC_IRQHandler (void) { while(1); }
|
||||
void DAC_IRQHandler (void) { while(1); }
|
||||
void PWM_IRQHandler (void) { while(1); }
|
||||
void CRCCU_IRQHandler (void) { while(1); }
|
||||
void ACC_IRQHandler (void) { while(1); }
|
||||
void USBD_IRQHandler (void) { while(1); }
|
||||
// void USBD_IRQHandler (void) { while(1); }
|
||||
|
||||
/*** EOF ***/
|
||||
Reference in New Issue
Block a user