Taranis internal module fix

This commit is contained in:
Bertrand Songis
2019-02-08 11:56:58 +01:00
parent aef7a1074f
commit ca66b25b8e
4 changed files with 0 additions and 21 deletions
-2
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@@ -174,8 +174,6 @@ void enablePulses(uint8_t module, uint8_t protocol)
{
// start new protocol hardware here
#warning "CHECK THAT ALL PROTOCOL INIT WON'T SEND A FIRST WRONG FRAME HERE"
switch (protocol) {
case PROTOCOL_CHANNELS_PXX:
init_pxx(module);
-4
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@@ -187,16 +187,12 @@ void SDRAM_Init(void);
#define IS_EXTERNAL_MODULE_ON() (GPIO_ReadInputDataBit(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) == Bit_SET)
#define IS_UART_MODULE(port) (port == INTERNAL_MODULE)
void init_no_pulses(uint32_t port);
void disable_no_pulses(uint32_t port);
void init_ppm(uint32_t module_index);
void disable_ppm(uint32_t module_index);
void init_pxx(uint32_t module_index);
void disable_pxx(uint32_t module_index);
void init_serial(uint32_t module_index, uint32_t baudrate, uint32_t period_half_us);
void disable_serial(uint32_t module_index);
void init_module_timer( uint32_t module_index, uint32_t period, uint8_t state);
void disable_module_timer( uint32_t module_index);
// Trainer driver
void init_trainer_ppm(void);
-13
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@@ -31,19 +31,6 @@ void extmodulePxxStart();
void extmodulePxx2Start();
void extmoduleSerialStart(uint32_t baudrate, uint32_t period_half_us);
void init_no_pulses(uint32_t port)
{
init_module_timer(port, 18, false);
}
void disable_no_pulses(uint32_t port)
{
if (port == INTERNAL_MODULE)
intmoduleStop();
else
extmoduleStop();
}
void init_ppm(uint32_t port)
{
if (port == EXTERNAL_MODULE) {
-2
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@@ -190,8 +190,6 @@ void init_pxx(uint8_t module);
void disable_pxx(uint8_t module);
void init_serial(uint8_t module, uint32_t baudrate, uint32_t period);
void disable_serial(uint8_t module);
void init_module_timer(uint8_t module, uint32_t period, uint8_t state);
void disable_module_timer(uint8_t module);
// Trainer driver
#define SLAVE_MODE() (g_model.trainerData.mode == TRAINER_MODE_SLAVE)