[Taranis] PPM polarities
This commit is contained in:
@@ -82,10 +82,18 @@ void setupPulsesPPM(unsigned int port) // Don't enable interru
|
||||
if (port == TRAINER_MODULE) {
|
||||
TIM3->CCR2 = rest - 1000 ; // Update time
|
||||
TIM3->CCR4 = (g_model.moduleData[port].ppmDelay*50+300)*2;
|
||||
if(!g_model.moduleData[TRAINER_MODULE].ppmPulsePol)
|
||||
TIM3->CCER |= TIM_CCER_CC4P;
|
||||
else
|
||||
TIM3->CCER &= ~TIM_CCER_CC4P;
|
||||
}
|
||||
else if (port == EXTERNAL_MODULE) {
|
||||
TIM8->CCR2 = rest - 1000; // Update time
|
||||
TIM8->CCR1 = (g_model.moduleData[port].ppmDelay*50+300)*2;
|
||||
if(!g_model.moduleData[EXTERNAL_MODULE].ppmPulsePol)
|
||||
TIM8->CCER |= TIM_CCER_CC1NP;
|
||||
else
|
||||
TIM8->CCER &= ~TIM_CCER_CC1NP;
|
||||
}
|
||||
else {
|
||||
TIM1->CCR2 = rest - 1000; // Update time
|
||||
|
||||
@@ -443,7 +443,9 @@ static void init_pa7_ppm()
|
||||
#if defined(REV3)
|
||||
TIM8->CCER = TIM_CCER_CC1E ;
|
||||
#else
|
||||
TIM8->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ;
|
||||
TIM8->CCER = TIM_CCER_CC1NE;
|
||||
if(!g_model.moduleData[EXTERNAL_MODULE].ppmPulsePol)
|
||||
TIM8->CCER |= TIM_CCER_CC1NP;
|
||||
#endif
|
||||
TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE ; // PWM mode 1
|
||||
TIM8->CCR1 = (g_model.moduleData[EXTERNAL_MODULE].ppmDelay*50+300)*2;
|
||||
|
||||
@@ -56,6 +56,8 @@ void init_trainer_ppm()
|
||||
TIM3->ARR = *TrainerPulsePtr++ ;
|
||||
TIM3->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 2000000 - 1 ; // 0.5uS
|
||||
TIM3->CCER = TIM_CCER_CC4E ;
|
||||
if(!g_model.moduleData[TRAINER_MODULE].ppmPulsePol)
|
||||
TIM3->CCER |= TIM_CCER_CC4P;
|
||||
TIM3->CCMR2 = TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4PE ; // PWM mode 1
|
||||
TIM3->CCR4 = (g_model.moduleData[TRAINER_MODULE].ppmDelay*50+300)*2;
|
||||
TIM3->BDTR = TIM_BDTR_MOE ;
|
||||
|
||||
Reference in New Issue
Block a user