[X9D] First compilation OK! Next step: integrate the code for the drivers (only LCD done) from FrSky...
This commit is contained in:
bsongis
@@ -0,0 +1,488 @@
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/*
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* Authors (alphabetical order)
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* - Bertrand Songis <bsongis@gmail.com>
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* - Bryan J. Rentoul (Gruvin) <gruvin@gmail.com>
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* - Cameron Weeks <th9xer@gmail.com>
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* - Erez Raviv
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* - Jean-Pierre Parisy
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* - Karl Szmutny <shadow@privy.de>
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* - Michael Blandford
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* - Michal Hlavinka
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* - Pat Mackenzie
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* - Philip Moss
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* - Rob Thomson
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* - Romolo Manfredini <romolo.manfredini@gmail.com>
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* - Thomas Husterer
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*
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* open9x is based on code named
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* gruvin9x by Bryan J. Rentoul: http://code.google.com/p/gruvin9x/,
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* er9x by Erez Raviv: http://code.google.com/p/er9x/,
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* and the original (and ongoing) project by
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* Thomas Husterer, th9x: http://code.google.com/p/th9x/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "../open9x.h"
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volatile uint8_t Buzzer_count ;
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// Must NOT be in flash, PDC needs a RAM source.
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// Amplitude reduced to 30% to allow for voice volume
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uint16_t Sine_values[] =
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{
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2048,2085,2123,2160,2197,2233,2268,2303,2336,2369,
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2400,2430,2458,2485,2510,2533,2554,2573,2590,2605,
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2618,2629,2637,2643,2646,2648,2646,2643,2637,2629,
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2618,2605,2590,2573,2554,2533,2510,2485,2458,2430,
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2400,2369,2336,2303,2268,2233,2197,2160,2123,2085,
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2048,2010,1972,1935,1898,1862,1826,1792,1758,1726,
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1695,1665,1637,1610,1585,1562,1541,1522,1505,1490,
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1477,1466,1458,1452,1448,1448,1448,1452,1458,1466,
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1477,1490,1505,1522,1541,1562,1585,1610,1637,1665,
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1695,1726,1758,1792,1826,1862,1898,1935,1972,2010
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};
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// Sound routines
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void startSound()
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{
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register Pio *pioptr ;
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start_timer1() ;
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initDac() ;
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init_twi() ;
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pioptr = PIOA ;
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#if defined(REVA)
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pioptr->PIO_CODR = 0x00010000L ; // Set bit A16 OFF
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pioptr->PIO_PER = 0x00010000L ; // Enable bit A16 (Stock buzzer)
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pioptr->PIO_OER = 0x00010000L ; // Set bit A16 as output
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#else
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pioptr->PIO_CODR = 0x02000000L ; // Set bit A25 OFF
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pioptr->PIO_PER = 0x02000000L ; // Enable bit A25 (Stock buzzer)
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pioptr->PIO_OER = 0x02000000L ; // Set bit A25 as output
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#endif
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}
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#if defined(REVA)
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void buzzer_on()
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{
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PIOA->PIO_SODR = 0x00010000L ; // Set bit A16 ON
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}
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void buzzer_off()
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{
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PIOA->PIO_CODR = 0x00010000L ; // Set bit A16 ON
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}
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#else
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void buzzer_on()
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{
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PIOA->PIO_SODR = 0x02000000L ; // Set bit A25 ON
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}
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void buzzer_off()
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{
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PIOA->PIO_CODR = 0x02000000L ; // Set bit A25 ON
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}
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#endif
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void buzzer_sound( uint8_t time )
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{
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buzzer_on() ;
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Buzzer_count = time ;
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}
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uint32_t currentFrequency = 0;
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uint32_t getFrequency()
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{
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return currentFrequency;
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}
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void setFrequency(uint32_t frequency)
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{
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if (currentFrequency != frequency) {
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currentFrequency = frequency;
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register Tc *ptc ;
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register uint32_t timer ;
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timer = Master_frequency / (8 * frequency) ; // MCK/8 and 100 000 Hz
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if (timer > 65535)
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timer = 65535 ;
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if (timer < 2)
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timer = 2 ;
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ptc = TC0 ; // Tc block 0 (TC0-2)
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ptc->TC_CHANNEL[1].TC_CCR = TC_CCR0_CLKDIS ; // Stop clock
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ptc->TC_CHANNEL[1].TC_RC = timer ; // 100 000 Hz
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ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ;
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ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger)
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}
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}
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// Start TIMER1 at 100000Hz, used for DACC trigger
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void start_timer1()
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{
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register Tc *ptc ;
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register uint32_t timer ;
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// Enable peripheral clock TC0 = bit 23 thru TC5 = bit 28
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PMC->PMC_PCER0 |= 0x01000000L ; // Enable peripheral clock to TC1
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timer = Master_frequency / 800000 ; // MCK/8 and 100 000 Hz
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ptc = TC0 ; // Tc block 0 (TC0-2)
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ptc->TC_BCR = 0 ; // No sync
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ptc->TC_BMR = 0 ;
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ptc->TC_CHANNEL[1].TC_CMR = 0x00008000 ; // Waveform mode
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ptc->TC_CHANNEL[1].TC_RC = timer ; // 100 000 Hz
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ptc->TC_CHANNEL[1].TC_RA = timer >> 1 ;
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ptc->TC_CHANNEL[1].TC_CMR = 0x0009C001 ; // 0000 0000 0000 1001 1100 0000 0000 0001
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// MCK/8, set @ RA, Clear @ RC waveform
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ptc->TC_CHANNEL[1].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger)
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// Sound_g.Frequency = 1000 ;
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}
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// Configure DAC0 (or DAC1 for REVA)
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// Not sure why PB14 has not be allocated to the DAC, although it is an EXTRA function
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// So maybe it is automatically done
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void initDac()
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{
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register Dacc *dacptr ;
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PMC->PMC_PCER0 |= 0x40000000L ; // Enable peripheral clock to DAC
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dacptr = DACC ;
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#if defined(REVA)
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dacptr->DACC_MR = 0x0B010215L ; // 0000 1011 0000 0001 0000 0010 0001 0101
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dacptr->DACC_CHER = 2 ; // Enable channel 1
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#else
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dacptr->DACC_MR = 0x0B000215L ; // 0000 1011 0000 0001 0000 0010 0001 0101
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dacptr->DACC_CHER = 1 ; // Enable channel 0
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#endif
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dacptr->DACC_CDR = 2048 ; // Half amplitude
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// Data for PDC must NOT be in flash, PDC needs a RAM source.
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dacptr->DACC_TPR = CONVERT_PTR(Sine_values);
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dacptr->DACC_TNPR = CONVERT_PTR(Sine_values);
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dacptr->DACC_TCR = 50 ; // words, 100 16 bit values
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dacptr->DACC_TNCR = 50 ; // words, 100 16 bit values
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dacptr->DACC_PTCR = DACC_PTCR_TXTEN ;
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NVIC_EnableIRQ(DACC_IRQn) ;
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}
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extern "C" void DAC_IRQHandler()
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{
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// Data for PDC must NOT be in flash, PDC needs a RAM source.
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if (audioQueue.state == AUDIO_PLAYING_WAV) {
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if (nextAudioData) {
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DACC->DACC_TNPR = CONVERT_PTR(nextAudioData);
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DACC->DACC_TNCR = nextAudioSize;
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nextAudioData = NULL;
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}
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else {
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toneStop();
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}
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}
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else if (audioQueue.state == AUDIO_PLAYING_TONE){
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DACC->DACC_TNPR = CONVERT_PTR(Sine_values);
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DACC->DACC_TNCR = 50 ; // words, 100 16 bit values
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}
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else {
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toneStop();
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}
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}
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void end_sound()
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{
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DACC->DACC_IDR = DACC_IDR_ENDTX ;
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DACC->DACC_IDR = DACC_IDR_TXBUFE ;
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NVIC_DisableIRQ(DACC_IRQn) ;
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TWI0->TWI_IDR = TWI_IDR_TXCOMP ;
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NVIC_DisableIRQ(TWI0_IRQn) ;
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PMC->PMC_PCER0 &= ~0x00080000L ; // Disable peripheral clock to TWI0
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PMC->PMC_PCER0 &= ~0x40000000L ; // Disable peripheral clock to DAC
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}
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// Set up for volume control (TWI0)
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// Need PA3 and PA4 set to peripheral A
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void init_twi()
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{
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register Pio *pioptr ;
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register uint32_t timing ;
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PMC->PMC_PCER0 |= 0x00080000L ; // Enable peripheral clock to TWI0
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/* Configure PIO */
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pioptr = PIOA ;
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pioptr->PIO_ABCDSR[0] &= ~0x00000018 ; // Peripheral A
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pioptr->PIO_ABCDSR[1] &= ~0x00000018 ; // Peripheral A
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pioptr->PIO_PDR = 0x00000018 ; // Assign to peripheral
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timing = Master_frequency * 5 / 1000000 ; // 5uS high and low
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timing += 15 - 4 ;
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timing /= 16 ;
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timing |= timing << 8 ;
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TWI0->TWI_CWGR = 0x00040000 | timing ; // TWI clock set
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TWI0->TWI_CR = TWI_CR_MSEN | TWI_CR_SVDIS ; // Master mode enable
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TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing
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NVIC_EnableIRQ(TWI0_IRQn) ;
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}
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static int8_t Volume_required ;
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static uint8_t Volume_read_pending ;
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static uint8_t CoProc_read_pending ;
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static uint8_t CoProc_write_pending ;
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static uint8_t CoProc_appgo_pending ;
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uint8_t Volume_read ;
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uint8_t Coproc_read ;
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int8_t Coproc_temp ;
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int8_t Coproc_maxtemp=-127 ;
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int8_t Coproc_valid ;
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bool get_onlytemp;
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static uint8_t *Twi_read_address ;
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static uint8_t TwiOperation ;
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#define TWI_NONE 0
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#define TWI_READ_VOL 1
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#define TWI_WRITE_VOL 2
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#define TWI_READ_COPROC 3
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#define TWI_COPROC_APPGO 4
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#define TWI_WAIT_STOP 5
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#define TWI_WRITE_COPROC 6
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// Commands to the coprocessor bootloader/application
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#define TWI_CMD_PAGEUPDATE 0x01 // TWI Command to program a flash page
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#define TWI_CMD_EXECUTEAPP 0x02 // TWI Command to jump to the application program
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#define TWI_CMD_SETREAD_ADDRESS 0x03 // TWI Command to set address to read from
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#define TWI_CMD_WRITE_DATA 0x04 // TWI Command send data to the application
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#define COPROC_RX_BUXSIZE 22
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uint8_t Co_proc_status[COPROC_RX_BUXSIZE] ;
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uint8_t *Co_proc_write_ptr ;
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uint32_t Co_proc_write_count ;
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// This is called from an interrupt routine, or
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// interrupts must be disabled while it is called
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// from elsewhere.
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void i2c_check_for_request()
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{
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if ( TWI0->TWI_IMR & TWI_IMR_TXCOMP )
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{
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return ; // Busy
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}
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if ( Volume_required >= 0 ) // Set volume to this value
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{
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TWI0->TWI_MMR = 0x002F0000 ; // Device 5E (>>1) and master is writing
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TwiOperation = TWI_WRITE_VOL ;
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TWI0->TWI_THR = Volume_required ; // Send data
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Volume_required = -1 ;
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TWI0->TWI_IER = TWI_IER_TXCOMP ;
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TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx
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}
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else if ( CoProc_read_pending )
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{
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Coproc_valid = 0 ;
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CoProc_read_pending = 0 ;
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TWI0->TWI_MMR = 0x00351000 ; // Device 35 and master is reading
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TwiOperation = TWI_READ_COPROC ;
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#ifndef SIMU
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TWI0->TWI_RPR = (uint32_t)&Co_proc_status[0] ;
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#endif
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TWI0->TWI_RCR = COPROC_RX_BUXSIZE - 1 ;
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if ( TWI0->TWI_SR & TWI_SR_RXRDY )
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{
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(void) TWI0->TWI_RHR ;
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}
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TWI0->TWI_PTCR = TWI_PTCR_RXTEN ; // Start transfers
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TWI0->TWI_CR = TWI_CR_START ; // Start Rx
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TWI0->TWI_IER = TWI_IER_RXBUFF | TWI_IER_TXCOMP ;
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}
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else if ( Volume_read_pending )
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{
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Volume_read_pending = 0 ;
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TWI0->TWI_MMR = 0x002F1000 ; // Device 5E (>>1) and master is reading
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TwiOperation = TWI_READ_VOL ;
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Twi_read_address = &Volume_read ;
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TWI0->TWI_CR = TWI_CR_START | TWI_CR_STOP ; // Start and stop Tx
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TWI0->TWI_IER = TWI_IER_TXCOMP ;
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}
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else if ( CoProc_appgo_pending )
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{
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CoProc_appgo_pending = 0 ;
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TWI0->TWI_MMR = 0x00350000 ; // Device 35 and master is writing
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TwiOperation = TWI_COPROC_APPGO ;
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TWI0->TWI_THR = TWI_CMD_EXECUTEAPP ; // Send appgo command
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TWI0->TWI_IER = TWI_IER_TXCOMP ;
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TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx
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}
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else if ( CoProc_write_pending )
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{
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CoProc_write_pending = 0 ;
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TWI0->TWI_MMR = 0x00350000 ; // Device 35 and master is writing
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TwiOperation = TWI_WRITE_COPROC ;
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#ifndef SIMU
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TWI0->TWI_TPR = (uint32_t)Co_proc_write_ptr ;
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#endif
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TWI0->TWI_TCR = Co_proc_write_count ;
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TWI0->TWI_THR = TWI_CMD_WRITE_DATA ; // Send write command
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TWI0->TWI_PTCR = TWI_PTCR_TXTEN ; // Start data transfer
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TWI0->TWI_IER = TWI_IER_TXBUFE | TWI_IER_TXCOMP ;
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}
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}
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static const uint8_t Volume_scale[NUM_VOL_LEVELS] =
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{
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0, 2, 4, 6, 8, 10, 13, 17, 22, 27, 33, 40,
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64, 82, 96, 105, 112, 117, 120, 122, 124, 125, 126, 127
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} ;
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void setVolume( unsigned char volume )
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{
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// PMC->PMC_PCER0 |= 0x00080000L ; // Enable peripheral clock to TWI0
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if ( volume >= NUM_VOL_LEVELS )
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{
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volume = NUM_VOL_LEVELS - 1 ;
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}
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volume = Volume_scale[volume] ;
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Volume_required = volume ;
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__disable_irq() ;
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i2c_check_for_request() ;
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__enable_irq() ;
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}
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void read_volume()
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{
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Volume_read_pending = 1 ;
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__disable_irq() ;
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i2c_check_for_request() ;
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__enable_irq() ;
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}
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void read_coprocessor(bool onlytemp)
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{
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if (onlytemp) {
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get_onlytemp=true;
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} else {
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get_onlytemp=false;
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}
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CoProc_read_pending = 1 ;
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__disable_irq() ;
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i2c_check_for_request() ;
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__enable_irq() ;
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}
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void write_coprocessor( uint8_t *ptr, uint32_t count )
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{
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Co_proc_write_ptr = ptr ;
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Co_proc_write_count = count ;
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CoProc_write_pending = 1 ;
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__disable_irq() ;
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i2c_check_for_request() ;
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__enable_irq() ;
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}
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void appgo_coprocessor()
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{
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CoProc_appgo_pending = 1 ;
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__disable_irq() ;
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i2c_check_for_request() ;
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__enable_irq() ;
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}
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#if !defined(SIMU)
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extern "C" void TWI0_IRQHandler()
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{
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if ( TwiOperation == TWI_READ_VOL )
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{
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if ( TWI0->TWI_SR & TWI_SR_RXRDY )
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{
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*Twi_read_address = TWI0->TWI_RHR ; // Read data
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}
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}
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if ( TwiOperation == TWI_READ_COPROC )
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{
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if ( TWI0->TWI_SR & TWI_SR_RXBUFF )
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{
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TWI0->TWI_IDR = TWI_IDR_RXBUFF ;
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TwiOperation = TWI_WAIT_STOP ;
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TWI0->TWI_CR = TWI_CR_STOP ; // Stop Rx
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TWI0->TWI_RCR = 1 ; // Last byte
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return ;
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}
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else
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{
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Coproc_valid = -1 ;
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}
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}
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if ( TwiOperation == TWI_WAIT_STOP )
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{
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Coproc_valid = 1 ;
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Coproc_read = Co_proc_status[0] ;
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||||
if ( Coproc_read & 0x80 ) {
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// Bootloader
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||||
CoProc_appgo_pending = 1 ; // Action application
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||||
}
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else {
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||||
// Got data from tiny app
|
||||
// Set the date and time
|
||||
struct gtm utm;
|
||||
if (!get_onlytemp) {
|
||||
utm.tm_sec = Co_proc_status[1] ;
|
||||
utm.tm_min = Co_proc_status[2] ;
|
||||
utm.tm_hour = Co_proc_status[3] ;
|
||||
utm.tm_mday = Co_proc_status[4] ;
|
||||
utm.tm_mon = Co_proc_status[5] - 1;
|
||||
utm.tm_year = (Co_proc_status[6] + ( Co_proc_status[7] << 8 )) - 1900;
|
||||
g_rtcTime = gmktime(&utm);
|
||||
}
|
||||
Coproc_temp = Co_proc_status[8];
|
||||
if (Coproc_temp > Coproc_maxtemp)
|
||||
Coproc_maxtemp=Coproc_temp;
|
||||
}
|
||||
TWI0->TWI_PTCR = TWI_PTCR_RXTDIS ; // Stop transfers
|
||||
if ( TWI0->TWI_SR & TWI_SR_RXRDY ) {
|
||||
(void) TWI0->TWI_RHR ; // Discard any rubbish data
|
||||
}
|
||||
}
|
||||
|
||||
// if ( TwiOperation == TWI_WRITE_VOL )
|
||||
// {
|
||||
|
||||
// }
|
||||
|
||||
if ( TwiOperation == TWI_WRITE_COPROC )
|
||||
{
|
||||
if ( TWI0->TWI_SR & TWI_SR_TXBUFE )
|
||||
{
|
||||
TWI0->TWI_IDR = TWI_IDR_TXBUFE ;
|
||||
TWI0->TWI_CR = TWI_CR_STOP ; // Stop Tx
|
||||
TWI0->TWI_PTCR = TWI_PTCR_TXTDIS ; // Stop transfers
|
||||
TwiOperation = TWI_NONE ;
|
||||
return ;
|
||||
}
|
||||
}
|
||||
|
||||
TWI0->TWI_IDR = TWI_IDR_TXCOMP | TWI_IDR_TXBUFE | TWI_PTCR_TXTDIS ;
|
||||
if ( TWI0->TWI_SR & TWI_SR_NACK )
|
||||
{
|
||||
}
|
||||
TwiOperation = TWI_NONE ;
|
||||
i2c_check_for_request() ;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user