feat(radio): I2S driver
This commit is contained in:
raphaelcoeffic
committed by
Malte Langermann
Malte Langermann
parent
5fe02b7316
commit
f22b9c0658
@@ -47,6 +47,7 @@ if(NOT NATIVE_BUILD)
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${STM32CUBE_SRC_PREFIX}_hal_rtc.c
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${STM32CUBE_SRC_PREFIX}_hal_i2c.c
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${STM32CUBE_SRC_PREFIX}_hal_i2c_ex.c
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${STM32CUBE_SRC_PREFIX}_hal_i2s.c
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${STM32CUBE_SRC_PREFIX}_hal_sd.c
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${STM32CUBE_SRC_PREFIX}_hal_dma.c
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${STM32CUBE_SRC_PREFIX}_hal_pcd.c
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@@ -87,6 +88,7 @@ if(NOT NATIVE_BUILD)
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${STM32CUBE_SRC_PREFIX}_hal_rtc.c
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${STM32CUBE_SRC_PREFIX}_hal_i2c.c
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${STM32CUBE_SRC_PREFIX}_hal_i2c_ex.c
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${STM32CUBE_SRC_PREFIX}_hal_i2s.c
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${STM32CUBE_SRC_PREFIX}_hal_sd.c
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${STM32CUBE_SRC_PREFIX}_hal_dma.c
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${STM32CUBE_SRC_PREFIX}_hal_mdma.c
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@@ -34,12 +34,16 @@
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inline static bool stm32_dma_check_tc_flag(DMA_TypeDef* DMAx, uint32_t DMA_Stream)
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{
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return LL_DMA_IsActiveFlag_TC(DMAx, DMA_Stream);
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if (!LL_DMA_IsActiveFlag_TC(DMAx, DMA_Stream)) return false;
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LL_DMA_ClearFlag_TC(DMAx, DMA_Stream);
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return true;
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}
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inline static bool stm32_dma_check_ht_flag(DMA_TypeDef* DMAx, uint32_t DMA_Stream)
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{
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return LL_DMA_IsActiveFlag_HT(DMAx, DMA_Stream);
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if (!LL_DMA_IsActiveFlag_HT(DMAx, DMA_Stream)) return false;
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LL_DMA_ClearFlag_HT(DMAx, DMA_Stream);
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return true;
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}
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#else // STM32H7RS
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@@ -0,0 +1,136 @@
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/*
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* Copyright (C) EdgeTX
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*
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* Based on code named
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* opentx - https://github.com/opentx/opentx
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* th9x - http://code.google.com/p/th9x
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* er9x - http://code.google.com/p/er9x
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* gruvin9x - http://code.google.com/p/gruvin9x
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*
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* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "stm32_i2s.h"
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#include "stm32_gpio.h"
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#include "stm32_spi.h"
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#include "stm32_dma.h"
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#include "hal/gpio.h"
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#include "stm32_hal_ll.h"
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static void i2s_gpio_init(const stm32_i2s_t* i2s)
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{
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stm32_i2s_pindef_t gpios[] = {
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i2s->MCK, i2s->WS, i2s->CK, i2s->SDO, i2s->SDI,
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};
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for (unsigned i = 0; i < sizeof(gpios) / sizeof(gpios[0]); i++) {
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gpio_init_af(gpios[i].pin, gpios[i].af, GPIO_PIN_SPEED_VERY_HIGH);
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}
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}
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static void i2s_dma_init(const stm32_i2s_t* i2s)
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{
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stm32_dma_enable_clock(i2s->DMA);
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LL_DMA_DeInit(i2s->DMA, i2s->DMA_Stream);
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LL_DMA_InitTypeDef dmaInit;
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LL_DMA_StructInit(&dmaInit);
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#if defined(STM32H7)
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dmaInit.Mode = LL_DMA_MODE_CIRCULAR;
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dmaInit.PeriphRequest = i2s->DMA_PeriphRequest;
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dmaInit.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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dmaInit.Priority = LL_DMA_PRIORITY_VERYHIGH;
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dmaInit.PeriphOrM2MSrcAddress = LL_SPI_DMA_GetTxRegAddr(i2s->SPIx);
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dmaInit.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_HALFWORD;
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dmaInit.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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dmaInit.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_HALFWORD;
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#elif defined(STM32H7RS)
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dmaInit.Request = i2s->DMA_PeriphRequest;
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dmaInit.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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dmaInit.Priority = LL_DMA_HIGH_PRIORITY;
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dmaInit.DestAddress = LL_SPI_DMA_GetTxRegAddr(i2s->SPIx);
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dmaInit.DestDataWidth = LL_DMA_DEST_DATAWIDTH_HALFWORD;
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dmaInit.SrcIncMode = LL_DMA_SRC_INCREMENT;
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dmaInit.SrcDataWidth = LL_DMA_SRC_DATAWIDTH_HALFWORD;
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#endif
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LL_DMA_Init(i2s->DMA, i2s->DMA_Stream, &dmaInit);
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}
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int stm32_i2s_init(const stm32_i2s_t* i2s)
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{
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if (!i2s) return -1;
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i2s_gpio_init(i2s);
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stm32_spi_enable_clock(i2s->SPIx);
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LL_I2S_Disable(i2s->SPIx);
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LL_I2S_InitTypeDef i2s_init;
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LL_I2S_StructInit(&i2s_init);
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i2s_init.Mode = LL_I2S_MODE_MASTER_TX;
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i2s_init.Standard = LL_I2S_STANDARD_PHILIPS;
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i2s_init.DataFormat = LL_I2S_DATAFORMAT_16B;
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i2s_init.MCLKOutput = LL_I2S_MCLK_OUTPUT_ENABLE;
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i2s_init.AudioFreq = LL_I2S_AUDIOFREQ_32K;
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if (LL_I2S_Init(i2s->SPIx, &i2s_init) != SUCCESS) return -1;
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LL_I2S_Enable(i2s->SPIx);
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if (i2s->DMA) i2s_dma_init(i2s);
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return 0;
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}
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void stm32_i2s_config_dma_stream(const stm32_i2s_t* i2s, void* buffer, uint32_t nb_xfer)
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{
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LL_I2S_Disable(i2s->SPIx);
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// clear HT & TC flags
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stm32_dma_check_ht_flag(i2s->DMA, i2s->DMA_Stream);
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stm32_dma_check_tc_flag(i2s->DMA, i2s->DMA_Stream);
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// setup DMA buffer address & length
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#if defined(STM32H7)
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LL_DMA_SetMemoryAddress(i2s->DMA, i2s->DMA_Stream, (uintptr_t)buffer);
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LL_DMA_SetDataLength(i2s->DMA, i2s->DMA_Stream, nb_xfer);
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#elif defined(STM32H7RS)
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LL_DMA_SetSrcAddress(i2s->DMA, i2s->DMA_Stream, (uintptr_t)buffer);
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LL_DMA_SetBlkDataLength(i2s->DMA, i2s->DMA_Stream, nb_xfer * 2); // bytes
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#endif
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}
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void stm32_i2s_start_dma_stream(const stm32_i2s_t* i2s)
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{
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#if defined(STM32H7)
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LL_DMA_EnableStream(i2s->DMA, i2s->DMA_Stream);
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#elif defined(STM32H7RS)
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LL_DMA_EnableChannel(i2s->DMA, i2s->DMA_Stream);
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#endif
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// enable DMA request
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LL_SPI_EnableDMAReq_TX(i2s->SPIx);
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// enable I2S
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LL_I2S_Enable(i2s->SPIx);
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// start transfer
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LL_SPI_StartMasterTransfer(i2s->SPIx);
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}
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bool stm32_i2s_is_xfer_started(const stm32_i2s_t* i2s)
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{
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return READ_BIT(i2s->SPIx->CR1, SPI_CR1_CSTART);
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}
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@@ -0,0 +1,49 @@
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/*
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* Copyright (C) EdgeTX
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*
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* Based on code named
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* opentx - https://github.com/opentx/opentx
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* th9x - http://code.google.com/p/th9x
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* er9x - http://code.google.com/p/er9x
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* gruvin9x - http://code.google.com/p/gruvin9x
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*
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* License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#pragma once
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#include "stm32_gpio.h"
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struct stm32_i2s_pindef_t {
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gpio_t pin;
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gpio_af_t af;
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};
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struct stm32_i2s_t {
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SPI_TypeDef* SPIx;
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stm32_i2s_pindef_t MCK;
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stm32_i2s_pindef_t WS;
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stm32_i2s_pindef_t CK;
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stm32_i2s_pindef_t SDO;
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stm32_i2s_pindef_t SDI;
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DMA_TypeDef* DMA;
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uint32_t DMA_Stream;
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uint32_t DMA_PeriphRequest;
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};
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int stm32_i2s_init(const stm32_i2s_t* i2s);
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void stm32_i2s_config_dma_stream(const stm32_i2s_t* i2s, void* buffer, uint32_t nb_xfer);
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void stm32_i2s_start_dma_stream(const stm32_i2s_t* i2s);
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bool stm32_i2s_is_xfer_started(const stm32_i2s_t* i2s);
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@@ -56,7 +56,7 @@ extern "C" {
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// #define HAL_HASH_MODULE_ENABLED
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// #define HAL_HCD_MODULE_ENABLED
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#define HAL_I2C_MODULE_ENABLED
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// #define HAL_I2S_MODULE_ENABLED
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#define HAL_I2S_MODULE_ENABLED
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// #define HAL_I3C_MODULE_ENABLED
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// #define HAL_ICACHE_MODULE_ENABLED
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// #define HAL_IRDA_MODULE_ENABLED
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@@ -63,7 +63,7 @@
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// #define HAL_HRTIM_MODULE_ENABLED
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// #define HAL_HSEM_MODULE_ENABLED
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#define HAL_I2C_MODULE_ENABLED
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// #define HAL_I2S_MODULE_ENABLED
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#define HAL_I2S_MODULE_ENABLED
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// #define HAL_IRDA_MODULE_ENABLED
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// #define HAL_IWDG_MODULE_ENABLED
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//#define HAL_JPEG_MODULE_ENABLED
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