gruvin@gmail.com
37387f91fd
and compensated for main clock synchronisation to get accurate 8us bit
lengths, as measured on the logic analsyser.
Specifically, all 1 and 0 bits now measure 8.000us in length, instead of
varyting from 6.250us to 10.750us, as before.
NOTE: A similar len-5 / len+3 compensation is almost certainly required
to improve bit timing on the stock board, in software bit-bang mode,
but I did not want to commit such a change to trunk without being
able to bench test it first. The values might differ slightly, due
to the number of instruction cycles executed before the actual
PORT B bit toggle code is reached. But it will NOT be the same for
both 1 and 0 bits.