605 lines
13 KiB
C++
605 lines
13 KiB
C++
/****************************************************************************
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* Copyright (c) 2014 by Michael Blandford. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of its contributors may
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* be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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****************************************************************************
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* Other Authors:
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* - Andre Bernet
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* - Bertrand Songis
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* - Bryan J. Rentoul (Gruvin)
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* - Cameron Weeks
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* - Erez Raviv
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* - Jean-Pierre Parisy
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* - Karl Szmutny
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* - Michal Hlavinka
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* - Pat Mackenzie
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* - Philip Moss
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* - Rob Thomson
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* - Romolo Manfredini
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* - Thomas Husterer
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*
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****************************************************************************/
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/*----------------------------------------------------------------------------
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* Headers
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*----------------------------------------------------------------------------*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include "AT91SAM3S4.h"
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uint8_t Eblock_buffer[4096] ;
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uint8_t Eblock_current[4096] ; // For erased checking
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int32_t EblockAddress ;
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uint8_t Spi_tx_buf[24] ;
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uint8_t Spi_rx_buf[24] ;
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uint32_t Spi_init_done = 0 ;
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uint32_t EepromBlocked = 1 ;
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extern uint8_t EE_timer ;
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// Test for EEPROM file
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uint32_t isEepromStart( uint8_t *p )
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{
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uint32_t csum ;
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uint32_t size = 7 ;
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csum = 0 ;
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while( size )
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{
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csum += *p++ ;
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size -= 1 ;
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}
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if ( csum == *p )
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{
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return 1 ;
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}
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return 0 ;
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}
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uint32_t eeprom_write_one( uint8_t byte, uint8_t count ) ;
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uint32_t eeprom_read_status( void ) ;
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void eeprom_write_enable( void ) ;
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void eeprom_wait_busy( void ) ;
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uint32_t spi_operation( register uint8_t *tx, register uint8_t *rx, register uint32_t count ) ;
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void init_spi( void ) ;
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uint32_t unprotect_eeprom( void ) ;
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uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count ) ;
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void AT25D_Read( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset) ;
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void AT25D_Write( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset ) ;
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uint32_t AT25D_EraseBlock( uint32_t memoryOffset ) ;
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void writeBlock( void ) ;
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uint32_t eeprom_write_one( uint8_t byte, uint8_t count )
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{
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register Spi *spiptr ;
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register uint32_t result ;
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spiptr = SPI ;
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spiptr->SPI_CR = 1 ; // Enable
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(void) spiptr->SPI_RDR ; // Dump any rx data
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spiptr->SPI_TDR = byte ;
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result = 0 ;
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while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 )
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{
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// wait for received
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if ( ++result > 10000 )
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{
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break ;
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}
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}
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if ( count == 0 )
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{
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spiptr->SPI_CR = 2 ; // Disable
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return spiptr->SPI_RDR ;
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}
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(void) spiptr->SPI_RDR ; // Dump the rx data
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spiptr->SPI_TDR = 0 ;
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result = 0 ;
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while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 )
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{
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// wait for received
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if ( ++result > 10000 )
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{
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break ;
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}
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}
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spiptr->SPI_CR = 2 ; // Disable
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return spiptr->SPI_RDR ;
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}
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uint32_t eeprom_read_status()
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{
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return eeprom_write_one( 5, 1 ) ;
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}
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void eeprom_write_enable()
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{
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eeprom_write_one( 6, 0 ) ;
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}
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void eeprom_wait_busy()
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{
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register uint32_t x ;
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register uint32_t y ;
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y = 0 ;
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do
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{
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y += 1 ;
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if ( y > 1000000 )
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{
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break ;
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}
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x = eeprom_read_status() ;
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} while ( x & 1 ) ;
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}
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uint32_t spi_operation( register uint8_t *tx, register uint8_t *rx, register uint32_t count )
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{
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register Spi *spiptr ;
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register uint32_t result ;
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// PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI
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result = 0 ;
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spiptr = SPI ;
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spiptr->SPI_CR = 1 ; // Enable
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(void) spiptr->SPI_RDR ; // Dump any rx data
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while( count )
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{
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result = 0 ;
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while( ( spiptr->SPI_SR & SPI_SR_TXEMPTY ) == 0 )
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{
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// wait
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if ( ++result > 10000 )
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{
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result = 0xFFFF ;
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break ;
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}
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}
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if ( result > 10000 )
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{
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break ;
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}
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// if ( count == 1 )
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// {
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// spiptr->SPI_CR = SPI_CR_LASTXFER ; // LastXfer bit
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// }
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spiptr->SPI_TDR = *tx++ ;
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result = 0 ;
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while( ( spiptr->SPI_SR & SPI_SR_RDRF ) == 0 )
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{
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// wait for received
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if ( ++result > 10000 )
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{
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result = 0x2FFFF ;
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break ;
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}
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}
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if ( result > 10000 )
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{
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break ;
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}
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*rx++ = spiptr->SPI_RDR ;
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count -= 1 ;
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}
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if ( result <= 10000 )
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{
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result = 0 ;
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}
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spiptr->SPI_CR = 2 ; // Disable
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// Power save
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// PMC->PMC_PCER0 &= ~0x00200000L ; // Disable peripheral clock to SPI
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return result ;
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}
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uint32_t spi_PDC_action( register uint8_t *command, register uint8_t *tx, register uint8_t *rx, register uint32_t comlen, register uint32_t count )
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{
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register Spi *spiptr ;
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// register uint32_t result ;
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register uint32_t condition ;
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static uint8_t discard_rx_command[4] ;
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// PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI
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// Spi_complete = 0 ;
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if ( comlen > 4 )
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{
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// Spi_complete = 1 ;
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return 0x4FFFF ;
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}
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condition = SPI_SR_TXEMPTY ;
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spiptr = SPI ;
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spiptr->SPI_CR = 1 ; // Enable
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(void) spiptr->SPI_RDR ; // Dump any rx data
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(void) spiptr->SPI_SR ; // Clear error flags
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spiptr->SPI_RPR = (uint32_t)discard_rx_command ;
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spiptr->SPI_RCR = comlen ;
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if ( rx )
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{
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spiptr->SPI_RNPR = (uint32_t)rx ;
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spiptr->SPI_RNCR = count ;
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condition = SPI_SR_RXBUFF ;
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}
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spiptr->SPI_TPR = (uint32_t)command ;
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spiptr->SPI_TCR = comlen ;
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if ( tx )
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{
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spiptr->SPI_TNPR = (uint32_t)tx ;
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}
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else
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{
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spiptr->SPI_TNPR = (uint32_t)rx ;
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}
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spiptr->SPI_TNCR = count ;
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spiptr->SPI_PTCR = SPI_PTCR_RXTEN | SPI_PTCR_TXTEN ; // Start transfers
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// Wait for things to get started, avoids early interrupt
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for ( count = 0 ; count < 1000 ; count += 1 )
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{
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if ( ( spiptr->SPI_SR & SPI_SR_TXEMPTY ) == 0 )
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{
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break ;
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}
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}
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count = 0 ;
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while( ( spiptr->SPI_SR & condition ) == 0 )
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{
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if ( ++count > 1000000 )
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{
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break ;
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}
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}
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spiptr->SPI_CR = 2 ; // Disable
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(void) spiptr->SPI_RDR ; // Dump any rx data
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(void) spiptr->SPI_SR ; // Clear error flags
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spiptr->SPI_PTCR = SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS ; // Stop tramsfers
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if ( count > 1000000 )
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{
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return 1 ;
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}
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return 0 ;
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}
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uint32_t unprotect_eeprom()
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{
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register uint8_t *p ;
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eeprom_write_enable() ;
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p = Spi_tx_buf ;
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*p = 0x39 ; // Unprotect sector command
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*(p+1) = 0 ;
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*(p+2) = 0 ;
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*(p+3) = 0 ; // 3 bytes address
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return spi_operation( p, Spi_rx_buf, 4 ) ;
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}
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void init_spi()
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{
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register Pio *pioptr ;
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register Spi *spiptr ;
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register uint32_t timer ;
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register uint8_t *p ;
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uint8_t spi_buf[4] ;
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if ( !Spi_init_done)
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{
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PMC->PMC_PCER0 |= 0x00200000L ; // Enable peripheral clock to SPI
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/* Configure PIO */
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pioptr = PIOA ;
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pioptr->PIO_ABCDSR[0] &= ~0x00007800 ; // Peripheral A bits 14,13,12,11
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pioptr->PIO_ABCDSR[1] &= ~0x00007800 ; // Peripheral A
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pioptr->PIO_PDR = 0x00007800 ; // Assign to peripheral
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spiptr = SPI ;
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timer = ( 64000000 / 3000000 ) << 8 ;
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spiptr->SPI_MR = 0x14000011 ; // 0001 0100 0000 0000 0000 0000 0001 0001 Master
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spiptr->SPI_CSR[0] = 0x01180009 | timer ; // 0000 0001 0001 1000 xxxx xxxx 0000 1001
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// NVIC_EnableIRQ(SPI_IRQn) ;
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p = spi_buf ;
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// *p = 0x39 ; // Unprotect sector command
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// *(p+1) = 0 ;
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// *(p+2) = 0 ;
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// *(p+3) = 0 ; // 3 bytes address
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// spi_operation( p, spi_buf, 4 ) ;
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eeprom_write_enable() ;
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*p = 1 ; // Write status register command
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*(p+1) = 0 ;
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spi_operation( p, spi_buf, 2 ) ;
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Spi_init_done = 1 ;
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}
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}
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void AT25D_Read( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset)
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{
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register uint8_t *p ;
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p = Spi_tx_buf ;
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*p = 3 ; // Read command
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*(p+1) = memoryOffset >> 16 ;
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*(p+2) = memoryOffset >> 8 ;
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*(p+3) = memoryOffset ; // 3 bytes address
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spi_PDC_action( p, 0, BufferAddr, 4, size ) ;
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}
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uint32_t ee32_read_512( uint32_t sector, uint8_t *buffer )
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{
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AT25D_Read( buffer, 512, sector * 512 ) ;
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return 1 ;
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}
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void AT25D_Write( uint8_t *BufferAddr, uint32_t size, uint32_t memoryOffset )
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{
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register uint8_t *p ;
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eeprom_write_enable() ;
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p = Spi_tx_buf ;
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*p = 2 ; // Write command
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*(p+1) = memoryOffset >> 16 ;
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*(p+2) = memoryOffset >> 8 ;
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*(p+3) = memoryOffset ; // 3 bytes address
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spi_PDC_action( p, BufferAddr, 0, 4, size ) ;
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eeprom_wait_busy() ;
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}
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uint32_t eeprom_block_erased( register uint8_t *p)
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{
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register uint32_t x ;
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register uint32_t result ;
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result = 1 ;
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for ( x = 0 ; x < 4096 ; x += 1 )
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{
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if ( *p++ != 0xFF )
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{
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result = 0 ;
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break ;
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}
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}
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return result ;
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}
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uint32_t eeprom_page_erased( register uint8_t *p)
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{
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register uint32_t x ;
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register uint32_t result ;
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result = 1 ;
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for ( x = 0 ; x < 256 ; x += 1 )
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{
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if ( *p++ != 0xFF )
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{
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result = 0 ;
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break ;
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}
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}
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return result ;
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}
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void writeBlock()
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{
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uint32_t x ;
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uint32_t address ;
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uint32_t i ;
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uint8_t *s ;
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x = eeprom_block_erased( Eblock_current ) ; // EEPROM block blanked?
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if ( x == 0 )
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{
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AT25D_EraseBlock( EblockAddress ) ;
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memset( Eblock_current, 0xFF, 4096 ) ; // Now erased
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}
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s = Eblock_buffer ;
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address = EblockAddress ;
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for ( i = 0 ; i < 16 ; i += 1 ) // pages in block
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{
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x = eeprom_page_erased( s ) ;
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if ( x == 0 ) // Not blank
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{
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//EeWriteCount += 1 ;
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AT25D_Write( s, 256, address ) ;
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}
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s += 256 ;
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address += 256 ;
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}
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EblockAddress = -1 ;
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EE_timer = 0 ;
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}
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void readBlock( uint32_t block_address )
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{
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AT25D_Read( Eblock_buffer, 4096, block_address ) ; // read block to write to
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memcpy( Eblock_current, Eblock_buffer, 4096 ) ; // Copy for erase checking
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EblockAddress = block_address ;
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}
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uint32_t ee32_write( const uint8_t *buffer, uint32_t sector, uint32_t count )
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{
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// EEPROM write
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uint32_t startMemoryOffset ;
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uint32_t memoryOffset ;
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uint32_t bytesToWrite ;
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uint8_t *pBuffer ;
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int32_t block_address ;
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if ( sector == 0 )
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{
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if ( isEepromStart( (uint8_t *) buffer ) )
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{
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EepromBlocked = 0 ;
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}
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else
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{
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EepromBlocked = 1 ;
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}
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}
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if ( EepromBlocked )
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{
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return 1 ;
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}
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startMemoryOffset = sector ;
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startMemoryOffset *= 512 ; // Byte address into EEPROM
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memoryOffset = startMemoryOffset;
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bytesToWrite = count * 512 ;
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unprotect_eeprom() ;
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pBuffer = (uint8_t *) buffer ;
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block_address = memoryOffset &0xFFFFF000 ; // 4k boundary
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if ( EblockAddress != -1 )
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{
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// Ram copy is dirty
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if ( EblockAddress != block_address )
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{
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// flush buffer
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writeBlock() ;
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}
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}
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// Now check for pre-read
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if ( EblockAddress != block_address )
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{
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readBlock( block_address ) ;
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// // Check to see if it is blank
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// x = eeprom_block_erased( Eblock_buffer ) ;
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// if ( x == 0 )
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// {
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// AT25D_EraseBlock( block_address ) ;
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// }
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}
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while (bytesToWrite)
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{
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uint32_t bytes_to_copy ;
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uint32_t i ;
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uint8_t *s ;
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uint8_t *dest ;
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if ( EblockAddress != block_address )
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{
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readBlock( block_address ) ;
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}
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dest = Eblock_buffer + (memoryOffset & 0x0FFF ) ;
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s = pBuffer ;
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bytes_to_copy = 4096 - ( memoryOffset - block_address ) ;
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if ( bytes_to_copy > bytesToWrite )
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{
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bytes_to_copy = bytesToWrite ;
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}
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for ( i = 0 ; i < bytes_to_copy ; i += 1 )
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{
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*dest++ = *s++ ;
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}
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memoryOffset += bytes_to_copy ;
|
|
bytesToWrite -= bytes_to_copy ;
|
|
|
|
if ( dest > &Eblock_buffer[4095] )
|
|
{
|
|
// copied data past end
|
|
writeBlock() ;
|
|
}
|
|
else
|
|
{
|
|
EE_timer = 30 ; // Write dirty block in 0.3 secs
|
|
}
|
|
}
|
|
return 1 ;
|
|
}
|
|
|
|
uint32_t AT25D_EraseBlock( uint32_t memoryOffset )
|
|
{
|
|
register uint8_t *p ;
|
|
register uint32_t x ;
|
|
|
|
// EeEraseCount += 1 ;
|
|
|
|
eeprom_write_enable() ;
|
|
p = Spi_tx_buf ;
|
|
*p = 0x20 ; // Block Erase command
|
|
*(p+1) = memoryOffset >> 16 ;
|
|
*(p+2) = memoryOffset >> 8 ;
|
|
*(p+3) = memoryOffset ; // 3 bytes address
|
|
x = spi_operation( p, Spi_rx_buf, 4 ) ;
|
|
|
|
eeprom_wait_busy() ;
|
|
return x ;
|
|
}
|
|
|
|
|