Files
edgetx-gx12/radio
Raphael CoefficandGitHub ffe4fe7e17 fix: clear internal module FIFO after DMA init (#2527)
Otherwise, NDTR will be 0 instead of [buffer size], and thus the read index will not be set to the correct value.
2022-10-13 09:33:51 +10:00
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2017-12-17 13:32:13 +01:00