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[Taranis] ADC DMA moved for X9E

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This commit is contained in:
Bertrand Songis
2016-06-06 19:01:09 +02:00
parent 5ff6341a34
commit 0cf81a7245
2 changed files with 16 additions and 16 deletions
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radio/src/targets/taranis/adc_driver.cpp
+10 -10
View File
@@ -112,35 +112,35 @@ void adcInit()
void adcSingleRead()
{
ADC1_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA
ADC1_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA
ADC1->SR &= ~(uint32_t)(ADC_SR_EOC | ADC_SR_STRT | ADC_SR_OVR);
ADC1_DMA->LIFCR = ADC1_DMA_FLAGS; // Write ones to clear bits
ADC1_DMA_Stream->CR |= DMA_SxCR_EN; // Enable DMA
ADC1_DMA->HIFCR = ADC1_DMA_FLAGS; // Write ones to clear bits
ADC1_DMA_Stream->CR |= DMA_SxCR_EN; // Enable DMA
ADC1->CR2 |= (uint32_t) ADC_CR2_SWSTART;
#if defined(REV9E)
ADC3_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA
ADC3_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA
ADC3->SR &= ~(uint32_t) ( ADC_SR_EOC | ADC_SR_STRT | ADC_SR_OVR );
ADC3_DMA->LIFCR = ADC3_DMA_FLAGS; // Write ones to clear bits
ADC3_DMA_Stream->CR |= DMA_SxCR_EN; // Enable DMA
ADC3_DMA_Stream->CR |= DMA_SxCR_EN; // Enable DMA
ADC3->CR2 |= (uint32_t)ADC_CR2_SWSTART;
#endif // defined(REV9E)
#if defined(REV9E)
for (unsigned int i=0; i<10000; i++) {
if ((ADC1_DMA->LISR & ADC1_DMA_FLAG_TC) && (ADC3_DMA->LISR & ADC3_DMA_FLAG_TC)) {
if ((ADC1_DMA->HISR & ADC1_DMA_FLAG_TC) && (ADC3_DMA->LISR & ADC3_DMA_FLAG_TC)) {
break;
}
}
ADC1_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA
ADC3_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA
ADC1_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA
ADC3_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA
#else
for (unsigned int i = 0; i < 10000; i++) {
if (ADC1_DMA->LISR & ADC1_DMA_FLAG_TC) {
if (ADC1_DMA->HISR & ADC1_DMA_FLAG_TC) {
break;
}
}
ADC1_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA
ADC1_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA
#endif
}
radio/src/targets/taranis/hal.h
+6 -6
View File
@@ -270,9 +270,9 @@
#define ADC_CHANNEL_STICK_LH ADC_Channel_2 // ADC1_IN2
#define ADC_CHANNEL_STICK_LV ADC_Channel_3 // ADC1_IN3
#define ADC1_DMA DMA2
#define ADC1_DMA_Stream DMA2_Stream0
#define ADC1_DMA_FLAGS (DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 | DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0)
#define ADC1_DMA_FLAG_TC DMA_LISR_TCIF0
#define ADC1_DMA_Stream DMA2_Stream4
#define ADC1_DMA_FLAGS (DMA_HIFCR_CTCIF4 | DMA_HIFCR_CHTIF4 | DMA_HIFCR_CTEIF4 | DMA_HIFCR_CDMEIF4 | DMA_HIFCR_CFEIF4)
#define ADC1_DMA_FLAG_TC DMA_HISR_TCIF4
#if defined(REV9E)
#define ADC_GPIO_PIN_POT1 GPIO_Pin_8 // PF.08
#define ADC_GPIO_PIN_POT2 GPIO_Pin_0 // PB.00
@@ -293,9 +293,9 @@
#define ADC_CHANNEL_SLIDER4 ADC_Channel_9 // ADC1_IN9
#define ADC_CHANNEL_BATT ADC_Channel_10 // ADC1_IN10
#define ADC3_DMA DMA2
#define ADC3_DMA_Stream DMA2_Stream1
#define ADC3_DMA_FLAGS (DMA_LIFCR_CTCIF1 | DMA_LIFCR_CHTIF1 | DMA_LIFCR_CTEIF1 | DMA_LIFCR_CDMEIF1 | DMA_LIFCR_CFEIF1)
#define ADC3_DMA_FLAG_TC DMA_LISR_TCIF1
#define ADC3_DMA_Stream DMA2_Stream0
#define ADC3_DMA_FLAGS (DMA_LIFCR_CTCIF0 | DMA_LIFCR_CHTIF0 | DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0 | DMA_LIFCR_CFEIF0)
#define ADC3_DMA_FLAG_TC DMA_LISR_TCIF0
#elif defined(REVPLUS)
#define ADC_GPIO_PIN_POT1 GPIO_Pin_6 // PA.06
#define ADC_GPIO_PIN_POT2 GPIO_Pin_0 // PB.00