Raphael CoefficandGitHub ffe4fe7e17 fix: clear internal module FIFO after DMA init (#2527) ...

Otherwise, NDTR will be 0 instead of [buffer size], and thus the read index will not be set to the correct value.

2022-10-13 09:33:51 +10:00

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stm32

fix: clear internal module FIFO after DMA init (#2527)

2022-10-13 09:33:51 +10:00

CMakeLists.txt

WiP PoC AFHDS3 internal module

2022-08-11 12:15:46 +02:00

loadboot.cpp

Changed uniformly to EdgeTX boiler plate (also added boiler for files that were missing it).

2021-10-02 14:22:01 +02:00